KR102458522B1 - Gate Driving Circuit for Display Device and Display Device having the same - Google Patents

Abstract

According to the present invention, the gate driving circuit (G-IC) includes a mode selection pin capable of selecting an odd driving mode for controlling only odd gate lines and an even driving mode for controlling only even gate lines, so that the gate By reducing the number of control signals and wiring for them, it can be used as it is without the need to change the timing controller or implement additional functions. can

Description

A gate driving circuit for a display device and a display device including the same {Gate Driving Circuit for Display Device and Display Device having the same}

The present invention relates to a gate driving circuit and a display device including the same, and more particularly, to a gate disposed on both sides of a display panel to selectively control an odd gate line group and an even gate line group It relates to a display device including a driving circuit.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode Various display devices such as an organic light emitting diode display device (OLED) are being used.

Among them, a liquid crystal display (LCD) displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix form, and a driving circuit for driving the liquid crystal display panel.

A plurality of gate lines GL and data lines DL intersect in the pixel array of the liquid crystal display panel, and thin film transistors for driving the liquid crystal cells Clc at the intersections of the gate lines GL and data lines GL (Thin Film Transistor; hereinafter referred to as "TFT") is formed. In addition, a storage capacitor Cst for maintaining the voltage of the liquid crystal cell Clc is formed in the liquid crystal display panel. The liquid crystal cell Clc includes a pixel electrode, a common electrode, and a liquid crystal layer. An electric field is applied to the liquid crystal layers of the liquid crystal cells Clc by the data voltage applied to the pixel electrode and the common voltage Vcom applied to the common electrode. An image is realized by controlling the amount of light passing through the liquid crystal layer by this electric field.

The driving circuit includes a gate driving circuit (G-IC) for sequentially supplying a gate output signal to the gate lines, and a data driving circuit (D-IC) for supplying a video signal (ie, a data voltage) to the data lines. includes The data driving circuit drives the data lines to supply data voltages to the liquid crystal cells Clc. The gate driving circuit sequentially drives the gate lines to select the liquid crystal cells Clc of the display panel to which the data voltage is to be supplied, one by one horizontal line.

The gate driving circuit functions to sequentially generate a gate output signal Vout_i to be provided to each gate line and provide it to each gate line, and the gate signal of the first level is sequentially generated once per frame to generate the corresponding gate supplied to the line.

On the other hand, such a gate driving circuit (G-IC) is formed only on one side of the display panel to drive a total of N gate lines in general. Since all of them must be disposed in the non-display area on one side of the display panel, there is a problem in that the bezel of the display panel on that side increases.

In order to overcome this problem, a two-gate driving circuit method is used in which two gate driving circuits are configured, respectively, disposed on both sides of the display panel, and each gate driving circuit controls a part (half) of N gate lines. .

However, in the conventional two-gate driving circuit methods, the number of gate control signal lines connecting each gate driving circuit from a timing controller (T-con) of the display panel increases, or a gate at which the timing controller is generated. There was a problem such as an increase in the number of control signals.

Against this background, an object of the present invention is to provide a gate driving circuit capable of simplifying a gate control signal wiring structure and the number of gate control signals using two gate driving circuits and a display device including the same.

Another object of the present invention is a gate driving circuit (G) including a mode selection pin capable of selecting an odd driving mode for controlling only odd gate lines and an even gate driving mode for controlling only even gate lines (G). An object of the present invention is to provide a gate driving circuit capable of easily operating in a two-gate driving circuit method without changing the structure of a timing controller by using an IC) chip and a display device including the same.

Another object of the present invention is to provide an odd gate line group and an even gate line group by disposing one gate driving circuit (G-IC) including a mode selection pin on both sides of a display panel, respectively. It is to provide a display device having a simple structure by allowing the display panel to be operated using only four gate control signals and four gate control signal wires.

In order to achieve the above object, according to an aspect of the present invention, a display panel including a plurality of data lines, a total of N gate lines and a plurality of pixels, and an odd gate driving circuit disposed on both sides of the display panel and an even gate driving circuit, wherein the odd gate driving circuit includes an odd/even mode selection pin and is connected to an odd (odd) gate line among the N gate lines, wherein the even gate driving circuit includes an odd/even mode selection pin an odd gate driving circuit and an even gate driving circuit connected to an even (even) gate line among the N gate lines, one or two gate start pulses (GSP1, GSP2), and one horizontal period (1H) Provided is a display device including a timing controller that generates a common gate shift clock (common GSC) and a common gate output enable (common GOE) signal having

According to another embodiment of the present invention, there is provided a gate driving circuit mounted on a display panel for a display device in which N gate lines are disposed and operated according to a control signal from a timing controller, wherein the gate driving circuit selects odd/even mode. pin, and when the mode selection signal applied to the odd/even mode selection pin is the odd selection signal, only the odd gate output signal among the gate output signals generated by the gate control signal received from the timing controller is sent to the odd gate line output, and when the mode selection signal applied to the odd/even mode selection pin is an even selection signal, only the even gate output signal among the gate output signals generated by the gate control signal received from the timing controller is output to the even gate line A gate driving circuit for a display device is provided.

According to an exemplary embodiment of the present invention, which will be described below, although the display panel uses two gate driving circuits, the structure of the display panel can be simplified by minimizing the gate control signal wiring structure and the number of gate control signals.

In addition, a mode selection pin for selecting an odd driving mode in which the gate driving circuits (G-IC) disposed on both sides of the display panel controls only odd gate lines and an even driving mode in which only even gate lines are controlled. By including it, there is an effect that the display panel can be operated only with three or four gate control signals and signal wirings therefor without changing the structure of the timing controller.

1 is a functional block diagram of a liquid crystal display of an overall driving type to which the present invention can be applied.
FIG. 2 shows a structure of a first type of display panel using a two-gate driving circuit, in contrast to the present invention, and FIG. 3 shows a configuration of a control signal and a timing diagram of a gate control signal in the first method.
4 shows a structure of a second type of display panel using a two-gate driving circuit in contrast to the present invention, and FIG. 5 shows a configuration of a control signal and a timing diagram of a gate control signal in the second type.
6 illustrates a structure of a display device according to an embodiment of the present invention.
7 shows a chip structure of a gate driving circuit that can be used in an embodiment of the present invention, and shows a structure including a mode selection pin.
8 is a diagram illustrating a configuration of a gate control signal and a signal flow of a display panel according to an exemplary embodiment of the present invention.
9 is a timing diagram of a gate control signal supplied to an odd gate driving circuit (G-IC_odd) and an even gate driving circuit (G-IC_even) and a gate output signal output from each gate driving circuit according to an embodiment of the present invention; to be.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It should be understood that each component may be “interposed” or “connected,” “coupled,” or “connected” through another component.

1 is a functional block diagram of a liquid crystal display of an overall driving type to which the present invention can be applied.

Referring to FIG. 1 , a typical liquid crystal display device includes a display panel 10 including an active area AA in which a plurality of pixels P are formed, and a display panel for controlling display of each pixel of the display panel. It may include a system board 20 that is a printed circuit board (PCB) including a driving circuit and the like for

The display panel 10 typically includes an array substrate as a lower substrate on which a plurality of gate lines, data lines, and thin film transistors are formed, a color filter substrate as an upper substrate on which a color filter and a black matrix (BM) are formed, and therebetween. It is composed of a liquid crystal layer injected into the

A plurality of pixels are formed in the display panel 10 , which is defined as an intersection region of the gate line GL and the data line DL. That is, the data lines D1 to Dm and the gate lines G1 to Gn cross each other on the lower array substrate, and m × n (m, n is a positive integer) liquid crystal cells Clc due to their cross structure. ) of pixels are formed in a matrix form.

Each of the liquid crystal cells Clc includes a TFT, a pixel electrode 1 connected to the TFT, and a storage capacitor Cst. The liquid crystal cell Clc is driven by the voltage difference between the pixel electrode 1 that charges the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied, and adjusts the amount of transmitted light to obtain image data. A display image corresponding to (DATA_RGB) is implemented.

Meanwhile, a black matrix, a color filter, and a common electrode are formed on the upper glass substrate of the display panel 10 . The common electrode 2 is formed on the upper glass substrate in the vertical electric field driving method such as the TN mode and the VA mode, and is formed on the lower glass substrate together with the pixel electrode 1 in the horizontal electric field driving method such as the IPS mode and the FFS mode. can be formed.

On the other hand, the gate driving circuit 13 for providing the gate output signal Vout to the gate line is formed of the display panel through the TFT array process according to the Gate-In-Panel (hereinafter referred to as 'GIP') method. It may be directly formed on the lower substrate, or manufactured as a separate chip and connected to the display panel by a bonding method and the like.

That is, the gate driving circuit 13 is formed in the non-display area NAA outside the display area 16 (AA) of the display panel 10 and is symmetrically formed on both left and right (or top and bottom) sides of the panel. may be, but is not limited thereto.

Meanwhile, the gate driving circuit 13 may include a plurality of GIP blocks or GIP circuit blocks, and each GIP block may be connected to each gate line to generate and provide a gate output signal Vouti to a corresponding gate line. .

1 shows an example in which the gate driving circuit 13 is formed only on one side (left side) of the display panel to provide gate output signals to N gate lines. FIGS. 2 and 3 show the gate driving circuits on both sides of the display panel. An example in which a furnace is formed is shown.

The system board 20 may be connected to the display panel 10 through a flexible printed circuit board (FPCB; 17) or a tape carrier package (TCP), and the system board 20 includes a timing controller ( 11), it may be implemented in the form of a printed circuit board (PCB) including a data driving circuit 12 and the like.

The timing controller 11 may be expressed as T-Con, and a data control signal ( SDC) and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13 and providing the generated gate control signal GDC to each driving circuit.

The data control signal SDC supplied from the timing controller 11 to the data driving circuit 12 is a source start signal (Source, Start Pulse, SSP), a source sampling clock (Source Sampling Clock, SSC), and a source output enable signal. (Source Output Enable, SOE), and may include a polarity control signal (POL).

In addition, the gate control signal GDC supplied from the timing controller 11 to the gate driving circuit 13 is a gate start signal (Gate Start Pulse, GSP), a gate shift clock (GSC), and a gate output enable signal. It may include a signal (Gate Output Enable, GOE), a polarity control signal (POL), and the like.

That is, when the timing controller 11 provides the GSP for starting the scanning of the gate line to the gate driving circuit 13 , the scanning of the gate line starts, and GSC and GOE having one horizontal period H are applied to the gate driving circuit. When provided as , a gate output signal Vout_i corresponding to each gate line is generated every one horizontal period and provided to the corresponding gate line.

To this end, although not shown, a total of N gate link wirings are formed in the non-display area on the left side of the display panel of FIG. 1 , and each data link wiring functions to connect each gate line to the gate driving circuit 13 . .

Here, the horizontal period or horizontal period period expressed by “H” may be defined as the inverse of a value obtained by multiplying the frame frequency and the number of gate lines. For example, if the display panel has a resolution of 1920*1080, the period of the horizontal section H is 1/(60Hz*1080), which is 15.4 μs.

The data driving circuit 12 may be expressed as a D-IC and includes a plurality of source drive ICs. Each of the source drive ICs samples and latches digital video data (DATA_RGB) input from the timing controller 11 in response to a data control signal SDC from the timing controller 11, and converts it into data of a parallel data system, Using it, a data output signal is generated and supplied to the data lines D1 to Dm.

On the other hand, in the method in which one gate driving circuit is disposed only on one side of the display panel to drive a total of N gate lines as shown in FIG. 1 , the gate link wiring for connecting the gate driving circuit and each gate line is not displayed on one side of the display panel. Since they must all be arranged in the area, there is a problem in that the bezel of the display panel on the side increases.

In order to overcome this problem, a two-gate driving circuit method is used in which two gate driving circuits are configured, respectively, disposed on both sides of the display panel, and each gate driving circuit controls a part (half) of N gate lines. .

2 to 5 are examples of a display panel including such a two-gate driving circuit, and for convenience, FIGS. 2 and 3 are shown in a first manner and FIGS. 4 and 5 are shown in a first manner.

FIG. 2 shows a structure of a first type of display panel using a two-gate driving circuit in contrast to the present invention, and FIG. 3 shows a configuration of a control signal and a timing diagram of a gate control signal.

In the first method as shown in FIGS. 2 and 3 , the first gate driving circuit G-IC #1; 230 is disposed at the lower left side of the display panel, and the first gate driving circuit 230 has a total of N/2 gates. Odd (odd) gate lines GL#1,3,5....(N-1) are connected through the link wiring.

In addition, a second gate driving circuit (G-IC #2; 230') is disposed on the lower right side of the display panel, and an even number (even number) is provided through a total of N/2 gate link wires in the second gate driving circuit 230'. Gate lines GL#2, 3, 6....N are connected.

As shown in FIG. 3A , in this first method, the timing controller 240 provides GSP1, GSC1, GOE1, etc. as gate control signals for controlling the first gate driving circuit 230 .

The first gate driving circuit 230 receiving the gate control signal uses the signal timing shown in FIG. 3B to the odd (odd) gate lines GL#1,3,5...(N-1) )) sequentially output the gate output signals Vout1, Vout3, ... Vout(N-1)), and after outputting the last odd gate output signal Vout(N-1)), the GSP carry signal GSP2 is transmitted to the timing controller 240 .

Then, the timing controller 240 receives the GSP carry signal GSP2, and then generates the gate control signals GSP3, GSC2, and GOE2 for starting the operation of the second gate driving circuit 230' to generate the second gate. It is transmitted to the driving circuit 230'.

The second gate driving circuit 230' outputs the even gate output signals Vout2, Vout4, ... VoutN in the same manner as above, and after outputting the last even gate output signal VoutN, the GSP carry signal By sending GSP4 back to the timing controller 240, scanning of one frame is completed.

On the other hand, as shown in (b) of FIG. 3, in the first method, GSC1/2 and GOE1/2 of the gate control signals supplied to the first gate driving circuit and the second gate driving circuit each have two horizontal periods ( 2H).

As described above, in the first method, the timing controller uses separate gate control signal waveforms (GSC, GOE) for the first gate driving circuit and the second gate driving circuit instead of the basic signal waveform generated in units of one horizontal period (1H). should create

Therefore, there is a disadvantage in that it is difficult to apply the first method if the display panel does not have a timing controller or if the timing controller cannot add the function of changing and generating the gate control signal as described above.

In addition, even if the display panel itself does not have a timing controller, set devices (TVs, monitors, etc.), which are electronic devices to which the display panel is mounted, have a timing controller for the set device. In addition to being able to add, since the timing controller for a set is designed to implement only basic functions for common use, it is difficult to apply the first method.

In addition to the design shortcomings of the timing controller, in the first method, a total of eight gate control signal wires for transmitting a gate control signal must be formed between the timing controller and the second gate driving circuit, so the wiring design is complicated and the bezel There is a disadvantage of increasing the size.

As such, in the two-gate driving circuit structure of the first method as shown in FIGS. 2 and 3, the number of gate control signals is 8, and accordingly, the structure change of the timing controller is required, and wiring design is difficult because there are many gate control signal wirings. The downside is that it is difficult.

As an alternative to overcome the shortcomings of the first method, the second method of the two-gate driving circuit structure shown in FIGS. 4 and 5 may be proposed.

4 shows a structure of a second type of display panel using a two-gate driving circuit in contrast to the present invention, and FIG. 5 shows a configuration of a control signal and a timing diagram of a gate control signal in the second type.

In the second method as shown in FIGS. 4 and 5 , a first gate driving circuit (G-IC #1; 430) is disposed at the lower left side of the display panel, and a total of N/2 gates are disposed in the first gate driving circuit 430 . The first 1 to N/2 gate lines GL#1, 2, 3, ..., N/2 are connected through the link wiring.

In addition, a second gate driving circuit (G-IC #2; 430') is disposed on the lower right side of the display panel, and N/ Two gate lines GL# (N/2+1), (N/2+2), ..., N are connected.

As shown in FIG. 5A , in the second method, the timing controller 440 has GSP1 and one horizontal period 1H as a gate control signal for controlling the first gate driving circuit 430 . GSC, GOE, etc.

The first gate driving circuit 430 receiving the gate control signal uses the signal timing shown in FIG. /2) sequentially outputs the gate output signals Vout1, Vout2... Vout(N/2), and after outputting the last gate output signal Vout(N/2)) in the first half, the GSP carry A signal, GSP2, is generated and transmitted to the second gate driving circuit 430'.

At this time, since the second gate driving circuit 430 ′ receives the same GSC and GOE as those received by the first gate driving circuit 430 from the timing controller 440 , it receives GSP2 from the first gate driving circuit 430 . After receiving, the operation is started, and the gate output signal Vout (N/2 +1), Vout(N/2+2), ... VoutN), and after outputting the last gate output signal VoutN of the second half, the GSP2 carry signal is transmitted to the timing controller 430 by , complete scanning one frame.

In this second method, as shown in (b) of FIG. 5 , a basic control signal waveform in which GSC/GOE of the gate control signals supplied to the first gate driving circuit and the second gate driving circuit has a general one horizontal period. In addition to being the same as , the same gate control signal is used as the 1/2 gate driving circuit.

Accordingly, in the second method, four gate control signals of GSP1, GSp2, GSC, and GOE are sufficient, and the basic control signal waveform can be used as it is, so that the disadvantages of the first method can be solved to some extent.

However, in the second method, the gate link wiring to GL#(N/2) which is the last gate line handled by the first gate driving circuit 430 and the first gate line handled by the second gate driving circuit 430' Because the gate link wiring to GL#(N/2+1) is not completely symmetrical in line design or process, a resistance difference may occur, and such a difference in resistance causes GL#(N/2) and GL#(N/2) A luminance non-uniformity such as a band line between #(N/2+1) may occur.

This display defect can be expressed as a gate block dim phenomenon.

Also, in the second method, the gate output signal Vout(N/2) applied to GL#(N/2), which is the last gate line in charge of the first gate driving circuit 430, proceeds from left to right. Due to the nature of the transfer, the waveform of the output signal at the left start point may be changed while arriving at the right end point.

Conversely, the gate output signal Vout(N/2+1) applied to the first gate line GL#(N/2+1) handled by the second gate driving circuit 430' proceeds from right to left. A signal waveform change similar to the above occurs during the transfer process.

As a result, in the case of adjacent pixels formed with the same data line between GL#(N/2) and GL#(N/2+1), the applied gate output signal waveforms are different, so that luminance non-uniformity may occur in units of pixels. .

As described above, in the second method, there is a disadvantage in that a display defect due to luminance non-uniformity occurs between the control region of the first gate driving circuit 430 and the control region of the second gate driving circuit 430 ′.

The present invention is to compensate for the shortcomings of the first and second methods, and provides two gate driving circuits including a mode selection pin capable of operating in one of an odd driving mode and an even driving mode. It is disposed on both sides of the display panel, and an odd/even mode selection signal is applied to the mode selection pin, and the timing controller includes one or two gate start pulses (GSP1, GSP2) and a common gate shift clock having one horizontal period. By transmitting the GSC and common gate output enable (GOE) signals to both gate driving circuits to operate, the gate control signal can be reduced to simplify the gate control signal wiring, and there is no need to change the structure of the timing controller, etc. A two-gate driving circuit structure that does not cause any defects is proposed.

6 illustrates an overall structure of a display device according to an embodiment of the present invention.

The display device according to the embodiment of the present invention largely includes a display panel 610, gate driving circuits 630 and 630' including odd/even mode selection pins, and a timing controller 640 that generates and outputs a gate control signal. ) is included.

A plurality of data lines DL and a total of N gate lines GL are formed in the display panel 610 , and a display area ( A/A) and a non-display area N/A that is formed around the display area but does not display an image.

Gate driving circuits 630 and 630' are respectively disposed on both sides of one side (lower side) of the non-display area N/A of the display panel 610 , and one or more data driving circuits D- IC; 620 is disposed.

One of the two gate driving circuits disposed on both sides includes an odd/even mode selection pin, and an odd gate driving circuit operating in an odd operation mode according to an odd mode selection signal applied to the odd/even mode selection pin from the outside ( G-IC_odd), and the other one includes an odd/even mode selection pin and an even gate driving circuit (G-IC_even) that operates in an even operation mode according to an even mode selection signal externally applied to the odd/even mode selection pin. )to be.

In FIG. 6, for convenience, the gate driving circuit disposed on the left is described as an odd gate driving circuit (G-IC_odd; 630), and the gate driving circuit disposed on the right is described as an even gate driving circuit (G-IC_even; 630'). Location and function may be interchanged.

The odd gate driving circuit G-IC_odd 630 is connected to the odd (odd) gate line among the N gate lines, and for the connection, N/2 gate link wires 612 are provided in the left non-display area of the display panel. is formed

Also, the even gate driving circuit G-IC_even 630' is connected to an even (even) gate line among the N gate lines. formed in the display area.

Meanwhile, the timing controller 640 according to the present embodiment generates a gate control signal and transmits it to the odd gate driving circuit G-IC_odd 630 and the even gate driving circuit G-IC_even 630', and a data control signal It functions to generate and provide to the data driving circuit (D-IC) 620 .

At this time, the gate control signal provided by the timing controller 640 to the odd gate driving circuit G-IC_odd 630 and the even gate driving circuit G-IC_even 630' is one or two gate start pulses GSP1. , GSP2), a common gate shift clock (common GSC) and a common gate output enable (common GOE) signal having one horizontal period (1H).

That is, the gate control signals GSP, GSC, and GOE used in the present embodiment are basic signal waveforms generated by the timing controller having a general structure, and it is necessary to change the gate control signal as in the first method as shown in FIGS. 2 and 3 . there is no

More specifically, GSP1 is a signal pulse generated by the timing controller to start scanning, and the common GSC and common GOE are basic signal pulses having one horizontal period (1H).

As described above, the gate control signals GSP, GOE, and GSC used in this embodiment are the same as the gate control signals used by the timing controller of the general display device described with reference to FIG. It can be used as is without it.

In addition, the timing controller 640 selects the mode of the gate driving circuit by generating an odd/even mode selection signal that selects the odd/even operation mode of the gate driving circuit at the initial driving time of the display panel, etc., separately from the aforementioned gate control signal. A function of transmitting to the control pin (710 in FIG. 7) is additionally provided. Of course, the odd/even mode selection signal according to the present embodiment does not need to be controlled by the timing controller, and by inputting a high or low signal to the odd/even mode selection pin 710 from the outside, the odd gate driving circuit It may be set to low or even gate driving circuit.

Meanwhile, a first GSP wiring, a common GSC wiring, a common GOE wiring, a second GSP wiring, and a mode selection wiring may be disposed on the display panel between the timing controller, the odd gate driving circuit, and the even gate driving circuit.

8 is a diagram illustrating a gate control signal configuration and signal flow of a display panel according to an embodiment of the present invention, and signal wiring required therefor.

As shown in FIG. 8, between the timing controller 640 and the odd gate driving circuit 630 and the even gate driving circuit 630', a first GSP wiring for transferring GSP1 simultaneously applied to the two gate driving circuits (631) is formed.

Similarly, between the timing controller 640 and the odd gate driving circuit 630 and the even gate driving circuit 630', a common GSC wiring is provided to respectively transmit a common GSC signal and a common GOE signal simultaneously applied to the two gate driving circuits. 633 and a common GOE wiring 632 are formed.

In addition, a mode selection wiring for transferring the odd/even mode selection signal to two gate driving circuits between the timing controller 640 and the odd gate driving circuit 630 and between the timing controller and the even gate driving circuit 630' 635 may be further formed. Of course, the odd/even mode selection signal according to the present embodiment does not need to be controlled by the timing controller, and by inputting a high or low signal to the odd/even mode selection pin 710 from the outside, the odd gate driving circuit It may be set to low or even gate driving circuit. In this case, as shown in FIG. 8 , the mode selection wiring 635 may not be formed on the display panel.

Also, optionally, a second GSP wiring 634 for transmitting GPS2 used for inversion driving may be further formed between the odd gate driving circuit 630 and the even gate driving circuit 630 ′.

GSP2 may not be used in a normal operation, and may be used only in inversion driving in which the last gate line GL#N is first scanned.

Meanwhile, in the odd gate driving circuit 630 according to the present embodiment, only the odd gate output signals Vout1, Vout3, ..., Vout(N-1) among the gate output signals generated by the gate control signal are the odd gate lines GL. #1, 3, 5, …, (N-1)), and the even gate driving circuit 630 ′ includes even gate output signals Vout2, Vout4, …, among the gate output signals generated by the gate control signal. VoutN) has a function of outputting only the even gate lines GL#2, 4, 6, ..., N.

Alternatively, the odd gate driving circuit 630 recognizes only the odd-th pulse among the pulses of the common GSC and common GOE signals among the gate control signals, and accordingly the odd-numbered gate output signals Vout1, Vout3, ..., Vout(N-1)) It is also possible to generate and output to the odd gate lines GL#1,3,5,...,(N-1).

That is, the odd gate driving circuit 630 and the even gate driving circuit 630' according to the present embodiment generate/output the gate output signal using the gate control signal received from the timing controller, It is also possible to generate and output only the gate output signal for the line (odd or even), and it generates all the gate output signals, but skips the output signal of the gate line that it is not in charge of and the gate line it is in charge of. It is also possible to “output” only the output signal of

Such a function may be implemented by a certain software or algorithm in the gate driving circuits 630 and 630' according to the present embodiment.

On the other hand, in the case of a liquid crystal display panel, the display panel 610 used in the display device according to the embodiment of the present invention includes a plurality of gate lines and data lines, and pixels defined in an intersection region thereof, and in each pixel. It may be configured to include an array substrate including a thin film transistor as a switching element for controlling the light transmittance, an upper substrate including a color filter and/or a black matrix, and a liquid crystal material layer formed therebetween.

As used herein, the term “display device” refers to a display device in a narrow sense such as a liquid crystal module (LCM) including a display panel and a driving unit for driving the display panel, as well as a notebook computer which is a finished product including such an LCM. , a television, a computer monitor, a mobile electronic device such as a smart phone or an electronic pad, or a set electronic device or even a set device is used as a concept.

That is, the display device in the present specification is used in the sense of including not only a narrow display device such as an LCM, but also a set device that is an application product including the same.

In addition, for convenience of description, the display device according to various embodiments of the present invention has been described as a display device including a liquid crystal display panel, but the present invention is not limited thereto, and the field emission display device, the plasma display panel, and the electric field are not limited thereto. It can be applied to all kinds of display devices operating by driving a plurality of gate lines, such as a light emitting display device, an organic light emitting display device, and an electrophoretic display device.

As described above, according to the embodiment of the present invention, since the gate control signal generated by the timing controller 640 is the same as a general gate control signal, there is no need to change the structure of the timing controller, and three or four gate control signals GSP1 , GSP2, common GSC, and common GOE) are used, so the signal structure is simple and wiring design for it is easy.

In addition, compared to the second method shown in FIGS. 4 and 5 , the structure according to the present embodiment is completely symmetrical, so there is no room for luminance non-uniformity due to a difference in resistance of the gate link line or a change in the left and right waveforms of the gate output signal. It has an advantage in that there is no

The driving flow of the display device according to the embodiment of the present invention as described above with reference to FIG. 9 is as follows,

9 is a timing diagram of a gate control signal supplied to an odd gate driving circuit (G-IC_odd) and an even gate driving circuit (G-IC_even) and a gate output signal output from each gate driving circuit according to an embodiment of the present invention; to be.

As shown in FIG. 9, in the embodiment of the present invention, odd/even mode selection signals are applied to the mode selection pins of the left and right gate driving circuits, respectively, at the time of initial driving of the display panel or manufacturing of the panel from the outside. One of the driving circuits is set as an odd gate driving circuit and the other as an even gate driving circuit.

For example, when the odd/even mode selection signal is Low, it may indicate an odd operation mode, and if HIGH, it may indicate an even operation mode.

Accordingly, a mode selection signal of LOW is generated from the outside and transmitted to the mode selection pin of the left odd gate driving circuit (G-IC-odd; 630), and the left gate driving circuit receiving it generates its operation mode in odds Set to operation mode.

That is, the gate driving circuit receiving the odd mode operation signal operates an internal algorithm to generate only the odd gate output signals Vout1, Vout3, ..., Vout(N-1) as described in FIG. 9(a). or operate to output.

At the same time, the timing controller 640 or an external separate device generates a HIGH mode selection signal and transmits it to the mode selection pin of the right gate driving circuit 630'. By setting the even operation mode, it operates to generate or output only the even gate output signals Vout2, Vout4, ..., VoutN, as will be described with reference to FIG. 9B.

After the mode selection is completed, the timing controller 640 performs the same gate control signal, GSP1 having one ON pulse, and one horizontal period (1H) as shown in the upper part of FIGS. 9A and 9B. A common GSC signal, which is a gate shift clock having a pulse that is repeated by , and a common GOE signal, which is a gate shift clock, which has a pulse that is repeated in one horizontal period (1H), is generated and is used in the left odd gate driving circuit (G-IC_odd; 630). ) and the right even gate driving circuit (G-IC_even; 630').

That is, according to the present embodiment, the timing controller 640 generates the same gate control signal combination consisting of three signals, GSP1, common GSC, and common GOE signal, and transmits the same to two gate driving circuits at the same time.

As shown in (a) of FIG. 9, the odd gate driving circuit (G-IC_odd; 630) receiving the gate control signals GSP1, common GSC, and common GOE signals is the same as the existing one-side driving type gate driving circuit. All gate output signals Vout1, Vout2, Vout3, ..., VoutN are generated every one horizontal period (1H).

However, the odd gate driving circuit G-IC_odd 630 uses only the odd gate output signals Vout1, Vout3, ..., Vout(N-1) among the gate output signals generated using the internal algorithm to the odd gate line GL# 1,3,5,...,(N-1)).

Of course, as described above, the algorithm implemented inside the odd gate driving circuit (G-IC_odd; 630) does not generate all gate output signals, and the odd-th pulse among the pulses of the common GSC and common GOE signals among the gate control signals. It recognizes only the odd gate output signals (Vout1, Vout3,…, Vout(N-1)) and then outputs it to the odd gate lines (GL#1,3,5,…,(N-1)). may be

Similarly, as shown in (b) of FIG. 9 , the even gate driving circuit G-IC_even 630 ′ that has received the gate control signals GSP1, common GSC, and common GOE signals every single horizontal period 1H. After generating the gate output signals Vout1, Vout2, Vout3, ..., VoutN, only the even gate output signals (Vout2, Vout4, ..., VoutN) of the gate output signals generated using the internal algorithm are the even gate lines GL #2,4,6,…,N).

Of course, as described above, the algorithm implemented inside the even gate driving circuit (G-IC_even; 630') does not generate all gate output signals, and the even-th among the pulses of the common GSC and common GOE signals among the gate control signals. It is also possible to recognize only the pulse, generate an even gate output signal according to it, and output it to the even gate line.

Using this embodiment of the present invention, the number of gate control signals is reduced compared to the first method or the second method shown in FIGS. 2 to 5 , and as shown in FIG. 8 , the timing controller and both gate driving circuits are connected For this purpose, the number and structure of wirings to be formed on the display panel are simplified, which is advantageous for panel design and advantageous for a narrow bezel.

In addition, since these gate control signals, GSP1, common GSC, and common GOE signals, are the same as the signals generated and used by the timing controller in a general overall driving display device, it is necessary to change the existing general-purpose timing controller or implement additional functions. It has the advantage of being able to use it as it is without it.

Meanwhile, the present invention may include not only the entire display device described above, but also the gate driving circuit itself operating in the above-described manner.

7 shows a chip structure of a gate driving circuit that can be used in an embodiment of the present invention, and shows a structure including a mode selection pin.

The gate driving circuit 700 as shown in FIG. 7 is a gate driving circuit mounted on a display panel for a display device on which N gate lines are disposed, and operated according to a control signal from a timing controller, and selects odd/even mode. It includes a pin 710 .

In this gate driving circuit, when the mode selection signal applied from the timing controller or an external separate device is the odd selection signal, only the odd gate output signal among the gate output signals generated by the gate control signal received from the timing controller is sent to the odd gate line. output, and when the mode selection signal received from the timing controller or an external separate device is an even selection signal, only the even gate output signal among the generated gate output signals is output to the even gate line.

In addition, the gate driving circuit 700 according to the present embodiment may select a normal mode operation in which the gate output signal generated by the gate control signal received from the timing controller is output to the corresponding gate line, respectively. It may further include a normal mode selection pin (720 in FIG. 7).

In addition to the various data input/output terminals or pins of the general gate driving circuit chip, the gate driving circuit 700 according to this embodiment has the odd/even mode selection pin 710 and the normal mode selection pin 720 described above. It may be implemented as a chip further comprising a.

In addition, when an odd mode selection signal or an even mode selection signal is applied to the inside of the gate driving circuit 700 according to the present embodiment through the odd/even mode selection pin 710, the gate line (odd or odd) it is responsible for is applied accordingly. Even), it is possible to generate and output only the gate output signals for It contains software or algorithms that "print out" the function.

In addition, in the gate driving circuit 700 according to the present embodiment, when the normal mode selection signal is applied through the normal mode selection pin 720, all gate output signals Vout1, Vout2, Vout3, ..., VoutN) may be output to all the corresponding gate lines GL#1, 2, 3, ..., N, respectively.

As described above, since the gate driving circuit 700 according to the present embodiment can be selected and operated even in the normal mode, it is not arranged on both sides of the display panel as described above, but is arranged on only one side of the display panel. There is an advantage that it can be used even in the structure of FIG. 1 for controlling the gate line.

As described above, using the embodiment of the present invention, the gate driving circuit (G-IC) can select an odd driving mode in which only odd gate lines are controlled and an even driving mode in which only even gate lines are controlled. By including the mode selection pin with the present invention, the number of gate control signals and wiring therefor are reduced, which is advantageous for panel design and has an advantageous effect on the narrow bezel.

In addition, since the gate control signals GSP1, common GSC, and common GOE signals used in this embodiment are the same as the signals generated and used by the timing controller in the display device of the general driving method, the existing general-purpose timing controller may be changed or It has the advantage of being able to use it as it is without the need to implement additional functions.

In addition, since the structure for driving the gate line becomes completely symmetrical on the left and right sides of the display panel, the gate block dim, which is a luminance non-uniformity phenomenon caused by a difference in resistance as in the left and right asymmetric structure (FIG. 4, etc.) or a change in the left and right waveforms of the gate output signal It also has the effect of preventing the phenomenon (Gate Block Dim).

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine configurations within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

600: display panel 620: data driving circuit (D-IC)
630: odd (Odd) gate driving circuit 630': Even gate driving circuit
640: timing controller (T-con) 700: gate driving circuit
710: odd/excellent mode selection pin 720: normal mode selection pin

Claims (9)

a display panel including a plurality of data lines, a total of N gate lines, and a plurality of pixels;
an odd gate driving circuit and an even gate driving circuit disposed on both sides of the display panel, wherein the odd gate driving circuit includes an odd/even mode selection pin and is connected to an odd (odd) gate line among the N gate lines, The even gate driving circuit includes an odd gate driving circuit and an even gate driving circuit including an odd/even mode selection pin and connected to an even (even) gate line among the N gate lines;
Generates a gate control signal including one or two gate start pulses (GSP1, GSP2), a common gate shift clock (common GSC) having one horizontal period (1H), and a common gate output enable (common GOE) signal a timing controller for providing the odd gate driving circuit and the even gate driving circuit;
includes
The odd gate driving circuit is set by the odd mode selection signal applied to the odd/even mode selection pin, and skips the even gate output signal among the gate output signals generated by the gate control signal and skips the odd gate output signal is output to the odd gate line, the even gate driving circuit is set by the even mode selection signal applied to the odd/even mode selection pin, and the odd gate output signal among the gate output signals generated by the gate control signal is skipped and a display device that outputs only an even gate output signal to an even gate line. delete According to claim 1,
a first GSP line, a common GSC line, a common GOE line, and a second GSP line are disposed on the display panel between the timing controller, the odd gate driving circuit, and the even gate driving circuit. 4. The method of claim 3,
The odd gate driving circuit and the even gate driving circuit further include a normal mode selection pin for selecting a normal mode operation to output all gate output signals to corresponding gate lines, respectively. A gate driving circuit mounted on a display panel for a display device on which N gate lines are disposed and operated according to a control signal from a timing controller, the gate driving circuit comprising:
The gate driving circuit includes an odd/even mode selection pin, and when the mode selection signal applied to the odd/even mode selection pin is an odd selection signal, a gate output signal generated by a gate control signal received from a timing controller The even gate output signal is skipped and only the odd gate output signal is output to the odd gate line, and when the mode selection signal applied to the odd/even mode selection pin is an even selection signal, the gate control received from the timing controller A gate driving circuit for a display device that skips an odd gate output signal among gate output signals generated by the signal and outputs only an even gate output signal to an even gate line. 6. The method of claim 5,
The gate control signal provided from the timing controller includes one or two gate start pulses (GSP1, GSP2), a common gate shift clock (common GSC) having one horizontal period (1H), and a common gate output enable (common GOE) ) a gate driving circuit for a display device including a signal. 7. The method of claim 6,
For a display device further comprising a normal mode selection pin for selecting a normal mode operation to output a gate output signal generated by a gate control signal received from the timing controller to a corresponding gate line, respectively gate driving circuit.
a display panel including a plurality of data lines, a total of N gate lines, and a plurality of pixels;
an odd gate driving circuit and an even gate driving circuit disposed on both sides of the display panel, wherein the odd gate driving circuit includes an odd/even mode selection pin and is connected to an odd (odd) gate line among the N gate lines, The even gate driving circuit includes an odd gate driving circuit and an even gate driving circuit including an odd/even mode selection pin and connected to an even (even) gate line among the N gate lines;
Generates a gate control signal including one or two gate start pulses (GSP1, GSP2), a common gate shift clock (common GSC) having one horizontal period (1H), and a common gate output enable (common GOE) signal a timing controller for providing the odd gate driving circuit and the even gate driving circuit to
The odd gate driving circuit and the even gate driving circuit further include a normal mode selection pin for selecting a normal mode operation to output all gate output signals to corresponding gate lines, respectively. A gate driving circuit mounted on a display panel for a display device on which N gate lines are disposed and operated according to a control signal from a timing controller, the gate driving circuit comprising:
The gate driving circuit includes an odd/even mode selection pin, and when the mode selection signal applied to the odd/even mode selection pin is an odd selection signal, a gate output signal generated by a gate control signal received from a timing controller Only the odd gate output signal is output to the odd gate line, and when the mode selection signal applied to the odd/even mode selection pin is the even selection signal, the even gate output signal generated by the gate control signal received from the timing controller is even. Outputs only the gate output signal to the even gate line,
For a display device further comprising a normal mode selection pin for selecting a normal mode operation to output a gate output signal generated by a gate control signal received from the timing controller to a corresponding gate line, respectively gate driving circuit.

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