KR20150080118A - Display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device. The liquid crystal display device includes a horizontal gate line which is connected to pixels arranged in a horizontal line, a vertical gate line which connects an input node of the horizontal gate line and a connection node, and a gate driver IC which supplies a gate pulse to the pixels through the horizontal gate line and the vertical gate line. The input node is located in a non-display region. The connection node is located in the connection node.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device capable of reducing an RC delay phenomenon.

The display field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) that replaces bulky cathode ray tubes (CRTs). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : EPD).

The flat panel display is arranged such that the data lines and the scan lines are orthogonal and the pixels are arranged in a matrix form. In a liquid crystal display device and an organic light emitting diode device, a scan line is sometimes referred to as a gate line because a gate electrode of a TFT is connected to scan lines. Video data voltages to be displayed are supplied to the data lines and gate pulses are sequentially supplied to the gate lines. The video data voltage is supplied to the pixels of the display line to which the gate pulse is supplied and all the display lines are sequentially scanned by the gate pulse to display the video data.

In recent years, the panel of the display device is often made large, and the length of the gate line is increasing with the panel becoming a large screen. The self-resistance increases as the length of the gate line becomes long, and the delay of the gate pulse becomes a problem at a position distant from the input terminal of the gate pulse. If the delay of the gate pulse becomes severe, not only the period in which the gate pulse is supplied is shortened but also the transistor can not be operated in severe cases.

The present invention is to provide a liquid crystal display capable of reducing the RC delay.

The liquid crystal display of the present invention includes a horizontal gate line connected to pixels arranged in a horizontal line, a vertical gate line connecting an input node and a connection node of the horizontal gate line, And a gate drive IC for supplying gate pulses to the input nodes, wherein the input nodes are located in a non-display area, and the connection nodes are located in a display area.

The present invention can improve the delay of the gate pulse due to the resistance of the gate line.

1 is a view showing a liquid crystal display device according to the present invention.
2 is a view showing a connection relationship between vertical gate lines and horizontal gate lines of the liquid crystal display according to the first embodiment;
3 is a plan view of a pixel in which a connection node is formed;
4 is a cross-sectional view of a connection node;
5 is a view showing a liquid crystal display device according to the present invention.
6 is a view showing a connection relationship between vertical gate lines and horizontal gate lines in the liquid crystal display according to the first embodiment;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

However, the present invention is not limited to the organic light emitting display (OLED), the field emission display (FED), the plasma display panel (PDP) PDP), and electrophoresis (EPD) display devices.

1 shows a liquid crystal display device according to the present invention.

1, a liquid crystal display device according to the present invention includes a display panel 10, a source drive IC (Integrated Circuit) 13, a gate drive IC (Integrated Circuit) 14, a timing controller (TCON) 12).

The liquid crystal display of the present invention can be implemented in all known liquid crystal modes such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Further, the liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, a reflective liquid crystal display device, and the like.

The display panel 10 includes an upper substrate and a lower substrate opposed to each other with the liquid crystal cell Clc therebetween. In the display panel 10, the image data is displayed in a pixel array area in which pixels are arranged in a matrix form. The pixel array includes a TFT array formed on the lower substrate and a color filter array formed on the upper substrate.

A common voltage Vcom is supplied from a power supply circuit (not shown) to the common voltage lines COML. The horizontal wirings include horizontal gate lines GL that receive gate pulses through vertical gate lines VGL. The horizontal gate lines GL are connected in a 1: 1 relationship with the vertical gate lines VGL to receive gate pulses through the vertical gate lines VGL.

In the TFT array, TFTs (Thin Film Transistors) are formed at intersections of the data lines DL and the horizontal gate lines HG. The TFT supplies the data voltage from the data line DL to the pixel electrode 1 of the liquid crystal cell Clc in response to the gate pulse from the horizontal gate line HG. Each of the liquid crystal cells Clc is driven by the voltage difference between the pixel electrode 1 for charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. The common voltage Vcom is applied to the common electrode of all the pixels through the common voltage lines COML. A storage capacitor Cst for holding the voltage of the liquid crystal cell for one frame period is connected to the liquid crystal cell Clc.

The timing controller 12 transfers the digital video data of the input image received from the host system 7 to the source drive IC 13. [ The timing controller 12 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock CLK from the host system 7. These timing signals are synchronized with the digital video data of the input image. The timing controller 12 controls a source timing control signal for controlling the operation timing of the source drive IC 14 and an operation timing of the gate drive IC 13 using the timing signals Vsync, Hsync, DE, and CLK And generates a gate timing control signal.

The host system 7 may be implemented as any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, have. The host system 14 converts the digital video data RGB of the input image into a format suitable for the display panel 10. The host system 14 transmits timing signals (Vsync, Hsync, DE, MCLK) to the timing controller 12 together with the digital video data of the input video.

The source driver IC 14 samples the digital video data of the input image under the control of the timing controller 12, and latches the digital video data to convert the digital video data into data of a parallel data structure. The source driver IC 14 generates a data voltage by converting the digital video data into an analog gamma compensation voltage using a digital-to-analog converter (ADC) under the control of the timing controller 12, To the data lines DL.

The gate drive IC 13 sequentially supplies gate pulses (or scan pulses) synchronized with the data voltage under the control of the timing controller 12. [ The gate drive IC 13 is formed on one side of the display panel 10 and supplies gate pulses to the first to m-th horizontal gate lines HG1 to HGm.

At this time, the first to m-th horizontal gate lines HG1 to HGm are branched from the first to m-th vertical gate lines, respectively. Embodiments of a horizontal gate line and a vertical gate line will be described below.

2 is a view showing an example of connection between a vertical gate line and a horizontal gate line according to the first embodiment.

One horizontal gate line is connected to pixels arranged in one horizontal line. For example, the first horizontal gate line HG1 is connected to n pixels arranged in the first horizontal line, and the mth horizontal gate line HG is connected to n pixels arranged in the mth horizontal line.

The first vertical gate line VG1 is branched at the first horizontal gate line HG and connects the first input node n1 and the first connection node n2 of the first horizontal gate line HG1. The input node n1 is formed in the non-display area Area2 where the first horizontal gate line HG1 receives the gate pulse through the gate drive IC 13. [ The connection node n2 is located inside the display area (Area1).

The first vertical gate line VG1 is branched at the first input node n1, bypasses the non-display area Area2, and is connected to the first connection node n1. That is, the first vertical gate line VG1 may include a bypass region a located in the non-display region Area2 and a vertical region b located in the display region Area1. The bypass region a of the first vertical gate line VG1 may be formed to have a width wider than the width of the first horizontal gate line HG1. As described above, the first vertical gate line VG1 is formed to have a larger width in at least some of the regions, so that the resistance value is lower than that of the first horizontal gate line HG1. Accordingly, in the process of simultaneously supplying the first input signal from the first input node n1 to the first vertical gate line VG1 and the first horizontal gate line HG1, the gate pulse provided through the first vertical gate line VG is The RC delay is maintained to be lower than the gate pulse provided through one horizontal gate line HG. Accordingly, the delay phenomenon of the gate pulse provided through the first horizontal gate line HG can be improved.

The vertical region (b) of the first vertical gate line (VG1) may be formed in a boundary region between red, green and blue sub-pixels to prevent the aperture ratio of the pixel from being lowered.

The second to m-th vertical gate lines VG2 to VGm correspond one-to-one to the second to m-th horizontal gate lines VG2 to VGm, respectively. Accordingly, the second to m-th vertical gate lines VG2 to VGm improve the delay of the gate pulse provided through the second to m-th horizontal gate lines VG2 to VGm, respectively.

In the first to m-th vertical gate lines VG1 to VGk according to the first embodiment, the half vertical gate lines are bent in the direction of the connection node from the top of the display area (Area1), and the other half of the vertical gate lines And is bent in the direction of the connection node from the bottom of the display area (Area 1). For example, the first to kth vertical gate lines VG1 to VGk are bent in the upper direction of the display area Area1, and the (k + 1) to mth vertical gate lines VG1 to VG ) Are bent in the lower direction of the display area (Area 1).

And the vertical regions of the first to k-th vertical gate lines (VG1 to VGk) are formed in the boundary region of different pixels. For example, the second vertical gate line VG2 may be formed to correspond to the pixels of the second column, and may be formed between the green sub-pixel and the blue sub-pixel. And the k-th vertical gate line VGk may be formed so as to correspond to a pixel in the n-th column.

In addition, the vertical regions of the (K + 1) th to (m + m) -th vertical gate lines VG (k + 1) are formed in the boundary region of different pixels.

The vertical gate lines bent in the display area Area1 in the other direction among the first to mth vertical gate lines VG1 to VGm may be formed on the same line. For example, the first vertical gate line (VG) and the m vertical gate line (VG) may be formed in a vertical line in which pixels of the first column are formed. Likewise, the k-th vertical gate line VG and the (k + 1) -th vertical gate line VG may be formed in the vertical line in which the pixels in the n-th column are formed.

As a result, when it is assumed that the number of horizontal lines is m and the vertical gate lines are formed one-to-one on each horizontal gate line, m / 2 minimum vertical lines capable of forming all the vertical gate lines in the display area (Area 1) . At this time, as mentioned above, the vertical gate lines may be formed at the interface of each sub-pixel. Two or more vertical gate lines may be formed at an interface between adjacent sub-pixels, but one vertical gate line may be formed at an interface between adjacent sub-pixels in order to prevent degradation of display quality. As a result, a vertical line capable of forming a vertical gate line is 3 x n, and a vertical gate line can be formed by selecting m / 2 vertical lines in 3 n vertical lines. At this time, the vertical gate line may be formed by selecting the vertical lines near the n-th column as the center. This is because the more distant the pixels are from the gate drive IC 13, the more serious the delay phenomenon and the vertical gate lines can be formed around the vertical lines close to the n-th column in order to compensate the delay phenomenon.

FIG. 3 is a view showing a planar array structure of a first pixel in which the first connection node n1 is formed, and FIG. 4 is a cross-sectional view taken along line I-I 'of FIG.

3 and 4, the first vertical gate line VG1 may be formed in a vertical line between the green sub-pixel G and the blue sub-pixel B of the first pixel P1. At this time, the vertical line is an interface between the sub-pixels, and the vertical gate line (VG) can be formed.

The first vertical gate line VG1 is connected to the first horizontal gate line HG1 at the first connection node n1.

The first connection node n1 is formed by connecting the first horizontal gate line HG and the first vertical gate line VG using a contact hole C_hole. The first connection node n1 has a structure in which a contact hole C_hole is formed in an insulating film covering the first horizontal gate line HG and a first vertical gate line VG is formed to fill the contact hole C_hole .

FIG. 5 is a view showing a liquid crystal display according to a second embodiment, and FIG. 6 is a diagram showing a connection relationship between a horizontal gate line and a vertical gate line according to the second embodiment. The same reference numerals are used for the components having the same functions as those of the above-described embodiment in the second embodiment, and a detailed description thereof will be omitted.

5 and 6, the liquid crystal display according to the second embodiment includes a display panel PNL, a source drive IC (Integrated Circuit) 14, first and second gate drive ICs (integrated circuits) 13a 13b, a timing controller (TCON) 12, and the like.

 The first and second source driver ICs 14 provide gate pulses to the first to sixth horizontal gate lines HG1 to HG6 on both sides of the display panel 10, respectively.

One horizontal gate line is connected to pixels arranged in one horizontal line. For example, the first horizontal gate line HG1 is connected to the n pixels arranged in the first horizontal line, and the sixth horizontal gate line HG6 is connected to the n pixels arranged in the sixth horizontal line.

Two horizontal gate lines are connected to one horizontal gate line. For example, the first horizontal gate line HG1 is connected to the first vertical gate line VG1 and the second vertical gate line VG2. The first vertical gate line VG1 branches at the first input node n1 where the first source drive IC 14 is located and is connected to the first connection node n1 of the first horizontal gate line HG1. The second vertical gate line VG2 branches at the second input node n2 where the second source drive IC 14 is located and is connected to the second connection node n2 of the first horizontal gate line HG1.

As such, since the second embodiment provides the gate pulses at both sides of the display panel 10, the delay of the gate pulse can be reduced. In particular, since the second embodiment branches the gate pulse using two vertical gate lines per one horizontal line, the delay of the gate pulse can be further reduced.

The third vertical gate line VG3 connects the first and second vertical gate lines VG1 and VG2 to one connection node. That is, the pixels P3 and P4 located in the center column are simultaneously supplied with gate pulses output from the first and second source drive ICs 14 through the third vertical gate line VG3.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display panel 12: timing controller
13: Gate drive IC 14: Source drive IC

Claims (7)

A horizontal gate line connected to pixels arranged in a horizontal line;
A vertical gate line connecting an input node and a connection node of the horizontal gate line; And
And a gate drive IC for supplying a gate pulse to the pixels through the horizontal gate line and the vertical gate line,
Wherein the input node is located in a non-display area, and the connection node is located in a display area.
The method according to claim 1,
Wherein the vertical gate line bypasses the non-display region at the input node, and is vertically bent at the upper side or the lower side of the display region.
3. The method of claim 2,
Wherein the vertical gate line has at least a portion formed to be wider than a width of the horizontal gate line.
3. The method of claim 2,
Wherein at least a portion of the vertical gate line is made of a material having a resistivity lower than a resistivity of the horizontal gate line.
The method according to claim 1,
The gate drive IC includes a first gate drive IC formed on one side of the display panel and a second gate drive IC formed on the other side of the display panel,
In one horizontal gate line,
A first vertical gate line for branching the gate pulse output from the first gate drive IC; And
And a second vertical gate line for dividing the gate pulse output from the second gate drive IC.
6. The method of claim 5,
Wherein the first and second vertical gate lines are connected to one connection node located in the display region.
The method according to claim 1,
Wherein the pixel includes red, green, and blue sub-pixels, and the vertical gate line is connected to one sub-pixel.

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