KR20160046981A - Display panel - Google Patents

Abstract

The present invention relates to a display panel in which white sub-pixels adapted to improve transmittance are added. A display panel according to an embodiment of the present invention comprises: k^th and (k+1)^th sub-pixels which are disposed on a j^th vertical line; and (k+2)^th and (k+3)^th sub-pixels which are disposed on a (j+1)^th vertical line. The k^th to (k+3)^th sub-pixels share an m^th data line.

Description

Display panel {DISPLAY PANEL}

The present invention relates to a display panel.

2. Description of the Related Art [0002] With the development of information electronic devices for realizing high-resolution and high-quality images such as portable telephones (portable phones), notebooks, computers, and HDTVs, flat panel displays Devices are increasingly in demand. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) have been actively studied. However, And realization of a large area screen, a liquid crystal display (LCD) is in the spotlight at present.

The liquid crystal display implements an image by adjusting the light transmittance of the liquid crystal cell on the liquid crystal panel in accordance with the gray level value of the data signal. However, when a direct current voltage is applied to the liquid crystal cell arranged in the liquid crystal panel for a long time, the light transmission characteristic of the liquid crystal cell deteriorates. That is, a DC fixing phenomenon occurs, which causes a residual image on an image displayed on the liquid crystal panel.

In order to prevent the aforementioned direct current fixing, an inversion type liquid crystal display device has been proposed in which data signals supplied to the liquid crystal cells of the liquid crystal panel are inverted based on the common voltage Vcom. In version scheme is classified into a frame inversion, a line inversion, a column inversion, and a dot inversion.

Among them, the dot inversion method implements a picture of good image quality compared to the frame inversion method and the line inversion method. However, when the liquid crystal display device is driven in the dot-inversion mode, the image quality of the liquid crystal display device may be deteriorated depending on the correlation between the polarity of the data voltage charged in the liquid crystal cells and the displayed image pattern. This is because the polarities of the data voltages charged in the liquid crystal cells are not balanced between the positive polarity and the negative polarity according to the data voltage charged in the liquid crystal cell, and one polarity becomes dominant polarity, and thereby the common voltage Vcom Because the ripple is generated in the semiconductor device. The common voltage ripple Vcom ripples the reference potential of the liquid crystal cells to shift the common voltage to the dominant polarity so that the observer can see dim or smear in the image displayed on the liquid crystal display, You can feel the phenomenon. In addition, in order to improve the polarity nonuniformity, there is a problem that the power consumption increases when the inversion method is a version method with a vertical 4 dot.

Embodiments of the present invention can provide a display panel to which white sub-pixels for improving transmittance are added.

The embodiment according to the present invention may also provide a display panel for reducing power consumption.

The embodiment according to the present invention may also provide a display panel with improved polarity shift.

The embodiment according to the present invention may also provide a display panel capable of preventing image defects due to polarity deviation.

A display panel according to an embodiment of the present invention includes a first sub pixel arranged in a sub pixel area defined by intersection of a plurality of gate lines and a plurality of data lines, Pixel, a second sub-pixel, a second sub-pixel, a second sub-pixel, a second sub-pixel, a third sub-pixel, a third sub- Th sub-pixel, the fourth sub-pixel, and the third sub-pixel, the fourth sub-pixel, the first sub-pixel, and the second sub- The second sub-pixel arranged in the intersection area of the (i + 1) -th horizontal line and the j-th vertical line in the horizontal line, the (i + Horizontal line and j + 1 The fourth sub-pixel arranged in the intersection area of the (i + 3) -th horizontal line and the (j + 1) -th vertical line in the third sub-pixel and the horizontal line intersecting with the vertical line, And a display panel sharing one of the data lines.

In addition, in the display panel according to the embodiment of the present invention, at least one data signal among the data signals of the first to fourth data lines has a negative polarity, the polarity of the remaining data signals is positive, And the polarity of the data signals of the eighth to the eighth data lines is opposite to the polarity of the data signals of the first to fourth data lines.

In the display panel according to the embodiment of the present invention, the polarity of the data signal includes a display panel which is inverted for each frame.

In the display panel according to the embodiment of the present invention, the first to fourth colors are red, green, blue and white.

In the display panel according to an embodiment of the present invention, the sub-pixel region includes a sub-pixel region for a thin film transistor, and the sub-pixel region for the thin film transistor includes a thin film transistor connected to a pixel electrode included in an adjacent sub- And a display panel.

In the display panel according to the embodiment of the present invention, the sub-pixel region for the thin film transistor includes a display panel including thin film transistors connected to each of three adjacent sub-pixels.

In the display panel according to the embodiment of the present invention, the sub-pixel region for the thin film transistor includes a display panel in which white sub-pixels are arranged.

Further, in the display panel according to the embodiment of the present invention, the first thin film transistor connected to the pixel electrode included in the left or right sub pixel region of the thin film transistor sub pixel region, A second thin film transistor connected to the pixel electrode included in the lower sub pixel area of the sub pixel area for the thin film transistor and a third thin film transistor connected to the pixel electrode included in the lower diagonal pixel area of the thin film transistor sub pixel area And a display panel.

The embodiment according to the present invention can provide a display panel capable of increasing transmittance and luminance by adding white sub-pixels, reducing power consumption, improving polarity shift, and improving the image level.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention. FIG.
2 is a diagram showing a pixel structure of a display panel according to a first embodiment of the present invention;
FIG. 3 is a view showing a structure of sub-pixels of a display panel according to the first embodiment of the present invention and their colors. FIG.
FIG. 4 is a diagram illustrating the structure of sub-pixels of a display panel according to the first embodiment of the present invention and the polarities of data signals applied to the sub-pixels and colors thereof.
5 is a diagram showing polarities of red sub-pixels according to an embodiment.
6 illustrates polarity of a green sub-pixel according to an embodiment.
7 is a diagram showing polarities of a blue sub-pixel according to an embodiment.
8 is a diagram showing a pixel structure of a display panel according to a second embodiment of the present invention.
9 is a view showing a structure of sub-pixels of a display panel according to a second embodiment of the present invention and the colors thereof.

Hereinafter, the display panel according to the embodiment of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification. The dimensions and relative sizes of the layers and regions in the figures may be exaggerated for clarity of illustration.

The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. &Quot; comprise "and / or" comprising ", as used in the specification, means that the presence of stated elements, Or additions.

1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a display panel 100, a timing controller 200, a data driving circuit 300, and a gate driving circuit 400.

The display panel 100 includes liquid crystal molecules disposed between two glass substrates. In this display panel 100, m × n (m, n is a positive integer) sub-pixel regions are defined in a matrix form by the intersection structure of the data lines D1 to Dm and the gate lines G1 to Gn And liquid crystal cells Clc are arranged in each of the sub pixel regions.

The sub pixel region defined by the intersection of the plurality of gate lines and the plurality of data lines includes a first sub pixel displaying a first color, a second sub pixel displaying a second color, a third sub pixel displaying a third color Pixel and a fourth sub-pixel for displaying a fourth color.

The lower glass substrate of the display panel 100 is connected to m data lines D1 to Dm, n gate lines G1 to Gn, TFT (Thin Film Transistor, thin film transistor, T) A pixel electrode 110 of the liquid crystal cell Clc, and a storage capacitor Cst are formed.

On the upper glass substrate of the display panel 100, a black matrix, a color filter, and a common electrode 120 are formed. The common electrode 120 is formed on the upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 120 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) It can be formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system.

An alignment film may be formed on the upper glass substrate and the lower glass substrate of the display panel 100 to attach a polarizing plate orthogonal to the optical axis and to set the pretilt angle of the liquid crystal on the inner surface in contact with the liquid crystal.

The data driving circuit 300 may include a plurality of data driver ICs. The data driving circuit 300 latches the digital video data RGBW under the control of the timing controller 200 and converts the digital video data into an analog positive / negative gamma compensation voltage to generate a positive / negative data voltage do. Each of the plurality of data driver ICs may provide a data signal to each of a plurality of grouped data lines D1 to Dm. Therefore, the number of the data driver integrated circuits may vary according to the degree of grouping of the data driver integrated circuits according to the resolution of the liquid crystal display device.

The data driving circuit 300 supplies a data voltage to the data lines D1 to Dm during each horizontal period in which the source output enable signal SOE is held in the low logic state.

The data driver integrated circuits may be mounted on a TCP (Tape Carrier Package) and bonded to a lower glass substrate of the display panel 100 by a TAB (Tape Automated Bonding) process.

The gate driving circuit 400 includes a level shifter for converting an output signal of the shift register and a shift register into a swing width suitable for driving the TFT of the liquid crystal cell and an output buffer connected between the level shifter and the gate lines G1 to Gn . The gate driving circuit 400 sequentially supplies gate signals having a pulse width of approximately one horizontal period to the gate lines G1 to Gn under the control of the timing controller 200. [ The gate driving circuit 400 is mounted on the TCP and bonded to the lower glass substrate of the display panel 100 by a TAB process or is directly connected to the lower glass substrate simultaneously with the pixel array by a GIP .

The timing controller 200 converts digital video data (RGB) RGBW video data input from a system board (not shown), rearranges the digital video data into RGBW video data, and supplies the rearranged data to the data driving circuit 300. The timing controller 200 receives a timing signal such as a vertical / horizontal synchronizing signal (Vsync, Hsync), a data enable signal and a clock signal (CLK) from the system board and supplies the timing signal to the data driving circuit 300 and the gate driving circuit (GCS, DCS) for controlling the operation timing of the memory device (400).

The gate timing control signal GCS for controlling the gate driving circuit 400 includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal Gate Output Enable, GOE) and the like. The gate start pulse (GSP) is generated once at the same time as the start of the frame period for one frame period to generate the first gate pulse. The gate shift clock GSC shifts the gate start pulse GSP with a clock signal commonly inputted to a plurality of stages constituting the shift register. The gate output enable signal GOE controls the output of the gate drive circuit 400. [

A source start pulse (SSP), a source sampling clock (SSC), a vertical polarity control signal (Polarity), and a polarity control signal (POL) are used as a data timing control signal DCS for controlling the data driving circuit 300 A source output enable signal (SOE), and the like. The source start pulse SSP is a signal for controlling the data sampling circuit start timing of the data driving circuit 300 and the source sampling clock SSC is a signal for controlling the rising or falling edge of each IC And is a clock signal for controlling sampling timing of data. The vertical polarity control signal POL controls the vertical polarity inversion timing of the data voltage output from the data driving circuit 300 for each of the gate lines G1 to Gn and the source output enable signal SOE And controls the output timing of the data driving circuit 300.

The data driving circuit 300 latches RGBW DATA input under the control of the timing controller 200. And converts the vertical polarity control signal Pol to an analog positive or negative gamma compensation voltage GAMMA and outputs the same to the display panel 100 through all the data lines D1 to Dm.

Specifically, the data driving circuit 300 can set the polarity of the data voltage output from the data driving circuit 300 to be positive when the vertical polarity control signal POL provided from the timing controller 200 is high logic , And the polarity of the data voltage output from the data driving circuit 300 at the time of the low logic can be negative.

The polarity can be inverted in units of vertical lines by the vertical polarity control signal POL.

≪ Display panel according to the first embodiment &

2 is a diagram illustrating a pixel structure of a display panel according to a first embodiment of the present invention.

Herein, i denotes an i-th horizontal line, j denotes a j-th vertical line, and (i, j) denotes a sub-pixel region or sub-pixel corresponding to an i-th horizontal line and a j- It can mean. The horizontal line is defined as an area between two adjacent gate lines, and the vertical line is defined as an area between two adjacent data lines. I and j are natural numbers.

2, a display panel 100 according to the first embodiment of the present invention includes a plurality of data lines m to m9 and a plurality of gate lines n to n5), and may include a plurality of sub-pixel regions 101 defined by intersecting data lines and gate lines.

And k + 2 and k + 3th sub-pixels arranged on the (k + 1) th vertical line and k + kth subpixel arranged on the jth vertical line, And the (+3) th sub-pixel may share the (m + 1) th data line. Th sub-pixel and the next sub-pixel of the (k) th to (k + 3) th sub-pixels may have a symmetric structure with the (k) th to (k + 3) th sub-pixels. Further, the sub-pixels arranged on one horizontal line can share one gate line.

(I + 1) th sub-pixel (k + 1), (i + 2, j + 1) (k + 2) and (i + 3, j + 1) th sub-pixel (k + 3). The liquid crystal cells included in each of the sub-pixels may be connected to a data line by a thin film transistor (T). (I + 4, j + 1) th sub-pixel, (i + 5, j) The liquid crystal cell of the pixel can be connected. Accordingly, the sub-pixel sharing the (m + 1) th data line may have a symmetrical structure for every four sub-pixels in the vertical direction, and may be arranged in a zigzag form for each of the two sub-pixels in the vertical direction. (I + 3, j + 2) th sub-pixel, (i + 1, j + Th sub-pixel, the (i + 5, j + 1) th sub-pixel, the (i + 6, j + 2) th sub-pixel and (i + 7, j + 2) th sub-pixel may be connected and may be repeated in the vertical direction. (I + 2, j + 3) th sub-pixel, (i + 3, j + 3) th sub- Th sub-pixel, the (i + 5, j + 2) th sub-pixel, the (i + 6, j + 3) sub-pixel and (i + 7, j + 3) th sub-pixel may be connected and may be repeated in the vertical direction. In addition, the remaining sub-pixels may be repeated in the vertical and horizontal directions as in the arrangement structure of the sub-pixels described above.

FIG. 3 is a view showing a structure of sub-pixels of a display panel according to the first embodiment of the present invention and their colors.

3, the display panel according to the first embodiment of the present invention is arranged in the order of the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel in the odd-numbered horizontal line, Pixel may be arranged in the order of the third sub-pixel, the fourth sub-pixel, the first sub-pixel and the second sub-pixel in a horizontal line, the first sub-pixel displays a first color, Red), the second sub-pixel may display a second color, the second color may be green, the third sub-pixel may display a third color, and the third The color may be blue, the fourth sub-pixel may display a fourth color, and the fourth color may be white.

green, blue and white subpixels sequentially arranged in an area corresponding to the jth vertical line and the j + 1 th to j + 3th vertical lines and the i th horizontal line, White, red and green sub-pixels sequentially arranged in an area corresponding to the (i + 1) -th horizontal line and the (i + 1) -th horizontal line. The kth to (k + 3) th sub-pixels may be red, green, blue, and white sub-pixels.

More specifically, red, green, blue and white sub-pixels are sequentially arranged on the i-th horizontal line, and red, green, blue and white sub-pixels are repeatedly arranged. That is, subpixels of (i, j), (i, j + 1), (i, j + 2), (i, j + 3) may be red, green, the subpixels of (i, j + 4), (i, j + 5), have. On the (i + 1) th horizontal line, blue, white, red and green sub-pixels are sequentially arranged, and blue, white, red and green sub-pixels are repeatedly arranged. That is, the sub-pixels of (i + 1, j), (i + 1, j + 1), (I + 1, j + 4), (i + 1, j + 5), The pixels may be blue, white, red and green sub-pixels in order. Further, red, green, blue and white sub-pixels are sequentially arranged on the (i + 2) th horizontal line, and red, green, blue and white sub-pixels are repeatedly arranged. That is, the sub-pixels of (i + 2, j), (i + 2, j + 1), (I + 2, j + 7), (i + 2, j + 4) The pixels may be red, green, blue and white sub-pixels in order. On the (i + 3) th horizontal line, blue, white, red and green sub-pixels are sequentially arranged, and blue, white, red and green sub-pixels are repeatedly arranged. That is, the sub-pixels of (i + 3, j), (i + 3, j + 1), (I + 3, j + 4), (i + 3, j + 5), The pixels may be blue, white, red and green sub-pixels in order. In addition, the remaining sub-pixels may be repeated in the vertical and horizontal directions as in the arrangement structure of the sub-pixels described above.

Since the display panel 100 according to the embodiment includes the white (W) sub-pixels, the brightness can be raised and the aperture ratio can be improved. Further, the red, green, blue and white sub-pixels are arranged in the zigzag form in units of two sub-pixels in the horizontal direction and the odd-numbered horizontal direction, respectively, thereby preventing the phenomenon that the entire luminance is increased and the line is visually recognized .

4 is a diagram illustrating the structure of sub-pixels of a display panel according to the first embodiment of the present invention and the polarities of data signals applied to the sub-pixels and the colors.

4, the plurality of data lines includes a plurality of data line groups, each of the plurality of data line groups includes first to eighth data lines, and the data signals of the first to fourth data lines And the polarity of the data signals of the fifth to eighth data lines may be different from the polarity of the data signals of the first to fourth data lines, Can be countered. For example, the polarities of the data signals of the first to eighth data lines may be +, -, +, -, +, +, - or +, +, -, +, -, - +. Specifically, the polarities of the data signals of the m-th data line and the data lines of the (m + 1) th to (m + 7) th data lines are +, -, +, -, +, + +, -, -, +. Also, the polarities of the data signals of the first to eighth data lines may be -, -, +, -, +, or +, +, -, +, -, -, +, -. Specifically, the polarities of the data signals of the m-th data line and the (m + 1) th to (m + 7) -th data lines of the next time are -, -, +, -, +, +, - -, -, +, -. Also, the polarities of the data signals of the first to eighth data lines may be -, +, -, +, -, +, - or +, -, +, -, -, +, -, +. Specifically, the polarities of the data signals of the m-th data line and the m + 1-th to (m + 7) -th data lines are respectively -, +, -, +, +, - -, +, -, +. Also, the polarities of the data signals of the first to eighth data lines may be +, -, +, +, -, -, -, +, -, -, +, -, +, +. Specifically, the polarities of the data signals of the m-th data line and the m + 1-th to (m + 7) -th data lines are +, -, +, +, -, +, - +, -, +, +. And the polarities of the data signals applied to the mth to (m + 7) th data lines may be reversed every frame. As described above, it is possible to prevent the image quality defect due to the polarization of the liquid crystal through the version of the frame in which the polarity of the data signal is inverted every frame.

For example, when the polarities of the data signals of the first to eighth data lines are -, -, +, -, +, -, + or +, +, -, +, -, -, + To be more specific, the polarity of the data signal applied to the m-th data line may have positive polarity, and the polarity of the data signal applied to the (m + 1) -th data line may have negative polarity , the polarity of the data signal applied to the (m + 2) th data line may be negative polarity, and the polarity of the data signal applied to the (m + 3) th data line may have positive polarity. The polarity of the data signal applied to the (m + 4) th to (m + 7) th data lines is opposite to the polarity of the data signal applied to the (m + The polarity of the data signal applied to the (m + 5) th data line may be positive, and the polarity of the data signal applied to the (m + + Polarity, and the polarity of the data signal applied to the (m + 7) th data line may be negative polarity. As described above, a positive or negative polarity data signal in which the polarity is maintained for one frame is supplied to any data line, and the polarity can be inverted in the next frame.

According to the polarity of the data signal, the data signal of the same polarity can be supplied to the sub-pixels sharing one data line.

By supplying the data signal with the polarity maintained during one frame as described above, the power consumption is reduced compared to the inversion mode.

FIG. 5 is a diagram showing the polarity of the red sub-pixel according to the embodiment, FIG. 6 is a view showing the polarity of the green sub-pixel according to the embodiment, FIG. 7 is a graph showing the polarity of the blue sub- Fig.

Referring to FIG. 5, the pixel electrode 110 included in the red sub-pixel 101 may alternately have a positive polarity and a negative polarity in a vertical direction indicated by a dotted line without polarity shift. This is because two sub-pixels sharing one data line are arranged in a zigzag form in the vertical direction, so that the same effect as the two-dot vertically-oriented version is obtained, thereby preventing the polarity from being shifted The image level can be improved. Also, referring to FIG. 6, the pixel electrode 110 included in the green sub-pixel 101 may alternately have a positive polarity and a negative polarity in a vertical direction indicated by a dotted line without a polarity shift. As a result, the polarity of the polarity can be prevented, thereby improving the flicker phenomenon and vertical line dimming. Also, referring to FIG. 7, the pixel electrode 110 included in the blue sub-pixel 101 may alternately have a positive polarity and a negative polarity in a vertical direction indicated by a dotted line without shifting the polarity. As described above, since the R, G, B, and W colors have a version of 1 dot based on each color, it is possible to prevent the polarity shift phenomenon and improve the image level.

On the other hand, in the polarities of the sub-pixels according to FIGS. 5 to 7, the polarities of the data signals on the first to eighth data lines are +, -, -, +, -, +, and - The polarities of the data signals are not limited to -, -, +, -, +, +, -, +, -, +, -, + , +, -, +, -, -, and the same effect can be obtained.

<Display panel according to the second embodiment>

8 is a diagram illustrating a pixel structure of a display panel according to a second embodiment of the present invention.

Referring to FIG. 8, the arrangement relationship of the sub-pixels according to the second embodiment can be described in the same manner as in the first embodiment. However, the thin film transistor T which responds to the gate signal on the gate lines n through n + 4 and provides the data signal on the data lines m through m + 7 to the pixel electrode 110 of the sub- The sub-pixel region 101 of FIG. That is, the sub pixel region including the thin film transistor connected to the adjacent sub pixel can be defined as the sub pixel region 102 for the thin film transistor.

The thin film transistor sub pixel region 102 includes thin film transistors T 1, T 2 and T 3 connected to three adjacent sub pixels and a thin film transistor T connected to sub pixels arranged in the sub pixel region 102 for the thin film transistor. You can include both. That is, the first thin film transistor (T1) connected to the pixel electrodes included in the left or right sub pixel region of the thin film transistor sub pixel region (102) and the first thin film transistor A second thin film transistor T2 connected to the pixel electrode included in the lower sub pixel region of the pixel region 102 and a pixel electrode included in the lower diagonal sub pixel region of the thin film transistor sub pixel region 102, And a third thin film transistor T3 connected thereto. Specifically, a thin film transistor T1 connected to a (j + 1) -th vertical line and a sub-pixel corresponding to the (i + 1) -th horizontal line is connected to the sub pixel region 102 for the (i + 1, j + 2) A thin film transistor T2 connected to the sub pixel corresponding to the +2th vertical line and the (i + 2) th horizontal line and the thin film transistor T2 connected to the (j + 3) th vertical line and the sub pixel corresponding to the (i + T3 may be disposed. A thin film transistor T1 connected to a (j + 3) -th vertical line and a sub-pixel corresponding to the i-th horizontal line in the sub pixel region for the (i, j + 4) Th thin film transistor T2 connected to the sub-pixel corresponding to the (i + 1) th horizontal line and the thin film transistor T3 connected to the (j + 3) th vertical line and the sub-pixel corresponding to the (i + 1) th horizontal line. A thin film transistor T1 connected to the (j + 5) -th vertical line and the (i + 2) -th horizontal line in the sub pixel region for the (i + 2, j + 4) And the thin film transistor T3 connected to the sub pixel corresponding to the (i + 3) th horizontal line and the (j + 5) th vertical line and the (j + . A thin film transistor T1 connected to the (j + 7) -th vertical line and the (i + 3) -th horizontal line in the sub pixel region for the (i + 3, j + 6) And a thin film transistor T3 connected to the sub pixel corresponding to the (i + 4) th horizontal line and the (j + 5) th vertical line and the thin film transistor T3 connected to the .

In this manner, the sub-pixel region for the thin film transistor corresponds to the jth vertical line and the i-th horizontal line, and the sub-pixel region for the thin film transistor corresponds to the (j-1) th or Th thin film transistor connected to a sub-pixel, a thin film transistor connected to the j th vertical line and a sub-pixel corresponding to an (i + 1) th horizontal line, and a thin film transistor connected to the (j + 1) th or The thin film transistors connected to the corresponding sub-pixels are arranged so as to have a zigzag structure in units of two sub-pixels in the vertical direction, so that the vertical two-dot version and the in-color inversion effect can be displayed.

9 is a view showing a structure of a sub-pixel of a display panel according to a second embodiment of the present invention, and a color thereof.

9, the display panel according to the second exemplary embodiment of the present invention includes red, green, and blue pixels sequentially arranged in an area corresponding to the jth vertical line, the j + 1 th to j + 3th vertical lines, White, red, and green subpixels sequentially including blue and white subpixels and corresponding to the jth to (j + 3) th vertical lines and the (i + 1) th horizontal line. The kth to (k + 3) th sub-pixels may be red, green, blue, and white sub-pixels.

In addition, white sub-pixels may be arranged in the sub-pixel region 102 for the thin film transistor.

As described above, the white sub-pixel is formed in the thin-film transistor sub-pixel region 102 so that the size of the pixel electrode included in the white sub-pixel can be smaller than the size of the pixel electrode of the other color. This structure can be referred to as an asymmetric pixel electrode structure.

The display panel 100 according to the embodiment of the present invention can increase the luminance by including the white sub-pixel and reduce the power consumption due to the increase in luminance. Further, the size of the pixel electrode included in the red, blue, and green sub-pixels can be increased by arranging the thin film transistors for all the color sub-pixels adjacent to the sub-pixel region in which the white sub-pixel is formed. Accordingly, the color reproduction rate can be increased. This asymmetric pixel electrode structure has a power consumption reduction effect and a color recall ratio increase effect as the luminance increases.

It is possible to supply a data signal in which polarity is maintained for one frame to each data line in the manner described in the first embodiment, and it is possible to bring about a version method with two dots and one dot per color depending on the arrangement relationship of the sub- Therefore, it is possible to further increase the power consumption reduction effect and the image level improvement effect.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100 display panel
101 sub pixel area
102 thin film transistor sub pixel region
200 timing controller
300 data drive circuit
400 gate drive circuit
110 pixel electrode
120 common electrode

Claims (8)

A first sub-pixel for displaying a first color, a second sub-pixel for displaying a second color, a second sub-pixel for displaying a second color, and a second sub- 3 sub-pixels and a fourth sub-pixel for displaying a fourth color,
The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel in the odd-numbered horizontal line,
The third sub-pixel, the fourth sub-pixel, the first sub-pixel, and the second sub-pixel in the odd-numbered horizontal line,
The first sub-pixel arranged in an intersection area of i (i is a natural number) horizontal line and j (j is a natural number) vertical line in a horizontal line, an i + 1th horizontal line and a j- And the third sub-pixel and the horizontal line arranged at intersections of the i + 2th horizontal line and the j + 1th vertical line among the horizontal lines, i + 3 Th horizontal line and the (j + 1) th vertical line share one data line among the plurality of data lines. The method according to claim 1,
The plurality of data lines including a plurality of data line groups,
Wherein each of the plurality of data line groups includes first to eighth data lines,
The polarity of at least one of the data signals of the first to fourth data lines is negative and the polarity of the remaining data signals is positive and the polarity of the data signals of the fifth to eighth data lines is And the polarity of the data signals of the first to fourth data lines. 3. The method of claim 2,
And the polarity of the data signal is inverted for each frame. The method of claim 3,
Wherein the first to fourth colors are red, green, blue, and white colors. The method according to claim 1,
Wherein the sub pixel region includes a sub pixel region for a thin film transistor,
Wherein the thin film transistor sub pixel region includes a thin film transistor connected to a pixel electrode included in adjacent sub pixels. 6. The method of claim 5,
Wherein the sub pixel region for the thin film transistor includes a thin film transistor connected to each of three adjacent sub pixels. The method according to claim 6,
And a white sub-pixel is disposed in the sub-pixel region for the thin film transistor. 8. The method of claim 7,
The sub-pixel region for the thin film transistor includes a first thin film transistor connected to the pixel electrode included in the left or right sub pixel region of the thin film transistor sub pixel region and a second thin film transistor included in the sub pixel region below the thin film transistor sub pixel region And a third thin film transistor connected to the pixel electrode included in the lower diagonal sub pixel region of the sub pixel region for the thin film transistor.

Images