KR20100128019A - Image display device and driving method of thereof - Google Patents

Abstract

PURPOSE: An image display device and a driving method of thereof are provided to increase the luminance of a 3D image by increasing the time of opening a shutter. CONSTITUTION: An LCD panel embodies 3D image including a left eye image and a right eye image. A data driving circuit applies data voltage for 2D image or 3D image to data lines. A gate driving circuit supplies a gate pulse to the gate lines. A timing controller controls a driving circuit by a first frame frequency in implementing 2D image. The timing controller controls the driving circuit by a second frame frequency in implementing 3D image. The second frequency is higher than the first frequency. A shutter glass opens a left eye shutter and a right eye shutter.

Description

Image display device and its driving method {IMAGE DISPLAY DEVICE AND DRIVING METHOD OF THEREOF}

The present invention relates to an image display device capable of realizing a two-dimensional plane image (hereinafter referred to as '2D image') and a three-dimensional stereoscopic image (hereinafter referred to as '3D image').

The image display device implements a 3D image by using a binocular parallax technique or an autostereoscopic technique.

The binocular parallax method uses a parallax image of the left and right eyes with a large stereoscopic effect, and there are glasses and no glasses, both of which are put to practical use. The autostereoscopic method is generally provided with an optical plate such as a parallax barrier for separating the optical axis of the left and right parallax images in front of or behind the display screen. The spectacle method displays left and right parallax images having different polarization directions on a liquid crystal display panel, and realizes a stereoscopic image using polarized glasses or liquid crystal shutter glasses.

The spectacle method may be roughly classified into a first polarization filter method using a pattern retarder film and polarizing glasses, a second polarization filter method using a switching liquid crystal layer and polarizing glasses, and a shutter glass method using liquid crystal shutter glasses.

In the first polarization filter method, the left eye image and the right eye image are alternately displayed in units of horizontal lines on the liquid crystal display panel, and the left eye image and the right eye image are switched by switching polarization characteristics incident on the polarizing glasses through the pattern retarder film on the liquid crystal display panel. 3D image is realized by spatially dividing the. In the second polarization filter method, the left eye image and the right eye image are alternately displayed on a liquid crystal display panel in units of frames, and the left and right eye images are spatiotemporally spaced by switching polarization characteristics incident on the polarizing glasses through the switching liquid crystal layer on the liquid crystal display panel. 3D image is realized by dividing into. In the case of the first and second polarization filter methods, the transmittance of the 3D image is reduced due to the pattern retarder film or the switching liquid crystal layer disposed on the liquid crystal display panel to serve as a polarization filter. The problem of lowering the transmittance of the image display device using the first and second polarization filter methods is still present when the 2D image is implemented.

In the shutter glass method, a left eye image and a right eye image are alternately displayed in units of frames on a liquid crystal display panel, and 3D image is realized by opening and closing the left and right eye shutters of the liquid crystal shutter glasses in synchronization with the display timing. The liquid crystal shutter glasses produce binocular parallax by controlling only the left eye shutter to open when the left eye image is displayed on the liquid crystal display panel, and only the right eye shutter to open when the right eye image is displayed on the liquid crystal display panel. In the shutter glass method, the above-described problem of decrease in transmittance does not occur.

However, the conventional shutter glass method has the following problems.

First, in the conventional shutter glass method, as shown in FIG. 1, since the shutter can be opened only after the image data is filled in the liquid crystal display panel and the liquid crystal molecules are completed by the image data, the shutter opening time is short. The luminance of the sensed 3D image is greatly reduced. In Fig. 1, 'Ta' represents an address period of image data, 'Tb' represents a liquid crystal response period, and 'Tc' represents a shutter opening period, respectively. According to this, the shutter opening period is less than about 10% of one frame period.

Second, the conventional shutter glass method requires a high speed drive in order to prevent flicker in displaying an image. That is, the conventional shutter glass method is required to be driven at a frame frequency of at least 120Hz for displaying the left and right eye images, the higher the frame frequency is effective to prevent flicker. However, since the charging time of the image data becomes shorter as the frame frequency increases, the conventional shutter glass method has a limitation in increasing the frame frequency.

Accordingly, it is an object of the present invention to provide an image display apparatus and a driving method thereof which increase the shutter opening time to increase the brightness of a 3D image and ensure good charging characteristics in response to a high frame frequency.

In order to achieve the above object, an image display apparatus according to an exemplary embodiment of the present invention has a plurality of gate lines and a plurality of data lines intersecting, and has a plurality of liquid crystal cells arranged in each of the crossing regions, and thus a 2D image or a frame period. A liquid crystal display panel for implementing a 3D image including a left eye image and a right eye image that are alternately displayed in units; A data driving circuit applying a data voltage for the 2D image or the 3D image to the data lines; A gate driving circuit configured to supply a gate pulse to the gate lines in synchronization with a data voltage for the 2D image or the 3D image; A tie and controller controlling the driving circuits at a first frame frequency when the 2D image is implemented, and controlling the driving circuits at a second frame frequency faster than the first frame frequency when the 3D image is implemented; And a shutter glass that, when the 3D image is implemented, opens its left eye shutter within a period during which the left eye image is displayed, and opens its right eye shutter within the period during which the right eye image is displayed; The gate lines are simultaneously driven two adjacent to each other by the supply of the gate pulses which are sequentially shifted when the 3D image is implemented.

When the 3D image is implemented, the gate pulses are simultaneously supplied to the 2k-1 (k is a positive integer) th gate line and the 2k th gate line adjacent to each other.

The gate lines are individually driven by the supply of the gate pulses which are sequentially shifted when the 2D image is implemented; The pulse width of the gate pulse supplied when the 3D image is implemented is substantially the same as the pulse width of the gate pulse supplied when the 2D image is implemented.

The first frame frequency is 120 Hz and the second frame frequency is 240 Hz.

The gate driving circuit may include: a shift register configured to sequentially shift a gate start pulse according to a gate shift clock; A plurality of AND gates for ANDing an output signal of the shift register and an inverted signal of a gate output enable signal; In the 2D image implementation, a signal input from the AND gates is output as it is, while in the 3D image implementation, the OR operation is performed in response to the simultaneously driven gate lines. Switching circuit; And a level shifter for shifting the output signal swing width of the switching circuit to drive the liquid crystal display panel to generate the gate pulse.

Liquid crystal cells arranged on the same vertical line among the liquid crystal cells may have a first data line disposed on their left side to supply a data voltage of a first polarity during a specific frame, and a second polarity disposed on their right side during the specific frame. Between the second data lines for supplying the data voltage of, two adjacent liquid crystal cells are connected in zigzag to the first and second data lines.

In addition, according to an embodiment of the present invention, a plurality of gate lines and a plurality of data lines intersect each other, and a plurality of liquid crystal cells arranged in each crossing area are displayed in 2D images or left eye images alternately displayed in units of frame periods. And a liquid crystal display panel for realizing a 3D image including a right eye image, and a shutter glass for realizing binocular disparity through the 3D image, the driving method comprising: a data voltage corresponding to the 2D image at a first frame frequency; Applying to the data lines or applying a data voltage corresponding to the 3D image to the data lines at a second frame frequency faster than the first frame frequency; Supplying a gate pulse to the gate lines in synchronization with a data voltage for the 2D image or the 3D image; And opening the left eye shutter of the shutter glass within a period during which the left eye image is displayed, and opening the right eye shutter of the shutter glass within the period during which the right eye image is displayed when the 3D image is implemented. The gate lines are simultaneously driven by two adjacent gate lines by the supply of the gate pulses which are sequentially shifted when the 3D image is implemented.

According to the present invention, the image display device and the driving method thereof sequentially drive the gate lines by one line in the 2D mode, whereas in the 3D mode, the gate lines are sequentially driven in pairs of gate line pairs, so that the vertical resolution is 1/2 of the 2D mode. By reducing, the address period of data is shortened to less than half of one frame period. Accordingly, the present invention can increase the left / right shutter opening period by approximately 30% of one frame period, thereby greatly improving the luminance of the 3D image.

In addition, the image display device and the driving method thereof according to the present invention, even if the frame frequency in the 3D mode is twice as fast as the frame frequency in the 2D mode to prevent flicker, by sequentially driving the gate lines in units of gate line pairs in the 3D mode The data charging time can be as much as the data charging time of the 2D mode.

Furthermore, the image display device and the driving method thereof according to the embodiment of the present invention are connected by connecting the liquid crystal cells arranged on the same vertical line to the data lines arranged on the left and right in a unit of predetermined liquid crystal cells in a zigzag manner. The logic inversion period of the polarity control signal for version driving can be extended to one frame period, so that the amount of heat generated by the data driving circuit can be greatly reduced in high speed driving.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 10.

2 shows an image display device according to an embodiment of the present invention.

2, an image display device according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a shutter control circuit 14. , And a shutter glass 15. The data driver circuit 12 includes a plurality of source drive ICs. The gate driving circuit 13 includes a plurality of gate drive ICs.

The liquid crystal display panel 10 includes two glass substrates and a liquid crystal layer formed therebetween. The liquid crystal display panel includes liquid crystal cells Clc arranged in a matrix by a cross structure of the data lines DL and the gate lines GL. A pixel array including data lines DL, gate lines GL, TFTs, and a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 10. The liquid crystal cells Clc are connected to the TFT and are driven by an electric field between the pixel electrodes 1 and the common electrode 2. The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 10. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed. The liquid crystal mode of the liquid crystal display panel 10 applicable to the present invention may be implemented in any liquid crystal mode as well as the above-described TN mode, VA mode, IPS mode, FFS mode. In addition, the liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit omitted in the drawings is required.

The liquid crystal display panel 10 displays a 2D image under the control of the timing controller 11 in the 2D mode MODE_2D, and displays a 3D image under the control of the timing controller 11 in the 3D mode MODE_3D.

The timing controller 11 multiplies the timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal Data Enable, DE, and the dot clock CLK by n times to obtain an input frame frequency of 60 Hz. The operation timings of the data driving circuit 12 and the gate driving circuit 13 are controlled at a frame frequency multiplied by n (n is a positive integer of 2 or more), and an interpolation frame image is inserted between the frame images. The timing controller 11 controls the driving circuits 12 and 13 in the 2D mode MODE_2D or the 3D mode MODE_3D in response to the mode signals MODE_2D / MODE_3D input from the outside. For example, the timing controller 11 may control the driving circuits 12 and 13 at a frame frequency of 120 Hz in the 2D mode MODE_2D, and the driving circuits 12 and 13 at a frame frequency of 240 Hz in the 3D mode MODE_3D. 13) can be controlled. The frame double speed driving technique of the timing controller 11 is proposed by Korean Patent Application Publication No. 10-2008-0002304, Korean Patent Application Publication No. 10-2008-0063435, Korean Patent Application No. 10-2008-0112933, etc. It can be applied by double speed restraint driving technology. Control signals of the driving circuits 12 and 13 generated by the timing controller 11 are operated by the gate timing control signal GDC for controlling the operation time of the gate driving circuit 13 and the data driving circuit 12. And a data timing control signal DDC for controlling the timing and polarity of the data voltage.

The gate timing control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP is applied to the gate drive IC generating the first gate pulse (or scan pulse). The gate shift clock GSC is a clock signal commonly input to gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The gate timing control signal GDC is multiplied by n times according to the frame frequency by the timing controller 11.

The data timing control signal (DDC) includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), a polarity control signal (Polarity: POL), and a source output enable signal (Source Output Enable). , SOE) and the like. The source start pulse SSP controls the data sampling start time of the data driving circuit 12. The source sampling clock SSC is a clock signal that controls the sampling operation of data in the data driving circuit 12 based on the rising or falling edge. The polarity control signal POL controls the vertical polarity of the data voltage output from the data driving circuit 12. The source output enable signal SOE controls the output of the data driver circuit 12. The data timing control signal DDC is multiplied by n times according to the frame frequency by the timing controller 11.

The timing controller 11 displays the digital video data (3D DATA) of the 3D data format input from the outside under the 3D mode MODE_3D, when the left side of the shutter glass 15 is opened (hereinafter, 'left eye data'). ) And data displayed when the right side of the shutter glass 15 is opened (hereinafter referred to as 'right eye data'), and then the left and right eye data are alternately rotated every one frame period. It supplies to the furnace 12. In addition, in the 2D mode MODE_2D, the timing controller 11 supplies the digital video data 2D DATA in the 2D data format input from the outside to the data driving circuit 12.

The data driving circuit 12 converts left / right eye data of a 3D data format into an analog data voltage based on the data timing control signal DDC multiplied at 240 Hz under the 3D mode MODE_3D to convert the data lines to the data lines DL. Is authorized. The data driving circuit 12 converts the digital video data 2D DATA of the 2D data format into an analog data voltage based on the data timing control signal DDC multiplied at 120 Hz under the 2D mode MODE_2D to convert the data line DL. )

The gate driving circuit 13 has a pulse width of one horizontal period 1H and one horizontal period 1H as shown in FIG. 4 based on the gate timing control signal GDC multiplied at 120 Hz under the 2D mode MODE_2D. Gate pulses that are sequentially shifted are generated and supplied to the gate lines GL. The gate driving circuit 13 has a pulse width of 2 horizontal periods (2H) as shown in FIG. 6 based on the gate timing control signal (GDC) multiplied at 240 Hz under the 3D mode (MODE_3D) for 2 horizontal periods (2H) Gate pulse pairs that are sequentially shifted are generated and supplied to the gate lines GL. The structure and operation of the gate driving circuit 13 will be described later in detail with reference to FIGS. 3 to 6.

The shutter control circuit 14 is operated under the 3D mode MODE_3D. The shutter control circuit 14 counts the vertical synchronization signal Vsync input from the outside and displays whether the current frame is a frame in which left eye data is displayed (hereinafter referred to as a left eye frame) or a right eye data DATA_R. It is determined whether the frame (hereinafter, referred to as 'right eye frame'). In addition, the shutter control circuit 14 includes a left eye shutter control signal STL for controlling the left eye shutter of the shutter glass 15 to be opened for a specific period of the left eye frame, and a right eye shutter of the shutter glass 15 for a specific period of the right eye frame. Generates a right eye shutter control signal STR for opening control.

The shutter glass 15 is a device worn by a spectator to three-dimensionally view left and right eye images displayed in units of frames on the liquid crystal display panel 10, and shutter control signals STL and STR from the shutter control circuit 14. ), His left and right shutters are alternately opened and closed frame by frame. By alternately blocking the left and right images, different images are formed in the left and right eyes of the shutter glass 15, thereby allowing the viewer to feel a three-dimensional effect.

3 shows the gate driving circuit 13 in detail.

Referring to FIG. 3, the gate driving circuit 13 includes a plurality of gate drive ICs for sequentially supplying gate pulses synchronized with data voltages supplied to the data lines DL, to the gate lines GL. .

Each of the gate drive ICs includes a shift register 40, a level shifter 43, and a plurality of AND gates (hereinafter referred to as “AND gates”) 41 connected between the shift register 40 and the level shifter 43. ), A switching circuit 42 for switching the output signals of the AND gates 41 differently according to the mode signals MODE_2D / MODE_3D input from the outside, and an inverter 44 for inverting the gate output enable signal GOE. ).

The shift register 40 sequentially shifts the gate start pulse GSP according to the gate shift clock GSC using a plurality of cascaded D-flip flops. Each of the AND gates 41 generates an output by ANDing the output signal of the shift register 40 and the inverted signal of the gate output enable signal GOE. The inverter 44 inverts the gate output enable signal GOE and supplies it to the AND gates 41.

The switching circuit 42 is an OR gate for performing an OR operation on the output signal A1 of the 2k-1 (k is a positive integer) th AND gate 41 and the output signal A2 of the 2k th AND gate 41 (hereinafter, referred to as an AND). , &Quot; OR gate " 4211, and output signal A1 of 2k-1 < th > AND gate 41 and output signal A3 of OR gate 4211 in response to mode signal MODE_2D / MODE_3D. Selectively outputs the first multiplexer 4212 and the output signal A2 of the 2kth AND gate 41 and the output signal A3 of the OR gate 4211 in response to the mode signals MODE_2D / MODE_3D. A plurality of switching units 421 including a second multiplexer 4213 to output each. Each of the switching units 421 outputs the output signal A1 and the 2k th AND gate of the 2k-1 th AND gate 41 through the first and second multiplexers 4212 and 4213 in response to the mode signal MODE_2D. The output signal A2 of 41 is outputted. On the other hand, each of the switching units 421 outputs the output signal A3 of the OR gate 4211 through the first and second multiplexers 4212 and 4213 respectively corresponding to the mode signal MODE_3D.

The level shifter 43 shifts the output voltage swing width of the switching circuit 42 to a swing width capable of operating the TFT of the liquid crystal display panel.

Meanwhile, the shift register 40 may be simultaneously formed on the pixel array and the glass substrate in the pixel array manufacturing process of the liquid crystal display panel 10. In this case, the level shifter 43 may be formed on the control board or the source printed circuit board together with the timing controller 11 without being formed on the glass substrate.

The operation of the switching circuit 42 is as follows.

The switching circuit 42 outputs the output signal A1 of the 2k-1 < th > AND gate 41 and each of the 2k < th > AND gates through the switching units 421 under the 2D mode MODE_2D driven at a frame frequency of 120 Hz. The output signal A2 of 41 is supplied to the level shifter 43. As a result, under the 2D mode MODE_2D, the gate pulses G1 to Gk output from the level shifter 43 have a pulse width of one horizontal period 1H and have one horizontal period 1H as shown in FIG. 4. Shifted sequentially

The switching circuit 42 supplies the output signal A3 of the OR gate 4211 to the level shifter 43 through each of the switching units 421 under the 3D mode MODE_3D driven at a frame frequency of 240 Hz. The output signal A3 of the OR gate 4211 has a pulse width of 2 horizontal periods 2H as shown in FIG. As a result, in the 3D mode MODE_3D, the gate pulses G1 to Gk output from the level shifter 43 are sequentially shifted by two horizontal periods 2H in sequence as shown in FIG. Will occur. The 2k-1 th gate pulses and the 2k th gate pulses constituting the gate pulse pair are generated at the same timing with a pulse width of 2 horizontal periods (2H). Since one horizontal period 1H under the 3D mode MODE_3D corresponds to half of one horizontal period 1H under the 2D mode MODE_2D, the pulse width 2H of the gate pulse pairs is generated under the 2D mode MODE_2D. It has a temporal magnitude substantially the same as the pulse width 1H of the gate pulse. In order to prevent flicker, even if the frame frequency under 3D mode (MODE_3D) is twice as fast as the frame frequency under 2D mode (MODE_2D), the data charging time under 2D mode (MODE_2D) That means you can secure as much as you can. In addition, since the number of gate lines individually driven is reduced by half because two gate lines are driven at the same time, it means that the vertical resolution under 3D mode MODE_3D is reduced to 1/2 compared to 2D mode MODE_2D. . As the vertical resolution decreases, the address period of the data in one frame also shortens.

7 shows that the shutter opening period of the shutter glass is increased by the reduction of the data address period, and FIG. 8 shows the operation timing of the left / right eye shutter synchronized with the display timing of the left / right eye data. In FIG. 7, 'Ta' indicates an address period of left / right eye data, 'Tb' indicates a liquid crystal response period, and 'Tc' indicates a left / right shutter opening period, respectively. In FIG. 8, 'Ta1' and 'Ta2' denote address periods of left eye and right eye data, respectively, 'Tb1' and 'Tb2' denote liquid crystal response periods, and 'Tc1' and 'Tc2' denote left and right eye shutters, respectively. Each opening period is shown.

Referring to FIG. 7, the present invention can reduce the vertical resolution under the 3D mode MODE_3D to 1/2 compared to the 2D mode MODE_2D through the above-described switching operation in the gate driving circuit. (Ta) can be reduced by almost half. As a result, the present invention can increase the left / right shutter opening period Tc by approximately 30% of one frame period. As the shutter opening period Tc increases, the luminance of the 3D image that the viewer feels increases accordingly.

In FIG. 8, the left eye shutter is opened for each of the specific periods t11 to t21 and Tc1 of the left eye frame at intervals of two frame periods in response to the left eye shutter control signal. The left eye shutter opening start time t11 indicates immediately after the left eye data is addressed to the liquid crystal display panel and the behavior of the liquid crystal molecules is completed by the left eye data, and may be predetermined through experiments. The left eye shutter opening end time t21 indicates immediately before the right eye data is addressed to the liquid crystal display panel.

In addition, the right eye shutter is opened every specific periods t12 to t22 and Tc2 of the right eye frame in response to the right eye shutter control signal. The right eye shutter opening start time t12 indicates immediately after the right eye data is addressed to the liquid crystal display panel and the behavior of the liquid crystal molecules is completed by the right eye data, and may be predetermined through experiments. The right eye shutter opening end time t22 indicates immediately before the left eye data is addressed to the liquid crystal display panel.

9 shows the connection configuration of the liquid crystal cells formed in the liquid crystal display panel and the polarity of the data voltage supplied to the liquid crystal cells. And, Figure 10 shows the waveform of the polarity control signal.

9 and 10, the polarity of the data voltage supplied to the data lines DL1 to DL5 is determined according to the logic level of the polarity control signal POL. Therefore, when the logic inversion period of the polarity control signal POL is increased in accordance with the multiplication of the frame frequency, that is, the frequency of the polarity control signal POL is increased in accordance with the frame frequency, the positive / negative analog data voltage in the data driving circuit is increased. The faster the switching speed, the higher the yield of the data drive circuit. Inversion driving of data voltage polarity in units of liquid crystal cells using a data driving circuit driven at a relatively high frame frequency such as a frame frequency of 120 Hz in 2D mode (MODE_2D) and a frame frequency of 240 Hz in 3D mode (MODE_3D) In the case of the above, the above problems become large.

Therefore, in order to reduce the amount of heat generated by the data driving circuit, the logic inversion period of the polarity control signal POL is increased to one frame period as shown in FIG. Instead, the pixel array of the liquid crystal display panel is implemented as shown in FIG. 9 to implement vertical two dot inversion in the liquid crystal display panel. Liquid crystal cells arranged on the same vertical line (VL # 1 / VL # 2 / VL # 3 / VL # 4) are arranged on the left side of the first data line to supply a data voltage of a first polarity for a specific frame, and Between the second data lines disposed on the right side and supplying the data voltages of the second polarity during the specific frame, zigzag is connected to the first and second data lines in units of two adjacent liquid crystal cells. In other words, among the liquid crystal cells arranged on the same vertical line VL # 1 / VL # 2 / VL # 3 / VL # 4, the 4k-3rd and 4k-2nd horizontal lines HL # 1, HL # 2 4k-1 of the liquid crystal cells arranged on the same vertical line (VL # 1 / VL # 2 / VL # 3 / VL # 4) are supplied with the data voltage of the first polarity from their left data line The liquid crystal cells of the first and fourth kth horizontal lines HL # 1 and HL # 2 receive a data voltage of a second polarity from their right data line. To this end, the TFTs for driving the liquid crystal cells of the 4k-3rd and 4k-2nd horizontal lines HL # 1 and HL # 2 are 4k-3rd and 4k-2nd gate lines GL1 and GL2. Connected to the intersection of the data lines D1 to D4 to transfer the data voltages from the data lines D1 to D4 to the 4k-3rd and 4k-2th horizontal lines HL # 1 and HL # 2. Supply to the pixel electrodes. The TFTs for driving the liquid crystal cells of the 4k-1th and 4kth horizontal lines HL # 3 and HL # 4 are the 4k-1st and 4kth gate lines GL3 and GL4 and the data lines D2 through. It is connected to the intersection of D5 to supply data voltages from the data lines D2 to D5 to the pixel electrodes of the 4k-1st and 4kth horizontal lines HL # 3 and HL # 4.

As described above, the image display apparatus and the driving method thereof according to the exemplary embodiment of the present invention sequentially drive the gate lines by one line in the 2D mode, whereas in the 3D mode, the gate lines are sequentially driven in the unit of a pair of gate lines, thereby providing vertical resolution. Is reduced to 1/2 of the 2D mode to shorten the address period of data to less than half of one frame period. Accordingly, the present invention can increase the left / right shutter opening period by approximately 30% of one frame period, thereby greatly improving the luminance of the 3D image.

Furthermore, the image display device and the driving method thereof according to the embodiment of the present invention sequentially drive the gate lines in pairs of gate line pairs even if the frame frequency in the 3D mode is twice as fast as the frame frequency in the 2D mode to prevent flicker. The data charging time in the 3D mode can be secured by the data charging time in the 2D mode.

Furthermore, the image display device and the driving method thereof according to the embodiment of the present invention are connected by connecting the liquid crystal cells arranged on the same vertical line to the data lines arranged on the left and right in a unit of predetermined liquid crystal cells in a zigzag manner. The logic inversion period of the polarity control signal for the version driving can be extended to one frame period, thereby greatly reducing the amount of heat generated by the data driving circuit in the high speed driving.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a view showing a shutter opening time in a conventional shutter glass method.

2 is a block diagram illustrating an image display device according to an exemplary embodiment of the present invention.

3 is a view showing in detail the gate driving circuit of FIG.

4 is a waveform diagram of a gate pulse generated under a 2D mode.

5 is a diagram illustrating input and output waveforms of the OR gate of FIG. 3.

6 is a waveform diagram of a gate pulse generated under a 3D mode.

7 is a view showing a shutter opening time according to the present invention.

Fig. 8 is a view showing the operation timing of the left / right eye shutter synchronized with the display timing of the left / right eye data.

9 is a view illustrating a connection configuration of liquid crystal cells formed in the liquid crystal display panel of FIG. 3 and polarities of data voltages supplied to the liquid crystal cells.

10 is a waveform diagram showing a logic inversion period of the polarity control signal.

<Description of Symbols for Main Parts of Drawings>

10 liquid crystal display panel 11 timing controller

12: data driving circuit 13: gate driving circuit

14: shutter control circuit 15: shutter glass

40: shift register 41: logical gate

42: switching circuit 43: level shifter

44: inverter

Claims (10)

A plurality of gate lines and a plurality of data lines intersect each other, and a plurality of liquid crystal cells arranged in each of the crossing regions implement a 2D image or a 3D image including a left eye image and a right eye image alternately displayed in units of frame periods. A liquid crystal display panel; A data driving circuit applying a data voltage for the 2D image or the 3D image to the data lines; A gate driving circuit configured to supply a gate pulse to the gate lines in synchronization with a data voltage for the 2D image or the 3D image; A tie and controller controlling the driving circuits at a first frame frequency when the 2D image is implemented, and controlling the driving circuits at a second frame frequency faster than the first frame frequency when the 3D image is implemented; And And a shutter glass for opening the left eye shutter within the period during which the left eye image is displayed, and opening the right eye shutter within the period during the right eye image when the 3D image is implemented; And the gate lines are driven simultaneously by two adjacent gate lines by the supply of the gate pulses which are sequentially shifted when the 3D image is implemented. The method of claim 1, And the gate pulses are simultaneously supplied to a 2k-1 (k is a positive integer) th gate line and a 2k th gate line when the 3D image is implemented. The method of claim 2, The gate lines are individually driven by the supply of the gate pulses which are sequentially shifted when the 2D image is implemented; And the pulse width of the gate pulse supplied when the 3D image is implemented is substantially the same as the pulse width of the gate pulse supplied when the 2D image is implemented. The method of claim 1, And the first frame frequency is 120 Hz and the second frame frequency is 240 Hz. The method of claim 1, The gate driving circuit, A shift register for sequentially shifting the gate start pulse according to the gate shift clock; A plurality of AND gates for ANDing an output signal of the shift register and an inverted signal of a gate output enable signal; In the 2D image implementation, a signal input from the AND gates is output as it is, while in the 3D image implementation, the OR operation is performed in response to the simultaneously driven gate lines. Switching circuit; And And a level shifter for shifting the output signal swing width of the switching circuit to drive the liquid crystal display panel to generate the gate pulse. The method of claim 1, Liquid crystal cells arranged on the same vertical line among the liquid crystal cells may have a first data line disposed on their left side to supply a data voltage of a first polarity during a specific frame, and a second polarity disposed on their right side during the specific frame. And zigzag connected to the first and second data lines in units of two adjacent liquid crystal cells between the second data lines supplying the data voltages of the plurality of data voltages. A plurality of gate lines and a plurality of data lines intersect each other, and a plurality of liquid crystal cells arranged in each of the crossing regions implement a 2D image or a 3D image including a left eye image and a right eye image alternately displayed in units of frame periods. In the driving method of the image display device including a liquid crystal display panel and a shutter glass for implementing binocular parallax through the 3D image, Applying a data voltage corresponding to the 2D image to the data lines at a first frame frequency, or applying a data voltage corresponding to the 3D image at the second frame frequency faster than the first frame frequency to the data lines. Making; Supplying a gate pulse to the gate lines in synchronization with a data voltage for the 2D image or the 3D image; And Opening the left eye shutter of the shutter glass within a period during which the left eye image is displayed, and opening the right eye shutter of the shutter glass within the period during which the right eye image is displayed when the 3D image is implemented; And the gate lines are driven simultaneously by two adjacent gate lines by supplying the gate pulses which are sequentially shifted when the 3D image is implemented. The method of claim 7, wherein And the gate pulses are simultaneously supplied to the 2k-1 (k is a positive integer) th gate line and the 2k th gate line when the 3D image is implemented. The method of claim 8, The gate lines are individually driven one by one by supplying the gate pulses sequentially shifted when the 2D image is implemented; The pulse width of the gate pulse supplied when the 3D image is implemented is substantially the same as the pulse width of the gate pulse supplied when the 2D image is implemented. The method of claim 1, And the first frame frequency is 120 Hz and the second frame frequency is 240 Hz.

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