KR101826352B1 - Liquid Crystal Display - Google Patents

Abstract

A liquid crystal display device according to the present invention includes: a liquid crystal display panel in which a plurality of pixel groups each including a first unit pixel and a second unit pixel neighboring each other are arranged; And a timing controller for aligning the input digital video data according to the pixel arrangement configuration of each of the pixel groups; Wherein the first unit pixel and the second unit pixel each have three subpixels; Each of the subpixels has a lateral width in a horizontal direction in which a gate line extends and a vertical width in a vertical direction in which the data lines extend; And the first and second gate lines sequentially arranged in the vertical direction are allocated to each of the pixel groups.

Description

[0001] Liquid crystal display [0002]

The present invention relates to a liquid crystal display device capable of reducing the number of data drive ICs (Integrated Circuits).

The liquid crystal display displays an image by controlling the light transmittance of the liquid crystal layer through an electric field applied to the liquid crystal layer in accordance with a video signal. Such a liquid crystal display device is a flat panel display device having advantages of small size, thinness and low power consumption, and is used as a portable computer such as a notebook PC, office automation equipment, audio / video equipment and the like. Particularly, an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell is capable of actively controlling a switching element, which is advantageous for a moving image.

A thin film transistor (hereinafter referred to as "TFT") is mainly used as a switching element used in an active matrix type liquid crystal display device as shown in Fig.

1, an active matrix type liquid crystal display device converts digital video data into an analog data voltage on the basis of a gamma reference voltage and supplies the analog data voltage to a data line DL, and simultaneously supplies a scan pulse to a gate line GL And charges the liquid crystal cell Clc with the data voltage. To this end, the gate electrode of the TFT is connected to the gate line GL, the source electrode thereof is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst And is connected to one electrode. A common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc. The storage capacitor Cst serves to charge the data voltage applied from the data line DL when the TFT is turned on to maintain the voltage of the liquid crystal cell Clc constant. When a scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode to apply a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc are changed in arrangement by the electric field between the pixel electrode and the common electrode to modulate the incident light.

Such a liquid crystal display device includes a gate drive IC (integrated circuit) for driving the gate lines GL and a data drive IC for driving the data lines DL. Since the number of signal lines GL and DL formed on the liquid crystal display panel increases as the size and resolution of the liquid crystal display device increase, the number of drive ICs for driving the signal lines GL and DL also continues to increase . Data drive ICs are relatively expensive compared to other devices. Accordingly, various methods for reducing the number of data drive ICs have been proposed to reduce manufacturing costs.

FIG. 2 illustrates one of the above schemes. In FIG. 2, instead of doubling the number of gate lines compared to the conventional normal configuration shown in FIG. 5A, the number of data lines is reduced to a half, (DRD) driving method that realizes the same resolution as the conventional one.

Referring to FIG. 2, a conventional liquid crystal display (LCD) device driven by the DRD scheme uses m (m is a natural number of 2 or more) liquid crystal cells arranged on one horizontal line by using two gate lines and m / 2 data lines . The DRD type conventional liquid crystal display device drives the data drive IC in the vertical two-dot version mode in order to minimize the flicker and reduce the power consumption. Thus, two liquid crystal cells adjacent to each other with the data line sandwiched therebetween are connected to two gate lines, respectively, to charge the same polarity data voltage supplied through the data line. For example, in a specific frame, the R liquid crystal cell and the G liquid crystal cell sharing the first data line D1 among the liquid crystal cells arranged in the first horizontal line HL1 are scanned from the gate lines G1 and G2 The R liquid crystal cell and the B liquid crystal cell sharing the second data line D2 in synchronization with the pulse supply timing are sequentially charged in synchronization with the supply timing of the scan pulses from the gate lines G1 and G2, And the B liquid crystal cells and the G liquid crystal cells sharing the third data line D3 are sequentially charged in the positive polarity in synchronization with the supply timing of the scan pulses from the gate lines G1 and G2. The arrow direction shown in Fig. 2 indicates the filling order of the liquid crystal cells connected to the respective data lines.

FIG. 3 shows a charge voltage waveform in each liquid crystal cell when the liquid crystal cells are charged along the direction of the arrow in FIG. 3, R liquid crystal cells connected to the first or third gate lines G1 and G3 are supplied with a positive voltage (or a negative voltage) rising (or falling) from a negative voltage (or a positive voltage) And a positive voltage (or a negative voltage) varying from a positive voltage (or a negative voltage) is applied to the G liquid crystal cells connected to the second or fourth gate lines G2 and G4. A positive voltage (or a negative voltage) rising (or falling) from a negative voltage (or a positive voltage) is applied to the B liquid crystal cells connected to the first or third gate lines G1 and G3 (Or a negative voltage) changing from a positive voltage (or a negative voltage) is applied to the B liquid crystal cells connected to the second or fourth gate lines G2 and G4. According to the known method, the charged amount of the liquid crystal cells to which the positive voltage (or the negative voltage) rising (or falling) from the negative voltage (or the positive voltage) is applied is changed from the positive voltage The polarity voltage (or the negative voltage) is lower than the charged amount of the liquid crystal cells to which the voltage is applied. This is because a rising time (or a falling time) of a positive voltage (or a negative voltage) rising (or falling) from a negative voltage (or a positive voltage) is long while a positive voltage (Or the polarity voltage) of the positive polarity voltage (or the negative polarity voltage) varying from the negative polarity voltage (or the negative polarity voltage) is relatively short.

Accordingly, in the conventional DRD type liquid crystal display device, the charged amount of the liquid crystal cells connected to the odd-numbered gate lines is smaller than the charged amount of the liquid crystal cells connected to the odd-numbered gate lines. In other words, the R liquid crystal cells are relatively fully charged, the G liquid crystal cells are all relatively strongly charged, and the B liquid crystal cells are repeatedly charged and charged in units of pixels. As a result, when only the B liquid crystal cells are turned on, an image quality defect of the vertical line dim is caused.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a liquid crystal display device capable of preventing image quality degradation while reducing the number of data driver ICs.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal display panel having a plurality of pixel groups each including a first unit pixel and a second unit pixel adjacent to each other; And a timing controller for aligning the input digital video data according to the pixel arrangement configuration of each of the pixel groups; Wherein the first unit pixel and the second unit pixel each have three subpixels; Each of the subpixels has a lateral width in a horizontal direction in which a gate line extends and a vertical width in a vertical direction in which the data lines extend; And the first and second gate lines sequentially arranged in the vertical direction are allocated to each of the pixel groups.

The liquid crystal display according to the present invention overcomes the problems of the conventional DRD driving method due to the structural features of the pixel configuration and the arrangement so that the number of source driver ICs can be effectively reduced without causing the vertical line dim .

Further, in the liquid crystal display device according to the present invention, the horizontal width of the subpixel is wider than the vertical width, thereby increasing the number of opening blocks in the subpixel, thereby increasing the overall aperture ratio of the panel.

1 is an equivalent circuit diagram of a pixel of a typical liquid crystal display device.
2 is a view showing a conventional liquid crystal display device driven by a DRD method.
FIG. 3 is a view showing a charge voltage waveform in each liquid crystal cell when the liquid crystal cells are charged along the arrow direction of FIG. 2. FIG.
4 is a view showing a liquid crystal display device according to an embodiment of the present invention.
5 is a diagram illustrating a unit pixel configuration of the present invention compared to a conventional normal unit pixel configuration;
6 shows a pixel arrangement 1 and a pixel arrangement 2 according to the invention;
7 and 8 are diagrams illustrating an example of a concrete connection of pixel organization 1;
Figures 9 and 10 are diagrams illustrating an example of a concrete connection of pixel organization 2;
11 and 12 are diagrams showing another example of a specific connection of the pixel structure 1;
13 and 14 are diagrams showing another example of a concrete connection of the pixel structure 2;
15 is a diagram showing an internal configuration of a timing controller for mapping data according to a pixel arrangement configuration of a liquid crystal display panel;
16 is a timing chart showing a data enable signal and an internal data enable signal in contrast to each other.
Figure 17 illustrates an example of data mapping for pixel configurations 1 and 2 of the present invention.
18 shows another example of data mapping for pixel configurations 1 and 2 of the present invention.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 4 to 18. FIG.

4 is a block diagram illustrating a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 4, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, and a gate driving circuit 13.

The liquid crystal display panel 10 has a liquid crystal layer formed between two glass substrates. This liquid crystal display panel 10 is formed by an intersection structure of m (m is a natural number) data lines D1 to Dm and 2n (n is a natural number) gate lines G1 (1) to Gn (2) And a plurality of liquid crystal cells Clc arranged in a matrix form. Data lines D1 to Dm, gate lines G1 (1) to Gn (2), TFTs, and a storage capacitor Cst are formed on a lower glass substrate of the liquid crystal display panel 10. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel 10, a black matrix, a color filter, and a common electrode 2 are formed. The common electrode 2 is formed on an upper glass substrate in a vertical field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed by a combination of IPS (In Plane Switching) mode, FFS (Fringe Field Switching) In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate together with the pixel electrode 1. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal cells Clc include a plurality of R (red) liquid crystal cells, G (green) liquid crystal cells and B (blue) liquid crystal cells. R liquid crystal cell functions as R sub-pixel including R color filter, G liquid crystal cell functions as G sub-pixel including G color filter, and B liquid crystal cell functions as B sub-pixel including B color filter . The R subpixel, the G subpixel, and the B subpixel implement a unit pixel. In particular, each subpixel is formed so that the horizontal width in the gate line extending direction is wider than the vertical width in the data line extending direction, and two gate lines are allocated to each unit pixel. The subpixel and unit pixel configuration will be described later in detail with reference to FIG. 5 to FIG.

The liquid crystal display panel 10 may be implemented in any form such as a transmissive type, a semi-transmissive type, and a reflective type. In the transmissive type and the semi-transmissive type, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 11 uses timing signals such as a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, a data enable signal DE and a dot clock DCLK supplied from a system (not shown) A data control signal for controlling the operation timing of the gate drive circuit 13 and a gate control signal for controlling the operation timing of the gate drive circuit 13 are generated. The data control signal is supplied to the data driving circuit 12 based on the source start pulse SSP, the rising edge or the falling edge indicating the sampling start point of the digital video data RGB, A source sampling clock SSC for instructing the latch operation of the digital video data RGB in the memory 12, a source output enable signal SOE for instructing the output of the data driving circuit 12, And a polarity control signal POL for controlling the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal cell Clc. The gate control signal is inputted to the shift register in the gate driving circuit 13 to output the gate start pulse GSP sequentially in the order of the gate start pulse GSP indicating the start horizontal line where the scan starts in one vertical period in which one screen is displayed, A gate shift clock signal GSC generated with a pulse width corresponding to the ON period of the TFT, a gate output enable signal GOE indicating the output of the gate driving circuit 13, And the like.

The timing controller 11 multiplies the data enable signal DE supplied from the system to generate an internal data enable signal Internal DE and modulates the data control signal and the gate control signal based on the internal data enable signal do. The timing controller 11 aligns the digital video data RGB supplied from the system to the unit pixel arrangement of the liquid crystal display panel 10 based on the internal data enable signal and supplies the digital video data RGB to the data driving circuit 12 Supply.

The data driving circuit 12 latches the digital video data RGB under the control of the timing controller 11. [ The data driving circuit 12 converts the digital video data RGB to an analog positive / negative polarity gamma voltage according to the polarity control signal POL to generate positive / negative analog data voltages, To the lines D1 to Dm. To this end, the data driving circuit 12 includes a plurality of data drive ICs.

The gate drive circuit 13 generates a scan pulse for selecting a horizontal line of the liquid crystal display panel 10 to be supplied with the analog data voltage under the control of the timing controller 11 and supplies the scan pulse to the gate lines G1 ) To Gn (2)). To this end, the gate drive circuit 13 includes a level shifter for converting the output signal of the shift register and the shift register into a swing width suitable for driving the TFT of the liquid crystal cell Clc, and an output circuit connected between the level shifter and the gate line Respectively. The shift register may be formed directly on the lower glass substrate of the liquid crystal display panel 10 by a GIP (Gate In Panel) method. The level shifter may be mounted on the control PCB (not shown) together with the timing controller 11. [

5 shows the unit pixel configuration of the present invention in comparison with the conventional normal unit pixel configuration. 6 shows a pixel configuration 1 and a pixel configuration 2 according to the present invention.

(Unit pixel number in the horizontal axis (X) direction) x 1 (number of unit pixels in the vertical axis (Y) direction) The unit pixel arrangement in the conventional and the present invention is as follows.

As shown in FIG. 5A, in the conventional 2 × 1 unit pixel array, six sub-pixels arranged in parallel in the X-axis direction (that is, the gate line extending direction) are provided. By the six subpixels, two unit pixels arranged along the horizontal axis X and having a square shape are constituted. Each of the subpixels is narrower in width in the X-axis direction than in the Y-axis direction (i.e., the data line extending direction). The ratio of the width to the width of each of the subpixels is 1: 3. Since each of the subpixels is connected to a different data line, six data lines are allocated to a conventional 2x1 unit pixel array.

In contrast, as shown in FIG. 5 (B), in the 2 × 1 unit pixel array of the present invention, some three sub-pixels arranged side by side in the horizontal axis (X) ) Direction, and the remaining three sub-pixels arranged in parallel in the X-axis direction are provided. Six subpixels are arranged along the horizontal axis X, and two unit pixels having a "┌" shape and a "┘" shape are configured (see FIG. 6A) ) And two unit pixels having a "└" shape and a "┐" shape can be arranged (see FIG. 6 (B)). Each of the subpixels is rather wider than the vertical width in the direction of the vertical axis (Y) in the transverse axis (X) direction. The ratio of the width to the width of each of the subpixels is 2: 1.5.

The number of data lines allocated to the 2x1 unit pixel array of the present invention is drastically reduced compared to the conventional case. For example, two subpixels vertically adjacent in the Y-axis direction share one data line (see FIGS. 7 to 10), so that three data lines are allocated to the 2x1 unit pixel array of the present invention do. As another example, two subpixels adjacent to each other diagonally in the vertical Y direction share one data line (see FIGS. 11 through 14), so that four data lines are allocated to the 2x1 unit pixel array of the present invention do. Since the data lines are connected to each of the output channels of the source driver IC at a ratio of 1: 1, if the number of data lines is reduced, the number of source driver ICs is also reduced.

The 2x1 unit pixel array according to the present invention can be grouped as pixel configuration 1 of Fig. 6 (A) or grouped as pixel configuration 2 of Fig. 6 (B).

The pixel structure 1 is grouped by including a first unit pixel P # 1 having a "┌" shape and a second unit pixel P # 2 having a "┘" shape as shown in FIG. 6A, Are repeatedly arranged in the liquid crystal display panel 10 in the form of a pixel group. The first unit pixel P # 1 includes a first sub-pixel SP # 1-1, a first sub-pixel SP # 1-2 and a first sub-pixel SP # 1-3 Quot; "). The second unit pixel P # 2 includes the second -1 subpixel SP # 2-1, the second -2 subpixel SP # 2-2, and the second 2-3 subpixel SP # 2-3 Quot; ").

The pixel structure 2 is grouped into a first unit pixel P # 1 having a "└" shape and a second unit pixel P # 2 having a "┐" shape as shown in FIG. 6B, Are repeatedly arranged in the liquid crystal display panel 10 in the form of a pixel group. The first unit pixel P # 1 includes a first sub-pixel SP # 1-1, a first sub-pixel SP # 1-2 and a first sub-pixel SP # 1-3 Quot; "). The second unit pixel P # 2 includes the second -1 subpixel SP # 2-1, the second -2 subpixel SP # 2-2, and the second 2-3 subpixel SP # 2-3 Quot; ").

According to the pixel configuration 1 or the pixel configuration 2, the number of source driver ICs can be effectively reduced without causing vertical line dim, which is a problem of the conventional DRD driving method, by a unique unit pixel structure. However, for this purpose, two gate lines must be allocated to the pixel group implemented with the pixel configuration 1 and the pixel configuration 2.

According to the pixel configuration 1 or the pixel configuration 2, since the width of the subpixel is wider than the vertical width, the number of opening blocks in the subpixel is increased, which increases the overall aperture ratio of the panel.

Figs. 7 and 8 show an example of a concrete connection of the pixel configuration 1, and Figs. 9 and 10 show an example of a concrete connection of the pixel configuration 2. Fig. 7 to 10, TFTs for connecting subpixels and signal lines (data lines and gate lines) are arranged in one row in the X-axis direction and in one row in the Y-axis direction.

Under such a TFT arrangement, two gate lines G1 (1) and G1 (2) sequentially arranged in the Y-axis direction are sequentially arranged in the pixel group of the pixel configuration 1 of FIG. Three data lines D1, D2 and D3 are allocated.

Referring to FIG. 7, the 1-1 subpixel SP # 1-1 is connected between the first data line D1 and the first gate line G1 (1) through the TFT, The sub-pixel SP # 1-2 is connected between the second data line D2 and the first gate line G1 (1) through the TFT, and the first to third sub-pixels SP # And is connected between the first data line D1 and the second gate line G1 (2) through the TFT. Each of the 1-1 subpixel SP # 1-1, the 1-2 subpixel SP # 1-2 and the 1-3 subpixel SP # A G subpixel to which the G data G11 is applied, and a B subpixel to which the B data B11 is applied.

The 2-1 subpixel SP # 2-1 is connected between the second data line D2 and the second gate line G1 (2) through the TFT, and the 2-2 subpixel SP (SP # 2-1) # 2-2 are connected between the third data line D3 and the second gate line G1 (2) through the TFT, and the second and third subpixels SP # 2-3 are connected through the TFT 3 data line D3 and the first gate line G1 (1). The R 2 data R 12 is applied to the 2-1 subpixel SP # 2-1, the 2-2 subpixel SP # 2-2, and the 2-3 subpixel SP # A G subpixel to which the G data G12 is applied, and a B subpixel to which the B data B12 is applied.

The pixel group constituting the pixel structure 1 may be repeated in units of one pixel group as shown in FIG. 7, but it is more preferable that the pixel group is repeated in units of three pixel groups as shown in FIG. 8 in view of picture quality compensation. 8, since R subpixel, G subpixel, and B subpixel are all included in each subpixel array line extending in the direction of the horizontal axis X and the vertical axis Y, it is effective to improve the line dim to be.

Referring to FIG. 8, the first 1-1 subpixel SP # 1-1 is implemented as a subpixel for displaying different colors in three groups of pixels arranged next to each other in the Y-axis direction, 2 subpixels SP # 1-2 are implemented as subpixels for displaying different colors in the three pixel groups, and the first to third subpixels SP # Lt; RTI ID = 0.0 > sub-pixels < / RTI > for different color displays. The 2-1 subpixel (SP # 2-1) is implemented as a subpixel for displaying different colors in the three pixel groups, and the 2-2 subpixel (SP # 2-2) (SP # 2-3) is implemented as a sub-pixel for displaying different colors in the three pixel groups . For example, the 1-1 and 2-1 subpixels (SP # 1-1 and SP # 2-1) are divided into R sub-pixels in the first pixel group, G sub-pixels in the second pixel group, (SP # 1-2, SP # 2-2) are implemented as B subpixels in the first pixel group and B subpixels in the second pixel group, and the 1-2 and 2-2 subpixels (SP # 1-3, SP # 2-3) are implemented in the first pixel group to the B subpixel, and the first to third subpixels , R subpixels in the second pixel group, and G subpixels in the third pixel group.

The pixel groups constituting the pixel configuration 2 of FIG. 9 also include two gate lines G1 (1) and G1 (2) sequentially arranged in the Y-axis direction and three data lines (D1, D2, D3).

9, the 1-1 subpixel SP # 1-1 is connected between the first data line D1 and the first gate line G1 (1) through the TFT, The sub-pixel SP # 1-2 is connected between the second data line D2 and the second gate line G1 (2) through the TFT, and the first to third sub-pixels SP # And is connected between the first data line D1 and the second gate line G1 (2) through the TFT. Each of the 1-1 subpixel SP # 1-1, the 1-2 subpixel SP # 1-2 and the 1-3 subpixel SP # A G subpixel to which the G data G11 is applied, and a B subpixel to which the B data B11 is applied.

The 2-1 subpixel SP # 2-1 is connected between the third data line D3 and the second gate line G1 (2) through the TFT, and the 2-2 subpixel SP (SP # 2-1) # 2-2 are connected between the third data line D3 and the first gate line G1 (1) through the TFT and the second and third subpixels SP # 2-3 are connected through the TFT 2 data line D2 and the first gate line G1 (1). The R 2 data R 12 is applied to the 2-1 subpixel SP # 2-1, the 2-2 subpixel SP # 2-2, and the 2-3 subpixel SP # A G subpixel to which the G data G12 is applied, and a B subpixel to which the B data B12 is applied.

The pixel group constituting the pixel structure 2 may be repeated in units of one pixel group as shown in FIG. 9, but it is more preferable that the pixel group is repeated in units of three pixel groups as shown in FIG. 10 in view of picture quality compensation. 10, R subpixels, G subpixels, and B subpixels are all included in each subpixel array line extending in the direction of the horizontal axis X and the vertical axis Y, to be.

Referring to FIG. 10, each of the 1-1 to 2-3 sub-pixels SP # 1-1 to SP # 2-3 is different in three pixel groups arranged adjacent to each other in the Y-axis direction And is implemented as a sub-pixel for color display. For example, the 1-1 and 2-1 subpixels (SP # 1-1 and SP # 2-1) are divided into R sub-pixels in the first pixel group, G sub-pixels in the second pixel group, (SP # 1-2, SP # 2-2) are implemented as B subpixels in the first pixel group and B subpixels in the second pixel group, and the 1-2 and 2-2 subpixels (SP # 1-3, SP # 2-3) are implemented in the first pixel group to the B subpixel, and the first to third subpixels , R subpixels in the second pixel group, and G subpixels in the third pixel group.

Figs. 11 and 12 show another example of the concrete connection of the pixel configuration 1, and Figs. 13 and 14 show another example of the concrete connection of the pixel configuration 2. 11 to 14, the TFTs for connecting the subpixels and the signal lines (data lines and gate lines) are arranged in one row in the X-axis direction, while the TFTs are arranged in the Y-axis direction in the Y-axis direction.

In this TFT arrangement, two gate lines G1 (1) and G1 (2) sequentially arranged in the Y-axis direction are sequentially arranged in the pixel group of the pixel configuration 1 of FIG. Four data lines D1, D2, D3 and D4 are allocated.

11, the 1-1 subpixel SP # 1-1 is connected between the second data line D2 and the first gate line G1 (1) through the TFT, The sub-pixel SP # 1-2 is connected between the third data line D3 and the first gate line G1 (1) through the TFT, and the first to third sub-pixels SP # And is connected between the first data line D1 and the second gate line G1 (2) through the TFT. Each of the 1-1 subpixel SP # 1-1, the 1-2 subpixel SP # 1-2 and the 1-3 subpixel SP # A G subpixel to which the G data G11 is applied, and a B subpixel to which the B data B11 is applied.

The 2-1 subpixel SP # 2-1 is connected between the second data line D2 and the second gate line G1 (2) through the TFT, and the 2-2 subpixel SP (SP # 2-1) # 2-2 are connected between the third data line D3 and the second gate line G1 (2) through the TFT, and the second and third subpixels SP # 2-3 are connected through the TFT 4 data line D4 and the first gate line G1 (1). The R 2 data R 12 is applied to the 2-1 subpixel SP # 2-1, the 2-2 subpixel SP # 2-2, and the 2-3 subpixel SP # A G subpixel to which the G data G12 is applied, and a B subpixel to which the B data B12 is applied.

The pixel group constituting the pixel structure 1 may be repeated in units of one pixel group as shown in FIG. 11, but it is more preferable that the pixel group is repeated in units of three pixel groups as shown in FIG. 12 in terms of image quality compensation. 12, R subpixels, G subpixels, and B subpixels are all included in each subpixel array line extending in the direction of the horizontal axis X and the vertical axis Y, to be.

Referring to FIG. 12, each of the 1-1 to 2-3 sub-pixels SP # 1-1 to SP # 2-3 is different from each other in three pixel groups arranged adjacent to each other in the Y-axis direction And is implemented as a sub-pixel for color display. For example, the 1-1 and 2-1 subpixels (SP # 1-1 and SP # 2-1) are divided into R sub-pixels in the first pixel group, G sub-pixels in the second pixel group, (SP # 1-2, SP # 2-2) are implemented as B subpixels in the first pixel group and B subpixels in the second pixel group, and the 1-2 and 2-2 subpixels (SP # 1-3, SP # 2-3) are implemented in the first pixel group to the B subpixel, and the first to third subpixels , R subpixels in the second pixel group, and G subpixels in the third pixel group.

The pixel group constituting the pixel structure 2 of FIG. 13 also includes two gate lines G1 (1) and G1 (2) sequentially arranged in the Y-axis direction and four data lines (D1, D2, D3, D4).

13, the 1-1 subpixel SP # 1-1 is connected between the second data line D2 and the first gate line G1 (1) through the TFT, The sub-pixel SP # 1-2 is connected between the second data line D2 and the second gate line G1 (2) through the TFT, and the first to third sub-pixels SP # And is connected between the first data line D1 and the second gate line G1 (2) through the TFT. Each of the 1-1 subpixel SP # 1-1, the 1-2 subpixel SP # 1-2 and the 1-3 subpixel SP # A G subpixel to which the G data G11 is applied, and a B subpixel to which the B data B11 is applied.

The 2-1 subpixel SP # 2-1 is connected between the third data line D3 and the second gate line G1 (2) through the TFT, and the 2-2 subpixel SP (SP # 2-1) # 2-2 are connected between the fourth data line D4 and the first gate line G1 (1) through the TFT, and the second and third subpixels (SP # 2-3) 3 data line D3 and the first gate line G1 (1). The R 2 data R 12 is applied to the 2-1 subpixel SP # 2-1, the 2-2 subpixel SP # 2-2, and the 2-3 subpixel SP # A G subpixel to which the G data G12 is applied, and a B subpixel to which the B data B12 is applied.

Although the pixel group constituting the pixel structure 2 may be repeated in units of one pixel group as shown in FIG. 13, it is more preferable that the pixel group is repeated in units of three pixel groups as shown in FIG. 14 in view of picture quality compensation. 14, R subpixels, G subpixels, and B subpixels are all included in each subpixel array line extending in the direction of the horizontal axis X and the vertical axis Y, to be.

Referring to FIG. 14, each of the 1-1 to 2-3 sub-pixels SP # 1-1 to SP # 2-3 is different in three pixel groups arranged adjacent to each other in the Y-axis direction And is implemented as a sub-pixel for color display. For example, the 1-1 and 2-1 subpixels (SP # 1-1 and SP # 2-1) are divided into R sub-pixels in the first pixel group, G sub-pixels in the second pixel group, (SP # 1-2, SP # 2-2) are implemented as B subpixels in the first pixel group and B subpixels in the second pixel group, and the 1-2 and 2-2 subpixels (SP # 1-3, SP # 2-3) are implemented in the first pixel group to the B subpixel, and the first to third subpixels , R subpixels in the second pixel group, and G subpixels in the third pixel group.

15 shows an internal configuration of the timing controller 11 for mapping data in accordance with the unit pixel arrangement configuration of the liquid crystal display panel 10. In FIG. 16 shows the data enable signal DE and the internal data enable signal Internal DE in contrast to each other. 17 and 18 show examples of data mapping for pixel configurations 1 and 2 of the present invention.

Referring to FIG. 15, the timing controller 11 includes a line memory 111, a timing signal modulator 112, and a data aligner 113.

The line memory 111 stores the digital video data RGB supplied from the system in units of one horizontal line, and sequentially supplies the data of the stored horizontal lines to the data alignment unit 113. Here, one horizontal line means the amount of data to be supplied to unit pixels (composed of three sub-pixels) arranged in one row along the horizontal axis (X) direction.

The timing signal modulator 112 multiplies the data enable signal DE supplied from the system as shown in FIG. 16 to generate an internal data enable signal Internal DE and then outputs the internal data enable signal Internal DE, To the data sorting unit (113). The internal data enable signal Internal DE is twice as fast as the data enable signal DE.

The data sorting section 113 outputs the data of one horizontal line inputted from the line memory 111 in synchronization with the data enable signal DE to the internal data enable signal Internal DE from the timing signal modulating section 112 , And supplies the mapped data (RGB) to the data driving circuit 12 after mapping the pixel data to the subpixels of the pixel configuration 1 or the pixel configuration 2.

For example, the data of the first horizontal line segment HL # a is input to the pixel structure 1 as shown in FIGS. 7 and 11 in synchronization with #a (a is a positive integer) of the data enable signal DE The data sorting section 113 outputs the data Ra1 of the input horizontal line segment HL # a using # a-1 of the internal data enable signal Internal DE as shown in FIG. 17 (B) (Ra1, Ga1, Ba2, Ra3, Ga3) of the a-1 horizontal line component (HL # a-1) from the Ga1, Ba1, Ra2, Ga2, Ba2, Ra3, Ga3, Ba3, Ra4, Ba1 and Ra4 of the input horizontal line segment HL # a are obtained by using the internal data enable signal Internal DE of # a-2, and the data Ra1, Ga1, Ba1, Ra2, (Ba1, Ra2, Ga2, Ba3, Ra4, Ga4) of the a-2 horizontal line component HL # a-2 are separated and rearranged from the Ga1, Ga2, Ba2, Ra3, Ga3, Ba3, Ra4, Ga4, Thereby mapping the subpixels of the pixel group constituting the pixel structure 1. [

When data of the first to third horizontal line segments HL # 1 to HL # 3 are input in synchronization with # 1 of the data enable signal DE with respect to the pixel configuration 1 as shown in FIGS. 8 and 12, , The data rearranging unit 113 outputs the data of the input first horizontal line HL # 1 (R11, G11) using # 1-1 of the internal data enable signal Internal DE as shown in FIG. 18 (B) R11, G11, B12, R13, G13, and B14 of the 1-1 horizontal line segment (HL # 1-1) from the horizontal line segment (HL # 1-1), B11, R12, G12, B12, R13, G13, B13, And the data R11, G11, B11, R12, G12, ... of the input first horizontal line portion HL # 1 by using the internal data enable signal Internal DE # 1-2. B12, R13, G13, B13, R14, G14, and B14 of the first horizontal line segment (HL # 1-2) To the subpixels of the first group of pixels constituting the pixel configuration 1. The data rearrangement unit 113 rearranges the data of the input second horizontal line (HL # 2) (R21, R22) by using # 2-1 of the internal data enable signal Internal DE as shown in (B) B21, R22, G23, B23, and B22 of the 2-1th horizontal line component (HL # 2-1) from the first horizontal line segment (G1, G2, G21, B21, R22, G22, B22, R23, G23, B23, R21, G21, B21, R22, and G22 of the input second horizontal line (HL # 2) using # 2-2 of the internal data enable signal (Internal DE) , The data R21, G22, B22, R23, G24, and B24 of the second-2 horizontal line component HL # 2-2 are rearranged and rearranged from the first horizontal line segment HL2-2, B22, R23, G23, B23, R24, G24, To the subpixels of the second group of pixels constituting the pixel structure 1. The data rearrangement unit 113 rearranges the data of the input third horizontal line HL # 3 (R31, R32) by using # 3-1 of the internal data enable signal Internal DE as shown in (B) R31, G32, B33, R33, B33, R33, R33, R33, R33, G31, B31, R32, and G32 of the input third horizontal line (HL # 3) using # 3-2 of the internal data enable signal (Internal DE) B32, R32, G33, B34, and R34 of the 3-2 horizontal line segment (HL # 3-2) are rearranged and rearranged from the horizontal lines (B32, R33, G33, B33, R34, G34, To the subpixels of the third group of pixels constituting the pixel configuration 1. The data alignment in Fig. 17B includes only RGB-BRG, while the data alignment in Fig. 18B includes RGB-BRG, GBR-RGB, and BRG-GBR.

9 and 13, the data of the horizontal line segment (HL # a) is input in synchronization with #a (a is a positive integer) of the data enable signal DE The data sorting unit 113 uses the data a1 of the internal data enable signal Internal DE as the data Ra1 of the input line horizontal line HL # a as shown in Figure 17C, (Ra1, Ba2, Ga2, Ra3, Ba4) of the (a-1) th horizontal line segment HL # a-1 from the Ga1, Ba1, Ra2, Ga2, Ba2, Ra3, Ga3, Ba3, Ra4, Ga4, Ga1, Ba1, Ra2, and Ga4 of the input horizontal line segment HL # a using # a-2 of the internal data enable signal Internal DE, (Ba1, Ga1, Ra2, Ba3, Ga3, Ga4) of the a-2 horizontal line component HL # a-2 are separated from the first line segment Ga2, Ba2, Ra3, Ga3, Ba3, Ra4, Ga4, To the subpixels of the pixel group constituting the pixel structure 2. [

When data of the first to third horizontal line segments HL # 1 to HL # 3 are input in synchronization with # 1 of the data enable signal DE with respect to the pixel configuration 2 as shown in FIGS. 10 and 14 , The data rearranging section 113 outputs the data (R11, G11) of the input first horizontal line component HL # 1 using # 1-1 of the internal data enable signal Internal DE as shown in (C) B12, G12, R13, B14, and G14 of the 1-1 horizontal line segment (HL # 1-1) from the horizontal line segment (HL # 1-1), B11, R12, G12, B12, R13, G13, B13, And the data R11, G11, B11, R12, G12, ... of the input first horizontal line portion HL # 1 by using the internal data enable signal Internal DE # 1-2. B11, G11, R12, B13, G13 and R14 of the first and second horizontal line segments (HL # 1-2) are rearranged and rearranged from the horizontal lines B12, R13, G13, B13, R14, G14, To the subpixels of the first group of pixels constituting the pixel structure 2. The data rearrangement unit 113 rearranges the data of the input second horizontal line (HL # 2) (R21, R22) by using # 2-1 of the internal data enable signal (Internal DE) R22, B22, G23, R24, and B22 of the 2-1th horizontal line component (HL # 2-1) from the first line segment G21, B21, R22, G22, B22, R23, G23, B23, B21, B21, R22, and G22 of the input second horizontal line (HL # 2) using # 2-2 of the internal data enable signal (Internal DE) B21, G22, R23, B23, and G24 of the second -2 horizontal line segment (HL # 2-2) are rearranged and rearranged from the first horizontal line segment (HL # 2-2), B22, R23, G23, B23, R24, G24, To the subpixels of the second group of pixels constituting the pixel structure 2. The data rearrangement unit 113 rearranges the data of the input third horizontal line HL # 3 (R31, R32) by using # 3-1 of the internal data enable signal Internal DE as shown in (C) G31, G32, R32, B33, G34, and B34 of the 3-1th horizontal line component (HL # 3-1) R31 and R32 of the input third horizontal line HL # 3 by using the internal data enable signal Internal DE # 3-2. , The data (G31, R31, B32, G33, R33, B34) of the 3-2 horizontal line segment (HL # 3-2) are rearranged from the B32, R33, G33, B33, R34, To the subpixels of the third group of pixels constituting the pixel structure 2. The data alignment in Fig. 17C includes only RBG-BGR, while the data alignment in Fig. 18C includes RBG-BGR, GRB-RBG, and BGR-GRB.

As described above, the liquid crystal display device according to the present invention overcomes the problems of the conventional DRD driving method by the structural features of the pixel configuration and the layout, thereby effectively reducing the number of source driver ICs without causing vertical line dim .

Further, in the liquid crystal display device according to the present invention, the horizontal width of the subpixel is wider than the vertical width, thereby increasing the number of opening blocks in the subpixel, thereby increasing the overall aperture ratio of the panel.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: liquid crystal display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
111: line memory 112: timing signal modulation section
113:

Claims (17)

A liquid crystal display panel in which a plurality of pixel groups each including a neighboring first unit pixel and a second unit pixel are arranged; And
And a timing controller for aligning the input digital video data in accordance with the pixel arrangement of each of the pixel groups;
Wherein the first unit pixel and the second unit pixel each have three subpixels;
When two subpixels of the first unit pixel and one subpixel of the second unit pixel are arranged in the first line, the remaining one subpixel of the first unit pixel and the remaining two subpixels of the second unit pixel The subpixel is disposed in the second line adjacent to the first line,
When one subpixel of the first unit pixel and two subpixels of the second unit pixel are arranged in the first line, the remaining two subpixels of the first unit pixel and the remaining one One sub-pixel is disposed in the second line,
Each of the subpixels has a lateral width in a horizontal direction in which a gate line extends and a vertical width in a vertical direction in which the data lines extend;
And the first and second gate lines sequentially arranged in the vertical direction are assigned to the pixel groups. The method according to claim 1,
Wherein a width-to-width ratio of each of the subpixels is 2: 1.5. The method according to claim 1,
Wherein each of the pixel groups is assigned first to third data lines sequentially arranged in the horizontal direction;
And the TFTs connected to the sub-pixels are arranged in one row in the horizontal axis and the vertical axis direction. The method of claim 3,
The first unit pixel is arranged in a "?"Shape including a 1-1 subpixel, a 1-2 subpixel, and a 1-3 subpixel;
Wherein the second unit pixel includes a 2-1 subpixel, a 2-2 subpixel, and a 2-3 subpixel, and is arranged in a "?" Shape. 5. The method of claim 4,
The first sub-pixel is connected to the first data line and the first gate line through a TFT;
The 1-2 sub-pixel is connected to the second data line and the first gate line through a TFT;
The first sub-pixel is connected to the first data line and the second gate line through a TFT;
The second -1 subpixel is connected to the second data line and the second gate line via a TFT;
The second -2 subpixel is connected to the third data line and the second gate line via a TFT;
And the second sub-pixel is connected to the third data line and the first gate line through a TFT. The method of claim 3,
The first unit pixel is arranged in a "?" Shape including a 1-1 subpixel, a 1-2 subpixel, and a 1-3 subpixel;
And the second unit pixel is arranged in a "┐" shape including the 2-1 subpixel, the 2-2 subpixel, and the 2-3 subpixel. The method according to claim 6,
The first sub-pixel is connected to the first data line and the first gate line through a TFT;
The first sub-pixel is connected to the second data line and the second gate line via a TFT;
The first sub-pixel is connected to the first data line and the second gate line through a TFT;
The second -1 sub-pixel is connected to the third data line and the second gate line via a TFT;
The second -2 subpixel is connected to the third data line and the first gate line via a TFT;
And the second sub-pixel is connected to the second data line and the first gate line through a TFT. The method according to claim 5 or 7,
Wherein the 1-1 and 2-1 sub-pixels are R (red) subpixels, the 1-2 and 2-2 subpixels are G (green) subpixels, the 1-3 & And the -3 sub-pixels are B (blue) sub-pixels. 9. The method of claim 8,
The first 1-1 subpixel is implemented as a subpixel for displaying different colors in three groups of pixels arranged next to each other in the vertical direction, The first to third subpixels are implemented as subpixels for displaying different colors in the three pixel groups;
The 2 < nd > -1 subpixel is implemented as a subpixel for displaying different colors in the 3 pixel groups, and the 2-2 subpixel is implemented as a subpixel And the second and third subpixels are implemented as subpixels for displaying different colors in the three pixel groups. The method according to claim 1,
Wherein each of the pixel groups is assigned first to fourth data lines sequentially arranged in the horizontal direction;
And the TFTs connected to the subpixels are arranged in a row in the horizontal direction and arranged in a jig in the vertical direction. 11. The method of claim 10,
The first unit pixel is arranged in a "?"Shape including a 1-1 subpixel, a 1-2 subpixel, and a 1-3 subpixel;
Wherein the second unit pixel includes a 2-1 subpixel, a 2-2 subpixel, and a 2-3 subpixel, and is arranged in a "?" Shape. 12. The method of claim 11,
The first sub-pixel is connected to the second data line and the first gate line through a TFT;
The 1-2 sub-pixel is connected to the third data line and the first gate line through a TFT;
The first sub-pixel is connected to the first data line and the second gate line through a TFT;
The second -1 subpixel is connected to the second data line and the second gate line via a TFT;
The second -2 subpixel is connected to the third data line and the second gate line via a TFT;
And the second sub-pixel is connected to the fourth data line and the first gate line through a TFT. 11. The method of claim 10,
The first unit pixel is arranged in a "?" Shape including a 1-1 subpixel, a 1-2 subpixel, and a 1-3 subpixel;
And the second unit pixel is arranged in a "┐" shape including the 2-1 subpixel, the 2-2 subpixel, and the 2-3 subpixel. 14. The method of claim 13,
The first sub-pixel is connected to the second data line and the first gate line through a TFT;
The first sub-pixel is connected to the second data line and the second gate line via a TFT;
The first sub-pixel is connected to the first data line and the second gate line through a TFT;
The second -1 sub-pixel is connected to the third data line and the second gate line via a TFT;
The second -2 subpixel is connected to the fourth data line and the first gate line via a TFT;
And the second sub-pixel is connected to the third data line and the first gate line through a TFT. 15. The method according to claim 12 or 14,
Wherein the 1-1 and 2-1 sub-pixels are R (red) subpixels, the 1-2 and 2-2 subpixels are G (green) subpixels, the 1-3 & And the -3 sub-pixels are B (blue) sub-pixels. 16. The method of claim 15,
The first 1-1 subpixel is implemented as a subpixel for displaying different colors in three groups of pixels arranged next to each other in the vertical direction, The first to third subpixels are implemented as subpixels for displaying different colors in the three pixel groups;
The 2 < nd > -1 subpixel is implemented as a subpixel for displaying different colors in the 3 pixel groups, and the 2-2 subpixel is implemented as a subpixel And the second and third subpixels are implemented as subpixels for displaying different colors in the three pixel groups. The method of claim 1, wherein
The timing controller includes:
A line memory for storing the input digital video data for one horizontal line and sequentially outputting data of the stored horizontal lines;
A timing signal modulator for modulating an externally input data enable signal to generate and output an internal data enable signal whose frequency is two times faster than the data enable signal; And
The data of one horizontal line input from the line memory in synchronism with the data enable signal is separated and rearranged based on an internal data enable signal from the timing signal modulating unit so that pixel arrangement of each of the pixel groups And a data arrangement unit for mapping the data to be displayed in accordance with the configuration.

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