KR102169032B1 - Display device - Google Patents

Abstract

In the present invention, a pixel array in a display device is divided into a plurality of first and second pixel blocks arranged in a chess shape. The polarities of the data voltages charged in the white and green subpixels are opposite to each other in the first pixel block and the second pixel block. The output terminal of the last even-th buffer connected to the m/2-th output channel of the data driver is connected to the rightmost odd-numbered switch element, the rightmost even-numbered switch element, and the dummy switch element of the multiplexer.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device in which each of the pixels is divided into a red (R) subpixel, a green (G) subpixel, a blue (B) subpixel, and a white (W) subpixel. will be.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices such as are being developed. The liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. In an active matrix driving type liquid crystal display device, a thin film transistor (hereinafter referred to as "TFT") is formed for each pixel.

In addition to the red (red, R) sub-pixels, green (G) sub-pixels, and blue (blue, B) sub-pixels, display devices in which white and W sub-pixels are added to each of the pixels are being developed. Hereinafter, a display device in which pixels are divided into RGBW sub-pixels is referred to as a "RGBW type display device". When the W sub-pixel is added to the pixels in the liquid crystal display, the luminance of the RGB sub-pixel and the luminance of the backlight unit can be lowered by the luminance of the W sub-pixel, thereby reducing power consumption of the liquid crystal display.

In the display device, when an observer moves according to a color arrangement and a polarity arrangement of pixels, a difference in luminance of pixels displaying data of the same gray scale may be felt. In particular, in the RGBW type display device, the observer feels the change in luminance of the W sub-pixel and the G sub-pixel more sensitively than other colors.

The present invention provides a display device in which an observer does not feel a difference in luminance of pixels displaying data of the same gray scale in a display device having subpixels of 4 colors.

The display device of the present invention includes a pixel array in which m+1 (m is an even number greater than 8) data lines and a plurality of gate lines cross each other and a plurality of sub-pixels are disposed; A plurality of odd-numbered buffers each including m/2 output channels including a buffer and outputting a data voltage of a first polarity through odd-numbered output channels, and a data voltage of a second polarity through even-numbered output channels. A data driver including a plurality of even-th buffers to output; And a multiplexer connecting m/2 output channels of the data driver to the m+1 data lines.
The multiplexer includes: a plurality of odd-numbered switch elements connecting output channels of the data driver to odd-numbered data lines in response to a pulse of a first control signal; A plurality of even-numbered switch elements connecting output channels of the data driver to even-numbered data lines in response to a pulse of a second control signal generated following the pulse of the first control signal; And a dummy switch element connected to a dummy data line positioned to the left of the first data line in the pixel array.
The output terminal of the last even-th buffer connected to the m/2-th output channel of the data driver is connected to the rightmost odd-numbered switch element, the rightmost even-numbered switch element, and the dummy switch element of the multiplexer.
The subpixels of the pixel array are divided into a plurality of first pixel blocks and a plurality of second pixel blocks arranged in a chess shape on the pixel array. The first pixel block includes white and green subpixels to which the data voltage of the first polarity is applied. The second pixel block includes white and green subpixels to which the data voltage of the second polarity is applied.

The display device of the present invention disperses the difference in brightness due to the difference in polarity by making the polarities of the white and green data voltages opposite between the pixel groups arranged in the form of chess, so that the viewer does not feel the difference in brightness when the viewer moves. As a result, the display device of the present invention can improve the display quality having sub-pixels of 4 colors.

1 is a block diagram showing a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a pixel array in which a difference in luminance can be felt in the same gray scale when an observer moves.
3 is a diagram showing a difference in perceived luminance for each color.
4 is a diagram showing a difference between a data voltage and a common voltage between polarities.
5 and 6 are circuit diagrams showing a multiplexer and a pixel array according to the first embodiment of the present invention.
7A and 7B are waveform diagrams showing an operation of a multiplexer and a pixel array according to the first embodiment of the present invention.
8 is a circuit diagram showing a multiplexer and a pixel array according to a second embodiment of the present invention.
9 is a waveform diagram showing an operation of a multiplexer and a pixel array according to a second embodiment of the present invention.

The display device of the present invention may be implemented as a flat panel display device capable of implementing colors such as a liquid crystal display (LCD), an organic light emitting diode display (OLED display), and a plasma display panel (PDP). Hereinafter, embodiments of the present invention will be described centering on a liquid crystal display device, but it should be noted that the present invention is not limited to the liquid crystal display device. For example, the arrangement of RGBW sub-pixels of the present invention is applicable to an organic light emitting diode display.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

Referring to FIG. 1, the display device of the present invention includes a display panel 100 on which a pixel array is formed, and a display panel driving circuit for writing data of an input image to the display panel 100. A backlight unit for uniformly irradiating light to the display panel 100 may be disposed under the display panel 100.

The display panel 100 includes an upper substrate and a lower substrate facing each other with a liquid crystal layer therebetween. The pixel array of the display panel 100 includes pixels arranged in a matrix form by a cross structure of data lines S0 to Sm and gate lines G1 to Gn.

The lower substrate of the display panel 100 includes data lines S0 to Sm, gate lines G1 to Gn, TFTs, a pixel electrode 1 connected to the TFT, and a storage connected to the pixel electrode 1 Includes a capacitor (Storage Capacitor, Cst).

Each of the pixels of the pixel array may be divided into an R sub-pixel, a G sub-pixel, a B sub-pixel, and a W sub-pixel. Each of the sub-pixels uses liquid crystal molecules driven by a voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied to determine the amount of light transmitted. Adjust.

TFTs formed on the lower substrate of the display panel 100 may be implemented as an amorphose Si (a-Si) TFT, a Low Temperature Poly Silicon (LTPS) TFT, an oxide TFT, or the like. The TFTs are connected 1:1 to the pixel electrode 1 of the sub pixels.

A color filter array including a black matrix (BM) and a color filter is formed on the upper substrate of the display panel 100. The common electrode 2 is formed on the upper substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) In the case of a horizontal electric field driving method such as a mode, it may be formed on the lower substrate together with the pixel electrode. A polarizing plate is attached to each of the upper and lower substrates of the display panel 100 and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The display device of the present invention may be implemented in any form such as a transmissive liquid crystal display, a transflective liquid crystal display, and a reflective liquid crystal display. Transmissive liquid crystal display devices and transflective liquid crystal display devices require a backlight unit. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel driving circuit writes data of an input image to pixels. Data written to the pixels includes R data, G data, B data and W data. The display panel driving circuit includes a data driver 102, a gate driver 104, and a timing controller 106. A multiplexer 103 may be disposed between the data driver 102 and the data lines S0 to Sm.

The data driver 102 includes a plurality of source drive integrated circuits ("IC"). In order to reduce the cost of the display device, a multiplexer (MUX) may be disposed between the source drive IC and data lines of the display panel. The multiplexer (MUX) time-divisions the data voltage output from the source drive IC and distributes it to the data lines, thereby reducing the number of source drive ICs required for driving the display panel.

Output channels of the source drive ICs may be connected to the data lines S0 to Sm through the multiplexer 103. The source drive ICs receive data of an input image from the timing controller 106. The digital video data transmitted to the source drive ICs includes R data, G data, B data, and W data. The source drive ICs convert RGBW digital video data of an input image into a positive/negative gamma compensation voltage under the control of the timing controller 106 and output a positive/negative data voltage. The output voltages of the source drive ICs are supplied to the data lines S0 to Sm.

Each of the source drive ICs inverts the polarities of data voltages to be supplied to the pixels under the control of the timing controller 106 and outputs them to the data lines S0 to Sm. The source drive IC can reverse the polarity of the data voltage by using a column inversion method. The column inversion method does not reverse polarities of data voltages applied to pixels through the same data line during one frame period, but reversely reverses the polarities of data voltages applied through neighboring data lines. For example, in the column inversion method, the polarity of the data voltage supplied through the first data line is maintained at the first polarity during the first frame period, and then inverted to the second polarity during the second frame period. Maintain the same polarity. The polarity of the data voltage supplied through the second data line is maintained at the second polarity during the first frame period, and then inverted to the first polarity during the second frame period, thereby maintaining the same polarity during the first frame period. If the polarity of the data voltage output from the source drive IC is inverted by the column inversion method, since the swing width of the data voltage is small and the number of transitions is small, the amount of current in the source drive IC can be reduced, thereby reducing power consumption and heat generation. The data voltages output from the source drive ICs maintain the same polarity for each data line, but the polarity of the pixel array is inverted by dot inversion.

The multiplexer 103 supplies the data voltage input from the source drive IC in time division to the data lines S0 to Sm under the control of the timing controller 106. In the case of a 1:2 multiplexer, the multiplexer time-divisions the data voltage input through one output channel of the source drive IC and supplies it to two data lines. Therefore, if the 1:2 multiplexer is used, the number of source drive ICs required to drive the display panel 100 can be reduced to 1/2. The multiplexer 103 may be built into the source drive IC.

The gate driver 104 supplies gate pulses to the gate lines G1 to Gn under the control of the timing controller 106.

The timing controller 106 converts RGB data of an input image received from the host system 110 into RGBW data and transmits the converted RGB data to the data driver 102. The timing controller 106 receives timing signals synchronized with data of an input image from the host system 110. The timing signals include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a main clock (DCLK). The timing controller 106 controls the operation timing of the data driver 102, the gate driver 104, and the multiplexer 103 based on the timing signals Vsync, Hsync, DE, and DCLK to synchronize the circuits. The timing controller 106 may transmit a polarity control signal POL for controlling the polarity of the pixel array to each of the source drive ICs of the data driver 102.

The host system 110 may be any one of a TV (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

FIG. 2 is a diagram illustrating an example of a pixel array in which a difference in luminance can be felt in the same gray scale when an observer moves. 3 is a diagram showing a difference in perceived luminance for each color. 4 is a diagram showing a difference between a data voltage and a common voltage between polarities. In Fig. 2, "OUT1 to OUT6" are output channels of the source drive IC. Amp(-) is a buffer amplifier connected to the output channels OUT1 to OUT6 of the source drive IC, and supplies a negative data voltage to the multiplexer 103. Amp(+) is a buffer amplifier connected to the output channels OUT1 to OUT6 of the source drive IC, and supplies a positive data voltage to the multiplexer 103.

2 to 4, the multiplexer MUX includes switches T1 that are alternately turned on according to first and second control signals M1 and M2 from the timing controller 106. , T2), the data voltage output from the source drive IC is time-divided and distributed to the data lines S1 to S12.

In all the horizontal lines L1 to L9 of the pixel array, each of the RGBW sub-pixels may be connected to the data lines S1 to S12 in the same form as shown in FIG. 2. As shown in FIG. 2, when the multiplexer (MUX) and data lines of the pixel array are connected, the polarities of the W sub-pixel and the G sub-pixel are reversed in units of four vertical lines. For example, all W and G sub-pixels connected to the second and fourth data lines S2 and S4 charge the positive data voltages +W and +G during the first frame period, and then the second frame During the period, the negative data voltages (-W, -G) are charged. Conversely, all W and G sub-pixels connected to the sixth and eighth data lines S6 and S8 charge the negative data voltages -W and -G during the first frame period, and then during the second frame period. Charges the positive data voltage (+W, +G).

In the RGBW sub-pixels, the luminance ratio of the W sub-pixel is 100%. Among the RGB sub-pixels, the perceived luminance ratio felt by the observer is R:G:B = 2:7:1. Accordingly, the change in luminance of the W sub-pixel and G sub-pixel perceived by the observer is more sensitive than the R sub-pixel and B sub-pixel. In particular, when the pixels having the opposite polarities of the W and G sub-pixels are arranged in a stripe shape as shown in FIG. 2, when the observer moves, the difference in luminance of the pixels is more easily recognized even in the same gray scale.

As shown in FIG. 4, the data voltage is a positive data voltage higher than the common voltage Vcom and a negative data voltage lower than the common voltage Vcom. In FIG. 4, GMA(A) is a positive gamma reference voltage corresponding to the positive data voltage of the highest gray scale. P(A) and P(B) are positive data voltages. GMA(A') is a negative gamma reference voltage corresponding to the negative data voltage of the highest gray scale. N(A) and N(B) are positive data voltages.

The common voltage Vcom is optimized to Vcom(A) so that the voltage of the liquid crystal cell is the same in the positive data voltage and the negative data voltage in the same gray scale.

Depending on the data pattern of the input image, the common voltage Vcom may be shifted or the common voltage Vcom may be changed due to ripple. In this case, the difference between the positive and negative data voltages in the liquid crystal cell is as large as twice the common voltage deviation (ΔVcom), and as a result, a difference in luminance of the pixels can be recognized even in the same gray scale.

4, GMA(A)-Vcom(A) = P(A), Vcom(A) -GAM(A') = N(A), and the voltage difference between P(A) and N(A) is the same. When, if Vcom(A) changes to Vcom(B).

P(A)-ΔVcom = P(B),

N(A) + ΔVcom = N(B). Therefore, since N(B) = P(B) + 2Vcom, when the common voltage Vcom changes, the data voltage deviation between polarities increases by twice the common voltage deviation ΔVcom.

In the present invention, as shown in FIGS. 5 and 8, the connection positions of pixels and data lines are shifted in a zigzag form in units of N (N is a positive integer of 1 or more and 4 or less) horizontal lines in a pixel array. Accordingly, a first pixel block in which a data voltage of a first polarity is charged to W and G subpixels having a high luminance ratio, and a second pixel block in which a data voltage of a second polarity is charged to the W and G subpixels, respectively The size of is reduced, and pixel blocks are alternately arranged to disperse the luminance difference due to the polarity difference of the data voltage. Accordingly, the present invention provides an RGBW type display device in which a data voltage is supplied to data lines of a pixel array through a multiplexer and the data voltage is inverted by a column inversion method, when the luminance difference is distributed in pixel blocks and the observer moves. It prevents you from feeling a difference in luminance in the same gradation.

5 and 6 are circuit diagrams showing a multiplexer and a pixel array according to the first embodiment of the present invention. 7A and 7B are waveform diagrams showing an operation of a multiplexer and a pixel array according to the first embodiment of the present invention. 5 to 7B, "OUT1 to OUT6" are output channels of the source drive IC. Amp(-) is a buffer amplifier connected to the output channels OUT1 to OUT6 of the source drive IC, and supplies a negative data voltage to the multiplexer 103. Amp(+) is a buffer amplifier connected to the output channels OUT1 to OUT6 of the source drive IC, and supplies a positive data voltage to the multiplexer 103.

5 to 7B, negative data voltages are output through the first, fourth, and fifth output channels OUT1, OUT4, and OUT5 of the source drive IC, and the second, third, and The negative data voltage is output through the sixth output channels OUT2, OUT3, and OUT6. The gate pulse is sequentially applied to the gate lines G1 to G9 from the first gate line G1 in synchronization with the data voltage.

The multiplexer MUX includes a plurality of switches T0 and T1 to T4. Control signals M1 and M2 are supplied to gates of the switches T0 to T4. The drains of the switches T0 to T4 are connected to the output channels OUT1 to OUT6 of the source drive IC, and the sources are connected to the data lines S0 to S12.

The multiplexer MUX time-divisions the data voltage output from the source drive IC according to the first and second control signals M1 and M2 from the timing controller 106 and distributes it to the data lines S0 to S12. The first and second control signals M1 and M2 are generated out of phase with each other. That is, the phase of the second control signal M2 is delayed by 180° compared to the first control signal M1. As a method of inverting the first control signal M1 with an inverter, a second control signal M2 may be generated. The switching period of the first and second control signals M1 and M2 is one horizontal period 1H. One horizontal period 1H is a time required to write data to pixels arranged on one horizontal line of the pixel array.

The first switch T1 is connected between the first output channel OUT1 and the first data line S1 to apply a first data voltage from the first output channel OUT1 in response to the first control signal M1. It is supplied to the data line S1. The second switch T2 is connected between the first output channel OUT1 and the third data line S3 to reduce the data voltage from the first output channel OUT1 to a third in response to the second control signal M2. It is supplied to the data line S3. The first and second switches T1 and T2 are alternately turned on.

The third switch T3 is connected between the second output channel OUT2 and the second data line S2 to reduce the data voltage from the second output channel OUT2 to a second in response to the first control signal M1. It is supplied to the data line S2. The fourth switch T4 is connected between the second output channel OUT2 and the fourth data line S4 to adjust the data voltage from the second output channel OUT2 to a fourth in response to the second control signal M2. It is supplied to the data line S4. The third and fourth switches T3 and T4 are alternately turned on.

The dummy switch T0 connects the dummy data line S0 and the m-th data line Sm in response to the second control signal M2. The dummy data line S0 is a data line positioned at the leftmost side of the pixel array. The m-th data line Sm is a data line positioned at the rightmost side of the pixel array. When the dummy switch T0 is turned on, it is connected to the m-th data line Sm through the dummy data line S0, the dummy switch T0, the routing line RL, and the fourth switch T4 on the rightmost side. do.

The second and third switches T2 and T3 and the second and third data lines S2 and S3 are alternately connected to each other. To this end, link wirings connecting the second and third switches T2 and T3 to the second and third data lines S2 and S3 are crossed with an insulating layer therebetween. Since the second switch T2 is connected to the third data line S3 and the third switch T3 is connected to the second data line S2, the polarity of the data voltage charged to the pixels arranged on the horizontal line is It is inverted in the form of dot inversion. Here, a dot has the same meaning as 1 sub-pixel.

In the even-th horizontal lines L2, L4, and L6, the colors of the sub-filters are arranged in the order of a first color, a second color, a third color, and a fourth color from the left. In the odd-numbered horizontal lines L1, L3, and L5, the colors of the sub-filters are arranged in the order of a third color, a fourth color, a first color, and a second color from the left. In the example of FIG. 5, the first color is red (R), the second color is green (G), the third color is blue (B), and the fourth color is white (W), but the present invention is not limited thereto. For example, the color arrangement of odd-numbered horizontal lines L1, L3, and L5 and even-numbered horizontal lines L2, L4, and L6 may be changed.

In the 8M (M is a positive integer of 0) + 1 and 8M + 5 vertical lines (C1, C5), the color of the sub-filter is from the top to the third color (B), the first color (R), and the third They are arranged in the order of color (B) and first color (R). In the 8M+2 and 8M+6 vertical lines (C2, C6), the color of the sub-filter is from the top to the fourth color (W), the second color (G), the fourth color (W), and the second color ( G) They are arranged in order. In the 8M+3 and 8M+7 vertical lines (C3, C7), the color of the sub-filter is from the top to the first color (R), the third color (B), the first color (R), and the third color ( B) They are arranged in order. In the 8M+4 and 8M+8 vertical lines (C4, C8), the color of the sub-filter is from the top to the second color (G), the fourth color (W), the second color (G), and the fourth color ( W) are arranged in order. The pixel polarities of the 8M+1 to 8M+4 vertical lines C1 to C4 are opposite to the 8M+5 to 8M+8 vertical lines C5 to C8.

Pixels of the pixel array are connected in a zigzag form to neighboring data lines in units of three horizontal lines. For example, the pixel electrode 1 of pixels belonging to the 6Mth (M is a positive integer of 0) +1 to 6M+3 horizontal lines (L1 to L3) is data located on its right side through the TFT It is connected to the lines S1 to Sm. The pixel electrodes 1 of pixels belonging to the 6M+4 to 6M+6 horizontal lines L4 to L6 are connected to the data lines S0 to Sm-1 located on their left through TFTs. As a result, the first pixel block 51 and the second pixel block 52 are alternately arranged in the horizontal direction (x) and the vertical direction (y). Each of the first and second pixel blocks 51 and 52 has a size including 4×3 pixels. Accordingly, in the present invention, since the first and second pixel blocks 51 and 52 of small size are alternately arranged in the form of a chess, the observer does not feel a difference in luminance in the same grayscale when moving.

The first pixel block 51 includes sub-pixels of second and fourth colors G and W to which the positive data voltage is charged. In addition, the first pixel block 51 includes subpixels of first and third colors R and B to which the negative data voltage is charged. The second pixel block 52 includes sub-pixels of second and fourth colors G and W to which the negative data voltage is charged. In addition, the second pixel block 52 includes subpixels of first and third colors R and B to which the positive data voltage is charged. Accordingly, the first and second pixel blocks 51 and 52 include subpixels of first to fourth colors, and polarities of data voltages in the same color are opposite to each other.

8 is a circuit diagram showing a multiplexer and a pixel array according to a second embodiment of the present invention. 9 are waveform diagrams showing an operation of a multiplexer and a pixel array according to a second embodiment of the present invention.

8 and 9, pixels of a pixel array are connected to neighboring data lines in a zigzag form. For example, the pixel electrode 1 of the pixels belonging to the first, third, fourth and sixth horizontal lines L1, L3, L4, and L6 is a data line S0 located on its left side through a TFT. It is connected to ~Sm-1). The pixel electrodes 1 of pixels belonging to the second and sixth horizontal lines L2 and L6 are connected to the data lines S1 to Sm located on the right side of the pixels through the TFT. As a result, the first pixel block 81 and the second pixel block 82 are alternately arranged in the horizontal direction (x) and the vertical direction (y). Each of the first and second pixel blocks 81 and 82 has a size including 4×1 pixels. Accordingly, in the present invention, since the first and second pixel blocks 81 and 82 of small size are alternately arranged in a chess shape, the difference in luminance is dispersed.

The first pixel block 81 includes subpixels of second and fourth colors G and W to which the positive data voltage is charged. In addition, the first pixel block 81 includes subpixels of the first color R to which the positive data voltage is charged, and subpixels of the third color (B) to which the negative data voltage is charged. The second pixel block 52 includes sub-pixels of second and fourth colors G and W to which the negative data voltage is charged. In addition, the second pixel block 52 includes subpixels of the first color R to which the negative data voltage is charged, and subpixels of the third color (B) to which the positive data voltage is charged.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

100: display panel 102: data driver
103: multiplexer 104: gate driver
106: timing controller 110: host system

Claims (10)

a pixel array in which m+1 (m is an even number greater than 8) data lines and a plurality of gate lines cross each other and a plurality of sub-pixels are disposed;
A plurality of odd-numbered buffers each including m/2 output channels including a buffer and outputting a data voltage of a first polarity through odd-numbered output channels, and a data voltage of a second polarity through even-numbered output channels. A data driver including a plurality of even-th buffers to output; And
A multiplexer connecting m/2 output channels of the data driver to the m+1 data lines,
The multiplexer
A plurality of odd-numbered switch elements connecting output channels of the data driver to odd-numbered data lines in response to a pulse of a first control signal;
A plurality of even-numbered switch elements connecting output channels of the data driver to even-numbered data lines in response to a pulse of a second control signal generated following the pulse of the first control signal; And
A dummy switch element connected to a dummy data line positioned on the left side of the first data line in the pixel array,
An output terminal of the last even-th buffer connected to the m/2th output channel of the data driver is connected to the rightmost odd-numbered switch element, the rightmost even-numbered switch element, and the dummy switch element of the multiplexer,
The sub-pixels of the pixel array are divided into a plurality of first pixel blocks and a plurality of second pixel blocks arranged in a chess shape on the pixel array,
The first pixel block includes white and green subpixels to which the data voltage of the first polarity is applied,
The second pixel block includes white and green subpixels to which the data voltage of the second polarity is applied. The method of claim 1,
In the pixel array,
A display device in which the connection positions of the sub-pixels and data lines are shifted in a zigzag form in units of N (N is a positive integer of 1 or more and 4 or less) horizontal lines. The method of claim 2,
Pixel electrodes of the subpixels belonging to the 6Nth (N is a positive integer of 0) +1 to 6N+3 horizontal lines are connected to a data line located on the right side of the subpixels through a thin film transistor (TFT),
A display device in which pixel electrodes of the sub-pixels belonging to 6N+4 to 6N+6th horizontal lines are connected to a data line positioned on the left side of the subpixel through a thin film transistor. The method of claim 3,
Each of the first and second pixel blocks has a size including 4×3 subpixels. The method of claim 2,
Pixel electrodes of the sub-pixels belonging to odd-numbered horizontal lines are connected to a data line positioned on the left side of the sub-pixels through a thin film transistor (TFT),
A display device in which pixel electrodes of the sub-pixels belonging to even-th horizontal lines are connected to a data line positioned on the right side of the sub-pixels through a thin film transistor. The method of claim 5,
Each of the first and second pixel blocks has a size including 4×1 subpixels. delete The method of claim 1,
Each of the buffers other than the last even-th buffer is connected to one odd-numbered switch element and one even-numbered switch element excluding the dummy data line. The method of claim 1,
The display device further comprising a routing line connecting the output terminal of the last even-th buffer to the dummy switch element. The method of claim 9,
Each of the switch elements includes a transistor including a gate, a first electrode, and a second electrode,
The dummy switch is
A gate to which the second control signal is applied, a first electrode connected to the routing line, and a second electrode connected to the dummy data line,
The rightmost odd-numbered switch element is
A gate to which the first control signal is applied, a first electrode connected to an output terminal of the last even-th buffer, and a second electrode connected to an m-2th data line,
The rightmost superior switch element,
A display device comprising: a gate to which the second control signal is applied, a first electrode connected to an output terminal of the last even-th buffer, and a second electrode connected to an m-th data line.

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