KR102326168B1 - Display device - Google Patents

Abstract

A display device of the present invention includes a display panel receiving data voltages through first to fourth data lines, a data driver outputting data voltages to first to fourth source channels, and a pad portion connecting the display panel and the data driver. do. The first to fourth source pads are respectively connected to the first to fourth source channels. The first to fourth data pads are respectively connected to the first to fourth data lines. The first link pattern connects the first source pad and the first data pad. The second link pattern overlaps partial regions of the second source pad and the second data pad. The third link pattern overlaps partial regions of the third source pad and the third data pad. The fourth link pattern connects the fourth source pad and the fourth data pad. The fifth link pattern overlaps partial regions of the second source pad and the third data pad. The sixth link pattern overlaps partial regions of the third source pad and the second data pad.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device having a thin film transistor array substrate.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices are being developed. A liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. In an active matrix driving type liquid crystal display device, a thin film transistor (hereinafter, referred to as “TFT”) is formed at the intersection of a data line and a gate line for each pixel.

A liquid crystal display device is a display panel in which pixels are arranged in a matrix form, a backlight unit irradiating light to the display panel, and a source drive integrated circuit (IC) for supplying data voltages to data lines of the display panel. ), a gate drive IC for supplying a gate pulse (or scan pulse) to the gate lines (or scan lines) of the display panel, and a control circuit for controlling the ICs, and a light source driving circuit for driving the light source of the backlight unit etc. are provided. The input image is displayed on the pixel array of the display panel.

The pixels include R (Red) sub-pixels, G (Green) sub-pixels, and B (Blue) sub-pixels for color implementation. The pixels may further include a W (White) sub-pixel in addition to the RGB sub-pixel. The W sub-pixel lowers the luminance of the backlight unit by increasing the luminance of each of the pixels, thereby reducing power consumption of the liquid crystal display. Hereinafter, an RGB-type display device means a display device in which pixels are divided into RGB sub-pixels, and an RGBW-type display device means a display device in which pixels are divided into RGBW sub-pixels.

Since the arrangement of each color pixel is different between the RGBW type display device and the RGB type display device, the polarity pattern of the data voltage input to each of them is different in consideration of image quality and power consumption. Therefore, since the RGBW type display device and the RGB type display device each have to use an independent source drive IC, it is difficult to manufacture the display devices of various models in common.

An object of the present invention is to provide a TFT array substrate and a source driver IC that can be applied to both an RGB type display device and an RGBW type display device.

A display device of the present invention includes a display panel receiving data voltages through first to fourth data lines, a data driver outputting data voltages to first to fourth source channels, and a pad portion connecting the display panel and the data driver. do. The first to fourth source pads are respectively connected to the first to fourth source channels. The first to fourth data pads are respectively connected to the first to fourth data lines. The first link pattern connects the first source pad and the first data pad. The second link pattern overlaps partial regions of the second source pad and the second data pad. The third link pattern overlaps partial regions of the third source pad and the third data pad. The fourth link pattern connects the fourth source pad and the fourth data pad. The fifth link pattern overlaps partial regions of the second source pad and the third data pad. The sixth link pattern overlaps partial regions of the third source pad and the second data pad.

The display device of the present invention provides a TFT array substrate that can be applied to two types of display devices through a connection method of a contact hole in a pad part common to an RGBW type display device and an RGB type display device. The display device of the present invention provides a thin film transistor substrate that can be applied to both the RGBW type display device and the RGB type display device. In addition, since the present invention can change the connection structure of the link pattern of the pad part so that the polarity input of the data voltage can be different depending on the RGBW type display device and the RGB type display device, one source drive IC can be used for the RGBW type display device and the RGB type display device. It can be applied to all display devices. In particular, the pad part of the present invention has the same electrode pad and link pattern applied to the RGBW type display device and the RGB type display device, and by simply changing only the mask in the process of etching the passivation layer, the RGBW type display device and the RGB type display device It is possible to implement a link structure of the pad unit that can be applied to all display devices.

1 is a block diagram illustrating a display device according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram illustrating a part of a TFT array substrate of the display panel shown in FIG. 1 .
3 is a diagram illustrating a color arrangement in an RGBW type display device.
4 is a diagram illustrating a color arrangement in an RGB type display device.
5 is a diagram illustrating a source driver IC according to the first embodiment.
6 is a waveform diagram showing a polarity control signal of an RGBW type display device.
FIG. 7 is a diagram illustrating polarities of pixels determined according to a polarity control signal as shown in FIG. 6 .
8 is a diagram illustrating an output of a data voltage in an RGBW type display device.
9 is a schematic diagram illustrating a connection structure of a pad unit in an RGB type display device.
10 is a diagram illustrating an output of a data voltage in an RGB type display device.
11 is a diagram illustrating a source driver IC according to the second embodiment.
12 is a plan view illustrating a pad part according to the first embodiment.
13 is a cross-sectional view illustrating a pad portion taken along line A-A' of FIG. 12 .
14 is a plan view illustrating a pad unit according to a second embodiment.
15 is a cross-sectional view showing a pad portion taken along line A-A' of FIG. 14 .

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Referring to FIG. 1 , the display device of the present invention includes a display panel 100 and a display panel driving circuit for writing input image data to the display panel 100 . A backlight unit for uniformly irradiating light to the display panel 100 may be disposed under the display panel 100 .

In order to reduce the number of source drive ICs, the display is implemented as a double rate driving (DRD) display in which two horizontally adjacent sub-pixels (in the x-axis or row-line direction) share one data line. In the DRD display device, since the number of data lines is reduced, the number of source drive ICs can be reduced by half. In a DRD display, the operating frequency of the source drive IC is doubled.

The display panel 100 includes a TFT array substrate and a color filter array substrate facing each other with a liquid crystal layer interposed therebetween. The display panel 100 includes pixels arranged in a matrix form by a cross structure of data lines S1 to Sm and gate lines G1 to Gn. Each of the pixels is divided into RGB sub-pixels or divided into RGBW sub-pixels.

The TFT array substrate of the display panel 100 includes data lines S1 to Sm, gate lines G1 to Gn, a TFT disposed at the intersection of the data line and the gate line, and a pixel electrode 11 connected to the TFT. , and a storage capacitor (Cst) connected to the pixel electrode 11 . Each of the pixels adjusts the amount of light transmission by using liquid crystal molecules driven by the voltage difference between the pixel electrode 11 that charges the data voltage through the TFT and the common electrode 12 to which the common voltage Vcom is applied. Displays images of video data.

A color filter array including a black matrix and a color filter is formed on the color filter substrate of the display panel 100 . The common electrode 12 is formed on the upper substrate in the case of a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. In the case of a horizontal electric field driving method such as mode, it may be formed on the TFT array substrate together with the pixel electrode 11 . A polarizing plate is attached to each of the TFT array substrate and the color filter array substrate of the display panel 100 , and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The display device of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. A backlight unit is required in a transmissive liquid crystal display device and a transflective liquid crystal display device. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel driving circuit writes input image data into pixels. The display panel driving circuit includes a data driver 102 , a gate driver 104 , a timing controller 20 , and a gamma correction unit 22 . In the RGB type display device, data written to the pixels includes R data, G data, and B data. In the RGBW type display device, data written to the pixels includes R data, G data, B data, and W data.

The data driver 102 includes a plurality of source drive ICs. Data source channels of the source drive ICs are connected to data lines S1 to Sm. The source drive ICs receive digital video data of an input image from the timing controller 20 . In the RGB type display device, digital video data transmitted to the source drive ICs includes R data, G data, and B data. In the RGBW type display device, digital video data transmitted to the source drive ICs includes R data, G data, B data, and W data. The source drive ICs convert digital video data of an input image into positive/negative gamma compensation voltages under the control of the timing controller 20 to output positive/negative data voltages. The output voltage of the data driver 102 is supplied to the data lines S1 to Sm.

Two horizontally adjacent sub-pixels share one data line as shown in FIG. 2 and receive time-divided data voltages through the data line. Due to the shared structure of data lines, the number of data lines and the number of source drive ICs can be reduced compared to a general pixel array structure at the same resolution.

Each of the source drive ICs may invert the polarity of the data voltage to be supplied to the pixels under the control of the timing controller 20 with an inversion period of 2 horizontal periods or more and N/2 (N is the vertical resolution of the display panel) horizontal period or less. . Although the embodiment of the present invention exemplifies an example in which the polarity of the data voltage is inverted every two horizontal periods 2H, the present invention is not limited thereto. Data voltages of 4 colors continuously output for 2 horizontal periods from the source drive IC are charged to 4 sub-pixels sharing the same data line.

In response to the polarity control signal POL received from the timing controller 20 , the source drive ICs maintain the data voltages of the four colors to be charged in the four sub-pixels in the same polarity for two horizontal periods 2H in the same polarity, The polarity of the data voltage is inverted every period (2H). Accordingly, the source drive ICs consecutively output 8 data voltages for 4 horizontal periods 4H, but invert the polarities of the data voltages every 2 horizontal periods. In the present invention, since the polarity inversion period of the data voltage is long, the number of data voltage transitions is small. As a result, power consumption and heat generation of the source drive ICs of the present invention can be reduced. The source drive ICs may further reduce the number of data voltage transitions by inverting the polarity of the data voltage to be supplied to the pixels under the control of the timing controller 20 in 4 horizontal periods.

The gate driver 104 sequentially supplies gate pulses to the gate lines G1 to Gn under the control of the timing controller 20 . The gate pulse output from the gate driver 104 is synchronized with the positive/negative video data voltage to be charged in the pixels. In order to reduce IC cost, the gate driver 104 may be directly formed on the TFT array substrate of the display panel 100 in the same manufacturing process. The gate driver 104 formed directly on the lower substrate of the display panel 100 is known as a “Gate in panel (GIP) circuit.

The timing controller 20 transmits the input image data received from the host system 30 to the data driver 102 . As an interface for data transmission between the timing controller 20 and the source drive ICs of the data driver 102 , a mini low-voltage differential signaling (LVDS) interface or an embedded panel interface (EPI) interface may be applied.

The timing controller 20 receives timing signals synchronized with input image data from the host system 24 . The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock DCLK. The timing controller 20 controls operation timings of the data driver 102 and the gate driver 104 based on the timing signals Vsync, Hsync, DE, and DCLK received together with the pixel data of the input image. The timing controller 20 may transmit a polarity control signal POL for controlling the polarity of the pixels to each of the source drive ICs of the data driver 102 . The Mini LVDS interface transmits the polarity control signal through a separate control wire. The EPI interface is an interface technology that encodes the polarity control information in the control data packet transmitted between the clock training pattern for CDR (Clok and Data Recovery) and the RGB/RGBW data packet and transmits it to each of the source drive ICs. am.

The timing controller 20 may convert RGB data of an input image into RGBW data using a well-known white gain calculation algorithm. The white gain calculation algorithm can be any known.

The host system 24 may be any one of a television (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The timing controller 20 refers to a set value stored in an Electrically Erasable Programmable Read-Only Memory (EEPROM) 21 to control the operation timing of the data driver 102 and the gate driver 104 with reference to a data/gate timing control signal occurs In the EEPROM 21 , a rising edge timing, a pulse duration, a falling edge timing, etc. for the data/gate timing control signal are preset.

In the present invention, the TFT array substrate and the data driver 102 are shared in the RGB type display device and the RGBW type display device.

2 is an equivalent circuit diagram illustrating a part of a TFT array substrate that can be commonly used in an RGB type display device and an RGBW type display device. In FIG. 2 , the common electrode 12 and the storage capacitor Cst are omitted.

Referring to FIG. 2 , a connection relationship between sub-pixels sharing the same data line S1 and sequentially charging data voltages of the same polarity is as follows.

When sub-pixels arranged on an odd-numbered line of the display panel 100 are denoted by P1 to P4 and sub-pixels arranged on an even-th line of the display panel 100 are denoted by P5 to P8, the sub-pixels are connected The relationship is described as follows.

The first sub-pixel P1 supplies a first data voltage supplied through the first data line S1 to the first pixel electrode PIX1 in response to a gate pulse received from the first gate line G1 . 1 TFT (T1) is included. The first TFT T1 includes a gate connected to the first gate line G1 , a drain connected to the first data line S1 , and a source connected to the first pixel electrode PIX1 .

The second sub-pixel P2 supplies a second data voltage supplied through the first data line S1 to the second pixel electrode PIX2 in response to a gate pulse received from the second gate line G2 . 2 TFTs (T2) are included. The second TFT T2 includes a gate connected to the second gate line G2 , a drain connected to the first data line S1 , and a source connected to the second pixel electrode PIX2 .

The third sub-pixel P6 supplies a third data voltage supplied through the first data line S1 to the third pixel electrode PIX3 in response to a gate pulse received from the third gate line G3 . 3 TFTs (T3) are included. The third TFT T3 includes a gate connected to the third gate line G3 , a drain connected to the first data line S1 , and a source connected to the third pixel electrode PIX3 .

The fourth sub-pixel P5 applies the fourth data voltage supplied through the J+1-th data line S1 to the fourth pixel electrode PIX4 in response to the fourth gate pulse from the fourth gate line G4 . and a fourth TFT (T4) for supplying it. The fourth TFT T4 includes a gate connected to the fourth gate line G4 , a drain connected to the first data line S1 , and a source connected to the fourth pixel electrode PIX4 .

The sub-pixels P3 , P4 , P7 , and P8 sharing the second data line S2 have the same connection relationship as the sub-pixels P1 , P2 , P5 , and P6 except for the data line.

3 shows a color arrangement in an RGBW type display device. In FIG. 3 , color filters may be arranged in an odd-numbered line of the color filter substrate in RGBW order, and color filters may be arranged in an even-numbered line in BWRG order. 4 shows a color arrangement in an RGB type display device. In FIG. 4 , color filters are arranged in RGB order on odd-numbered and even-numbered lines of the color filter substrate, respectively.

5 is a circuit diagram showing a source drive IC according to the first embodiment of the present invention. 6 is a waveform diagram showing a polarity control signal of an RGBW type display device. 6 shows polarity control signals POL(S1) to POL(S4) supplied to the first to fourth data lines S1 to S4. FIG. It is a diagram showing the polarity of pixels.

5 to 7 , the source drive IC includes a plurality of buffers P1 , P2 , N3 , and N4 , a plurality of switches, and a plurality of source channels OUT1 to OUT4 .

The buffers P1, P2, N3, and N4 are the P buffers P1 and P2 for supplying the positive data voltage (+Vdata) input from the PDAC to the source channels, and the negative data voltage (+Vdata) input from the NDAC. -Vdata) to the source channels, including N buffers (N3, N4). The first P buffer P1 includes the first data Data1 to be supplied to the first data line S1 through the first source channel OUT1 and the third data line S3 through the third source channel OUT3. ), the positive data voltage (+Vdata) of the third data Data3 to be supplied is output. The second P buffer P2 includes the second data Data2 to be supplied to the second data line S2 through the second source channel OUT2 and the fourth data line S4 through the fourth source channel OUT4. ), the positive data voltage (+Vdata) of the fourth data Data4 to be supplied is output. The first N buffer N3 includes the first data Data1 to be supplied to the first data line S3 through the first source channel OUT1 and the third data line S3 through the third source channel OUT3. ), the negative data voltage (-Vdata) of the third data Data3 to be supplied is output. The second N buffer N4 includes the second data Data2 to be supplied to the second data line S2 through the second source channel OUT2 and the fourth data line S4 through the fourth source channel OUT4. ), the negative data voltage (-Vdata) of the fourth data Data4 to be supplied is output.

The switches include a multiplexer (MUX) for data distribution, switches SW1 to SW4 for data voltage supply, and switches SW5 and SW6 for charge share.

The multiplexer includes mux switches SA1 , SB1 , SA3 , SB3 , SC2 , SD2 , SC4 and SD4 for distributing a data voltage output through one buffer to a plurality of source channels. The multiplexer selects the polarities of the data voltages (+Vdata, -Vdata) in response to the polarity control signals POL(S1), POL(S2), POL(S3), and POL(S4) shown in FIG.

The first MUX switch SA1 connected to the first P buffer P1 connects the output terminal of the first P buffer P1 to the first source channel in response to the first logic value of the first polarity control signal POL(S1). (OUT1) The second MUX switch SB1 connected to the first P-buffer P1 is connected to the first P-buffer P1 in response to a first logic value of the first polarity control signal POL(S1). The output terminal is connected to the third source channel OUT3 The first and second MUX switches SA1 and SB1 are turned off when the first polarity control signal POL(S1) has a second logic value. )do.

The third MUX switch SC2 connected to the second P buffer P2 connects the output terminal of the second P buffer P2 to the second source channel in response to the first logic value of the second polarity control signal POL(S2). (OUT2) The fourth MUX switch SD2 connected to the second P-buffer P2 is connected to the second P-buffer P2 in response to the first logic value of the second polarity control signal POL(S2). An output terminal is connected to the fourth source channel OUT4 The third and fourth MUX switches SC2 and SD2 are turned off when the second polarity control signal POL(S2) has a second logic value.

The fifth MUX switch SB3 connected to the first N buffer N3 connects the output terminal of the first N buffer N3 to the first source channel in response to the second logic value of the third polarity control signal POL (S3). (OUT1) The sixth MUX switch SA3 connected to the first N buffer N3 is connected to the first N buffer N3 in response to the second logic value of the third polarity control signal POL(S3). The output terminal is connected to the third source channel OUT3 The fifth and sixth MUX switches SB3 and SA3 are turned off when the third polarity control signal POL(S3) has the first logic value.

The seventh MUX switch SD4 connected to the second N buffer N4 connects the output terminal of the second N buffer N2 to the fourth source channel in response to the second logic value of the fourth polarity control signal POL (S4). (OUT4) The eighth MUX switch SC4 connected to the second N buffer N4 is connected to the second N buffer N2 in response to the second logic value of the fourth polarity control signal POL (S4). The output terminal is connected to the fourth source channel OUT4 The seventh and eighth MUX switches SD4 and SC4 are turned off when the fourth polarity control signal POL(S4) has the first logic value.

The data voltage supply switches SW1 to SW4 are disposed between the multiplexer and the source channel to apply the positive data voltage (+Vdata) and the negative data voltage (-Vdata) from the multiplexer to the source channels OUT1 to OUT4. supply Each of the data voltage supply switches SW1 to SW4 includes an input terminal connected to two MUX switches and an output terminal connected to one source channel.

Charge share switches (SW5, SW6, hereinafter referred to as "CS switch") connect source channels in which the polarity of the data voltage changes at the same time when the polarity of the data voltage changes.

The first CS switch SW5 is connected to the first and third source channels OUT1 and OUT3 connected to the data lines of the first data line group. The first CS switch SW5 is turned on at the first charge share timing to charge share the data lines S1 and S3 of the first data line group. The first charge share timing is controlled by the first source output enable signal SOE1 . The first CS switch SW5 connects the first and third source channels OUT1 and OUT3 in response to a first logic value of the first source output enable signal SOE1 to form a charge share of the first data line group carry out

The second CS switch SW6 is connected to the first and third source channels OUT1 and OUT3 connected to the data lines S2 and S4 of the second data line group. The second CS switch SW6 is turned on at the first charge share timing to charge-share the data lines S2 and S4 of the second data line group. The second charge share timing is controlled by the second source output enable signal SOE2 . The second CS switch SW6 connects the second and fourth source channels OUT2 and OUT4 in response to the first logic value of the second source output enable signal SOE2 to form a charge share of the second data line group. carry out

The source drive IC inverts the polarity of the data voltage in response to the first to fourth polarity control signals POL(S1) to POL(S4). The polarities of the pixels are the polarity control signals POL(S1) to POL(S1) as shown in FIG. The POL(S4) is controlled as shown in Fig. 7. The pixel array includes pixels in which the polarity of the data voltage is inverted in units of 1 dot and pixels in which the polarity of the data voltage is inverted in units of 2 dots between neighboring sub-pixels. 1 dot means 1 sub-pixel The polarity control signals POL(S1) to POL(S4) as shown in Fig. 6 can be seen when the same polarity is concentrated in a line or block form in an RGBW display device. In addition, the polarity control signals POL(S1) to POL(S4) as shown in Fig. 6 show that the polarities of pixels arranged along the vertical and horizontal directions in the RGBW display device are different from each other. It is possible to prevent shift of the common voltage Vcom by not biasing it to either side, and when the common voltage Vcom is shifted, the data voltage charging rate is different between the positive pixel and the negative pixel at the same gray level, so that the positive pixel and the negative pixel are different. Therefore, the polarity control signals POL(S1) to POL(S4) as shown in Fig. 6 may realize optimal image quality in the RGBW display device.

As a result of repeating various image quality tests, the inventors of the present application found that the image quality deteriorates when the polarity control signals POL(S1) to POL(S4) as shown in Fig. 6 are applied to the RGB display device. By repeatedly experimenting with numerous image quality tests while changing the polarity of the pixel array with the polarity patterns of various candidates, an optimal polarity control method that does not degrade the image quality when applying the TFT array substrate of the RGBW display device to the RGB display device was derived. This polarity control method will be described with reference to FIGS. 8 and 9 .

8 is a diagram showing the polarities of data voltages provided to the first to fourth data lines S1 to S4 of the RGB type display device, and FIG. 9 is a diagram showing the polarities of pixels determined by the data voltages shown in FIG. 8 . am.

As shown in FIG. 9 , the pixel array includes pixels in which the polarity of the data voltage is inverted in units of 1 dot between neighboring sub-pixels, and pixels in which the polarity of the data voltage is inverted in units of 2 dots. The pixel array displayed with the polarity as shown in FIG. 9 can prevent a luminance difference and flicker that can be seen when the same polarity is concentrated in a line or block form in an RGB display device. In addition, the shift of the common voltage Vcom may be prevented by preventing the polarities of pixels disposed in the vertical and horizontal directions in FIG. 9 and the RGB display device from being biased toward either side.

As shown in FIG. 8 , the polarities of the first and second data voltages are symmetric to each other, and the polarities of the third and fourth data voltages are symmetric to each other. In order to have different timing at which the polarity provided to each data line is reversed, an individual source drive IC must be used. However, when the polarity of the data voltage shown in FIG. 8 is compared with the polarity of the data voltage shown in FIG. 6 , the polarities of the second and third data voltages are reversed. Accordingly, in the display device of the present invention, the source drive IC shown in FIG. 5 can be applied to the RGB type display panel shown in FIG. 4 by changing the structure of the pad part of the data line connected to the source channel as shown in FIG. 10 .

11 is a circuit diagram showing a source drive IC according to a second embodiment of the present invention. In FIG. 11, a shift register, a latch, a DAC, and the like of the source drive IC are omitted.

Referring to FIG. 11 , the source drive IC includes a plurality of buffers P1 , P2 , N3 , and N4 , a plurality of switches, and a plurality of source channels OUT1 to OUT4 .

The buffers P1, P2, N3, and N4 are the P buffers P1 and P3 that supply the positive data voltage (+Vdata) input from the PDAC to the source channels, and the negative data voltage (+Vdata) input from the NDAC. -Vdata) to the source channels, including N buffers (N2, N4). The P buffers P1 and P3 and the N buffers N2 and N4 may be alternately arranged in the form shown in FIG. 11 . The first P buffer P1 includes the first data Data1 to be supplied to the first data line S1 through the first source channel OUT1 and the second data line S2 through the second source channel OUT2. ), the positive data voltage (+Vdata) of the second data Data2 to be supplied is output. The first N buffer N2 includes the first data Data1 to be supplied to the first data line S3 through the first source channel OUT1 and the second data line S2 through the second source channel OUT2. ), the negative data voltage (-Vdata) of the second data Data2 to be supplied is output. The second P buffer P3 includes the third data Data3 to be supplied to the third data line S3 through the third source channel OUT3 and the fourth data line S4 through the fourth source channel OUT4. ), the positive data voltage (+Vdata) of the fourth data Data4 to be supplied is output. The second N buffer N4 includes the third data Data3 to be supplied to the third data line S3 through the third source channel OUT3 and the fourth data line S4 through the fourth source channel OUT4. ), the negative data voltage (-Vdata) of the fourth data Data4 to be supplied is output.

The switches include a multiplexer MUX for data distribution, switches S1 to S4 for data voltage supply, and switches S5 and S6 for charge share.

The multiplexer MUX includes MUX switches SA1 , SB1 , SA3 , SB3 , SC2 , SD2 , SC4 , and SD4 for distributing a data voltage output through one buffer to a plurality of source channels. The multiplexer MUX selects the polarities of the data voltages +Vdata and -Vdata in response to the polarity control signals POL(S1), POL(S2), POL(S3), and POL(S4).

The data voltage supply switches SW1 to SW4 are disposed between the multiplexer and the source channel to apply the positive data voltage (+Vdata) and the negative data voltage (-Vdata) from the multiplexer to the source channels OUT1 to OUT4. supply Each of the data voltage supply switches S1 to S4 includes an input terminal connected to two MUX switches and an output terminal connected to one source channel. The switches SW1 and SW2 for supplying the first and second data voltages apply positive/negative data voltages to the first and second source channels in response to the second logic value of the first source output enable signal SOE1. are supplied to OUT1 and OUT2. The third and fourth data voltage supply switches SW3 and SW4 apply positive/negative data voltages to the third and fourth source channels in response to the second logic value of the second source output enable signal SOE2. are supplied to OUT3 and OUT4.

The CS switches SW5 and SW6 connect source channels in which the polarity of the data voltage changes at the same time when the polarity of the data voltage changes. The first CS switch SW5 is connected to the first and second source channels OUT1 and OUT2 and is connected to the first and second source channels in response to a first logic value of the first source output enable signal SOE1. Connect (OUT1, OUT2) to perform charge sharing. The second CS switch SW6 is connected to the third and fourth source channels OUT3 and OUT4 to connect the third and fourth source channels in response to a first logic value of the second source output enable signal SOE2. Connect (OUT3, OUT4) to perform charge sharing.

The source drive IC according to the second embodiment shown in FIG. 11 outputs a data voltage having the same polarity as shown in FIG. 8 . That is, the source drive IC of the second embodiment is advantageous to be applied to the RGB type display panel.

However, as in the first embodiment, the source drive IC shown in FIG. 11 can exhibit the same effect as the driving using the polarity control signal shown in FIG. 6 by changing the pad portion of the display panel as shown in FIG. 10 .

In order to apply the source drive ICs shown in FIGS. 5 and 11 to the RGBW type display panel and the RGB type display panel, respectively, the connection structure of the pad part must be designed differently. The present invention proposes the following pad part for common use of the pad part of the display panel.

12 is a plan view of the pad part according to the first embodiment, and FIG. 13 is a view showing a cross-section taken along line A-A' shown in FIG. 12 . 14 is a plan view of the pad part according to the second embodiment, and FIG. 15 is a view showing a cross-section taken along line A-A' shown in FIG. 15 . The pad part according to the first embodiment shows the pad part shown in FIGS. 5 and 11 in detail, and the pad part according to the second embodiment shows the structure of the pad part shown in FIG. 10 . The process of forming the metal array layer and the pads of the pad part according to the present invention is the same, and may be divided into the first and second embodiments according to the formation position of the contact hole.

12 and 13 , the pad unit 110 according to the first embodiment includes first to fourth source pads SP1, SP2, SP3, and SP4, first to fourth data pads DP1, DP2, DP3, DP4) and first to sixth link patterns LINK1, LINK2, LINK3, LINK4, LINK5, LINK6. The first to fourth source pads SP1, SP2, SP3, and SP4 are respectively connected to the first to fourth source channels OUT1, OUT2, OUT3, and OUT4, and the first to fourth data pads DP1, DP2, DP3 and DP4 are respectively connected to the first to fourth data lines S1, S2, S3, and S4.

A brief look at the formation process of the pad part 110 is as follows. The first to fourth source pads SP1 , SP2 , SP3 , and SP4 are formed on the substrate GLS by using the first metal layer. The insulating layer GI is formed to cover the first to fourth source pads SP1, SP2, SP3, and SP4, and the first to fourth data pads DP1, DP2, DP3, and DP4 are formed on the insulating layer GI. do. The passivation layer PAS is formed to cover the first to fourth data pads DP1, DP2, DP3, and DP4. The first to fourth contact holes CONT1 , CONT2 , CONT3 , and CONT4 are formed by selectively etching the passivation layer PAS using a mask.

The first source pad SP1 is connected to the first link pattern LINK1 through the first contact hole CONT1, and the first data pad SP1 is connected to the first link pattern LINK1 through the second contact hole CONT2. LINK1) is connected. Accordingly, the data voltage output from the first source channel OUT1 is connected to the first data line S1 .

The second source pad SP2 is connected to the second link pattern LINK2 through the third contact hole CONT3, and the second data pad SP2 is connected to the second link pattern LINK2 through the fourth contact hole CONT4. LINK2) is connected. Accordingly, the data voltage output from the second source channel OUT2 is connected to the second data line S2 .

The third source pad SP3 is connected to the third link pattern LINK3 through the fifth contact hole CONT5, and the third data pad DP3 is connected to the third link pattern LINK3 through the sixth contact hole CONT6. LINK3). Accordingly, the data voltage output from the third source channel OUT3 is connected to the third data line S3 .

The fourth source pad SP4 is connected to the fourth link pattern LINK4 through the seventh contact hole CONT7, and the fourth data pad DP4 is connected to the fourth link pattern LINK4 through the eighth contact hole CONT8. LINK4). Accordingly, the data voltage output from the fourth source channel OUT4 is connected to the fourth data line S4 .

14 and 15 , the pad part 111 according to the second embodiment includes first to fourth source pads SP1, SP2, SP3, and SP4, first to fourth data pads DP1, DP2, DP3, DP4) and first to sixth link patterns LINK1, LINK2, LINK3, LINK4, LINK5, LINK6. The first to fourth source pads SP1, SP2, SP3, and SP4 are respectively connected to the first to fourth source channels OUT1, OUT2, OUT3, and OUT4, and the first to fourth data pads DP1, DP2, DP3 and DP4 are respectively connected to the first to fourth data lines S1, S2, S3, and S4.

The first source pad SP1 is connected to the first link pattern LINK1 through the first contact hole CONT1, and the first data pad DP1 is connected to the first link pattern LINK1 through the second contact hole CONT2. LINK1) is connected. Accordingly, the data voltage output from the first source channel OUT1 is connected to the first data line S1 .

The second source pad SP2 is connected to the fifth link pattern LINK5 through the third contact hole CONT3, and the third data pad DP3 is connected to the fifth link pattern LINK5 through the fourth contact hole CONT4. LINK5). Accordingly, the data voltage output from the second source channel OUT2 is connected to the third data line S3 .

The third source pad SP3 is connected to the sixth link pattern LINK6 through the fifth contact hole CONT5, and the second data pad DP2 is connected to the sixth link pattern LINK6 through the sixth contact hole CONT6. LINK6). Accordingly, the data voltage output from the third source channel OUT3 is connected to the second data line S2 .

The fourth source pad E4 is connected to the fourth link pattern LINK4 through the seventh contact hole CONT7, and the fourth data pad E4 is connected to the fourth link through the eighth contact hole CONT8. It is connected to the pattern (LINK4). Accordingly, the data voltage output from the fourth source channel OUT4 is connected to the fourth data line S4 .

The pad part according to the first and second embodiments is formed in the same process up to the process of forming the passivation layer PAS. The pad parts 110 and 111 of the first and second embodiments are formed by changing only the process of aligning the mask in order to selectively etch the passivation layer PAS. That is, since the pad parts 110 and 111 of the first and second embodiments perform the same process of forming the first to sixth link patterns LINK1, LINK2, LINK3, LINK4, LINK5, and LINK6, it is It is advantageous to apply to all RGB type display panels.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 102: data driver
104: gate driver 20: timing controller
21: EEPROM POL(S1) ~ POL(S4): Polarity control signal

Claims (9)

a display panel receiving data voltages through first to fourth data lines;
a data driver outputting the data voltage to first to fourth source channels; and
a pad unit connecting the display panel and the data driver;
the pad part
first to fourth source pads respectively connected to the first to fourth source channels;
first to fourth data pads respectively connected to the first to fourth data lines;
a first link pattern connecting the first source pad and the first data pad;
a second link pattern overlapping partial regions of the second source pad and the second data pad;
a third link pattern overlapping the third source pad and a partial region of the third data pad;
a fourth link pattern connecting the fourth source pad and the fourth data pad;
a fifth link pattern overlapping partial regions of the second source pad and the third data pad; and
and a sixth link pattern overlapping partial regions of the third source pad and the second data pad.
The method of claim 1,
The display panel is
first and second sub-pixels connected to the first data line in an odd-numbered line;
third and fourth sub-pixels connected to the second data line on an even-th line;
a second gate line connected to the first subpixel;
a first gate line connected to the second subpixel;
a fourth gate line connected to the third subpixel; and
and a third gate line connected to the fourth subpixel.
The method of claim 1,
The first to fourth source pads are positioned on the substrate,
The first to fourth data pads are positioned on an insulating layer covering the first to fourth source pads,
The display device further comprising a passivation layer covering the first to fourth data pads.
4. The method of claim 3,
the second source pad and the second data pad are connected to the second link pattern through a contact hole;
The third source pad and the third data pad are connected to the third link pattern through a contact hole.
5. The method of claim 4,
The display panel includes RGBW type sub-pixels,
The data driver
first and second P buffers outputting positive data voltages; and
It includes first and second N buffers for outputting a negative data voltage,
The first P buffer outputs positive data voltages of first data provided to the first data line through the first source channel and third data provided to the third data line through the third source channel. do,
the second P buffer outputs a positive voltage of the second data supplied to the second data line through a second source channel and the fourth data supplied to the fourth data line through a fourth source channel;
the first N buffer outputs negative data voltages of the first data and the third data;
The second N buffer outputs negative data voltages of the second data and the fourth data.
5. The method of claim 4,
The display panel includes RGB sub-pixels,
The data driver
first and second P buffers outputting positive data voltages; and
It includes first and second N buffers for outputting a negative data voltage,
The first P buffer outputs positive data voltages of the first data provided to the first data line through the first source channel and the second data provided to the second data line through the second source channel. do,
the first N buffer outputs negative data voltages of the first data and the second data;
the second P buffer outputs a positive polarity voltage of the third data supplied to the third data line through a third source channel and the fourth data supplied to the fourth data line through a fourth source channel;
The second N buffer outputs negative data voltages of the third data and the fourth data.
4. The method of claim 3,
the second source pad and the third data pad are connected to the fifth link pattern through a contact hole;
The third source pad and the second data pad are connected to the sixth link pattern through a contact hole.
8. The method of claim 7,
The display panel includes RGB type sub-pixels,
The data driver
first and second P buffers outputting positive data voltages; and
It includes first and second N buffers for outputting a negative data voltage,
The first P buffer outputs positive data voltages of first data provided to the first data line through the first source channel and third data provided to the third data line through the third source channel. do,
the second P buffer outputs a positive voltage of the second data supplied to the second data line through a second source channel and the fourth data supplied to the fourth data line through a fourth source channel;
the first N buffer outputs negative data voltages of the first data and the third data;
The second N buffer outputs negative data voltages of the second data and the fourth data.
8. The method of claim 7,
The display panel includes RGBW type sub-pixels,
The data driver
first and second P buffers outputting positive data voltages; and
It includes first and second N buffers for outputting a negative data voltage,
The first P buffer outputs positive data voltages of the first data provided to the first data line through the first source channel and the second data provided to the second data line through the second source channel. do,
the first N buffer outputs negative data voltages of the first data and the second data;
the second P buffer outputs a positive polarity voltage of the third data supplied to the third data line through a third source channel and the fourth data supplied to the fourth data line through a fourth source channel;
The second N buffer outputs negative data voltages of the third data and the fourth data.

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