KR102184043B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, and includes a plurality of data lines, a plurality of gate lines, and a plurality of R subpixels, a plurality of G subpixels, a plurality of B subpixels, and thin film transistors connected to the subpixels. And a formed pixel array. The pixel array may include a plurality of first pixels including a first R sub-pixel and a first G sub-pixel; A plurality of second pixels including a first B sub-pixel and a second R sub-pixel; And a plurality of third pixels including a second G sub-pixel and a second B sub-pixel. The color configurations of neighboring pixels in the pixel array are different from each other.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device in which each of the pixels is divided into two sub-pixels having different colors.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices such as are being developed. The liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. In an active matrix driving type liquid crystal display device, a thin film transistor (hereinafter referred to as "TFT") is formed for each pixel.

Liquid crystal display devices include a liquid crystal display panel, a backlight unit that irradiates light to the liquid crystal display panel, a source drive integrated circuit (Integrated Circuit, hereinafter referred to as "IC") for supplying data voltage to the data lines of the liquid crystal display panel, and liquid crystal. A gate drive IC for supplying a gate pulse (or scan pulse) to the gate lines (or scan lines) of the display panel, a control circuit for controlling the ICs, a light source driving circuit for driving a light source of the backlight unit, etc. Equipped.

In order to reduce power consumption, an RGBW type display device in which a W (White) subpixel is added in addition to the R (Red) subpixel, G (Green) subpixel, and B (Blue) subpixel to each of the pixels has been developed. Pentile pixel array Pixels composed of R and G sub-pixels and pixels composed of B and W sub-pixels are arranged so as to cross the pixel array to increase resolution. However, conventional RGBW type display devices or pentile type pixel arrays have low color expression and low legibility due to the addition of W sub-pixels.

The present invention provides a display device capable of increasing the aperture ratio and transmittance of pixels, and improving color expression and readability.

The display device of the present invention is a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of R subpixels, a plurality of G subpixels, a plurality of B subpixels, and thin film transistors connected to the subpixels are formed. Includes.

The pixel array may include a plurality of first pixels including a first R sub-pixel and a first G sub-pixel; A plurality of second pixels including a first B sub-pixel and a second R sub-pixel; And a plurality of third pixels including a second G sub-pixel and a second B sub-pixel.

The color configurations of neighboring pixels in the pixel array are different from each other.

In the display device of the present invention, in a pixel array composed of RGB sub-pixels without W sub-pixels, one pixel is divided into two sub-pixels with different colors, thereby increasing the aperture ratio and transmittance of each of the pixels, and improving color expression and readability. have.

1 is a block diagram showing a display device according to an exemplary embodiment of the present invention.
2 is a plan view comparing the pixel structure of the prior art and the pentile pixel structure of the present invention.
3 is a diagram showing a pixel array according to the first embodiment of the present invention.
4 is a diagram showing a pixel array according to a second embodiment of the present invention.
5 is a diagram showing a pixel array according to a third embodiment of the present invention.
6 is a diagram showing a pixel array according to a fourth embodiment of the present invention.
7 to 9 are views showing a pentile rendering method according to an embodiment of the present invention.
10A and 10B are diagrams showing a color arrangement of an island-type pixel array in which it is difficult to represent white according to a data pattern.
11A and 11B are diagrams showing a color arrangement of an island type pixel array capable of representing white color according to a data pattern.
FIG. 12 is a diagram showing an example in which TFTs are arranged in a zigzag form at intervals of 2 horizontal lines in an island type pixel array.
FIG. 13 is a diagram showing an example in which TFTs are arranged in a zigzag form at intervals of one horizontal line in an island type pixel array.
14A and 14B are diagrams illustrating an example in which TFTs are arranged in a zigzag shape at intervals of 2 horizontal lines and colors are arranged along an oblique line in the island type pixel array.
15A and 15B are diagrams illustrating an example in which TFTs are arranged in a zigzag shape at intervals of one horizontal line, and colors are arranged along an oblique or zigzag line in an island type pixel array.
16 and 17 are waveform diagrams showing an example in which data voltages of the same polarity are supplied to data lines during one frame period.

The display device of the present invention may be implemented as a flat panel display device capable of implementing colors such as a liquid crystal display (LCD), an organic light emitting diode display (OLED display), and a plasma display panel (PDP). In the present invention, in an RGB type display device without a W sub-pixel, a pixel array of a display device is constructed in a pentile pixel structure in which pixels are composed of two sub-pixels having different colors.

Hereinafter, embodiments of the present invention will be described centering on a liquid crystal display device, but it should be noted that the present invention is not limited to the liquid crystal display device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

Referring to FIGS. 1 and 2, the display device of the present invention includes a display panel 100 in which a pixel array is formed, and a display panel driving circuit for writing data of an input image to the display panel 100. A backlight unit for uniformly irradiating light to the display panel 100 may be disposed under the display panel 100.

The display panel 100 includes an upper substrate and a lower substrate facing each other with a liquid crystal layer therebetween. The pixel array of the display panel 100 includes pixels arranged in a matrix form by an intersection structure of the data lines S1 to Sm and the gate lines G1 to Gn.

The pixel array of the display panel 100 includes RGB subpixels without a W subpixel, and implements one pixel with two subpixels having different colors. In the display device of the present invention, a pentile rendering algorithm is applied according to an RGB sub-pixel structure to compensate for color by distributing a data value of a color insufficient in each of the pixels to one or more pixels located nearby. In the display device of the present invention, since a pixel array is formed of only RGB sub-pixels without W sub-pixels, color expression and readability are improved. In the display device of the present invention, since each of the pixels includes only two sub-pixels as shown in FIGS. 2 to 4, the aperture ratio and transmittance of each of the pixels are increased, so that an input image can be reproduced brightly and clearly in a high-resolution display.

Each of the horizontal lines L1 to L4 of the pixel array includes a plurality of first pixels PIX1, a plurality of second pixels PIX2, and a plurality of third pixels PIX3. In the vertical and horizontal lines of the pixel array, pixels are arranged so that the color configurations of neighboring pixels are different from each other. Each of the first pixels PIX1 is divided into a first R sub-pixel and a first G sub-pixel. The B data of the first pixels PIX1 is among the B subpixels in the second and third pixels PIX2 and PIX3 arranged around the first pixel PIX1 by a predetermined ratio determined by the pentile pixel rendering algorithm. Distributed into one or more sub-pixels. Each of the second pixels PIX2 is divided into a first B sub-pixel and a second R sub-pixel. The G data of the second pixels PIX2 is among the G subpixels in the first and third pixels PIX1 and PIX3 disposed around the second pixel PIX2 by a predetermined ratio determined by the pentile pixel rendering algorithm. Distributed into one or more sub-pixels. Each of the third pixels PIX3 is divided into a second G sub-pixel and a second B sub-pixel. The R data of the third pixels PIX3 is among the R subpixels in the first and second pixels PIX1 and PIX2 arranged around the third pixel PIX3 by a predetermined ratio determined by the pentile pixel rendering algorithm. Distributed into one or more sub-pixels. The sub-pixels are manufactured in a structure with excellent readability, that is, a structure in which the Y-axis length (or vertical length) is longer than the X-axis length (or horizontal length).

The pixel array is arranged in an island type or a stripe type. An example of the island type pixel array is shown in FIG. 3. In the island type pixel array, subpixels of the same color are separated along a vertical line (Y axis) of the pixel array, and subpixels of different colors are disposed between them. An example of a stripe type pixel array is shown in FIG. 4. In the stripe type pixel array, subpixels of the same color are arranged in a straight line along a vertical direction (Y).

The lower substrate of the display panel 100 includes data lines S1 to Sm, gate lines G1 to Gn, TFTs, a pixel electrode 1 connected to the TFT, and a storage connected to the pixel electrode 1 Includes a capacitor (Storage Capacitor, Cst). Each of the RGB subpixels uses liquid crystal molecules driven by a voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied to determine the amount of light transmitted. Adjust.

TFTs formed on the lower substrate of the display panel 100 may be implemented as an amorphose Si (a-Si) TFT, a Low Temperature Poly Silicon (LTPS) TFT, an oxide TFT, or the like. The TFTs are connected 1:1 to the pixel electrode of the sub-pixels.

A color filter array including a black matrix (BM) and a color filter is formed on the upper substrate of the display panel 100. The common electrode 2 is formed on the upper substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) In the case of a horizontal electric field driving method such as a mode, it may be formed on the lower substrate together with the pixel electrode. A polarizing plate is attached to each of the upper and lower substrates of the display panel 100 and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The display device of the present invention may be implemented in any form such as a transmissive liquid crystal display, a transflective liquid crystal display, and a reflective liquid crystal display. Transmissive liquid crystal display devices and transflective liquid crystal display devices require a backlight unit. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel driving circuit writes data of an input image to pixels. Data written to the pixels includes R data, G data, and B data. The display panel driving circuit includes a data driver 102, a gate driver 104, and a timing controller 106.

The data driver 102 includes a plurality of source drive ICs. The data output channels of the source drive ICs are connected 1:1 to the data lines S1 to Sm of the pixel array. The source drive ICs receive input image data from the timing controller 106. The digital video data transmitted to the source drive ICs includes R data, G data, and B data. The source drive ICs convert RGB digital video data of an input image into a positive/negative gamma compensation voltage under the control of the timing controller 106 and output a positive/negative data voltage. The output voltages of the source drive ICs are supplied to the data lines S1 to Sm.

Each of the source drive ICs inverts the polarity of data voltages to be supplied to the pixels under the control of the timing controller 106 and outputs them to the data lines S1 to Sm. The source drive ICs supply a data voltage of the first polarity to the odd-numbered data lines (S1, S3, Sm-1) through the odd-numbered output channel as shown in FIGS. 16 and 17, and the polarity Keep it. In addition, the source drive ICs supply the data voltage of the second polarity to the even-th data lines S2, S4...Sm through the even-th output channel as shown in FIGS. 16 and 17 and change the polarity of the data voltage for one frame period. Keep. Therefore, the source drive IC outputs a data voltage whose polarity is reversed in the form of a column inversion. In the display device of the present invention, since the polarity of the data voltage does not change for one frame period in each of the data lines S1 to Sm, power consumption and heat generation of the source drive ICs can be reduced.

In the pixel array, TFTs are arranged in a zigzag shape along a vertical direction. Accordingly, the data voltage output through the output channels of the source drive IC is maintained at the same polarity for one frame period, but the polarity of the pixel array is reversed to dot inversion as shown in FIGS. 3 and 4. One dot is equal to one sub-pixel. In the pixel array of Fig. 3, the polarity of the pixel array is inverted into two vertical dots and one horizontal dot inversion. The polarity of the pixel array of Fig. 4 is inverted to a vertical 1 dot and a horizontal 1 dot inversion. As shown in FIGS. 3 and 4, when the polarity of the pixel array is inverted to dot inversion and the positive and negative polarities are balanced in vertical and horizontal lines, there is no shift of the common voltage Vcom, so crosstalk ( There is no crosstalk), so you can get a uniform image quality across the screen.

The gate driver 104 sequentially supplies gate pulses to the gate lines G1 to Gn under the control of the timing controller 106. The gate pulse output from the gate driver 104 is synchronized with the positive/negative video data voltage to be charged to the pixels. The gate driver 104 may be directly formed on the lower substrate of the display panel 100 together with the pixel array in the same manufacturing process to reduce IC cost.

The timing controller 106 transmits the RGB data of the input image received from the host system 110 to the source drive ICs of the data driver 102. An interface for data transmission between the timing controller 106 and the source drive ICs of the data driver 102 may use a mini LVDS (low-voltage differential signaling) interface or an EPI (Embedded Panel Interface) interface. EPI interface is a Korean patent application filed by the applicant of the present application 10-2008-0127458 (2008-12-15), US application 12/543,996 (2009-08-19), Korean patent application 10-2008-0127456 (2008-12) -15), US application 12/461,652 (2009-08-19), Korean patent application 10-2008-0132466 (2008-12-23), and US application 12/537,341 (2009-08-07).

The timing controller 106 receives timing signals synchronized with the input image data from the host system 110. Timing signals include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), a dot clock (DCLK), and the like. The timing controller 106 controls operation timings of the data driver 102 and the gate driver 104 based on timing signals Vsync, Hsync, DE, and DCLK received together with pixel data of an input image. The timing controller 106 may transmit a polarity control signal for controlling the polarity of the pixel array to each of the source drive ICs of the data driver 102. Mini LVDS interface transmits polarity control signals through separate control wiring. The EPI interface is an interface technology that encodes polarity control information in a control data packet transmitted between a clock training pattern for CDR (Clok and Data Recovery) and an RGBW data packet and transmits it to each of the source drive ICs.

The host system 110 may be any one of a TV (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

3 is a diagram showing a pixel array according to the first embodiment of the present invention.

Referring to FIG. 3, the pixel array is implemented as an island type pixel array. When the polarity of the data voltage output from the source drive IC is inverted in the column inversion form as shown in FIGS. 16 and 17, the polarity of the pixel array is inverted in the vertical 2 dot and horizontal 1 dot inversion form. This is because the TFTs in the pixel array are arranged in a zigzag pattern at intervals of 2 horizontal lines along the vertical direction.

In the odd-numbered horizontal lines L1 and L3 of the pixel array, the color arrangement of sub-pixels is arranged in the order of R G B from left to right. The color arrangement of sub-pixels in the even-th horizontal lines L2 and L4 of the pixel array is arranged in the order of G B R from left to right.

In the 4ith (i is a positive integer of 0)+1 and the 4i+2th horizontal lines L1 and L2, the TFTs T1 and T2 are connected to the right side of the data lines S1 to S8. In the 4i+3 and 4i+4th horizontal lines L3 and L4, the TFTs T3 and T4 are connected to the left side of the data lines S1 to S8.

The first TFT T1 changes the data voltage from the data lines S1 to S8 to 4i+1 in response to the first gate pulse from the 4ith (i is a positive integer of 0) +1 gate line G1. It is supplied to the pixel electrode P1 formed on the horizontal line L1. The second TFT (T2) is a pixel electrode formed on the 4i+2 horizontal line (L2) to apply the data voltage from the data lines (S1 to S8) in response to the second gate pulse from the 4i+2 gate line (G2). Supply to (P2).

The third TFT (T3) is a pixel electrode formed on the 4i+3 horizontal line (L3) to supply the data voltage from the data lines (S1 to S8) in response to the third gate pulse from the 4i+3 gate line (G3). Supply to (P3). The fourth TFT (T4) is a pixel electrode formed on the 4i+4 horizontal line (L4) to apply the data voltage from the data lines (S1 to S8) in response to the fourth gate pulse from the 4i+4 gate line (G4). Supply to (P4).

4 is a diagram showing a pixel array according to a second embodiment of the present invention.

Referring to FIG. 4, the pixel array is implemented as a stripe-type pixel array. When the polarity of the data voltage output from the source drive IC is inverted in a column inversion format as shown in FIGS. 16 and 17, the polarity of the pixel array is inverted in a vertical 1-dot and horizontal 1-dot inversion format. This is because the TFTs in the pixel array are arranged in a zigzag shape with one horizontal line interval along the vertical direction.

In the odd-numbered horizontal lines L1 and L3 of the pixel array, the color arrangement of sub-pixels is arranged in the order of R G B from left to right. The color arrangement of sub-pixels in the even-th horizontal lines L2 and L4 of the pixel array is arranged in the order of G B R from left to right.

In the odd-numbered horizontal lines L1 and L3, the TFTs T11 and T13 are connected to the right side of the data lines S1 to S8. In the even-th horizontal line L2, the TFTs T12 are connected to the left side of the data lines S1 to S8.

The first TFT T1 applies the data voltage from the data lines S1 to S8 to the pixel electrode P1 formed on the first horizontal line L1 in response to the first gate pulse from the first gate line G1. Supply. The second TFT T2 applies a data voltage from the data lines S1 to S8 to the pixel electrode P2 formed on the second horizontal line L2 in response to a second gate pulse from the second gate line G2. Supply. The third TFT T3 applies the data voltage from the data lines S1 to S8 to the pixel electrode P3 formed on the third horizontal line L3 in response to the third gate pulse from the third gate line G3. Supply.

In the display device of the present invention, in order to reduce the number of source drive ICs, the pixel array is driven by double rate driving (DRD) in which two sub-pixels adjacent horizontally (x-axis or low-line direction) share one data line. can do. In the DRD driving method, the operating frequency of the source drive IC is doubled. The DRD driving method can reduce the number of data lines and source drive ICs by half. 5 and 6 show a pixel array driven by a DRD driving method.

5 is a diagram showing a pixel array according to a third embodiment of the present invention.

Referring to FIG. 5, the pixel array is implemented as an island type pixel array. When the polarity of the data voltage output from the source drive IC is inverted in a column inversion format as shown in FIGS. 16 and 17, the polarity of the pixel array is inverted in a vertical 1-dot and horizontal 2-dot inversion format. The sub-pixels are driven by the DRD driving method. Accordingly, two adjacent sub-pixels are connected to one data line. These sub-pixels are time-division driven by sequentially charging data voltages continuously supplied through one data line.

6 is a diagram showing a pixel array according to a fourth embodiment of the present invention.

Referring to FIG. 6, the pixel array is implemented as a stripe-type pixel array. When the polarity of the data voltage output from the source drive IC is inverted in a column inversion format as shown in FIGS. 16 and 17, the polarity of the pixel array is inverted in a vertical 1-dot and horizontal 1-dot inversion format. The sub-pixels are driven by the DRD driving method. Accordingly, two adjacent sub-pixels are connected to one data line. These sub-pixels are time-division driven by sequentially charging data voltages continuously supplied through one data line.

7 to 9 are views showing a pentile rendering method according to an embodiment of the present invention.

7 to 9, each of the first pixels PIX1 includes an R subpixel and a G subpixel without a B subpixel. The B data of the first pixels PIX1 is among the B subpixels in the second and third pixels PIX2 and PIX3 arranged around the first pixel PIX1 by a predetermined ratio determined by the pentile pixel rendering algorithm. Distributed into one or more sub-pixels. When the B data of the first pixel PIX1 is scattered among four B subpixels included in the surrounding pixels of the first pixel PIX1, each quarter of the B data value of the first pixel PIX1 It is added to the B data of the surrounding pixels.

Each of the second pixels PIX2 includes a B subpixel and an R subpixel without a G subpixel. The G data of the second pixels PIX2 is among the G subpixels in the first and third pixels PIX1 and PIX3 arranged around the second pixel PIX2 by a predetermined ratio determined by the pentile pixel rendering algorithm. Distributed into one or more sub-pixels. When the G data of the second pixel PIX2 is scattered among the four G subpixels included in the surrounding pixels of the second pixel PIX2, each quarter of the G data value of the second pixel PIX2 It is added to the G data of the surrounding pixels.

Each of the third pixels PIX3 includes a G subpixel and a B subpixel without an R subpixel. The R data of the third pixels PIX3 is among the R subpixels in the first and second pixels PIX1 and PIX2 arranged around the third pixel PIX3 by a predetermined ratio determined by the pentile pixel rendering algorithm. Distributed into one or more sub-pixels. When the R data of the third pixel PIX3 is scattered among the four R subpixels included in the surrounding pixels of the third pixel PIX3, 1/4 of the R data value of the third pixel PIX3 It is added to the R data of the surrounding pixels.

When a specific data pattern is displayed on the pixel array as shown in FIGS. 3 and 4, the color expression power may decrease. As an example of such a data pattern, there is a data pattern as shown in FIGS. 10A and 10B. The data patterns shown in FIGS. 10A and 10B include white grayscale data on odd-numbered vertical lines and black grayscale data on even-numbered vertical lines. When such a data pattern is displayed on the pixel array as shown in FIGS. 3 and 4, a color other than white is displayed on pixels of odd-numbered vertical lines in which white is to be displayed.

In the example of FIG. 10A, since there are many G sub-pixels in the pixels of the first vertical line compared to other colors, the first vertical line is not white, but a color close to green is displayed. Since the pixels of the third vertical line have more B sub-pixels than other colors, a color close to blue is displayed on the third vertical line.

In the example of FIG. 10B, since the pixels of the first vertical line include R and G sub-pixels without the B sub-pixel, the first vertical line is displayed in yellow. Since the pixels of the third vertical line include G and B subpixels without R subpixels, the third vertical line is displayed in cyan.

In order to solve the color distortion problem of FIGS. 10A and 10B, it is preferable to change the color arrangement of the pixel array as shown in FIGS. 11A and 11B.

Referring to FIGS. 11A and 11B, the same pixels are arranged along a diagonal line or along a zigzag line so that pixels of the same color are not adjacent in each of the horizontal lines and the vertical lines.

In the example of Fig. 11A, the color arrangement of the first horizontal line L1 is arranged in R G B order from left to right. The color arrangement of the second horizontal line L2 is arranged in the order of G B R from left to right. The color arrangement of the third horizontal line L3 is arranged in the order of B R G from left to right. The color arrangement of the fourth horizontal line L4 is the same as that of the first horizontal line L1. As a result, in the island type pixel array, the same pixels and subpixels of the same color are arranged along a diagonal line. When the X-axis is 0° and the Y-axis is 90°, the diagonal line as shown in FIG. 11A is an oblique line at an angle between 30° and 60°.

In the example of Fig. 11B, the color arrangement of the first horizontal line L1 is arranged in R G B order from left to right. The color arrangement of the second horizontal line L2 is arranged in the order of G B R from left to right. The color arrangement of the third horizontal line L3 is arranged in the order of B R G from left to right. The color arrangement of the fourth horizontal line L4 is the same as that of the second horizontal line L2. As a result, in the island type pixel array, the same pixels and subpixels of the same color are arranged along the zigzag line. In the zigzag line as shown in FIG. 11B, when the X axis is 0° and the Y axis is 90°, the first diagonal line between 30° and 60° and the second diagonal line between 110° and 150° connected to the end of the first diagonal line Includes.

Accordingly, when subpixels of the same pixel and the same color are arranged along a diagonal or zigzag line in an island-type pixel array, color expression can be improved.

12 is an example in which TFTs are arranged in a zigzag form at intervals of 2 horizontal lines in an island type pixel array. In this case, the positive polarity and the negative polarity in the sub-pixels of the same color are balanced in the vertical line, the horizontal line, and the oblique line, so that neither polarity is biased. The polarity balance can prevent smudges on the displayed image.

13 is an example in which TFTs are arranged in a zigzag form at intervals of one horizontal line in an island type pixel array. In this case, the polarities of the sub-pixels of the same color arranged on one vertical line are biased to either side. Such a polarity imbalance may cause the display image to become uneven.

14A and 14B are diagrams illustrating an example in which TFTs are arranged in a zigzag shape at intervals of 2 horizontal lines and colors are arranged along an oblique line in the island type pixel array. In this case, the positive polarity and the negative polarity in the sub-pixels of the same color are balanced in the vertical line, the horizontal line, and the oblique line, so that neither polarity is biased. The polarity balance can prevent smudges on the displayed image.

15A and 15B are diagrams illustrating an example in which TFTs are arranged in a zigzag shape at intervals of one horizontal line, and colors are arranged along an oblique or zigzag line in an island type pixel array. In the case of Fig. 15A, the polarities of sub-pixels of the same color arranged along the diagonal line are biased to either side. In the case of Fig. 15B, the polarities of sub-pixels of the same color arranged along the vertical line are biased to either side. Such a polarity imbalance may cause the display image to become uneven.

Therefore, in order to realize the polarity balance of the pixel array in the island-type pixel array, it is preferable that the TFTs are arranged in a zigzag form at intervals of two horizontal lines.

16 is an example of outputting a data voltage without charge sharing from a source drive IC when data voltages of the same polarity are supplied to data lines during one frame period. FIG. 17 is an example of outputting a data voltage after performing charge-sharing in every horizontal period in a source drive IC when data voltages of the same polarity are supplied to data lines during one frame period. In FIGS. 16 and 17, "VB" is a vertical blank period without a data voltage.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

100: display panel 102: data driver
104: gate driver 106: timing controller
110: host system

Claims (4)

A pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of R sub-pixels, a plurality of G sub-pixels, a plurality of B sub-pixels, and thin film transistors connected to the sub-pixels are formed,
The pixel array,
A plurality of first pixels including a first R sub-pixel and a first G sub-pixel;
A plurality of second pixels including a first B sub-pixel and a second R sub-pixel; And
Including a plurality of third pixels including a second G sub-pixel and a second B sub-pixel,
The color configurations of neighboring pixels in the pixel array are different from each other,
The thin film transistors disposed on the 4ith (i is a positive integer of 0)+1 and the 4i+2th horizontal lines (L1, L2) are connected to the right side of the data lines,
The thin film transistors disposed on the 4i+3 and 4i+4th horizontal lines L3 and L4 are connected to the left side of the data lines. The method of claim 1,
The B data of the first pixel is distributed to at least one of the B subpixels in the second and third pixels disposed around the first pixel,
The G data of the second pixel is distributed to one or more of the G sub-pixels in the first and third pixels disposed around the second pixel,
The R data of the third pixel is distributed to one or more subpixels of R subpixels in first and second pixels disposed around the third pixel. The method of claim 2,
The pixels are arranged in the order of the first pixel, the second pixel, and the third pixel along a horizontal line of the pixel array,
Sub-pixels of different colors are disposed between sub-pixels of the same color disposed adjacently along a vertical line of the pixel array,
A display device in which subpixels of the same color are arranged in the pixel array along diagonal or zigzag lines. delete

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