KR102160121B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, comprising: a plurality of data lines, a plurality of gate lines, and a plurality of R subpixels, a plurality of G subpixels, a plurality of B subpixels and a plurality of W subpixels, and the subpixels A display device having TFTs connected thereto; And a black matrix BM overlapping the data lines, the gate lines, and the TFTs. The W subpixels include a plurality of TFTs connected to neighboring subpixels of different colors. An aperture ratio of each of the R subpixels and the G subpixels is greater than that of each of the W subpixels.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device in which each of the pixels is divided into a red (R) subpixel, a green (G) subpixel, a blue (B) subpixel, and a white (W) subpixel. will be.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices such as are being developed. The liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. In an active matrix driving type liquid crystal display device, a thin film transistor (hereinafter referred to as "TFT") is formed for each pixel.

The liquid crystal display includes a liquid crystal display panel, a backlight unit that irradiates light to the liquid crystal display panel, a source drive integrated circuit ("IC") for supplying data voltages to the data lines of the liquid crystal display panel, and liquid crystal. A gate drive IC for supplying a gate pulse (or scan pulse) to the gate lines (or scan lines) of the display panel, a control circuit for controlling the ICs, a light source driving circuit for driving a light source of the backlight unit, etc. Equipped.

In addition to the R (Red) sub-pixel, G (Green) sub-pixel, and B (Blue) sub-pixel to each of the pixels, a liquid crystal display in which a W (White) sub-pixel is added is being developed. Hereinafter, a display device in which pixels are divided into RGBW sub-pixels is referred to as a "RGBW type display device". The W sub-pixel may lower the brightness of the backlight unit by increasing the brightness of each of the pixels, thereby lowering the power consumption of the liquid crystal display.

Conventional display devices have limitations in improving aperture ratio and transmittance by forming TFTs for every sub-pixel. In addition, although the RGBW type display device has an advantage of improving power consumption, there is a problem that the color expression power is deteriorated due to the W sub-pixel.

The present invention provides a display device capable of improving aperture ratio, transmittance, and color expression.

The display device of the present invention includes a plurality of data lines, a plurality of gate lines, a plurality of R sub-pixels, a plurality of G sub-pixels, a plurality of B sub-pixels and a plurality of W sub-pixels, and a TFT connected to the sub-pixels. A display device formed therein; And a black matrix BM overlapping the data lines, the gate lines, and the TFTs.

The W subpixels include a plurality of TFTs connected to neighboring subpixels of different colors.

An aperture ratio of each of the R subpixels and the G subpixels is greater than that of each of the W subpixels.

The display device of the present invention can improve the aperture ratio and transmittance of the sub-pixels by reducing the number of TFTs in at least the R sub-pixels and the G sub-pixels among RGB sub-pixels excluding the W sub-pixels, and improve color expression.

1 is a block diagram showing a display device according to an exemplary embodiment of the present invention.
2 and 3 are diagrams showing a pixel array according to a first embodiment of the present invention.
4 is a diagram showing a black matrix of a pixel array according to the first embodiment of the present invention.
5 is a diagram comparing a conventional RGBW type display device with a yellow color expression of the present invention.
6 is a diagram showing a black matrix of a pixel array according to a second embodiment of the present invention.
7 is a diagram showing a black matrix of a pixel array according to a second embodiment of the present invention.
8 is a diagram showing a black matrix of a pixel array according to a third embodiment of the present invention.
9 is a diagram showing a black matrix of a pixel array according to a fourth embodiment of the present invention.
10 is a diagram showing a black matrix of a pixel array according to a fifth embodiment of the present invention.
11 is a waveform diagram illustrating an example of outputting a data voltage without charge sharing from a source drive IC when data voltages of the same polarity are supplied to data lines during one frame period.
FIG. 12 is a waveform diagram showing an example of outputting a data voltage after performing charge-sharing in every horizontal period in a source drive IC when data voltages of the same polarity are supplied to data lines during one frame period.
13 is a diagram showing a black matrix of a pixel array according to a sixth embodiment of the present invention.
14 is a diagram showing a black matrix of a pixel array according to a seventh embodiment of the present invention.
15 is a diagram showing a black matrix of a pixel array according to an eighth embodiment of the present invention.
FIG. 16 is a diagram illustrating in detail the structure of pixels by enlarging pixels in a rectangular box in FIG. 15.

The display device of the present invention may be implemented as a flat panel display device capable of implementing colors such as a liquid crystal display (LCD), an organic light emitting diode display (OLED display), and a plasma display panel (PDP). Hereinafter, embodiments of the present invention will be described centering on a liquid crystal display, but it should be noted that the present invention is not limited to the liquid crystal display. For example, the arrangement of RGBW sub-pixels of the present invention is applicable to an organic light emitting diode display.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

Referring to FIG. 1, the display device of the present invention includes a display panel 100 on which a pixel array is formed, and a display panel driving circuit for writing data of an input image to the display panel 100. A backlight unit for uniformly irradiating light to the display panel 100 may be disposed under the display panel 100.

The display panel 100 includes an upper substrate and a lower substrate facing each other with a liquid crystal layer therebetween. The pixel array of the display panel 100 includes pixels arranged in a matrix form by an intersection structure of the data lines S1 to Sm and the gate lines G1 to Gn.

The lower substrate of the display panel 100 includes data lines S1 to Sm, gate lines G1 to Gn, TFTs, a pixel electrode 1 connected to the TFT, and a storage connected to the pixel electrode 1 Includes a capacitor (Storage Capacitor, Cst).

Each of the pixels may be divided into two sub-pixels having different colors or four sub-pixels having different colors. For example, a first pixel may include R and G subpixels, and a second pixel may include B and W subpixels. When each of the pixels is divided into four sub-pixels, each of the pixels includes RGBW sub-pixels.

Each of the sub-pixels adjusts the amount of light transmitted by using liquid crystal molecules driven by a voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. do. As shown in FIGS. 2 to 9, among RGBW sub-pixels, W sub-pixels are manufactured in an asymmetric structure having a small size. One of the RGB sub-pixels may be manufactured to have a smaller size than the sub-pixels of other colors. The asymmetric structure of the pixels and the enlargement of the size of the RGB sub-pixels improve the aperture ratio, transmittance, and color expression of the pixels compared to the prior art.

The W sub-pixels include two or four TFTs connected to neighboring sub-pixels of different colors. Accordingly, W subpixels have a smaller aperture ratio than that of neighboring subpixels of other colors.

TFTs formed on the lower substrate of the display panel 100 may be implemented as an amorphose Si (a-Si) TFT, a Low Temperature Poly Silicon (LTPS) TFT, an oxide TFT, or the like. The TFTs are connected 1:1 to the pixel electrode of the sub-pixels.

A color filter array including a black matrix (BM) and a color filter is formed on the upper substrate of the display panel 100. The common electrode 2 is formed on the upper substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) In the case of a horizontal electric field driving method such as a mode, it may be formed on the lower substrate together with the pixel electrode. A polarizing plate is attached to each of the upper and lower substrates of the display panel 100 and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The display device of the present invention may be implemented in any form such as a transmissive liquid crystal display, a transflective liquid crystal display, and a reflective liquid crystal display. Transmissive liquid crystal display devices and transflective liquid crystal display devices require a backlight unit. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel driving circuit writes data of an input image to pixels. Data written to the pixels includes R data, G data, B data and W data. The display panel driving circuit includes a data driver 102, a gate driver 104, and a timing controller 106.

The data driver 102 includes a plurality of source drive ICs. The data output channels of the source drive ICs are connected to the data lines S1 to Sm of the pixel array. The source drive ICs receive input image data from the timing controller 106. The digital video data transmitted to the source drive ICs includes R data, G data, B data, and W data. The source drive ICs convert RGBW digital video data of an input image into a positive/negative gamma compensation voltage under the control of the timing controller 106 and output a positive/negative data voltage. The output voltages of the source drive ICs are supplied to the data lines S1 to Sm.

Each of the source drive ICs inverts the polarity of data voltages to be supplied to the pixels under the control of the timing controller 106 and outputs them to the data lines S1 to Sm. As shown in FIGS. 2 to 9, 11, and 12, the source drive ICs may maintain the polarity of the data voltage applied to the data lines for one frame period, and then reverse the polarity of the data voltage every frame. According to the present invention, since the polarity of the data voltage is not changed for one frame period in each of the data lines, power consumption and heat generation of the source drive ICs can be reduced. Also, the source drive ICs may invert the polarity of the data voltages applied to the data lines in a period of 2 horizontal periods as shown in FIG. 10.

The gate driver 104 sequentially supplies gate pulses to the gate lines G1 to Gn under the control of the timing controller 106. The gate pulse output from the gate driver 104 is synchronized with the positive/negative video data voltage to be charged to the pixels. The gate driver 104 may be directly formed on the lower substrate of the display panel 100 together with the pixel array in the same manufacturing process to reduce IC cost.

The timing controller 106 converts RGB data of an input image received from the host system 110 into RGBW data and transmits the converted RGB data to the data driver 102. An interface for data transmission between the timing controller 106 and the source drive ICs of the data driver 102 may use a mini LVDS (low-voltage differential signaling) interface or an EPI (Embedded Panel Interface) interface. EPI interface is a Korean patent application filed by the applicant of the present application 10-2008-0127458 (2008-12-15), US application 12/543,996 (2009-08-19), Korean patent application 10-2008-0127456 (2008-12) -15), US application 12/461,652 (2009-08-19), Korean patent application 10-2008-0132466 (2008-12-23), US application 12/537,341 (2009-08-07), etc. Can be applied as

The timing controller 106 receives timing signals synchronized with the input image data from the host system 110. Timing signals include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), a dot clock (DCLK), and the like. The timing controller 106 controls operation timings of the data driver 102 and the gate driver 104 based on timing signals Vsync, Hsync, DE, and DCLK received together with pixel data of an input image. The timing controller 106 may transmit a polarity control signal for controlling the polarity of the pixel array to each of the source drive ICs of the data driver 102. Mini LVDS interface transmits polarity control signals through separate control wiring. The EPI interface is an interface technology that encodes polarity control information in a control data packet transmitted between a clock training pattern for CDR (Clok and Data Recovery) and an RGBW data packet and transmits it to each of the source drive ICs.

The timing controller 106 may convert RGB data of an input image into RGBW data using a white gain calculation algorithm. Any known white gain calculation algorithm is possible. For example, Korean Patent Application No. 10-2005-0039728 (2005. 05. 12), Korean Patent Application No. 10-2005-0052906 (2005. 06. 20), Korean Patent Application No. 10-2005 previously filed by the applicant of the present application The white gain calculation algorithms proposed in -0066429 (2007. 07. 21) and Korean Patent Application No. 10-2006-0011292 (2006. 02. 06) can be applied.

The host system 110 may be any one of a TV (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

In the display device of the present invention, pixels are fabricated in an asymmetric structure having a relatively small size of a W sub-pixel as shown in FIGS. 2 to 9 in order to improve the aperture ratio, transmittance, and color expression of pixels. In addition, among the RGB sub-pixels, the B sub-pixel may have a smaller size than the R and G sub-pixels.

2 and 3 are diagrams showing a pixel array according to a first embodiment of the present invention. 4 is a diagram showing a black matrix of a pixel array according to the first embodiment of the present invention.

2 to 4, color arrangement of sub-pixels in odd-numbered horizontal lines L1 and L3 of the pixel array is arranged in the order of W R B G from left to right. In the odd-numbered horizontal lines L1 and L3, the W subpixel is disposed at the 4ith (i is a positive integer of 0) + 1th subpixel. Here, the value of i increases as it goes to the right. The R subpixel is disposed in the 4i+2 th subpixel. The B subpixel is disposed in the 4i+3th subpixel, and the G subpixel is disposed in the 4i+4th subpixel.

Color arrangements of sub-pixels in the even-th horizontal lines L2 and L4 of the pixel array are arranged in the order of B G W R from left to right. In the even-th horizontal lines L2 and L4, the B subpixel is disposed in the 4i+1th subpixel. Here, the value of i increases as it goes to the right. The G subpixel is disposed in the 4i+2 th subpixel. The W sub-pixel is disposed in the 4i+3 th sub-pixel, and the R sub-pixel is disposed in the 4i+4 th sub-pixel.

The pixel electrodes P11 to P18 of each of the sub-pixels are connected to the TFT. In order to increase the aperture and transmittance of the R and G sub-pixels, the size of the R and G sub-pixels is made larger than that of the W and B sub-pixels. To this end, the R and G sub-pixels are connected to a TFT disposed in the W and B sub-pixels.

The W sub-pixel includes two TFTs T11, T12, T17 and T18. When two TFTs (T11, T12, T17, T18) are arranged in the W sub-pixels, in order to secure the space of the TFTs, the distance between the neighboring data lines with the W sub-pixels between them as shown in FIG. 16 is The spacing can be large at the TFT position. In Fig. 16, "L1" is a distance between neighboring data lines with two TFTs interposed therebetween, and "L2" is a distance between neighboring data lines in a central region of a pixel in which TFTs are not arranged.

The B sub-pixel includes two TFTs T13, T14, T15 and T16. When two TFTs (T13, T14, T15, T16) are arranged in the B sub-pixels, in order to secure a space for the TFTs, the data lines adjacent to the B sub-pixels between them as shown in FIG. The gap can be large.

In the odd-numbered horizontal lines (L1, L3), the first TFT (T11) disposed in the W sub-pixel responds to the odd-numbered gate lines (G1, G3), j-th (j is a positive integer) + 1 data The W data voltage supplied through the lines S1 and S5 is supplied to the first pixel electrode P11 in the W subpixel. The gate of the first TFT T11 is connected to the odd-numbered gate lines G1 and G3. The drain of the first TFT T11 is connected to the j+1th data lines S1 and S5, and the source of the first TFT T11 is connected to the first pixel electrode P11.

In the odd-numbered horizontal lines (L1, L3), the second TFT (T12) disposed in the W sub-pixel is supplied through the j+2th data lines (S2, S6) in response to the odd-numbered gate lines (G1, G3). The R data voltage is supplied to the second pixel electrode P12 in the R subpixel. The gate of the second TFT T12 is connected to the odd-numbered gate lines G1 and G3. The drain of the second TFT T12 is connected to the j+2th data lines S2 and S6, and the source of the second TFT T12 is connected to the second pixel electrode P12. Therefore, since the R sub-pixel does not include a TFT, the aperture ratio and transmittance can be increased compared to the W sub-pixel including two TFTs.

In the odd-numbered horizontal lines (L1, L3), the third TFT (T13) disposed in the B sub-pixel is supplied through the j+3th data lines (S3, S7) in response to the odd-numbered gate lines (G1, G3). The B data voltage is supplied to the third pixel electrode P13 in the B subpixel. The gate of the third TFT T13 is connected to the odd-numbered gate lines G1 and G3. The drain of the third TFT T13 is connected to the j+3th data lines S3 and S7, and the source of the third TFT T13 is connected to the third pixel electrode P13.

In the odd-numbered horizontal lines (L1, L3), the fourth TFT (T14) disposed in the B sub-pixel is supplied through the j+4th data lines (S4, S8) in response to the odd-numbered gate lines (G1, G3). The G data voltage is supplied to the fourth pixel electrode P14 in the G subpixel. The gate of the fourth TFT T14 is connected to the odd-numbered gate lines G1 and G3. The drain of the fourth TFT T14 is connected to the j+4th data lines S4 and S8, and the source of the fourth TFT T14 is connected to the fourth pixel electrode P14. Therefore, since the G sub-pixel does not include a TFT, the aperture ratio and transmittance can be increased compared to the B sub-pixel including two TFTs.

In the even-th horizontal lines (L2, L4), the fifth TFT (T15) disposed in the B sub-pixel is supplied through the j+1th data lines (S1, S5) in response to the even-th gate lines (G2, G4). The resulting B data voltage is supplied to the fifth pixel electrode P15 in the B subpixel. The gate of the fifth TFT T15 is connected to the even-th gate lines G2 and G4. The drain of the fifth TFT T15 is connected to the j+1th data lines S1 and S5, and the source of the fifth TFT T15 is connected to the fifth pixel electrode P15.

In the even-th horizontal lines (L2, L4), the sixth TFT (T16) disposed in the B sub-pixel is supplied through the j+2th data lines (S2, S6) in response to the even-th gate lines (G2, G4). The G data voltage is supplied to the sixth pixel electrode P16 in the G subpixel. The gate of the sixth TFT T16 is connected to the even-th gate lines G2 and G6. The drain of the sixth TFT T16 is connected to the j+2th data lines S2 and S6, and the source of the sixth TFT T16 is connected to the sixth pixel electrode P16. Therefore, since the G sub-pixel does not include a TFT, the aperture ratio and transmittance can be increased compared to the B sub-pixel including two TFTs.

In the even-th horizontal lines (L2, L4), the seventh TFT (T17) disposed in the W sub-pixel is supplied through the j+3th data lines (S3, S7) in response to the even-th gate lines (G2, G4). The resulting W data voltage is supplied to the seventh pixel electrode P17 in the W subpixel. The gate of the seventh TFT T17 is connected to the even-th gate lines G2 and G4. The drain of the seventh TFT T17 is connected to the j+3th data lines S3 and S7, and the source of the seventh TFT T17 is connected to the seventh pixel electrode P17.

In the even-th horizontal lines (L2, L4), the eighth TFT (T18) disposed in the W sub-pixel is supplied through the j+4th data lines (S4, S8) in response to the even-th gate lines (G2, G4). The R data voltage is supplied to the eighth pixel electrode P18 in the R subpixel. The gate of the eighth TFT T18 is connected to the even-th gate lines G2 and G4. The drain of the eighth TFT T18 is connected to the j+4th data lines S4 and S8, and the source of the eighth TFT T18 is connected to the eighth pixel electrode P18. Therefore, since the R sub-pixel does not include a TFT, the aperture ratio and transmittance can be increased compared to the W sub-pixel including two TFTs.

The black matrix BM overlaps the TFTs and the wirings S1 to S8 and G1 to G3 so that the TFTs and the wirings S1 to S8 and G1 to G3 are not visible. The horizontal line width of the black matrix BM is wide (W1) in the W sub-pixel and the B sub-pixel, and narrow in the R and G sub-pixels (W2), as shown in FIG. 4.

By increasing the aperture ratio and transmittance of the R and G sub-pixels, it is possible to improve the expressive power of yellow compared to the conventional RGBW type display device. As a result of increasing the aperture ratio of the R and G sub-pixels by 9.8% compared to the conventional RGBW type display device and measuring the color temperature of yellow, as shown in FIG. 5, the color temperature of yellow in both outdoors, indoors, and peak control. Was measured high, indicating that the color expression of yellow was improved.

There is no horizontal crosstalk since there is no shift of the common voltage Vcom when the polarities of the sub-pixels of the same color are balanced in the same horizontal lines L1 to L4. The voltages of the data lines S1 to S8 are maintained at the same polarity for one frame period as shown in FIGS. 11 and 12. To satisfy this, the polarity of the data voltage supplied to the pixels through the j+1th, j+4, j+6th, and j+7th data lines S1, S4, S6, S7 is N ( N is a positive integer) maintaining the first polarity during the frame period, and then inverting the next frame period to maintain the second polarity during the N+1th frame period. The polarity of the data voltage supplied to the pixels through the j+2, j+3, j+5, and j+8th data lines S2, S3, S5, and S8 is the second polarity during the Nth frame period Is maintained, and is inverted in the next frame period to maintain the first polarity during the N+1th frame period.

Charge sharing is performed by short circuiting the data lines S1 to S8 before outputting the next data voltage to reduce the voltage of the data lines to the average potential of the positive data voltage and the negative data voltage simultaneously applied to the data lines. This is how to adjust. If the next data voltage is output after performing charge sharing, the amount of current is lowered compared to the output buffer current of the source drive IC that occurs when the data voltage is output with the opposite polarity without charge sharing, thus reducing the power consumption and heat generation of the source drive IC. Can be reduced. This is because the swing width when the data voltage of the next polarity is output from the average potential is smaller than the swing width when the data voltage of the opposite polarity is changed without charge sharing.

The asymmetric structure of the pixel array is not limited to FIGS. 2 to 4 as shown in FIGS. 2 to 16 and may be variously modified.

6 is a diagram showing a black matrix of a pixel array according to a second embodiment of the present invention. 7 is a diagram showing a black matrix of a pixel array according to a second embodiment of the present invention.

6 and 7, color arrangements of sub-pixels in odd-numbered horizontal lines L1 and L3 of the pixel array are arranged in the order of W R G B from left to right. The color arrangement of sub-pixels in the even-th horizontal lines L2 and L4 of the pixel array is arranged in the order of G B W R from left to right.

The pixel electrodes of each of the sub-pixels are connected to the TFTs T21 to T36. In order to increase the aperture ratio and transmittance of the RGB sub-pixels, the size of each of the RGB sub-pixels is made larger than that of the W sub-pixel. To this end, TFTs connected to the RGB sub-pixels are arranged in the W sub-pixel.

The black matrix BM overlaps the TFTs and the wirings S1 to S8 and G1 to G3 so that the TFTs and the wirings S1 to S8 and G1 to G3 are not visible. The horizontal line width of the black matrix BM is wide (W1) in the W subpixel and narrow (W2) in the RGB subpixels, as shown in FIG. 6.

There is no horizontal crosstalk since there is no shift of the common voltage Vcom when the polarities of the sub-pixels of the same color are balanced in the same horizontal lines L1 to L4. The voltages of the data lines S1 to S8 are maintained at the same polarity for one frame period as shown in FIGS. 11 and 12. To meet this, the polarity of the data voltages supplied to the pixels through the j+1th, j+4, j+6th, and j+7th data lines S1, S4, S6, S7 is the Nth frame. The first polarity is maintained during the period, and then inverted in the next frame period to maintain the second polarity during the N+1th frame period. The polarity of the data voltage supplied to the pixels through the j+2, j+3, j+5, and j+8th data lines S2, S3, S5, and S8 is the second polarity during the Nth frame period Is maintained, and is inverted in the next frame period to maintain the first polarity during the N+1th frame period.

8 is a diagram showing a black matrix of a pixel array according to a third embodiment of the present invention.

Referring to FIG. 8, color arrangement of subpixels in odd-numbered horizontal lines L1 and L3 of the pixel array is arranged in the order of R G B W from left to right. Color arrangements of sub-pixels in the even-th horizontal lines L2 and L4 of the pixel array are arranged in the order of B W R G from left to right.

The pixel electrodes of each of the sub-pixels are connected to the TFTs T41 to T58. In order to increase the aperture ratio and transmittance of the RGB sub-pixels, the size of each of the RGB sub-pixels is made larger than that of the W sub-pixel. To this end, TFTs connected to the RGB sub-pixels are arranged in the W sub-pixel.

The black matrix BM overlaps the TFTs and the wirings S1 to S8 and G1 to G3 so that the TFTs and the wirings S1 to S8 and G1 to G3 are not visible. The horizontal line width of the black matrix BM is wide (W1) in W subpixels and narrow (W2) in RGB subpixels.

There is no horizontal crosstalk since there is no shift of the common voltage Vcom when the polarities of the sub-pixels of the same color are balanced in the same horizontal lines L1 to L4. The voltages of the data lines S1 to S8 are maintained at the same polarity for one frame period as shown in FIGS. 11 and 12. To meet this, the polarity of the data voltages supplied to the pixels through the j+1th, j+2, j+4th, and j+7th data lines S1, S2, S4, S7 is the Nth frame. The first polarity is maintained during the period, and then inverted in the next frame period to maintain the second polarity during the N+1th frame period. The polarity of the data voltage supplied to the pixels through the j+3, j+5, j+6, and j+8th data lines S3, S5, S6, and S8 is the second polarity during the Nth frame period. Is maintained, and is inverted in the next frame period to maintain the first polarity during the N+1th frame period.

In order to implement the pixel array as shown in FIG. 8, it is necessary to add a dummy data line to one end of the pixel array and add a line memory to the timing controller 102. In contrast, a separate dummy data line or line memory is not required to implement the pixel array as shown in FIGS. 6 and 7.

In the pixel array shown in FIGS. 2 to 8, all sub-pixels arranged on one horizontal line are connected to one gate line. Accordingly, in the pixel array of FIGS. 2 to 8, when a gate pulse is applied to one gate line, all pixels of one horizontal line connected to the gate line charge the data voltage.

9 is a diagram showing a black matrix of a pixel array according to a fourth embodiment of the present invention.

Referring to FIG. 9, color arrangement of subpixels in odd-numbered horizontal lines L1 and L3 of the pixel array is arranged in the order of R G B W from left to right. Color arrangements of sub-pixels in the even-th horizontal lines L2 and L4 of the pixel array are arranged in the order of B W R G from left to right.

The pixel electrodes of each of the sub-pixels are connected to the TFTs T61 to T78. In order to increase the aperture ratio and transmittance of the RGB sub-pixels, the size of each of the RGB sub-pixels is made larger than that of the W sub-pixel. To this end, TFTs connected to the RGB sub-pixels are arranged in the W sub-pixel.

The black matrix BM overlaps the TFTs and the wirings S1 to S8 and G1 to G3 so that the TFTs and the wirings S1 to S8 and G1 to G3 are not visible. The horizontal line width of the black matrix BM is wide (W1) in W subpixels and narrow (W2) in RGB subpixels.

There is no horizontal crosstalk since there is no shift of the common voltage Vcom when the polarities of the sub-pixels of the same color are balanced in the same horizontal lines L1 to L4. The voltages of the data lines S1 to S8 are maintained at the same polarity for one frame period as shown in FIGS. 11 and 12. To meet this, the polarity of the data voltages supplied to the pixels through the j+1th, j+4, j+6th, and j+7th data lines S1, S4, S6, S7 is the Nth frame. The first polarity is maintained during the period, and then inverted in the next frame period to maintain the second polarity during the N+1th frame period. The polarity of the data voltage supplied to the pixels through the j+2, j+3, j+5, and j+8th data lines S2, S3, S5, and S8 is the second polarity during the Nth frame period Is maintained, and is inverted in the next frame period to maintain the first polarity during the N+1th frame period.

In the pixel array as shown in FIG. 9, all sub-pixels arranged on two horizontal lines are connected to three gate lines. Accordingly, in the pixel array as shown in FIG. 9, gate pulses must be sequentially applied to the three gate lines so that all pixels disposed on the two horizontal lines charge the data voltage. For example, in FIG. 9, when a first gate pulse is applied to the first gate line G1, the TFTs T63 and T64 are turned on, so that the B and W sub-pixels of the first horizontal line L1 Charge the data voltage. Subsequently, when a second gate pulse is applied to the second gate line G2, the TFTs T61, T62, T67, and T68 are turned on, and R and G disposed on the first and second horizontal lines L1 and L2 are turned on. The sub-pixels charge the data voltage. Subsequently, when a third gate pulse is applied to the third gate line G3, the TFTs T65, T66, T72, and T73 are turned on to turn on the B and W subpixels disposed on the second horizontal line L2, and 3 W and R sub-pixels arranged on the horizontal line L3 charge the data voltage.

10 is a diagram showing a black matrix of a pixel array according to a fifth embodiment of the present invention.

Referring to FIG. 10, color arrangements of subpixels in odd-numbered horizontal lines L1 and L3 of the pixel array are arranged in the order of R G B W from left to right. Color arrangements of sub-pixels in the even-th horizontal lines L2 and L4 of the pixel array are arranged in the order of B W R G from left to right.

The pixel electrodes of each of the sub-pixels are connected to the TFTs T81 to T88. In order to increase the aperture ratio and transmittance of the RGB sub-pixels, the size of each of the RGB sub-pixels is made larger than that of the W sub-pixel. To this end, TFTs connected to the RGB sub-pixels are arranged in the W sub-pixel.

The black matrix BM overlaps the TFTs and the wirings S1 to S8 and G1 to G3 so that the TFTs and the wirings S1 to S8 and G1 to G3 are not visible. The horizontal line width of the black matrix BM is wide (W1) in W subpixels and narrow (W2) in RGB subpixels.

There is no horizontal crosstalk since there is no shift of the common voltage Vcom when the polarities of the sub-pixels of the same color are balanced in the same horizontal lines L1 to L4. In a display with a large number of moving pictures and a large screen, for example, a display device such as a monitor or a television of a computer may generate vertical crosstalk due to an increase in off current of a TFT. In order to improve this problem, the polarity of the pixel array can be controlled by dot inversion. In this case, by controlling the polarities of the subpixels of the same color adjacent to each other in the vertical line to be opposite to each other, uniformity of image quality can be improved without spots on the entire screen. One dot is equal to one sub-pixel. When the polarity of the pixel array is vertical 2-dot inversion, the polarity of the data voltage applied to the data lines S1 to S8 is inverted in units of 2 horizontal periods. The polarity of the data voltage supplied to the pixels through the j+1th, j+4, j+6, and j+7th data lines S1, S4, S6, and S7 is the first polarity during the Nth frame period Is maintained, and is inverted in the next frame period to maintain the second polarity during the N+1th frame period. The polarity of the data voltage supplied to the pixels through the j+2, j+3, j+5, and j+8th data lines S2, S3, S5, and S8 is the second polarity during the Nth frame period Is maintained, and is inverted in the next frame period to maintain the first polarity during the N+1th frame period.

In the pixel array as shown in FIG. 10, all subpixels arranged on one horizontal line are connected to one gate line. Accordingly, in the pixel array as shown in FIG. 10, when a gate pulse is applied to one gate line, all pixels of one horizontal line connected to the gate line charge the data voltage.

11 is an example of outputting a data voltage without charge sharing from a source drive IC when data voltages of the same polarity are supplied to data lines for one frame period. FIG. 12 is an example of outputting a data voltage after performing charge-sharing in every horizontal period in a source drive IC when data voltages of the same polarity are supplied to data lines during one frame period. 11 and 12, "VB" is a vertical blank period without a data voltage.

13 is a diagram showing a black matrix of a pixel array according to a sixth embodiment of the present invention.

Referring to FIG. 13, color arrangements of subpixels in odd-numbered horizontal lines L1 and L3 of the pixel array are arranged in the order of W R B G from left to right. Color arrangements of sub-pixels in the even-th horizontal lines L2 and L4 of the pixel array are arranged in the order of B G W R from left to right.

The pixel electrodes of each of the sub pixels are connected to the TFT. In order to increase the aperture ratio and transmittance of the RG sub-pixels, the size of each of the RG sub-pixels is made larger than that of the WB sub-pixel. To this end, a TFT connected to the R sub-pixel is disposed in the W sub-pixel. The TFT connected to the G sub-pixel is disposed in the B sub-pixel.

The black matrix overlaps with the TFTs and the wirings S1 to S8 and G1 to G3 so that the TFTs and wirings are not visible. The line width of the horizontal line of the black matrix BM is wide (W1) in the WB subpixels and narrow (W2) in the RG subpixels.

The voltages of the data lines S1 to S8 are maintained at the same polarity for one frame period as shown in FIGS. 11 and 12. The polarity of the data voltage supplied to the pixels through the j+1th, j+4, j+6, and j+7th data lines S1, S4, S6, and S7 is the first polarity during the Nth frame period Is maintained, and is inverted in the next frame period to maintain the second polarity during the N+1th frame period. The polarity of the data voltage supplied to the pixels through the j+2, j+3, j+5, and j+8th data lines S2, S3, S5, and S8 is the second polarity during the Nth frame period Is maintained, and is inverted in the next frame period to maintain the first polarity during the N+1th frame period.

14 is a diagram showing a black matrix of a pixel array according to a seventh embodiment of the present invention.

Referring to FIG. 14, color arrangement of subpixels in odd-numbered horizontal lines L1 and L3 of the pixel array is arranged in the order of W R B G from left to right. Color arrangements of sub-pixels in the even-th horizontal lines L2 and L4 of the pixel array are arranged in the order of B G W R from left to right.

The pixel electrodes of each of the sub pixels are connected to the TFT. In order to increase the aperture ratio and transmittance of the RG sub-pixels, the size of each of the RG sub-pixels is made larger than that of the WB sub-pixel. To this end, a TFT connected to the R sub-pixel is disposed in the W sub-pixel. The TFT connected to the G sub-pixel is disposed in the B sub-pixel.

The black matrix overlaps with the TFTs and the wirings S1 to S8 and G1 to G3 so that the TFTs and wirings are not visible. The line width of the horizontal line of the black matrix BM is wide (W1) in the WB subpixels and narrow (W2) in the RG subpixels.

The voltages of the data lines S1 to S8 are inverted every two horizontal periods. The polarity of the data voltage supplied to the pixels through the j+1th, j+4, j+6, and j+7th data lines S1, S4, S6, and S7 is the first polarity during the Nth frame period Is maintained, and is inverted in the next frame period to maintain the second polarity during the N+1th frame period. The polarity of the data voltage supplied to the pixels through the j+2, j+3, j+5, and j+8th data lines S2, S3, S5, and S8 is the second polarity during the Nth frame period Is maintained, and is inverted in the next frame period to maintain the first polarity during the N+1th frame period. Accordingly, the polarity of the pixel array is inverted in a vertical 2-line period, and inverted in a horizontal 1-dot and horizontal 2-dot period.

In the case of the horizontal electric field driving method, the pixel electrode 1 and the common electrode 2 are formed together on the lower substrate of the display panel. In this case, the pixel electrode 1 is disposed over the common electrode 2, and an insulating film is formed between them. Further, the common electrode 2 may be disposed on the pixel electrode 1 and an insulating film may be formed therebetween.

15 and 16 are diagrams showing a black matrix of a pixel array according to an eighth embodiment of the present invention.

Referring to FIGS. 15 and 16, color arrangements of sub-pixels in odd-numbered horizontal lines L1 and L3 of the pixel array are arranged in the order of B R W G from left to right. The color arrangement of sub-pixels in the even-th horizontal lines L2 and L4 of the pixel array is arranged in the order of G W R B from left to right.

The pixel electrodes of each of the sub pixels are connected to the TFT. In order to increase the aperture ratio and transmittance of the RG sub-pixels, the size of each of the RG sub-pixels is made larger than that of the W sub-pixel. To this end, a TFT connected to the R sub-pixel is disposed in the W sub-pixel. The TFT connected to the G sub-pixel is disposed in the B sub-pixel.

The black matrix overlaps with the TFTs and the wirings S1 to S8 and G1 to G3 so that the TFTs and wirings are not visible. The line width of the horizontal line of the black matrix BM is wide (W1) in the WB subpixels and narrow (W2) in the RG subpixels.

The voltages of the data lines S1 to S8 are maintained at the same polarity for one horizontal period. It is reversed by a period of 2 horizontal periods. The polarity of the data voltage supplied to the pixels through the j+1th, j+4, j+6, and j+7th data lines S1, S4, S6, and S7 is the first polarity during the Nth frame period Is maintained, and is inverted in the next frame period to maintain the second polarity during the N+1th frame period. The polarity of the data voltage supplied to the pixels through the j+2, j+3, j+5, and j+8th data lines S2, S3, S5, and S8 is the second polarity during the Nth frame period Is maintained, and is inverted in the next frame period to maintain the first polarity during the N+1th frame period.

On the other hand, each of the pixels of the OLED display includes two or more TFTs including a switch TFT and a driving TFT. In such an organic light emitting diode display, the above-described embodiments may be applied to include TFTs connected to subpixels of different colors in the W subpixels. Here, TFTs connected to the subpixels of different colors may be one or more of a switch TFT and a driving TFT.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

100: display panel 102: data driver
104: gate driver 106: timing controller
110: host system

Claims (10)

A pixel array including a plurality of data lines, a plurality of gate lines, and a plurality of R sub-pixels, a plurality of G sub-pixels, a plurality of B sub-pixels and a plurality of W sub-pixels, and thin film transistors connected to the sub-pixels; And
And a black matrix overlapping the data lines, the gate lines, and the thin film transistors,
Each of the W subpixels includes a plurality of TFTs connected to neighboring subpixels of different colors,
An aperture ratio of each of the R subpixels and the G subpixels is greater than that of each of the W subpixels,
The R, G, B, and W subpixels are arranged in a first order on an odd-numbered horizontal line of the pixel array, and the R, G, B, and W sub-pixels are arranged on an even-numbered horizontal line of the pixel array. Arranged in a second order different from the first order,
All of the R, G, B, and W sub-pixels arranged on each horizontal line of the odd-numbered and even-numbered horizontal lines are connected to the same gate line. The method of claim 1,
The W sub-pixels include two TFTs connected to neighboring sub-pixels of different colors,
A display device without a TFT in the R sub-pixels and the G sub-pixels. The method of claim 2,
The line width of the black matrix is widened in the W sub-pixels and narrowed in the R sub-pixels and the G sub-pixels. The method of claim 1,
The W sub-pixels include four TFTs connected to neighboring sub-pixels of different colors,
The aperture ratio of each of the B subpixels is greater than that of each of the W subpixels,
A display device without a TFT in the R sub-pixels, the G sub-pixels, and the B sub-pixels. The method of claim 4,
A display device in which a line width of the black matrix is widened in the W subpixels and narrowed in the R subpixels, the G subpixels, and the B subpixels. The method of claim 1,
The first order is an order of W, R, B, and G subpixels from the first side to the second side of the odd-numbered horizontal line, and the second order is from the first side of the even-numbered horizontal line to the second side. A display device in the order of B, G, W and R sub-pixels toward the side. The method of claim 1,
The first order is the order of W, R, G, and B subpixels from the first side to the second side of the odd-numbered horizontal line, and the second order is from the first side of the even-numbered horizontal line to the second side. A display device in the order of the G, B, W and R sub-pixels toward the side. The method of claim 1,
The first order is an order of R, G, B, and W subpixels from the first side to the second side of the odd-numbered horizontal line, and the second order is from the first side of the even-numbered horizontal line to the second side. A display device in the order of B, W, R and G sub-pixels to the side. The method of claim 1,
The first order is the order of B, R, W, and G subpixels from the first side to the second side of the odd-numbered horizontal line, and the second order is from the first side of the even-numbered horizontal line to the second side. A display device in the order of G, W, R and B sub-pixels to the side. A pixel array including a plurality of data lines, a plurality of gate lines, and a plurality of R sub-pixels, a plurality of G sub-pixels, a plurality of B sub-pixels and a plurality of W sub-pixels, and thin film transistors connected to the sub-pixels; And
And a black matrix overlapping the data lines, the gate lines, and the thin film transistors,
Each of the W subpixels includes a plurality of TFTs connected to neighboring subpixels of different colors,
An aperture ratio of each of the R subpixels and the G subpixels is greater than that of each of the W subpixels,
The R, G, B, and W subpixels are arranged in a first order on an odd-numbered horizontal line of the pixel array, and the R, G, B, and W sub-pixels are arranged on an even-numbered horizontal line of the pixel array. Arranged in a second order different from the first order,
The first order is an order of R, G, B, and W subpixels from the first side to the second side of the odd-numbered horizontal line, and the second order is from the first side of the even-numbered horizontal line to the second side. A display device in the order of B, W, R and G sub-pixels to the side.

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