KR102458079B1 - Display device and charge sharing methode thereof - Google Patents

Abstract

The present invention relates to a display device and a charge sharing method thereof, wherein a plurality of data lines and a plurality of gate lines are crossed, sub-pixels are arranged in a matrix form, and a light emitting device including a cathode and an anode in each of the sub-pixels is provided. an arranged display panel; a data driver supplying a data voltage without polarity inversion to the data lines in every frame; and a charge share circuit that shorts the data lines before the next data voltage is generated from the data driver.

Description

DISPLAY DEVICE AND CHARGE SHARING METHODE THEREOF

The present invention relates to a display device for performing charge sharing on preset data lines and a charge sharing method therefor.

The flat panel display includes a liquid crystal display (LCD), an electroluminescence display, a field emission display (FED), and a plasma display panel (PDP). The electroluminescent display is divided into an inorganic light emitting display and an organic light emitting display according to the material of the light emitting layer. Pixels of the organic light emitting diode display display an image using organic light emitting diodes (hereinafter, referred to as "OLEDs"), which are self-luminous devices.

Various driving methods for reducing power consumption in such a flat panel display are applied. As an example, there is a charge share method applied to a liquid crystal display device. In the charge share method, the data lines supplied with the positive data voltage and the data lines supplied with the negative data voltage are short-circuited to adjust the voltages of the data lines to the average voltage of the positive data voltage and the negative data voltage. Then, the power consumption is reduced by supplying the next data voltage to the data lines. Compared to the driving current of the data lines generated when the voltage of the data lines is changed from the previous data voltage to the next data voltage, the driving current of the data lines when the average voltage between the positive data voltage and the negative data voltage is changed to the next data voltage is reduced Such a charge share circuit is applied only to a liquid crystal display in which the polarity of the data voltage is inverted. In an organic light emitting diode display, an OLED, which is a light emitting element of pixels, has a polarity. For this reason, when the polarity of the data voltage is reversed in the organic light emitting diode display, the pixels cannot emit light because the OLED is not turned on in either polarity of the data voltage. Accordingly, the charge share circuit circuit is not applied in the organic light emitting diode display.

The present invention provides a display device capable of reducing power consumption by using a charge share in a display device in which the polarity of a data voltage is not inverted, and a charge sharing method thereof.

A display device of the present invention includes: a display panel in which a plurality of data lines and a plurality of gate lines intersect, sub-pixels are disposed in a matrix, and a light emitting device including a cathode and an anode is disposed in each of the sub-pixels; a data driver supplying a data voltage without polarity inversion to the data lines in every frame; and a charge share circuit that shorts the data lines before the next data voltage is generated from the data driver.
The charge share circuit short-circuits first and second data lines to which data voltages of first and second colors are supplied.
The data driver alternately outputs the data voltages of the first and second colors to the first data line through a first channel, in an order opposite to the order of the first and second colors output from the first channel The data voltages of the first and second colors are alternately output to the second data line through a second channel.

delete

delete

The charge sharing method of the display device includes supplying a data voltage of a first color to a first data line and simultaneously supplying a data voltage of a second color to a second data line, and shorting the first and second data lines. performing charge sharing between the first and second data lines, and supplying the next data voltage of the second color to the first data line and the data voltage of the first color to the second data line It includes the step of supplying

According to the present invention, power consumption of a display device can be improved by performing charge sharing between data lines in which data voltages of different colors are alternated.

In addition, according to the present invention, the charge share effect can be maximized without side effects by selectively performing the charge share based on the result of analyzing the image pattern having the charge share effect. According to the experimental results, the power consumption reduction effect of about 30% was confirmed in the analog power supply that supplies the output buffer driving power of the data driver based on the red/blue monochromatic pattern or the white pattern.

1A and 1B are views showing an electroluminescent display device according to an embodiment of the present invention.
2 is a circuit diagram illustrating an example of a pixel circuit according to an embodiment of the present invention.
3 is a waveform diagram showing a pixel driving signal.
4A and 4B are diagrams illustrating color arrangement of a pixel array.
FIG. 5A is a waveform diagram illustrating a driving signal of the pixel array and a control signal of a charge share circuit illustrated in FIG. 4A .
FIG. 5B is a waveform diagram illustrating a driving signal of the pixel array and a control signal of a charge share circuit shown in FIG. 4B.
6A to 6C are circuit diagrams illustrating a charge share circuit according to a first embodiment of the present invention.
7A to 7D are circuit diagrams illustrating a charge share circuit according to a second embodiment of the present invention.
8A and 8B are diagrams illustrating an image analysis unit and a CS control unit.
9A and 9B are waveform diagrams illustrating a control signal for controlling a charge share.
10A and 10B are diagrams illustrating a charge share effect in a white pattern.
11A and 11B are diagrams illustrating an example of a charge sharing method in which power consumption is not reduced.
12A to 18B are diagrams illustrating examples of applying a charge share in various image patterns displayed on the pixel array shown in FIG. 4A .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains It is provided to fully understand the scope of the invention, and the invention is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiment of the present invention are exemplary, the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When "includes", "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it may be interpreted as the plural unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship between the two components is described as 'on One or more other elements may be interposed between those elements in which 'directly' or 'directly' are not used.

The first, second, etc. may be used to distinguish the components, but the functions or structures of these components are not limited to the ordinal number or component name attached to the front of the component.

The present invention can be applied to various display devices. Although an organic light emitting diode display will be mainly described as an example of a display device in the following embodiments, the present invention is not limited thereto.

The following embodiments can be partially or wholly combined or combined with each other, and technically various interlocking and driving are possible. Each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

In the display device of the present invention, the pixel circuits and the gate driver may include a plurality of transistors. The transistors may include an n-channel MOSFET (NMOS) or a p-channel MOSFET (PMOS), and may be implemented as a thin film transistor (TFT) on a substrate of the display panel. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the TFT. In a transistor, the flow of carriers flows from source to drain. In the case of an n-channel MOSFET (NMOS), the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-channel MOSFET (NMOS), the direction of current flows from drain to source. In the case of a p-channel MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel MOSFET (PMOS), current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain are not fixed. For example, the source and drain may be changed according to an applied voltage. Accordingly, the invention is not limited by the names of the source and the drain. In the following description, the source and the drain will be referred to as first and second electrodes.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1 , the display device of the present invention includes a display panel 100 and a display panel driving circuit.

The display panel 100 includes an active area AA for displaying an input image on the screen. A pixel array is disposed in the active area AA. The pixel array includes a plurality of data lines 102 , a plurality of gate lines 103 intersecting the data lines 102 , and pixels arranged in a matrix form.

Each of the pixels may be divided into a red (Red, R) sub-pixel, a green (G) sub-pixel, and a blue (Blue, B) sub-pixel for color implementation. Each of the pixels may further include a white (W) sub-pixel. Each of the sub-pixels 101 includes a pixel circuit. The pixel circuit may include an internal compensation circuit. As an example, the pixel circuit may be implemented as a circuit as in the example of FIG. 2 , but is not limited thereto.

As shown in FIGS. 4A and 4B in which colors are arranged in a pixel array, three colors or four colors are arranged in various forms. According to the present invention, charge sharing is performed between the 4n+1th and 4n+3th data lines to which the data voltages of the first and second colors are alternated and the data voltages of different colors are applied at the same time.

Touch sensors may be disposed on the display panel 100 . The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors may be implemented as in-cell type touch sensors disposed on the screen of a display panel or embedded in a pixel array as on-cell type or add-on type. can

The display panel driving circuit includes a data driver 110 and a gate driver 120 . The display panel driving circuit may further include a demultiplexer (not shown) disposed between the data driver 110 and the data lines 102 . The demultiplexer is disposed between the data driver 110 and the data lines 102 to time-division a voltage (hereinafter, referred to as a “data voltage”) of a data signal output from the data driver 110 to the data lines 102 . Thus, the number of channels of the data driver 110 can be reduced.

The display panel driving circuit writes input image data into pixels of the display panel 100 under the control of a timing controller (TCON) 130 . The display panel driving circuit may further include a touch sensor driver for driving the touch sensors. The touch sensor driver is omitted from FIG. 1 . In the case of a mobile device, as shown in FIG. 1B , the data driver 110 , the timing controller 130 , and a power circuit (not shown) may be integrated into one drive IC (Drive IC) 200 .

The data driver 110 generates a data voltage using digital data of an input image received from the timing controller 130 using a digital to analog converter (DAC). The DAC converts digital data into a gamma compensation voltage and outputs a data voltage. The data voltage is supplied to data lines through an output buffer in each of the channels of the data driver 110 . In the case of a large screen display device such as a TV or a monitor, the data driver 110 includes a plurality of source drive ICs.

The data driver 110 may include a charge share circuit that performs charge sharing between an Nth (N is a natural number) data voltage and an N+1th data voltage under the control of the timing controller 130 . The charge share circuit of the present invention includes a first data line connected to a first channel of the data driver 110 to which data voltages of first and second colors are alternately output, and a first data line output from the first channel and of the first and second colors. Charge sharing is performed by short-circuiting the second data line to which the data voltages of the first and second colors are alternately output in an order opposite to the order.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit that is directly formed on the substrate of the display panel 100 together with the TFT array of the active area AA. The gate driver 120 outputs a gate signal to the gate lines 103 under the control of the timing controller 130 . The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signal may include, but is not limited to, a scan signal for selecting pixels of a line in which data is to be written, and a light emission signal (hereinafter, referred to as “EM signal”) defining an emission time of pixels charged with data voltage. does not

The gate driver 120 may include a first gate driver 121 and a second gate driver 122 . The first gate driver 121 outputs a scan signal and sequentially shifts the scan signal according to a shift clock. The second gate driver 122 outputs the EM signal and sequentially shifts the EM signal according to the shift clock.

The timing controller 130 receives digital video data DATA of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The host system may be any one of a television (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, and a system of a mobile device.

The timing controller 130 multiplies the input frame frequency by i (i is a positive integer greater than 0) to control the operation timing of the display panel drivers 110, 112, and 120 with a frame frequency of the input frame frequency×i Hz. can The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase-Alternating Line) scheme. The timing controller 130 may lower the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower the refresh rate of pixels in the low-speed driving mode.

The timing controller 130 controls an operation timing of the gate driver 120 and a data timing control signal for controlling the operation timing of the data driver 110 based on the timing signals Vsync, Hsync, DE received from the host system. to generate a gate timing control signal for The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120 . The gate-on voltage is a voltage at which the transistor is turned on, and the gate-off voltage is a voltage at which the transistor is turned off. The level shifter converts a low level voltage of the gate timing control signal into a gate low voltage VGL, and converts a high level voltage of the gate timing control signal into a gate high voltage VGH. . In the case of the n-channel transistor, the gate-on voltage may be the gate high voltage VGH, and the gate-off voltage may be the gate low voltage VGL. In the case of the p-channel transistor, the gate-on voltage may be the gate low voltage VGL, and the gate-off voltage may be the gate high voltage VGH.

The timing controller 130 includes an image analyzer for controlling the charge share. The image analyzer analyzes the input image to detect an image pattern in which power consumption is reduced when activating the charge share, and activates the charge share only in this image pattern. The image analyzer deactivates the charge share in a worst pattern in which power consumption increases when activating the charge share. Accordingly, the charge share circuit is driven in an image other than the worst pattern under the control of the image analysis unit.

The display device of the present invention can maximize the charge share effect without side effects by selectively performing the charge share based on the result of analyzing the image pattern having the charge share effect. According to the experimental results, the effect of reducing power consumption by approximately 30% was confirmed in the red/blue monochromatic pattern or the white pattern.

2 is a circuit diagram illustrating an example of a pixel circuit according to an embodiment of the present invention. 3 is a waveform diagram showing a pixel driving signal.

2 and 3 , the pixel circuit includes a light emitting device OLED, a plurality of transistors T1 to T6 and DT, a capacitor Cst, and the like. The transistors T1 to T6 and DT may be implemented as thin film transistors (TFTs) having an n-channel MOSFET structure or a p-channel MOSFET structure. Hereinafter, the transistor of the pixel circuit will be described as “TFT”.

Power voltages such as a pixel driving voltage VDD, a low potential power voltage VSS, and an initialization voltage Vini are supplied to the pixel circuit. The power supply voltage may be VDD=5V, VSS=-5V, and Vini=1V to -1V, but is not limited thereto. The gate signal swings between the gate high voltage VGH and the gate low voltage VGL. VGH and VGL may be VGH=10V, VGL=-5V, but is not limited thereto. The data voltage Vdata may be a voltage between 5V and 1V, but is not limited thereto. This voltage may vary depending on the driving characteristics of the display panel or the product model.

After the pixel circuit is initialized in the initialization step t01, a data voltage Vdata compensated by the threshold voltage is charged to the capacitor Cst by sampling the threshold voltage of the driving device DT in the sampling step t02. Then, the pixel circuit emits light in the light emission step t04 after the hold step. In the initialization step t01, the fifth switch TFT T5 is turned on in response to the N-1 th scan signal SCAN(N-1). In the sampling step t02 , the first, second, and sixth switch TFTs T1 , T2 , and T6 are turned on in response to the Nth scan signal SCAN(N) synchronized with the data voltage Vdata. do. In the hold step t03, the switch TFTs T1 to T6 maintain an off state, so that the main nodes n1, n3, n4, and n6 of the pixel circuit float to maintain their previous state. In the light emission step t04, the third and fourth switch TFTs T3 and T4 are turned on.

The light emitting device OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the fourth and sixth switch TFTs T4 and T6 through the sixth node n6. The cathode of the OLED is connected to the VSS line to which the low potential power voltage (VSS) is applied. The OLED emits light with a current supplied through the driving TFT (DT). The current path of the OLED is switched by the third and fourth switch TFTs T3 and T4.

The capacitor Cst is connected between the first node n1 and the second node n2. The data voltage Vdata compensated by the threshold voltage Vth of the driving TFT DT is charged in the capacitor Cst. Since the data voltage Vdata in each of the sub-pixels 101 is compensated as much as the threshold voltage Vth of the driving TFT DT, the characteristic deviation of the driving TFT DT in the sub-pixels 101 is compensated for uniformity. It can be driven by driving characteristics.

The first switch TFT T1 is turned on in response to the N-th scan signal SCAN(N) in the sampling step t02. When the first switch TFT T1 is turned on, the first node n1 and the fourth node n4 are connected. The first node n1 is connected to the gate of the driving TFT DT, the first electrode of the capacitor Cst, and the first electrode of the first switch TFT T1. The fourth node n4 is connected to the second electrode of the driving TFT DT, the second electrode of the first switch TFT T1, and the first electrode of the fourth switch TFT T4. The gate of the first switch TFT T1 is supplied with the N-th scan signal SCAN(N). The first electrode of the first switch TFT (T) is connected to the first node (n1), and the second electrode of the first switch TFT (T1) is connected to the fourth node (n4).

The second switch TFT T2 is turned on in response to the N-th scan signal SCAN1 in the sampling step t02. When the second switch TFT T2 is turned on, the data voltage Vdata is supplied to the third node n3. The gate of the second switch TFT T2 receives the N-th scan signal SCAN(N). The first electrode of the second switch TFT T2 is connected to the third node n3. The second electrode of the second switch TFT T2 is supplied with the data voltage Vdata through the data line. The third node n3 is connected to the first electrode of the second switch TFT T20, the second electrode of the third TFT T3, and the second electrode of the driving TFT DT.

The third switch TFT T3 is turned on in response to the EM signal EM(N) in the light emission step t04. When the third switch TFT T3 is turned on, the second node n2 is connected to the third node n3. The gate of the third switch TFT T3 receives the EM signal EM(N). The first electrode of the third switch TFT T3 is connected to the second node n2. The second electrode of the third switch TFT T3 is connected to the third node n3. The second node n2 is connected to the VDD line 104 to which the pixel driving voltage VDD is supplied and the second electrode of the capacitor Cst.

The fourth switch TFT T4 is turned on in response to the EM signal EM(N) in the light emission step t04. When the fourth switch TFT T4 is turned on, the fourth node n4 is connected to the sixth node n6. The fifth node n5 is connected to the second electrode of the fourth switch TFT T4 , the second electrode of the sixth switch TFT T6 , and the anode of the light emitting element EL. The gate of the fourth switch TFT T4 receives the EM signal EM(N). The first electrode of the fourth switch TFT T4 is connected to the fourth node n4 , and the second electrode is connected to the sixth node n6 . The sixth node n6 is connected to the second electrode of the fourth switch TFT T4 , the second electrode of the sixth switch TFT T6 , and the anode of the light emitting element EL.

The fifth switch TFT T5 is turned on in response to the N-1 th scan signal SCAN(N-1) in the initialization step t01. When the fifth switch TFT T5 is turned on, the first node n1 is connected to the fifth node n5. The fifth node n5 is connected to the Vini line to which the initialization voltage Vini is supplied, the second electrode of the fifth switch TFT T5, and the first electrode of the sixth switch TFT T6. The gate of the fifth switch TFT T5 receives the N-1 th scan signal SCAN(N-1). The first electrode of the fifth switch TFT T5 is connected to the first node n1 , and the second electrode is connected to the Vini line 105 through the fifth node n5 .

The sixth switch TFT T6 is turned on in response to the Nth scan signal SCAN(N) in the sampling step t02. When the sixth switch TFT T6 is turned on, the fifth node n5 is connected to the sixth node n6. The gate of the sixth switch TFT T6 receives the N-th scan signal SCAN(N). The first electrode of the sixth switch TFT T6 is connected to the fifth node n5 , and the second electrode is connected to the sixth node n6 .

The driving TFT DT is a driving element that controls the current flowing through the light emitting element EL. The driving TFT DT includes a gate connected to the first node n1 , a first electrode connected to the third node n3 , and a third electrode connected to the second node n2 .

4A and 4B are diagrams illustrating color arrangement of a pixel array. In FIGS. 4A and 4B , “L1 to L4” denote display lines in the horizontal direction (X), and “C1 to C8” denote columns in the vertical direction (Y). When data lines are shorted between columns indicated by arrows in FIGS. 4A and 4B , a charge share effect in which a consumption strategy is reduced may be obtained. FIG. 5A is a waveform diagram illustrating driving signals DATA(S1) to DATA(S4) and SCAN1 to SCAN4 of the pixel array and a control signal CS of the charge share circuit shown in FIG. 4A. FIG. 5B is a waveform diagram illustrating driving signals DATA(S1) to DATA(S4), SCAN1 to SCAN4 and a wah control signal CS of the pixel array shown in FIG. 4b. The control signal CS controls the charge share timing. 5A and 5B, “1H” is one horizontal period. One horizontal period is equal to one period of the horizontal synchronization signal Hsync and the data enable signal DE. The data driver 110 outputs the data voltage to be charged in the pixels of the N-th display line for one horizontal period (1H), and is then charged to the pixels of the N+1-th horizontal line for the next one horizontal period (2H). Output the data voltage.

4A and 5A , the R sub-pixels and the B sub-pixels are alternately arranged along the 4n+1 (n is a positive integer) column C1 and C5 and the 4n+3 column C3, C7. is placed as The colors of the sub-pixels of the 4n+1 and 4n+3 columns C1, C3, C5, and C7 are alternated in the vertical and horizontal directions (X, Y), respectively. The G sub-pixels are arranged along the 4n+2 and 4n+4 columns C2, C4, C6, and C8.

In the 4n+1th column C1 and C5, the R sub-pixels R are disposed at intersections of the 4n+1th column C1 and C5 and the odd-numbered display lines L1 and L3. In the 4n+3 th column C3 and C7, the R sub-pixels R are disposed at intersections of the 4n+3 th column C3 and C7 and the even-th display lines L2 and L4. In the 4n+1th column (C1, C5), the B sub-pixels (B) are disposed at intersections of the 4n+1th columns (C1, C5) and the even-th display lines (L2, L4). In the 4n+3 columns C3 and C7, the B sub-pixels B are disposed at intersections of the 4n+3 columns C3 and C7 and the odd-numbered display lines L1 and L3.

During the first horizontal period, the data driver 110 supplies the red data voltage to the 4n+1-th data line through the 4n+1-th channel output buffer, and at the same time, supplies the 4n+th red data voltage through the 4n+3-th channel output buffer. 3 Apply the blue data voltage to the data line. Subsequently, the data driver 110 performs charge sharing between the 4n+1-th channel and the 4n+3 channel, and then, during the second horizontal period, a 4n+1-th data line through the output buffer of the 4n+1-th channel At the same time as supplying a blue data voltage to the 4n+3 channel, a red data voltage is supplied to the 4n+3th data line through the output buffer of the 4n+3th channel.

In the present invention, charge sharing is performed in the columns C1, C3, C5, and C7 in which sub-pixels of the first and second colors are alternately arranged using a charge share circuit in the pixel array shown in FIG. 4A. The charge share circuit is applied to the sub-pixels of the corresponding columns C1, C3, C5, and C7 within a horizontal blank period HB before the next data voltage is generated from the data driver in response to the control signal CS. The connected data lines S1 and S3 are shorted. The control signal CS may be generated from the timing controller 130 or the image analyzer. On the other hand, when data lines are short-circuited between columns in which sub-pixels of the same color are arranged, since data voltages of the same color are almost the same, the charge share effect is almost nonexistent. In FIG. 4A , the first color is red (R). The second color is blue (B).

4B and 5B , the R sub-pixels R and the W sub-pixels are alternately arranged along the 4n+1 and 4n+4th columns C1, C4, C5, and C8. The G sub-pixels and the B sub-pixels are alternately disposed along the 4n+2 and 4n+3 columns C2, C3, C6, and C7.

In the 4n+1th column C1 and C5, the R sub-pixels R are disposed at intersections of the 4n+1th column C1 and C5 and the odd-numbered display lines L1 and L3. In the 4n+4 columns C4 and C8, the R sub-pixels R are disposed at intersections of the 4n+4 columns C4 and C8 and the even-th display lines L2 and L4. In the 4n+1th column ( C1 , C5 ), the W sub-pixels W are disposed at the intersection of the 4n+1th column ( C1 , C5 ) and the even-th display lines ( L2 , L4 ). In the 4n+4 columns C4 and C8, the W sub-pixels W are disposed at intersections of the 4n+4 columns C4 and C8 and the odd-numbered display lines L1 and L3.

In the 4n+2 column C2 and C6, the G sub-pixels G are disposed at the intersection of the 4n+2 column C2 and C6 and the odd-numbered display lines L1 and L3. In the 4n+3 columns C3 and C7, the G sub-pixels G are disposed at intersections of the 4n+3 columns C3 and C7 and the even-th display lines L2 and L4. In the 4n+2 column C2 and C6, the B sub-pixels B are disposed at the intersection of the 4n+2 column C2 and C6 and the even-th display lines L2 and L4. In the 4n+3 columns C3 and C7, the B sub-pixels B are disposed at intersections of the 4n+3 columns C3 and C7 and the odd-numbered display lines L1 and L3.

In the present invention, charge sharing is performed in the columns C1, C4, C5, and C8 in which sub-pixels of the first and second colors are alternately arranged by using a charge share circuit in the pixel array shown in FIG. 4B. The charge share circuit is a data line connected to the sub-pixels of the columns C1, C4, C5, and C8 in the horizontal blank period HB before the next data voltage is generated from the data driver in response to the control signal CS. The fields S1, S4, S5, and S8 are short-circuited. At the same time, according to the present invention, charge sharing is performed in the columns C2, C3, C6, and C7 in which sub-pixels of the third and fourth colors are alternately arranged using a charge share circuit in the pixel array shown in FIG. 4B. . The charge share circuit includes data lines S2 and S3 connected to sub-pixels of the corresponding columns C2, C3, C6, and C7 within the horizontal blank period HB before the next data voltage is generated from the data driver 110 . , S6, S7) are short-circuited. In FIG. 4B , the first color is red (R). The second color is white (W). The third color is green (G). The fourth color is blue (B).

6A to 6C are circuit diagrams illustrating the charge share circuit 20 according to the first embodiment of the present invention. This charge share circuit 20 can be applied to the pixel array shown in FIG. 4A. The circuits shown in FIGS. 6A to 6C are repeated to fit the repeating structure of the pixel array.

6A to 6C , the data driver 110 supplies a data voltage of a first color to a first data line and a data voltage of a second color to a second data line. Subsequently, the charge share circuit performs charge sharing between the first and second data lines by shorting the first and second data lines, and then the data driver 110 applies the next data voltage of the second color to the first data line. while supplying the data voltage of the first color to the second data line.

The charge share circuit 20 includes a charge share line CSL, and a plurality of charge share (CS) switch elements SB1 and SB2 connecting the charge share line CSL and the data lines S1 and S3. do. The charge share circuit 20 may be embedded in the IC together with the data driver 110 .

The CS switch elements SB1 and SB2 may be individually turned on/off according to the control signal CS. The CS switch elements SB1 and SB2 share charge shares of the 4n+1th and 4n+3th data lines S1 and S3 to which the red and blue (R, B) data voltages are supplied during the horizontal blank period HB. Connect to line (CSL).

The data driver 110 includes output buffers AMP1 to AMP4 that output data voltages, and a plurality of AMP switch elements SA1 to connecting the output buffers AMP1 to AMP4 and the data lines S1 to S4. SA4).

The AMP switch elements SA1 to SA4 and the CS switch elements SB1 and SB2 are alternately turned on/off. When the AMP switch elements SA1 to SA4 are turned on, the CS switch elements SB1 and SB2 are turned off so that the data voltages from the output buffers AMP1 to AMP4 are applied to the data lines S1 to S4. is supplied

When the AMP switch elements SA1 to SA4 are turned off, the CS switch elements SB1 and SB2 are turned on to induce a charge share of the data lines S1 and S3. At this time, since the output buffers APM1 to AMP4 are not driven, power consumption does not occur in the output buffers APM1 to AMP4 .

The AMP switch elements SA1 to SA4 are turned on under the control of the timing controller 130 . The AMP switch elements SA1 to SA4 are turned on according to a control signal from the timing controller 130 as shown in FIG. 6B to transmit the N-th data voltage from the output buffers AMP1 to AMP4 to the data lines. After supplying to (S1 to S4), it is turned off during the horizontal blank period (HB). At this time, the output buffers AMP1 to AMP4 are driven to generate power consumption. Subsequently, as shown in FIG. 6C , the CS switch elements SB1 and SB2 are turned on during the horizontal blank period HB to connect the data lines S1 to S4 to the charge share line CSL. Subsequently, the AMP switch elements SA1 to SA4 are turned on again, and the N+1th data voltage from the output buffers AMP1 to AMP4 is supplied to the data lines S1 to S4 .

During the horizontal blank period HB in which the AMP switch elements SA1 to SA4 are turned off, the output terminals of the output buffers AMP1 to AMP4 are floated to be in a high impedance state. At this time, since no current flows in all channels of the data driver 100 , power consumption is not generated. When the data lines S1 and S3 are connected to the charge share line CSL, the data lines S1 and S3 are short-circuited so that the voltage of the data lines S1 and S3 is charged to the capacitor Cst of the pixel circuit. It changes to the average voltage of the red data voltage and the blue data voltage.

7A to 7D are circuit diagrams illustrating a charge share circuit according to a second embodiment of the present invention. This charge share circuit 20 can be applied to the pixel array shown in FIGS. 4A and 4B . The circuits shown in FIGS. 7A to 7D are repeated in units of 8 channels in the data driver 110 according to the repetition structure of the pixel array.

7A to 7D , the charge share circuit 20 connects the first and second charge share lines CSL1 and CSL2, the first charge share line CSL1 and the data lines S1 to S3. and a plurality of CS switch elements SB11 to SB14, and a plurality of CS switch elements SB21 to SB24 connecting the second charge share line CSL2 and the data lines S1 to S4. The charge share circuit 20 may be embedded in the IC together with the data driver 110 .

The CS switch elements SB11 to SB14 and SB21 to SB24 are individually turned on/off by a control signal. The CS switch elements SB11 to SB14 and SB21 to SB24 may be turned on during the horizontal blank period HB to induce a charge share of the data lines S1 to S4 . The charge share circuit 20 may be applied without limitation to the pixel array shown in FIGS. 4A and 4B as well as the color arrangement of the pixel array.

In the case of the pixel array shown in FIG. 4A , the AMP switch elements AMP1 to AMP4 are turned on according to a control signal from the timing controller 130 as shown in FIG. 7B , and the output buffers AMP1 to AMP4 are turned on. After supplying the N-th data voltage from ? to the data lines S1 to S4 , they are turned off during the horizontal blank period HB. Subsequently, the CS switch elements SB11 and SB13 are turned on during the horizontal blank period HB as shown in FIG. 7C to connect the data lines S1 and S3 to the first charge share line CSL1. A charge share of these data lines S1 and S3 is derived. Subsequently, the AMP switch elements SA1 to SA4 are turned on again, and the N+1th data voltage from the output buffers AMP1 to AMP4 is supplied to the data lines S1 to S4 .

In the case of the pixel array shown in FIG. 4B , the AMP switch elements AMP1 to AMP4 are turned on according to a control signal from the timing controller 130 as shown in FIG. 7B , and the output buffers AMP1 to AMP4 are turned on. After supplying the N-th data voltage from ? to the data lines S1 to S4 , they are turned off during the horizontal blank period HB. Subsequently, as shown in FIG. 7D , the CS switch elements SB11 and SB14 are turned on during the horizontal blank period HB to connect the data lines S1 and S4 to the first charge share line CSL1. A charge share of these data lines S1 and S4 is derived. Simultaneously, the CS switch elements SB22 and SB23 are turned on during the horizontal blank period HB to connect the data lines S2 and S3 to the second charge share line CSL2 so that the data lines S2 , S3) is derived. Subsequently, the AMP switch elements SA1 to SA4 are turned on again, and the N+1th data voltage from the output buffers AMP1 to AMP4 is supplied to the data lines S1 to S4 .

8A and 8B are diagrams illustrating the image analysis unit 30 and the CS control unit 40 . 8A is a diagram illustrating an implementation method of the image analysis unit 30 and the CS control unit 40 in a large screen display device such as a TV model. 8B is a diagram illustrating an implementation method of the image analysis unit 30 and the CS control unit 40 in a display device of a mobile device such as a smart phone or a wearable device.

The image analyzer 30 analyzes INPUT DATA of an input image using a frame memory and an image analysis algorithm. The image analyzer 30 detects image patterns having a charge share effect and an image pattern without a charge share effect based on the input image analysis result. As described above, the difference share effect refers to an effect of improving power consumption when data lines are connected before the next data voltage is supplied to the data lines.

The CS control unit 40 controls the CS switch SB according to a command code input from the image analysis unit 30 . In the horizontal blank section HB, the AMP switch elements SA1 to SA4 are always turned off. When an image pattern having a charge share effect is input to the display device, the CS switch SB is turned on under the control of the CS controller 40 to perform charge sharing. On the other hand, when an image pattern having no charge share effect is input to the display device, the CS switch SB is turned off under the control of the CS controller 40 . Accordingly, the CS control unit 40 activates the charge share only when an image pattern having the charge share effect is input.

Referring to FIG. 8A , the image analyzer 30 may be implemented as a logic circuit in the timing controller 130 . The CS controller 40 may be formed in each of the source drive ICs of the data driver 110 .

The command code generated by the image analyzer 130 is coded into a preset data packet together with control signals such as data of an input image and a source output enable (SOE). The data packet may be coded in an Embedded 　Point-Point Interface (EPI) standard. The timing controller 130 transmits a bit stream of the data packet to the source drive IC of the data driver 110 through the transmission unit TX. The data driver 110 decodes the data packet through the receiver RX connected to the EPI interface and provides the command code generated from the image analyzer 30 to the CS controller 40, and data of the input image is not shown. provided to the DAC. The data voltage output from the DAC in each channel of the data driver 110 is output to the data lines S1 to S4 through the output buffer AMP.

Referring to FIG. 8B , the image analyzer 30 and the CS controller 40 may be integrated in the drive IC 200 together with the timing controller 130 and the data driver 110 .

9A and 9B are waveform diagrams illustrating a control signal CS for controlling a charge share. 9A shows a control signal CS generated by a display device of a TV model. 9B shows a control signal CS generated from a display device of a mobile device.

Referring to FIG. 9A , the timing controller 130 may generate the source output enable signal SOE in synchronization with the horizontal synchronization signal Hsync. The data driver 110 outputs the data voltage to the data lines S1 to S4 through the output buffer in the low logic section of the source output enable signal SOE. The CS controller 40 controls the CS switch SB by outputting a control signal CS(SOE) having the same phase as the source output enable signal SOE in the image pattern having the charge share effect.

Referring to FIG. 9B , the CS controller 40 outputs a control signal CS of an image pattern. The charge share timing and the driving timing of the output buffer may be adjusted with register setting values SOUT_S and SOUT_E of the drive IC 200 .

10A and 10B are diagrams illustrating a charge share effect in a white pattern.

Referring to FIG. 10A , as shown in FIG. 10A , in the white pattern, the highest grayscale data voltage is applied to the R subpixel, the G subpixel, and the B subpixel. The highest gray level is 255 in 8-bit data, and the data voltage of the highest gray level varies depending on the luminous efficiency of the R sub-pixel, the G sub-pixel, and the B sub-pixel. The highest grayscale has the same meaning as the white grayscale. For example, as shown in FIG. 10A , the red data voltage Red data may be lower than the blue data voltage Blue in the highest grayscale. In the case of the pixel circuit shown in FIG. 2 , since the voltage sampled to the capacitor Cst is VDD-Vdata-Vth, as the data voltage Vdata applied to the pixel circuit decreases, the light emitting device OLED emits light with higher luminance. . Vth is the threshold voltage of the driving TFT DT.

In FIG. 10A , the red data voltage is charged in the capacitor Cst of the R sub-pixels disposed in the 4n+1th columns C1 and C5 in the Nth display line L(N), and the 4n+3th column ( The blue data voltage is charged in the capacitor Cst of the B sub-pixels disposed at C3 and C7. After the charge sharing of the data lines, the next data voltage is supplied to the sub-pixels of the N+1-th display line L(N+1) through the data lines.

The data driver 110 transfers the data lines from the N+1-th display line L(N+1) to the 4n+1-th columns C1 and C5 through output buffers for driving the N+1-th channels after the charge sharing of the data lines. A blue data voltage to be supplied to the arranged B sub-pixels is output to the 4n+1th data lines. At the same time, the data driver 110 uses the output buffers for driving the N+3 channels through the R arranged in the 4n+3th columns C3 and C7 in the N+1th display line L(N+1). A red data voltage to be supplied to the sub-pixels is output to the 4n+3th data lines.

A blue data voltage equal to or similar to the blue data voltage to be charged in the B sub-pixels disposed in the 4n+1th columns C1 and C5 of the N+1th display line L(N+1) is applied to the B subpixels. Previously, the B sub-pixels disposed in the 4n+3th columns C3 and C7 of the N-th display line L(N+1) are filled. Accordingly, the charge is connected to the data line S1 connected to the sub-pixels of the 4n+1th columns C1 and C5 and the data line S3 connected to the sub-pixels of the 4n+3th columns C3 and C7 are connected. When sharing is performed, power consumption can be reduced as shown in FIG. 10B . In FIG. 10B , the dotted line indicates that the data lines S1 and S3 are short-circuited through the charge share circuit 20 so that the voltage of the data lines S1 and S3 is close to the next data voltage without driving the output buffer of the data driver 110 . Indicates a changing charge share section. During the charge share period, the voltages of the data lines S1 and S3 change without driving the output buffer of the data driver 110 . The voltages of the data lines S1 and S3 are averaged by the charge share and pre-charged to an average voltage close to the next data voltage before the next data voltage to be supplied to the data lines is supplied. As a result, when the next data voltage is supplied to the data lines S1 and S3 during a driving period in which the output buffers are driven after the charge share, the voltage swing width of the data lines S1 and S3 is decreased. reduced by 1/2. A solid line in FIG. 10B is a driving section of the output buffer. Accordingly, current consumption required for driving in the output buffers is reduced, thereby reducing power consumption.

Meanwhile, in the case of charge-sharing data lines supplied with data voltages of the same color, since the voltages of the data lines are the same or have a small difference, the average voltage due to charge-sharing is not significantly different from the data voltages of the same color. In this case, since there is no charge-sharing effect, it is not necessary to perform the charge-sharing. For example, in the example of FIG. 4A , a charge share between the data lines S2 and S4 is not required.

In the example of FIG. 4A , if charge sharing is performed between the data line S1 connected to the subpixels of the 4n+1th column and the data line S2 connected to the subpixels of the 4n+2th column, consumption is rather consumed as shown in FIG. 11B . The power may be further increased.

11A and 11B are diagrams illustrating an example of a charge sharing method in which power consumption is not reduced. These figures show data voltages supplied to the data lines S1 and S2 of the 4n+1th and 4n+2th columns C1 and C2 in the pixel array of FIG. 4A . 11A is a data voltage in a state in which charge sharing is not performed, and FIG. 11B is a data line voltage in a state in which charge sharing is performed between the data lines S1 and S2.

11A , in the white pattern, the data driver 110 converts the red data voltage and the blue data voltage alternating in units of one horizontal period (1H) to the first data line S1 through the 4n+1 channel. print out The data driver 110 outputs the green data voltage to the second data line S2 through the 4n+2 channel without color alternating. As described above, the data voltage level of the highest grayscale may be different for each color due to the difference in luminous efficiency between the sub-pixels. In FIG. 11A , the data voltage level is different from green data voltage > red data voltage > blue data voltage.

When the data driver 110 short-circuits the data lines S1 and S2 by performing charge sharing between the 4n+1th and 4n+2th channels, the voltages of the data lines S1 and S2 increase with the 4n+1th channel. It converges to an average voltage of the data voltage output through the output buffer AMP1 of the channel and the data voltage output through the output buffer AMP2 of the 4n+2th channel. At this time, as shown in FIG. 11B , when the red data voltage is changed from the red data voltage to the blue data voltage (Red -> Blue), the voltages of the data lines S1 and S2 are adjusted to the target level of the blue data voltage (target level) due to the charge share. level) and the output buffers AMP1 and AMP2 are additionally driven compared to when charge sharing is not performed, so power consumption increases.

12A to 18B are diagrams illustrating examples of applying a charge share in various image patterns displayed on the pixel array shown in FIG. 4A . In this example, the charge share circuit 20 operates through the 4n+1 and 4n+3 channels ( (4n+1)th ch. and (4n+3)th ch.) are connected to each other by performing charge sharing to connect the 4n+1th and 4n+3th data lines S1 and S3. In FIGS. 12A to 18B , the data voltage of the white gray is supplied to the sub-pixels emitting light in the white gradation, and the data voltage of the black gradation is supplied to the non-light-emitting sub-pixels expressed in the black gradation. The white gradation is the highest gradation representing the maximum luminance. The black gradation is the lowest gradation in which the sub-pixel is not lit and appears black.

In FIGS. 12A to 12B , red is a charge share section.

12A and 12B , in a red pattern, the R sub-pixel emits light with a luminance of this white gray scale, and the B and G sub-pixels do not emit light. In the red pattern, the data voltage of the white gray scale is supplied to the R sub-pixels. A data voltage of a black gray scale is supplied to the blue and green sub-pixels in the red pattern. The white gradation is the highest gradation representing the maximum luminance.

As shown in FIG. 12B , the driving current of the output buffer is lowered due to the charge share in the red pattern, thereby reducing power consumption.

In this red pattern, the drive current of the output buffer is lowered due to the charge share, thereby reducing power consumption.

13A and 13B , the driving current of the output buffer is lowered due to the charge share in the red pattern, so that power consumption is reduced.

14A and 14B , sub-pixels arranged in the 4n+1 and 4n+2 columns C1, C2, C5, and C6 in a V-line pattern emit light with a white grayscale and The sub-pixels arranged in the 4n+3 and 4n+4 columns C3, C4, C7, and C8 do not emit light. In the vertical line pattern, a white gradation voltage is supplied to the sub-pixels arranged in the 4n+1 and 4n+2 columns C1, C2, C5, and C6, and the 4n+3 and 4n+4 columns C3 , C4, C7, and C8) are supplied with a data voltage of a black grayscale.

In the case of this vertical line pattern, as shown in FIG. 14B , the output buffer driving current of the data driver rather increases due to the charge share, thereby increasing power consumption. The charge share circuit 20 does not perform charge share in the vertical line pattern under the control of the CS controller 40 .

15A and 15B , sub-pixels disposed in the 4n+1 and 4n+3 columns C1, C3, C5, and C7 in the vertical sub pattern (V-Sub pattern) emit light with a white grayscale and The sub-pixels disposed in the 4n+2 and 4n+4 columns C2, C4, C6, and C8 do not emit light. In the vertical sub-pattern, a white gray voltage is supplied to the sub-pixels disposed in the 4n+1 and 4n+3 columns C1, C3, C5, and C7, and the 4n+2 and 4n+4 columns C2 , C4, C6, and C8) are supplied with a data voltage of a black grayscale.

Due to the charge share in the vertical sub-pattern, the driving current of the output buffer is lowered, thereby reducing power consumption.

16A and 16B , in a dot pattern, 4n+1 and 4n+2 display lines L1 and L2 and 4n+1 and 4n+2 columns C1, C2, C5, The sub-pixels in the portion where C6 intersects emit white gradation, and the 4n+3 and 4n+4 display lines L3 and L4 and the 4n+3 and 4n+4 columns C3, C4, C7, The sub-pixels in the portion where C8) intersect emit light with a white gradation. In the dot pattern, the sub-pixels at the intersection of the 4n+1 and 4n+2 display lines L1 and L2 and the 4n+3 and 4n+4 columns C3, C4, C7, and C8 do not emit light. , sub-pixels in a portion where the 4n+3 and 4n+4 display lines L3 and L4 and the 4n+1 and 4n+2 columns C1, C2, C5, and C6 intersect do not emit light.

When charge-sharing is performed in the dot pattern, power consumption is equivalent to that of the driving method without charge-sharing. Accordingly, the charge share may be deactivated in the dot pattern.

17A and 17B , in a sub dot pattern, 4n+1 and 4n+3 display lines L1 and L3 and 4n+1 and 4n+3 columns C1, C3, The sub-pixels in the portion where C5 and C7 intersect emit white gradation, and the 4n+2 and 4n+4 display lines L2 and L4 and the 4n+2 and 4n+4 columns C2, C4, The sub-pixels in the portion where C6 and C8 intersect each other emit light with a white gradation. In the sub dot pattern, the sub-pixels at the intersection of the 4n+1 and 4n+3 display lines L1 and L3 and the 4n+2 and 4n+4 columns C2, C4, C6, and C8 do not emit light. Otherwise, the sub-pixels at the intersection of the 4n+2 and 4n+4 display lines L2 and L4 and the 4n+1 and 4n+3 columns C1, C3, C5, and C7 do not emit light.

When charge-sharing is performed on the sub-dot pattern, power consumption is equivalent to that of the driving method without charge-sharing. Accordingly, the charge share may be deactivated in the vertical dot pattern.

18A and 18B , in the H-line pattern, sub-pixels disposed on the 4n+1 and 4n+3 lines L1 and L3 emit white light, and the 4n+2 and The sub-pixels disposed on the 4n+4th lines L2 and L4 do not emit light.

When charge-sharing is performed in a horizontal pattern, power consumption is equivalent to the driving method without charge-sharing. Accordingly, the charge share may be deactivated in the horizontal pattern.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

20: charge share circuit 30: image analysis unit
40: CS control unit 100: display panel
101: sub-pixel 102: data line
103: gate line 110: data driver
120: gate driver 130: timing controller
AMP1~AMP4 : Output buffer SA of the data driver, SA1~SA4 : AMP switch
SB, SB1, SB2, SB11 to SB14, SB21 to SB24: CS switch

Claims (11)

a display panel in which a plurality of data lines and a plurality of gate lines intersect and sub-pixels are arranged in a matrix form;
a data driver supplying a data voltage to the data lines; and
and a charge share circuit that short-circuits the data lines before the next data voltage is generated from the data driver;
the charge share circuit short-circuits first and second data lines to which data voltages of first and second colors are supplied;
The data driver,
alternately outputting the data voltages of the first and second colors to the first data line through a first channel;
alternately outputting the data voltages of the first and second colors to the second data line through a second channel in an order opposite to the order of the first and second colors output from the first channel;
The charge share circuit may include a charge share line; and a plurality of first switch elements connecting the charge share line and preset data lines, wherein the data driver includes a plurality of output buffers for outputting data voltages to the data lines through a plurality of channels; A plurality of second switch elements are turned on when one switch element is in an off state to connect the output buffers and the data lines, and when the second switch elements are in an off state, the first switch elements are turned on - turned on, or
The charge share circuit includes first and second charge share lines, a plurality of first switch elements connecting the first charge share line and the data lines, and a plurality of second charge share lines connecting the data lines. a plurality of output buffers for outputting a data voltage to the data lines through the channels, and a plurality of third switches connecting the output buffers and the data lines through the channels. elements, wherein the first and second switch elements are turned on when the third switch elements are in an off state;
display device. The method of claim 1,
The pixel array of the display panel is
The sub-pixels of the first and second color are arranged along a 4n+1 (n is a positive integer) column and a 4n+3 column, and the third color is arranged along a 4n+2 and 4n+4 column. sub-pixels are placed,
A display device in which first and second colors are alternated in vertical and horizontal directions in the 4n+1th column and the 4n+3th column. The method of claim 1,
the charge share circuit short-circuits third and fourth data lines to which data voltages of third and fourth colors are supplied;
The data driver,
alternately outputting the data voltages of the third and fourth colors to the third data line through a third channel;
A display device configured to alternately output the data voltages of the third and fourth colors to the fourth data line through a fourth channel in an order opposite to that of the third and fourth colors output from the third channel. 4. The method of claim 3,
The pixel array of the display panel is
The first and second color sub-pixels are arranged along a 4n+1 (n is a positive integer) column and a 4n+4 column, and the third and third colors are arranged along the 4n+2 and 4n+3 columns. 4 color sub-pixels are arranged,
The first and second colors are alternated in vertical and horizontal directions in the 4n+1 column and the 4n+4 column,
The third and fourth colors alternate in the vertical and horizontal directions in the 4n+2 column and the 4n+3 column. delete delete The method of claim 1,
an image analysis unit that analyzes the input image; and
A display device configured to deactivate the charge share circuit in a preset image pattern in response to a command from the image analyzer. delete delete delete 8. The method of claim 7,
The preset image pattern includes at least one of a red pattern, a white pattern, and a vertical sub-pattern.

Images