KR102618390B1 - Display device and driving method thereof - Google Patents

Abstract

A display device and a method of driving the same are disclosed. This display device sequentially generates pulses of the first scan signal, pulses of the second scan signal, and pulses of the third scan signal within the pulse duration of the shared EM signal, and determines the pulse timing of any one of the scan signals. pixels of at least two pixel lines sharing the shared EM signal are initialized simultaneously.

Description

Display device and its driving method {DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to a display device that changes the initialization voltage of pixels in real time and a method of driving the same.

Electroluminescent displays are roughly divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness, and viewing angle. There is an advantage. Organic light emitting display devices have a light emitting diode (called "Organic Light Emitting Diode, OLED") formed in each pixel. Organic light emitting display devices not only have a fast response speed and excellent luminous efficiency, brightness, and viewing angle, but also have a black color. Because gradations can be expressed in complete black, the contrast ratio and color reproduction rate are excellent.

Organic light emitting display devices do not require a backlight unit and can be implemented on flexible materials such as plastic substrates, thin glass substrates, and metal substrates. Therefore, the flexible display can be implemented as an organic light emitting display device.

The pixels of an organic light emitting display device include an OLED, a driving element that drives the OLED by controlling the current flowing through the OLED according to the gate-source voltage (Vgs), and a storage capacitor that maintains the gate voltage of the driving element.

The driving element may be implemented as a transistor. In order to maintain uniform image quality across the screen of an organic light emitting display device, the driving element must have uniform electrical characteristics among all pixels. However, due to process deviations and device characteristic deviations resulting from the display panel manufacturing process, there may be differences in the electrical characteristics of the driving elements between pixels, and these differences may become larger as the driving time of the pixels elapses. To compensate for differences in electrical characteristics of driving elements between pixels, internal compensation technology and/or external compensation technology may be applied to the organic light emitting display device.

Internal compensation technology uses an internal compensation circuit built into each pixel to sense the threshold voltage of the driving element for each sub-pixel and compensates the data voltage by the threshold voltage. External compensation technology uses an external compensation circuit to sense the current or voltage of driving elements that change according to the electrical characteristics of the driving elements in real time. External compensation technology compensates in real time for the deviation (or change) in the electrical characteristics of the driving element in each pixel by modulating the pixel data (digital data) of the input image by the deviation (or change) in the electrical characteristics of the driving element sensed for each pixel.

In an organic light emitting display device, luminance differences may occur between pixels depending on the structure or driving method of the display panel. For example, luminance deviation may occur between pixel lines.

The present invention aims to solve the above-described needs and/or problems.

The present invention provides a display device and a method of driving the same that can reduce luminance deviation between pixels.

The object of the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

The display device of the present invention includes a data line to which a data voltage is applied; A shared EM line to which a shared EM signal is applied; a first scan line to which a first scan signal is applied; a second scan line to which a second scan signal generated following the first scan signal is applied; a third scan line to which a third scan signal generated following the second scan signal is applied; a first pixel circuit connected to the data line, the shared EM line, the first scan line, and the second scan line; and a second pixel circuit connected to the data line, the shared EM line, the second scan line, and the third scan line.

Each of the first and second pixel circuits includes a driving element including a gate connected to a capacitor; a light emitting element that emits light by a current flowing through the driving element; and an initialization switch that applies a predetermined initialization voltage to the anode of the light emitting device in response to one of the scan signals.

Pulses of the first scan signal, pulses of the second scan signal, and pulses of the third scan signal are generated within the pulse duration of the shared EM signal.

The same scan signal is applied to the gates of the initialization switches of the first and second pixel circuits, so that the initialization voltage is simultaneously applied to the light emitting devices of the first and second pixel circuits.

The method of driving the display device includes generating a shared EM signal; sequentially generating pulses of a first scan signal, pulses of a second scan signal, and pulses of a third scan signal within the pulse duration of the shared EM signal; and simultaneously initializing pixels of at least two pixel lines sharing the shared EM signal at any one pulse timing of the pulse of the first scan signal, the pulse of the second scan signal, and the pulse of the third scan signal. Includes.

The present invention can reduce the number of output channels of the gate driver by connecting the gate signal lines to neighboring pixel lines so that the gate signal lines to which the gate signal is applied are shared with the neighboring pixel lines.

The present invention minimizes the luminance difference between pixels due to differences in initialization timing between neighboring pixel lines by connecting the gate of the switch element for initializing the node connected to the anode of the light emitting element in neighboring pixel lines to the same scan line. It is possible to improve luminance uniformity in low gray levels.

In the present invention, the luminance of the light emitting device is reduced in the initialization step, thereby lowering the luminance of the black grayscale.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram showing a display device according to an embodiment of the present invention.
Figure 2 is a diagram showing an example of pentile pixel arrangement.
Figure 3 is a diagram showing an example of real pixel arrangement.
FIG. 4 is a block diagram showing the drive IC configuration shown in FIG. 1.
Figure 5 is a diagram schematically showing the pixel circuit of the present invention.
Figure 6 is a circuit diagram showing a pixel circuit including an internal compensation circuit.
FIGS. 7A to 9B are diagrams showing step-by-step the operation of the pixel circuit shown in FIG. 6.
FIG. 10 is a diagram showing an example in which gate signal wires are shared between neighboring pixel lines.
FIGS. 11A and 12B are diagrams showing an initialization step of neighboring pixels in a display device in which gate signal wires are shared between neighboring pixel lines.
FIGS. 13A and 13B are diagrams showing parasitic capacitance between a third gate line and a fourth node in pixel circuits of neighboring pixel lines where gate signal wires are shared.
FIGS. 14A and 14B are diagrams showing gate signals and fourth node voltages in pixel circuits of neighboring pixel lines where gate signal wires are shared.
FIGS. 15A and 15B are diagrams showing current flowing in light emitting devices in pixel circuits of neighboring pixel lines sharing gate signal wires.
16A to 20B are diagrams showing pixel circuits of a display device and a driving method thereof according to the first embodiment of the present invention.
Figures 21A and 21B are flowcharts showing a method of initializing pixel circuits of neighboring pixel lines with shared gate signal wires in the display device according to the first embodiment of the present invention.
Figures 22a and 22b are simulation result diagrams showing the effect of the display device according to the first embodiment of the present invention.
FIG. 23 is a diagram showing an example in which gate signal wires are shared between neighboring pixel lines in a display device according to a second embodiment of the present invention.
FIGS. 24A to 25C are diagrams showing pixel circuits of a display device and a driving method thereof according to a second embodiment of the present invention.
FIG. 26 is a diagram showing an example in which gate signal wires are shared between neighboring pixel lines in a display device according to a third embodiment of the present invention.
27A to 27D are diagrams showing pixel circuits of a display device and a driving method thereof according to a third embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the description of the embodiment, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

Features of various embodiments may be partially or entirely combined or combined with each other, and various technological interconnections and operations are possible, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the display device of the present invention, the pixel circuit and the gate driver may include multiple transistors. Transistors can be implemented as Oxide TFT (Thin Film Transistor) containing an oxide semiconductor, LTPS TFT containing Low Temperature Poly Silicon (LTPS), etc. Each of the transistors may be implemented as a transistor with a p-channel MOSFET (metal-oxide-semiconductor field effect transistor) or n-channel MOSFET structure. In the embodiment, the description is centered on an example in which the transistors of the pixel circuit are implemented as p-channel transistors, but the present invention is not limited thereto.

A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal swings between Gate On Voltage and Gate Off Voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate on voltage, while the transistor is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage (Gate High Voltage, VGH), and the gate-off voltage may be the gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be the gate low voltage (VGL) and the gate-off voltage may be the gate high voltage (VGH).

In the following embodiments, the pixel circuit will be described focusing on an example implemented with p-channel transistors, but the present invention is not limited thereto. In an embodiment, “VGL” is the gate-on voltage of the scan signal, “VGH” is the gate-off voltage of the scan signal, “VEL” is the luminescence control signal (hereinafter referred to as “EM signal”), and “VEH” is the EM signal. represents the gate-off voltage of respectively.

Each of the pixels of the present invention includes a light emitting element, a driving element that adjusts the current flowing through the light emitting element according to the gate-source voltage, and a threshold voltage of the driving element in a sensing step defined by a pulse of the scan signal. It includes an internal compensation circuit that supplies the capacitor. The internal compensation circuit includes a capacitor connected to the gate of the driving element, and one or more switch elements connecting the capacitor to the driving element and the light-emitting element. The internal compensation circuit may include the capacitor shown in FIG. 6 and multiple switch elements.

The display device of the present invention includes a driving device for driving pixels. The driving device may receive a brightness value (DBV) input from the outside and change the data voltage and low potential power supply voltage (ELVSS) according to this brightness value to limit the maximum brightness of the pixel data. The driving device can vary the initialization voltage (Vini) in real time based on one or more of the gray level of the pixel data, the low potential power supply voltage (ELVSS) that varies depending on the brightness value, and the threshold value of the driving element of the pixels. The driving device is described as drive IC 300 in the following embodiments.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

1 to 4, the display device of the present invention includes a display panel 100 and display panel drivers 120 and 300.

The display panel drivers 120 and 300 write pixel data of the input image to pixels on the screen and display the image on the screen. The display panel drivers 120 and 300 supply gate signals to the gate lines GL1 to GL2 of the display panel 100 and convert pixel data to the voltage of the data signal (hereinafter referred to as “data voltage”). It includes a data driver 306 that converts data into data and supplies it to data lines through data output channels, and a timing controller 303 that controls the operation timing of the data driver 306 and the gate driver 120. The data driver 306 and timing controller 303 may be integrated into a drive IC (Integrated Circuit, 300).

The screen of the display panel 100 consists of data lines DL1 to DL6, gate lines GL1 and GL2 that intersect the data lines DL1 to DL6, and pixels P arranged in a matrix form. Contains array (AA). Pixels P are arranged in the pixel array AA in a matrix form defined by data lines DL1 to DL6 and gate lines GL1 and GL2. Pixels P display an image by applying a pixel data voltage.

Each of the pixels P includes subpixels of different colors for color implementation. Subpixels include red (hereinafter referred to as “R subpixel”), green (hereinafter referred to as “G subpixel”), and blue (hereinafter referred to as “B subpixel”). Although not shown, additional white subpixels may be included. Hereinafter, a pixel may be interpreted as a subpixel.

Each subpixel may include an internal compensation circuit that compensates for the gate voltage of the driving device by sensing the electrical characteristics of the driving device, for example, a threshold voltage.

Pixels P may be arranged as real color pixels and pentile pixels. Pentile pixels use a preset Pentile pixel rendering algorithm to drive two sub-pixels of different colors as one pixel (P) as shown in Figure 2, achieving higher resolution than real color pixels. It can be implemented. The Pentile pixel rendering algorithm compensates for insufficient color expression in each pixel (P) with the color of light emitted from adjacent pixels.

In the case of real color pixels, one pixel (P) is composed of R, G, and B subpixels as shown in FIG. 3.

When the resolution of the pixel array AA is n*m, the pixel array AA includes n pixel columns and m pixel lines that intersect the pixel columns. In Figures 2 and 3, #1 and #2 indicate pixel line numbers. A pixel column contains pixels arranged along the Y-axis direction. A pixel line includes pixels arranged along the X-axis direction. 1 horizontal period (1H) is the time divided by 1 frame period by the number of m pixel lines. The gate driver 120 may sequentially output a gate signal from the first pixel line to the mth pixel line to progressively scan the pixels line by line. The pixels of 1 pixel line can operate with initialization, sensing, and data writing within 1 horizontal period (1H).

The pixel array AA of the display panel 100 may be formed on a glass substrate, a metal substrate, or a plastic substrate. In the case of a plastic OLED panel, a pixel array (AA) is formed on a plastic substrate and can be implemented as a flexible panel. A plastic OLED panel includes a pixel array (AA) on an organic thin film glued on a back plate. A touch sensor array may be formed on the pixel array (AA).

The back plate may be a PET (Polyethylene terephthalate) substrate. An organic thin film is formed on the back plate. A pixel array (AA) and a touch sensor array may be formed on the organic thin film. The back plate blocks moisture permeation toward the organic thin film to prevent the pixel array (AA) from being exposed to humidity. The organic thin film may be a thin polyimide (PI) film substrate. A multi-layer buffer film may be formed on the organic thin film using an insulating material not shown. Wires for supplying power or signals applied to the pixel array (AA) and the touch sensor array may be formed on the organic thin film.

The gate driver 120 may be mounted on the substrate of the display panel 100 along with the pixel array AA. The gate driver 120 formed directly on the substrate of the display panel 100 is known as a gate in panel (GIP) circuit.

The gate driver 120 is disposed on one of the left and right bezels of the display panel 100 and can supply a gate signal to the gate lines GL1 and GL2 using a single feeding method. In the case of the single feeding method, one of the two gate drivers 120 in FIG. 1 is not needed.

The gate driver 120 is disposed on each of the left and right bezels of the display panel 100 and can supply a gate signal to the gate lines GL1 and GL2 using a double feeding method. In the case of the double feeding method, gate signals can be applied simultaneously from both ends of one gate line.

The gate driver 120 is driven according to the gate timing signal supplied from the drive IC 300 using a shift register to supply gate signals GATE1 and GATE2 to the gate lines GL1 and GL2. The shift register can sequentially supply the gate signals (GATE1, GATE2) to the gate lines (GL1, GL2) by shifting the gate signals (GATE1, GATE2). The gate signals (GATE1, GATE2) may include scan signals [SCAN(N-1), SCAN(N)], EM signals [EM(N)], etc. shown in FIGS. 6 and 7.

The drive IC 300 may output a gate timing signal for controlling the gate driver 120 through gate timing signal output channels. The gate timing signal may include a start signal and a shift clock input to the shift register. The drive IC 300 is connected to the data lines DL1 to DL6 through data output channels and supplies a data voltage Vdata to the data lines DL1 to DL6.

The drive IC 300 may be connected to the host system 200, the first memory 301, and the display panel 100 as shown in FIG. 4. The drive IC 300 may include a data operation unit 308, a timing controller 303, and a data driver 306. The drive IC 300 may further include a second memory 302, a gamma compensation voltage generator 305, a power supply unit 304, and a level shifter 307.

The timing controller 303 provides pixel data (PDATA) of the input image received from the host system 200 to the data driver 306. The timing controller 303 generates a gate timing signal for controlling the gate driver 120 and a source timing signal for controlling the data driver 306 to control the operation timing of the gate driver 120 and the data driver 306. You can control it.

The drive IC 300 may generate gate timing signals for driving the gate driver 120 through the timing controller 303 and the level shifter 307. The gate timing signal includes gate timing signals such as a start pulse (VST) and a shift clock (GCLK), and gate voltages such as a gate on voltage (VGL) and a gate off voltage (VGH). The start pulse (VST) and shift clock (GCLK) swing between the gate-on voltage (VGL) and gate-off voltage (VGH).

The data calculation unit 308 includes a receiver that receives pixel data input as a digital signal from the host system 200, and a data calculation unit that improves image quality by modulating the pixel data input through the receiver with a preset image quality algorithm. The data operation unit 308 includes a data restoration unit that decodes and restores compressed pixel data, an optical compensation unit that adds a preset optical compensation value to the pixel data, and a luminance level by calculating the average picture level (APL) of the input image. and a brightness adjustment unit that controls power consumption. The optical compensation value may be set as a value for correcting the luminance of each pixel data based on the luminance of the screen measured based on camera images captured during the manufacturing process.

The data driver 306 converts the pixel data (digital signal) received from the timing controller 303 into a gamma compensation voltage using a digital to analog converter (hereinafter referred to as “DAC”) to produce a data voltage ( Vdata) is output. The data voltage Vdata output from the data driver 306 is supplied to the data lines DL1 to DL6 of the pixel array AA through an output buffer connected to the data channel of the drive IC 300.

The gamma compensation voltage generator 305 divides the gamma reference voltage from the power supply unit 304 through a voltage divider circuit to generate a gamma compensation voltage for each gray level. The gamma compensation voltage is an analog voltage whose voltage is set for each gray level of pixel data. The gamma compensation voltage output from the gamma compensation voltage generator 305 is provided to the data driver 306.

The level shifter 307 converts the low level voltage of the gate timing signal received from the timing controller 303 into the gate on voltage (VGL) and the high level voltage of the gate timing signal. Convert to gate-off voltage (VGH). The level shifter 307 outputs a gate timing signal and gate voltages (VGH, VGL) through gate timing signal output channels and supplies them to the gate driver 120.

The power supply unit 304 uses a DC-DC converter to generate power required to drive the pixel array (AA), gate driver 120, and drive IC 300 of the display panel 100. . The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. The power unit 304 adjusts the direct current input voltage from the host system 200 to a gamma reference voltage and a gate-on voltage (VGL). Direct current power such as gate-off voltage (VGH), pixel driving voltage (ELVDD), low-potential power supply voltage (ELVSS), and initialization voltage (Vini) can be generated.

The gamma reference voltage is supplied to the gamma compensation voltage generator 305. The gate-on voltage (VGL) and gate-off voltage (VGH) are supplied to the level shifter 307 and the gate driver 120. Pixel power, such as the pixel driving voltage (ELVDD), low-potential power supply voltage (ELVSS), and initialization voltage (Vini), is commonly supplied to the pixels (P).

The gate voltage can be set to VGH = 15V, VEH = 13V, VGL = -6V, VEL = -6V, but is not limited to this. The pixel power can be set to ELVDD = 13V, ELVSS = 0V, but is not limited to this. The voltage range of the data voltage (Vdata) determined by the gamma reference voltage may be Vdata = 0 to 5V, but is not limited thereto. The initialization voltage Vini is set to a direct current voltage lower than the data voltage Vdata and lower than the threshold voltage of the light emitting device EL to suppress light emission of the light emitting device EL and initialize main nodes of the pixels.

The second memory 302 stores compensation values, register setting data, etc. received from the first memory 301 when power is input to the drive IC 300. Compensation values can be applied to various algorithms that improve image quality. The compensation value may include an optical compensation value.

The register setting data defines the operation of the data driver 306, timing controller 303, gamma compensation voltage generator 305, and power supply unit 34, the timing of the waveform, and the output voltage level of the power supply unit 34. The first memory 301 may include flash memory. The second memory 302 may include static RAM (SRAM).

The host system 200 may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile system, and a wearable system.

In a mobile system, the host system 200 may be implemented as an Application Processor (AP). In a mobile system, the host system 200 may transmit pixel data of an input image to the drive IC 300 through MIPI (Mobile Industry Processor Interface). The host system 200 may be connected to the drive IC 300 through a flexible printed circuit (FPC) 310, for example.

Figure 5 is a diagram schematically showing the pixel circuit of the present invention.

Referring to FIG. 5 , the pixel circuit may include first to third circuit units 10, 20, and 30 and first to third connection units 12, 23, and 13. One or more components may be omitted or added to this pixel circuit.

The first circuit unit 10 supplies the pixel driving voltage ELVDD to the driving element DT. The driving element DT may be implemented as a transistor including a gate (DRG), a source (DRS), and a drain (DRD). The second circuit unit 20 charges the capacitor Cst connected to the gate DRG of the driving element DT and maintains the voltage of the capacitor Cst for one frame period. The third circuit unit 30 converts the current into light by providing the current supplied from the pixel driving voltage ELVDD to the light emitting element EL through the driving element DT.

The third circuit unit 30 may be connected to a sensing unit that senses changes in the threshold voltage or electrical characteristics of the driving element DT in real time.

The first connection part 12 connects the first circuit part 10 and the second circuit part 20. The second connection portion 23 connects the second circuit portion 20 and the third circuit portion 30. The third connection part 13 connects the third circuit part 30 and the first circuit part 10. Each of the first connection part 12, the second connection part 23, and the third connection part 13 may include one or more transistors and wiring.

The internal compensation circuit may be connected to the circuit parts 10, 20, 30 and the connections 12, 23, 13.

The pixel circuit may be implemented as a pixel circuit including an internal compensation circuit as shown in FIG. 6. The internal compensation circuit shown in FIG. 6 may be divided into an initialization stage (Ti), a sensing stage (Ts), and a light emission stage (Tem).

The pixel circuit shown in FIG. 6 illustrates an arbitrary sub-pixel circuit belonging to the Nth (N is a natural number) pixel line. The pixel circuit includes an internal compensation circuit that senses the threshold voltage (Vth) of the driving element (DT) and compensates the gate voltage of the driving element (DT) by the threshold voltage (Vth).

As shown in FIG. 6, the display panel 100 has a first power line (VDDL) for supplying the pixel driving voltage (ELVDD) to the pixels (P) and a low-potential power supply voltage (ELVSS) to the pixels (P). It may further include a second power line (VSSL) for supplying the initialization voltage (Vini) to the pixels (P), and a third power line (INIL) for supplying the initialization voltage (Vini) to the pixels (P).

Referring to FIG. 6, the pixel circuit includes a light emitting element (EL), a plurality of transistors (T11 to T16, DT), a capacitor (Cst), etc.

The transistors (T11 to T16, DT) may be implemented as p-channel transistors. The transistors (T11 to T16, DT) can be divided into switch elements (T11 to T16) and driving elements (DT).

Gate signals such as the N-1th scan signal [SCAN(N-1)], the Nth scan signal [SCAN(N)], and the EM signal [EM(N)] may be applied to the pixel circuit. The pulse of the N-1th scan signal [SCAN(N-1)] is synchronized with the data voltage (Vdata) of the N-1th pixel line. The pulse of the Nth scan signal [SCAN(N)] is synchronized with the data voltage (Vdata) of the Nth pixel line. The pulse of the Nth scan signal [SCAN(N)] is generated with the same pulse width as the N-1th scan signal (SCAN(N-1)), and the pulse of the Nth scan signal [SCAN(N-1)] is generated with the same pulse width as the N-1th scan signal [SCAN(N-1)]. It occurs later than the pulse. The pulse width of the scan signal [SCAN(N-1), SCAN(N)] can be set to 1 horizontal period (1H).

The capacitor Cst is connected between the first node n11 and the second node n12. The pixel driving voltage ELVDD is supplied to the pixels P through the first power line VDDL. The first node n11 is connected to the first power line VDDL, the first electrode of the third switch element T13, and the first electrode of the capacitor Cst.

The second node n12 is connected to the second electrode of the capacitor Cst, the gate of the driving element DT, the first electrode of the first switch element T11, and the first electrode of the fifth switch element T15. do.

The first switch element T11 is turned on according to the gate-on voltage VGL of the Nth scan signal [SCAN(N)] and connects the gate of the driving element DT to the second electrode. The first switch element T11 includes a gate connected to the second gate line SN, a first electrode connected to the second node n12, and a second electrode connected to the third node n13. The third node n13 is connected to the second electrode of the driving element DT, the second electrode of the first switch element T11, and the first electrode of the fourth switch element T14. The Nth scan signal [SCAN(N)] is supplied to the pixels P through the second gate line SN.

The first switch element (T11) is turned on only for 1 horizontal period (1H) when the Nth scan signal [SCAN(N)] is generated as the gate-on voltage (VGL) in 1 frame period, and then turns on for 1 frame period. Keep it off. Accordingly, the first switch element T11 may be implemented as a transistor with a dual gate structure capable of reducing leakage current as shown in FIG. 6, but is not limited thereto.

The second switch element T12 is turned on according to the gate-on voltage VGL of the Nth scan signal [SCAN(N)] and applies the data voltage Vdata to the first electrode of the driving element DT. The second switch element T12 includes a gate connected to the second gate line SN, a first electrode connected to the fifth node n15, and a second electrode connected to the data line 131. The fifth node n15 is connected to the first electrode of the driving element DT, the first electrode of the second switch element T12, and the second electrode of the third switch element T13.

The third switch element T13 supplies the pixel driving voltage ELVDD to the first electrode of the driving element DT in response to the EM signal [EM(N)]. The EM signal [EM(N)] is supplied to the pixels P through the third gate line EML. The third switch element T13 includes a gate connected to the third gate line EML, a first electrode connected to the first power line VDDL via the first node n11, and a fifth node n15. Includes a second electrode.

The fourth switch element T14 is turned on according to the gate-on voltage VEL of the EM signal [EM(N)] to connect the second electrode of the driving element DT to the anode of the light emitting element EL. The gate of the fourth switch element T14 is connected to the third gate line EML. The first electrode of the fourth switch element T14 is connected to the second electrode of the driving element DT via the third node n13, and the second electrode of the fourth switch element T14 is connected to the fourth node ( It is connected to the anode of the light emitting element (EL) via n14). The fourth node n14 is connected to the anode of the light emitting element EL, the second electrode of the fourth switch element T14, and the second electrode of the sixth switch element T16.

The fifth switch element (T15) is turned on according to the gate-on voltage (VEL) of the N-1 scan signal [SCAN(N-1)] to connect the second node (n12) to the third power line (INIL). By connecting, the gate of the capacitor (Cst) and the driving element (DT) are initialized during the initialization phase (Ti). The N-1th scan signal [SCAN(N-1)] is supplied to the pixels P through the first gate line SN-1. The initialization voltage Vini is supplied to the pixels P through the third power line INIL. The fifth switch element T15 includes a gate connected to the first gate line SN-1 to which the N-1 scan signal [SCAN(N-1)] is applied, a first electrode connected to the second node n12, and and a second electrode connected to the third power line (INIL).

The fifth switch element T15 may be implemented as a transistor with a dual gate structure that can reduce leakage current because of its long off period, but is not limited to this.

The sixth switch element (T16) is turned on according to the gate-on voltage (VGL) of the N scan signal [SCAN(N)] and connects the third power line (INIL) to the light emitting element (EL) in the sensing stage (Ts). Connect to the anode of During the sensing phase (Ts), the anode voltage of the light emitting element (EL) is the initialization voltage (Vini). In the sensing stage (Ts), the light emitting element (EL) does not emit light because the voltage between the anode and the cathode is less than its threshold voltage. The sixth switch element T16 includes a gate connected to the second gate line SN, a first electrode connected to the third power line INIL, and a second electrode connected to the fourth node n14.

The driving element DT drives the light emitting element EL by controlling the current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the second node n12, a first electrode connected to the fifth node n15, and a second electrode connected to the third node n13.

The operation of the internal compensation circuit of the pixel circuit consists of an initialization stage (Ti) in which the main nodes of the pixel circuit are initialized, and a sensing stage in which the threshold voltage of the driving element (DT) is sensed and the gate voltage of the driving element (DT) is compensated by this threshold voltage. (Ts), and a light emission stage (Tem) in which the light emitting element (EL) emits light with a current flowing according to the gate-source voltage (Vgs) of the driving element (DT).

FIGS. 7A to 9B are diagrams showing step-by-step the operation of the pixel circuit shown in FIG. 6. FIG. 7A is a diagram showing a current path flowing through a pixel circuit in the initialization phase (Ti). Figure 8a is a diagram showing the current path flowing through the pixel circuit in the sensing stage (Ts). The sensing step (Ts) can be interpreted as a programming step or a data writing step. FIG. 9A is a diagram showing a current path flowing through a pixel circuit during the light emission phase (Tem). The light emission stage (Tem) can be interpreted as a display driving stage. FIGS. 7B, 8B, and 9B are waveform diagrams showing gate signals applied to the pixel circuit shown in FIG. 6.

Referring to FIGS. 7A and 7B, the voltage of the N-1th scan signal [SCAN(N-1)] in the initialization step (Ti) is the gate-on voltage (VGL). The fifth switch element T15 is turned on in the initialization stage Ti, and the voltage of the second node n12 is discharged to the initialization voltage Vini. As a result, in the initialization step (Ti), the capacitor (Cst) and the gate voltage of the driving element (DT) are initialized to the initialization voltage (Vini).

Referring to FIGS. 8A and 8B, the voltage of the Nth scan signal [SCAN(N)] in the sensing stage (Ts) is the gate-on voltage (VGL). The first, second, and sixth switch elements T11, T12, and T16 are turned on in the sensing stage (Ts). At this time, the data voltage Vdata is applied to the second node n12, and the voltage of the second node n12 changes from Vini to Vdata - |Vth|. The data voltage (Vdata) compensated by the threshold voltage (Vth) of the driving element (DT) sensed in the sensing stage (Ts) is charged in the capacitor (Cst) and applied to the gate of the driving element (DT). Therefore, even if there is a deviation in the threshold voltage (Vth) of the driving element (DT) between pixels or a change in the threshold voltage (Vth) occurs over time, the gate voltage of the driving element (DT) can be compensated by the threshold voltage (Vth). there is.

Referring to FIGS. 9A and 9B, the voltage of the EM signal [EM(N)] changes to the gate-on voltage (VEL) in the light emission stage (Tem). The third and fourth switch elements T13 and T14 are turned on in the light emission stage Tem. During the light emission phase Tem, current may flow to the light emitting device EL through the driving device DT and the light emitting device EL may emit light.

The amount of current flowing through the light emitting element (EL) is adjusted according to the gate-source voltage (Vgs) of the driving element (DT). The gate-source voltage (Vgs) of the driving element (DT) is Vgs = Vdata-|Vth|-ELVDD during the light emission phase (Tem). In order to precisely express the luminance of low gray levels, the EM signal [EM(N)] is generated between the gate-on voltage (VEL) and the gate-off voltage (VEH) at a predetermined duty ratio during the emission phase (Tem). There can be a transition.

In order to reduce the number of output channels of the gate driver 120, a method of sharing gate signal wires to which gate signals are applied to neighboring pixel lines, as in the example of FIG. 10, may be considered.

In the example of FIG. 10, (2N-1)th line is the 2N-1 pixel line, “(2N)th line” is the 2N pixel line, and “(2N+1)th line” is the 2N+1 pixel line. , “(2N+2)th line” represents the 2N+2th pixel line, respectively.

Each of the gate signal wires (EML, SN-2, SN-1, and SN) is connected 1:1 to each of the output channels of the gate driver 120. And each of the gate signal wires (EML, SN-2, SN-1, SN) is branched into two and connected to two neighboring pixel lines.

The 2N-1 pixel line [(2N-1)th line] is the gate of the N-2 scan line (SN-2), the N-1 scan line (SN-1), and the shared EM line (EML). Connected to signal wires. The 2Nth pixel line ((2N)th line) is connected to gate signal lines such as the N-1th scan line (SN-1), the Nth scan line (SN), and the shared EM line (EML). Accordingly, the shared EM line (EML) is connected to the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line [(2N)th line]. Additionally, the N-1th scan line SN-1 is shared by the 2N-1th pixel line [(2N-1)th line] and the 2Nth pixel line [(2N)th line]. The Nth scan line SN is shared by the 2Nth pixel line [(2N)th line] and the 2N+1 pixel line [(2N+1)th line].

In a display device in which gate signal wires are shared between neighboring pixel lines, a fourth node (n14), that is, a light emitting element ( The turn-on timing of the initialization switch element (T16) for initializing the anode of EL) may vary. In this case, in the initialization step (Ti), the voltage of the fourth node (n14) increases, causing current to flow to the light emitting device (EL), and a luminance difference may be visible in neighboring pixel lines. This will be explained in conjunction with FIGS. 11A to 15B.

FIGS. 11A and 12B are diagrams showing an initialization step of neighboring pixels in a display device in which gate signal wires are shared between neighboring pixel lines.

Referring to FIGS. 11A and 11B, pulses of the shared EM signal (EM) may be generated over three horizontal periods. In the case of FIGS. 11A and 11B, the pulse of the shared EM signal is an example generated with a pulse width of approximately 4 horizontal periods within t1 to t5.

The pixels of the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line [(2N)th line] receive the shared EM signal (EM). A pulse of the shared EM signal (EM) is generated with a gate-off voltage (VEL). A pulse of the N-2th scan signal [SCAN(N-2)], a pulse of the N-1th scan signal [SCAN(N-1)], and a pulse duration of the shared EM signal (EM), and A pulse of the Nth scan signal [SCAN(N)] is generated. Pulses of scan signals [SCAN(N-2), SCAN(N-1), SCAN(N)] are generated with a gate-on voltage (VGL) and are sequentially shifted by a shift register.

The shared EM signal (EM) is inverted during the 4 horizontal period with the gate-off voltage (VEH) at t1, maintained at the gate-off voltage (VEH) for t2 to t4, and then inverted to the gate-on voltage (VEH) at t5. VEL) can be inverted to generate a pulse with a pulse width of approximately 4 horizontal periods. The N-2th scan signal [SCAN(N-2)] is inverted by the gate-on voltage (VGL) at t2 and is generated as a pulse with a pulse width of 1 horizontal period (1H). The N-1th scan signal [SCAN(N-1)] is inverted by the gate-on voltage (VGL) at t3 and is generated as a pulse with a pulse width of 1 horizontal period (1H). The Nth scan signal [SCAN(N)] is inverted to the gate-on voltage (VGL) at t4 and is generated as a pulse with a pulse width of 1 horizontal period (1H).

The initialization step Ti is different in the pixels of the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line [(2N)th line]. Hereinafter, the sixth switch element T16 that initializes the fourth node n14 in the initialization step Ti is referred to as an “initialization switch element.”

The pixels of the 2N-1th pixel line [(2N-1)th line] have the shared EM signal (EM), the N-2th scan signal [SCAN(N-2)], and the Nth line as shown in FIG. 11A. -1 Receives gate signals such as scan signal [SCAN(N-1)]. The initialization step (Ti) of these pixels is performed at t3. The initialization switch elements (T16-11) of the 2N-1 pixel line [(2N-1)th line] turn in response to the pulse of the N-1 scan signal [SCAN(N-1)] input to t3. - Turns on and initializes the fourth node (n14) to Vini.

The pixels of the 2Nth pixel line [(2N)th line] have a shared EM signal (EM), an N-1th scan signal [SCAN(N-1)], and an Nth scan signal [SCAN] as shown in FIG. 11B. (N)], etc. are input. The initialization step (Ti) of these pixels is performed at t4. The initialization switch elements (T16-12) of the 2Nth pixel line [(2N)th line] are turned on in response to the pulse of the Nth scan signal [SCAN(N)] input to t4 and are connected to the fourth node (n14). ) is initialized to Vini.

Referring to FIGS. 12A and 12B, the gate of the initialization switch elements T16-21 of the 2N-1 pixel line [(2N-1)th line] is connected to the N-2 scan line SN-2. You can. The gates of the initialization switch elements T16-22 of the 2Nth pixel line ((2N)th line) may be connected to the N-1th scan line SN-1. In this case, the initialization switch elements T16-21 and T16-22 may be turned on in response to the scan signal input first among scan signals input sequentially within the pulse duration of the shared EM signal EM.

The pixels of the 2N-1th pixel line [(2N-1)th line] have the shared EM signal (EM), the N-2th scan signal [SCAN(N-2)], and the Nth line as shown in FIG. 12A. -1 Receives gate signals such as scan signal [SCAN(N-1)]. The initialization step (Ti) of these pixels is performed at t2. The initialization switch elements (T16-21) of the 2N-1th pixel line [(2N-1)th line] turn in response to the pulse of the N-2th scan signal [SCAN(N-2)] input at t2. - Turns on and initializes the fourth node (n14) to Vini.

The pixels of the 2Nth pixel line [(2N)th line] have a shared EM signal (EM), an N-1th scan signal [SCAN(N-1)], and an Nth scan signal [SCAN] as shown in FIG. 12B. (N)], etc. are input. The initialization step (Ti) of these pixels is performed at t3. The initialization switch elements T16-22 of the 2Nth pixel line [(2N)th line] are turned on in response to the pulse of the N-1th scan signal [SCAN(N-1)] input to t3, 4 Initialize the node (n14) to Vini.

Parasitic capacitance (Cpar) may exist between the shared EM line (EML) and the fourth node (n14) as shown in FIGS. 13A and 13B. When the voltage of the shared EM signal (EM) increases at t1, the voltage (Vini) of the fourth node (n14) increases due to the parasitic capacitance (Cpar), which may cause an increase in the anode voltage of the light emitting device (EL). In this case, current flows to the light emitting device (OLED) and weak light may be visible from the light emitting device (OLED). At this time, the voltage of the fourth node n14 in the neighboring pixel lines increases simultaneously, but a difference in luminance may be visible between the pixel lines due to the time difference in the initialization step Ti.

FIGS. 14A and 14B are diagrams showing gate signals and fourth node voltages in pixel circuits of neighboring pixel lines where gate signal wires are shared.

As shown in FIGS. 14A and 14B, when the voltage of the shared EM signal (EM) rises, referring to FIGS. 14A and 14B, the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line The voltage Vn14 of the fourth node n14 simultaneously increases due to the parasitic capacitance Cpar in the pixels of [(2N1)th line]. Subsequently, the voltage (Vn14) of the fourth node (n14) in the pixels of the 2N-1th pixel line [(2N-1)th line] is the pulse of the N-1th scan signal [SCAN(N-1)]. After being lowered when generated, the voltage Vn14 of the fourth node n14 in the pixels of the 2Nth pixel line [(2N)th line] is lowered when the pulse of the Nth scan signal [SCAN(N)] is generated. .

Due to the time difference in the initialization step (Ti), the amount of charge accumulated at the fourth node (n14) in the pixels of the 2N-1 pixel line [(2N-1)th line] is 2N pixel line [(2N)th line]. There are more pixels than ]. As a result, as shown in FIGS. 15A and 15B, the brightness of the 2N-1 pixel line [(2N-1)th line] becomes higher than the brightness of the 2N pixel line [(2N)th line].

The present invention can reduce the luminance difference between neighboring pixel lines and suppress an increase in luminance of black grayscale by simultaneously performing the initialization step of neighboring pixel lines with shared gate signal wires.

The 2N-1 pixel line [(2N-1)th line] may include a first pixel circuit, and the 2N pixel line [(2N)th line] may include a second pixel circuit. The first and second pixel circuits may be adjacent to each other vertically and share one data line DL. The first pixel circuit may be connected to a data line DL, a shared EM line to which a shared EM signal is applied, a first scan line to which a first scan signal is applied, and a second scan line to which a second scan signal is applied. The second pixel circuit may be connected to the data line DL, the shared EM line, the second scan line, and a third scan line to which a third scan signal is applied. 16A to 20B, the first scan signal can be interpreted as SCAN(N-2), the second scan signal can be interpreted as SCAN(N-1), and the third scan signal can be interpreted as SCAN(N).

Pulses of the first scan signal, pulses of the second scan signal, and pulses of the third scan signal may be generated within the pulse duration of the shared EM signal.

Each of the first and second pixel circuits includes a capacitor (Cst) connected between the first node (n11) and the second node (n12), a driving element (DT) including a gate connected to the second node (n12), and It may include a light emitting element (EL) that emits light by a current flowing through the driving element (DT). When a pulse of the second scan signal is generated, the anode voltages of the light emitting elements EL in the first and second pixel circuits may be initialized simultaneously.

The first and second pixel circuits have substantially the same circuit configuration, except that the connection relationship between the scan lines and the switch elements is different. For convenience, if the components of the first pixel circuit are divided into 1-X and the components of the second pixel circuit are divided into 2-X, the components of the first pixel circuit and the second pixel circuit can be organized as follows.

The first pixel circuit has a gate connected to the second scan line SN-1, a first electrode connected to the 1-2 node n12, and a second electrode connected to the 1-3 node n13. -1 switch element (T11); A 1-2 switch element (T12) having a gate connected to the second scan line (SN-1), a first electrode connected to the 1-5 node (n15), and a second electrode connected to the data line (DL) ; A gate connected to the shared EM line (EML), a first electrode connected to the 1-1 node (n11) to which a pixel driving voltage (ELVDD) is applied, and a second electrode connected to the 1-5 node (n15) 1-3 switch elements (T13) having a; A gate connected to the shared EM line (EML), a first electrode connected to the 1-3 node (n13), and a second electrode connected to the anode of the light emitting device of the first pixel circuit via the 1-4 node (n14). 1st-4th switch element (n14) having an electrode; A 1-5 switch element ( T15); and a gate connected to the second scan line SN-1, a first electrode to which the initialization voltage Vini is applied, and a 1-6 switch element T16-31 connected to the 1-4 node n14. ) includes. The capacitor Cst of the first pixel circuit is connected between the 1-1 node (n11) and the 1-2 node (n12).

The second pixel circuit has a gate connected to the third scan line SN, a first electrode connected to the 2-2 node n12, and a second electrode connected to the 2-3 node n13. -1 switch element (T11); a 2-2 switch element (T12) having a gate connected to the third scan line (SN), a first electrode connected to the 2-5 node (n15), and a second electrode connected to the data line (DL); A gate connected to the shared EM line (EML), a first electrode connected to the 2-1 node (n11) to which the pixel driving voltage (ELVDD) is applied, and a second electrode connected to the 2-5 node (n15) 2nd-3rd switch element (T13) having an electrode; A gate connected to the shared EM line (EML), a first electrode connected to the 2-3 node (n13), and a second electrode connected to the anode of the light emitting device of the second pixel circuit via the 2-4 node (n14). 2-4 switch element (T14); A 2-5 switch element having a gate connected to the second scan line (SN-1), a first electrode connected to the 2-2 node (n12), and a second electrode to which the initialization voltage (Vini) is applied. (T15); and a gate connected to the second scan line (SN-1), a first electrode to which the initialization voltage (Vini) is applied, and a 2-6 switch element (T16-32) connected to the 2-4 node (n14). ) includes.

The configuration and operational effects of these first and second pixel circuits will be described in detail with reference to FIGS. 16A to 21B.

16A to 20B are diagrams showing pixel circuits of a display device and a driving method thereof according to the first embodiment of the present invention. In the pixel circuit shown in FIGS. 16A to 20B, parts that are substantially the same as those in FIG. 6 are given the same reference numerals and detailed descriptions thereof are omitted. Transistors shaded in FIGS. 16A to 20B are transistors excluding the initialization switch element T16. Arrows indicate current flow.

Each pixel circuit of the pixels of the 2N-1 pixel line [(2N-1)th line] includes a light emitting element EL and a plurality of transistors as shown in FIGS. 16A, 17A, 18A, and 19A. (T11~T16-31, DT), capacitor (Cst), etc. The transistors (T11 to T16-31, DT) can be divided into switch elements (T11 to T16-31) and driving elements (DT).

16A, 17A, 18A, and 19A, the gate of the first switch element T11, the gate of the second switch element T12, and the gate of the initialization switch element T16-31 are the Nth -1 It is connected to the N-1 scan line (SN-1) to which the scan signal [SCAN(N-1)] is applied. The first switch element (T11), the second switch element (T12), and the initialization switch element (T16-31) turn in response to the gate-on voltage (VGL) of the N-1 scan signal [SCAN(N-1)]. -It comes on.

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element (T15) is connected to the N-2th scan line (SN-2) to which the N-2th scan signal [SCAN(N-2)] is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-2th scan signal [SCAN(N-2)].

Each pixel circuit of the pixels of the 2N pixel line ((2N)th line) includes a light emitting element EL and a plurality of transistors T11 to T16-32, DT), capacitor (Cst), etc. The transistors (T11 to T16-32, DT) can be divided into switch elements (T11 to T16-32) and driving elements (DT).

Referring to FIGS. 16B, 17B, 18B, and 19B, the gates of the first and second switch elements T11 and T12 have the Nth scan line (SN) to which the Nth scan signal [SCAN(N)] is applied. ) is connected to. The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the Nth scan signal [SCAN(N)].

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element (T15) and the gate of the initialization switch element (T16-32) are the N-1th scan line (SN-1) to which the N-1th scan signal [SCAN(N-1)] is applied. connected to The fifth switch element T15 and the initialization switch element T16-32 are turned on in response to the gate-on voltage VGL of the N-1 scan signal [SCAN(N-1)].

Figures 16a and 16b show the operation of pixels of the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line [(2N)th line] at time t1.

Referring to FIGS. 16A and 16B, in the light emission phase Tem of the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line [(2N)th line], the driving element DT Current flows through the light emitting element (EL) according to the gate-source voltage (Vgs). When the shared EM signal (EM) is generated as a pulse of the gate-off voltage (VEH) at time t1, the third and fourth switch elements (T13, 14) are turned off and no current flows to the light emitting element (EL). .

Figures 17a and 17b show the operation of pixels of the 2N-1th pixel line [(2N-1)th line] and the 2Nth pixel line [(2N)th line] at t2.

The pulse of the N-2th scan signal [SCAN(N-2)] is applied to the 2N-1th pixel line [(2N-1)th line] as the gate-on voltage (VGL) at time t2, as shown in FIG. 17A. . At this time, the fifth switch element T15 is turned on in the pixels of the 2N-1 pixel line [(2N-1)th line], and Vini is applied to the second node n12, and the capacitor Cst and The gate of the driving device (DT) is initialized to Vini.

All transistors (T1 to T16-32, DT) in the pixels of the 2N pixel line [(2N)th line] share the scan signals [SCNA(N-1), SCAN(N)] as shown in FIG. 17B. Since the EM signal (EM) is the gate-off voltage (VGH, VEH), it is turned off at time t2.

Figures 18a and 18b show the operation of pixels of the 2N-1th pixel line [(2N-1)th line] and the 2Nth pixel line [(2N)th line] at t3.

Referring to FIGS. 18A and 18B, the pixels of the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line [(2N)th line] are the N-1 scan signal applied at time t3. It operates as a synchronization initialization step (Ti) according to the pulse of the gate-on voltage (VGL) of [SCAN(N-1)]. At the same time, the sensing step (Ts) is performed on the pixels of the 2N-1 pixel line [(2N-1)th line], and the data voltage (Vdata) is applied to the second node (n2) to the capacitor (Cst). The compensated data voltage (Vdata) is charged by the threshold voltage (Vth) of the driving element (DT).

The pulse of the N-1th scan signal [SCAN(N-1)] is applied to the 2N-1th pixel line [(2N-1)th line] as the gate-on voltage (VGL) at time t3, as shown in FIG. 18A. . At this time, the first switch element (T11), the second switch element (T12), and the initialization switch element (T16-31) are turned on in the pixels of the 2N-1 pixel line [(2N-1)th line]. Vini is applied to the fourth node (n14), and the anode of the light emitting element (EL) is initialized to Vini. At the same time, the data voltage Vdata is applied to the second node n12 through the second switch element T12 and the first and second electrodes of the driving element DT. At this time, the voltage of the second node (n2) changes to Vdata-|Vth|.

The pulse of the N-1th scan signal [SCAN(N-1)] is applied to the 2Nth pixel line [(2N)th line] as the gate-on voltage (VGL) at time t3, as shown in FIG. 18B. At this time, the fifth switch element T15 and the initialization switch element T16-32 are turned on in the pixels of the 2N pixel line [(2N)th line] to turn on the second node n2 and the fourth node ( Vini is authorized in n14). As a result, the capacitor Cst, the gate of the driving element DT, and the anode of the light emitting element EL are initialized to Vini.

Figures 19a and 19b show the operation of pixels of the 2N-1th pixel line [(2N-1)th line] and the 2Nth pixel line [(2N)th line] at t4.

Referring to FIGS. 19A and 19B, the gate signals [SCAN(N-2), SCAN(N-1) applied to the pixels of the 2N-1 pixel line [(2N-1)th line] at time t4. , EM] are all gate-off voltages. Accordingly, the transistors (T11 to T16-31, DT) of the 2N-1 pixel line [(2N-1)th line] remain in the off state, thereby maintaining the 2N-1 pixel line [(2N-1)th line]. The pixels of maintain their previous state.

The pixels of the 2Nth pixel line ((2N)th line) perform a sensing step (Ts) according to the pulse of the gate-on voltage (VGL) of the Nth scan signal [SCAN(N)] applied at time t4. In the sensing step (Ts), the data voltage (Vdata) in the pixels of the 2N pixel line ((2N)th line) is applied to the second switch element (T12) and the first and second electrodes of the driving element (DT). It is applied to the second node (n12) through . At this time, the voltage of the second node (n2) changes to Vdata-|Vth|.

Figures 20a and 20b show the operation of pixels of the 2N-1th pixel line [(2N-1)th line] and the 2Nth pixel line [(2N)th line] at t5.

Referring to FIGS. 20A and 20B, the shared EM signal (EM) applied to the pixels of the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line [(2N)th line] is t5. At this point, the gate-on voltage (VEL) is inverted and the light emission stage (Tem) begins. In the light emission stage Tem, the third and fourth switch elements T13 and 14 are turned on and current flows through the light emitting element EL. At this time, the voltage (Vgs) between the gate and source of the driving element (DT) is Vgs = Vdata-|Vth|-ELVDD.

As described above, the method of driving a display device according to an embodiment of the present invention includes generating a shared EM signal (EM) and generating a first scan signal [S( N-2)], sequentially generating a pulse of the second scan signal [S(N-1)], and a pulse of the third scan signal [S(N)], and the first scan signal [ The shared EM at any one of the pulse timing of the pulse of [S(N-2)], the pulse of the second scan signal [S(N-1)], and the pulse of the third scan signal [S(N)]. and simultaneously initializing pixels [(2N-1)th line pixel, (2N)th line pixel] of at least two pixel lines that share the signal EM.

An initialization voltage (Vini) is simultaneously applied to the anode of the light emitting element (EL) disposed in each of the pixels [(2N-1)th line pixel, (2N)th line pixel] of at least two pixel lines sharing the shared EM signal. approved.

The pixels [(2N-1)th line pixel, (2N)th line pixel] of the pixel lines are divided by the scan signals [S(N-2), S(N-1), S(N)]. Each line is scanned sequentially.

Figures 21A and 21B are flowcharts showing a method of initializing pixel circuits of neighboring pixel lines with shared gate signal wires in the display device according to the first embodiment of the present invention.

Referring to FIGS. 21A and 21B, within the pulse duration of the shared EM signal (EM), the N-2th scan signal [SCAN(N-2)], the N-1th scan signal [SCAN(N-1)], The Nth scan signal [SCAN(N)] is generated sequentially (S11 to S13). The 2N-1th pixel line [(2N-1)th line] is a shared EM signal (EM), the N-2th scan signal [SCAN(N-2)], and the N-1th scan signal [SCAN(N-1) )], etc., and the fourth node (n14) is initialized at the pulse timing of the N-1th scan signal [SCAN(N-1)] (S15). At the same time, the 2Nth pixel line [(2N)th line] is the gate of the shared EM signal (EM), the N-1th scan signal [SCAN(N-1)], and the Nth scan signal [SCAN(N)]. Upon receiving the signal, the fourth node (n14) is initialized at the pulse timing of the N-1th scan signal [SCAN(N-1)] (S15).

As can be seen from the simulation results of FIGS. 22A and 22B, the display device of the present invention has the same time from when the shared EM signal (EM) rises to the start of the initialization step (Ti), so the time of the light emitting element (EL) is the same. The current (iel) is substantially the same. As a result, the luminance of the light emitting element (EL) is reduced in the initialization step (Ti), which not only reduces the increase in luminance of the black grayscale, but also minimizes the luminance deviation between neighboring pixel lines to which the shared EM signal (EM) is applied. It can be.

The display device according to the second embodiment of the present invention is an example in which a shared EM signal is applied to three neighboring pixel lines.

In the example of FIG. 23, (3N-1)th line is the 3N-1 pixel line, “(3N)th line” is the 3N pixel line, and “(3N+1)th line” is the 3N+1 pixel line. represents each.

Each of the gate signal wires (EML, SN-2, SN-1, and SN) is connected 1:1 to each of the output channels of the gate driver 120. And each of the gate signal wires (EML, SN-2, SN-1, SN) is branched into three and connected to three neighboring pixel lines. Although some of the branch lines are omitted in the figure, the N-2th scan line (SN-2), Nth scan line (SN), and N+1 scan line (SN+1) are also branched into three gate lines. .

The 3N-1 pixel line [(3N-1)th line] may include a first pixel circuit, and the 3N pixel line [(3N)th line] may include a second pixel circuit. The 3N+1 pixel line [(3N+1)th line] may include a third pixel circuit.

The first to third pixel circuits may be adjacent vertically and share one data line DL.

N-2th scan signal [SCAN(N-2)], N-1th scan signal [SCAN(N-1)], Nth scan signal [SCAN(N)], N+1th scan signal [SCAN( N + 1)] as the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal, respectively, in the embodiments shown in FIGS. 24A to 24C, the first to third pixel circuits The configuration can be defined as follows.

The first to third pixel circuits have substantially the same circuit configuration, except that the connection relationship between the scan lines and the switch elements is different. For convenience, if the components of the first pixel circuit are divided into 1-X, the components of the second pixel circuit are divided into 2-X, and the components of the third pixel circuit are divided into 3-X, then the first, second and third The components of the pixel circuit can be organized as follows.

As shown in FIG. 24A, the first pixel circuit has a gate connected to the second scan line SN-1, a first electrode connected to the 1-2 node n12, and a 1-3 node n13. A 1-1 switch element (T11) having a connected second electrode; A 1-2 switch element (T12) having a gate connected to the second scan line (SN-1), a first electrode connected to the 1-5 node (n15), and a second electrode connected to the data line (DL) ; A gate connected to the shared EM line (EML), a first electrode connected to the 1-1 node (n11) to which a pixel driving voltage (ELVDD) is applied, and a second electrode connected to the 1-5 node (n15) 1-3 switch elements (T13) having a; A gate connected to the shared EM line (EML), a first electrode connected to the 1-3 node (n13), and a second electrode connected to the anode of the light emitting device of the first pixel circuit via the 1-4 node (n14). 1st-4th switch element (n14) having an electrode; and a 1-5 switch element having a gate connected to the first scan line (SN-2), a first electrode connected to the 1-2 node (n12), and a second electrode to which an initialization voltage (Vini) is applied. (T15); and a gate connected to the second scan line SN-1, a first electrode to which the initialization voltage Vini is applied, and a 1-6 switch element T16-41 connected to the 1-4 node n14. ) includes.

As shown in FIG. 24B, the second pixel circuit has a gate connected to the third scan line SN, a first electrode connected to the 2-2 node n12, and a 2-3 node connected to the 2-3 node n13. 2-1 switch element (T11) having a second electrode; a 2-2 switch element (T12) having a gate connected to the third scan line (SN), a first electrode connected to the 2-5 node (n15), and a second electrode connected to the data line (DL); A gate connected to the shared EM line (EML), a first electrode connected to the 2-1 node (n11) to which the pixel driving voltage (ELVDD) is applied, and a second electrode connected to the 2-5 node (n15) 2nd-3rd switch element (T13) having an electrode; A gate connected to the shared EM line (EML), a first electrode connected to the 2-3 node (n13), and a second electrode connected to the anode of the light emitting device of the second pixel circuit via the 2-4 node (n14). 2-4 switch element (T14); A 2-5 switch element having a gate connected to the second scan line (SN-1), a first electrode connected to the 2-2 node (n12), and a second electrode to which the initialization voltage (Vini) is applied. (T15); and a gate connected to the second scan line (SN-1), a first electrode to which the initialization voltage (Vini) is applied, and a 2-6 switch element (T16-42) connected to the 2-4 node (n14). ) includes.

As shown in FIG. 24C, the third pixel circuit includes a gate connected to the fourth scan line (SN+1), a first electrode connected to the 3-2 node (n12), and a 3-3 node (n13). A 3-1 switch element (T11) having a second electrode connected to; A 3-2 switch element (T12) having a gate connected to the fourth scan line (SN+1), a first electrode connected to the 3-5 node (n15), and a second electrode connected to the data line (DL) ); A gate connected to the shared EM line (EML), a first electrode connected to the 3-1 node (n11) to which the pixel driving voltage (ELVDD) is applied, and a second electrode connected to the 3-5 node (n15) 3-3 switch element (T13) having an electrode; A gate connected to the shared EM line (EML), a first electrode connected to the 3-3 node (n13), and a second electrode connected to the anode of the light emitting device of the second pixel circuit via the 3-4 node (n14). 3-4 switch element (T14); A 3-5 switch element (T15) having a gate connected to the third scan line (SN), a first electrode connected to the 3-2 node (n12), and a second electrode to which the initialization voltage (Vini) is applied. ); and a 3-6 switch having a gate connected to the second scan line (SN-1), a first electrode to which the initialization voltage (Vini) is applied, and a second electrode connected to the 3-4 node (n14). Includes element (T16-43).

The configuration and operational effects of these first to third pixel circuits will be described in detail with reference to FIGS. 24A to 24C.

FIGS. 24A to 25C are diagrams showing pixel circuits of a display device and a driving method thereof according to a second embodiment of the present invention.

In each of the pixels of the 3N-1 pixel line [(3N-1)th line] shown in FIG. 24A, the gate of the first switch element T11, the gate of the second switch element T12, and the initialization switch element The gate of (T16-41) is connected to the N-1th scan line (SN-1) to which the N-1th scan signal [SCAN(N-1)] is applied. The first switch element (T11), the second switch element (T12), and the initialization switch element (T16-41) turn in response to the gate-on voltage (VGL) of the N-1 scan signal [SCAN(N-1)]. -It comes on.

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element (T15) is connected to the N-2th scan line (SN-2) to which the N-2th scan signal [SCAN(N-2)] is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-2th scan signal [SCAN(N-2)].

In each of the pixels of the 3Nth pixel line [(3N)th line] shown in FIG. 24B, the gates of the first and second switch elements T11 and T12 receive the Nth scan signal [SCAN(N)]. It is connected to the Nth scan line (SN). The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the Nth scan signal [SCAN(N)].

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element (T15) and the gate of the initialization switch element (T16-42) are the N-1th scan line (SN-1) to which the N-1th scan signal [SCAN(N-1)] is applied. connected to The fifth switch element T15 and the initialization switch element T16-42 are turned on in response to the gate-on voltage VGL of the N-1 scan signal [SCAN(N-1)].

In each of the pixels of the 3N+1th pixel line [(3N+1)th line] shown in FIG. 24C, the gates of the first and second switch elements T11 and T12 transmit the N+1th scan signal [SCAN( N+1)] is connected to the applied N+1 scan line (SN+1). The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the N+1 scan signal [SCAN(N+1)].

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the Nth scan line SN to which the Nth scan signal [SCAN(N)] is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the Nth scan signal [SCAN(N)]. The gate of the initialization switch element (T16-43) is connected to the N-1th scan line (SN-1) to which the N-1th scan signal [SCAN(N-1)] is applied. The initialization switch element (T16-43) is turned on in response to the gate-on voltage (VGL) of the N-1th scan signal [SCAN(N-1)].

In the display device according to the second embodiment of the present invention, the first to third pixel circuits respond to the pulse of the third scan signal, that is, the Nth scan signal [SCAN(N)], as shown in FIGS. 25A to 25C. 4 nodes (n14) can be initialized simultaneously.

In each of the pixels of the 3N pixel line [(3N-1)th line] shown in FIG. 25A, the gates of the first and second switch elements T11 and T12 receive the N-1 scan signal [SCAN(N- 1)] is connected to the applied N-1 scan line (SN-1). The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the N-1 scan signal [SCAN(N-1)].

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element (T15) is connected to the N-2th scan line (SN-2) to which the N-2th scan signal [SCAN(N-2)] is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-2th scan signal [SCAN(N-2)].

The gate of the initialization switch element T16-41 is connected to the Nth scan line SN to which the Nth scan signal [SCAN(N)] is applied. The initialization switch element (T16-41) is turned on in response to the gate-on voltage (VGL) of the Nth scan signal [SCAN(N)].

In each of the pixels of the 3N pixel line [(3N)th line] shown in FIG. 25B, the gates of the first switch element T11, the second switch element T12, and the initialization switch element T16-42 are the It is connected to the Nth scan line (SN) to which the N scan signal [SCAN(N)] is applied. The first switch element T11, the second switch element T12, and the initialization switch element T16-42 are turned on in response to the gate-on voltage VGL of the Nth scan signal [SCAN(N)].

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the N-1th scan line SN-1 to which the N-1th scan signal [SCAN(N-1)] is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-1 scan signal [SCAN(N-1)].

In each of the pixels of the 3N+1th pixel line [(3N+1)th line] shown in FIG. 25C, the gates of the first and second switch elements T11 and T12 transmit the N+1th scan signal [SCAN( N+1)] is connected to the applied N+1 scan line (SN+1). The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the N+1 scan signal [SCAN(N+1)].

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gates of the fifth switch element T15 and the initialization switch element T16-43 are connected to the Nth scan line SN to which the Nth scan signal [SCAN(N)] is applied. The fifth switch element T15 and the initialization switch element T16-43 are turned on in response to the gate-on voltage VGL of the Nth scan signal [SCAN(N)].

FIG. 26 is a diagram showing an example in which gate signal wires are shared between neighboring pixel lines in a display device according to a third embodiment of the present invention.

The display device according to the third embodiment of the present invention is an example in which a shared EM signal is applied to four neighboring pixel lines.

In the example of FIG. 26, (4N-1)th line is the 4N-1 pixel line, “(4N)th line” is the 4N pixel line, and “(4N+1)th line” is the 4N+1 pixel line. , “(4N+2)th line” represents the 4N+2th pixel line, respectively.

Each of the gate signal wires (EML, SN-2, SN-1, SN, SN+1, SN+2) is connected 1:1 to each of the output channels of the gate driver 120. And each of the gate signal wires (EML, SN-2, SN-1, SN, SN+1, SN+2) is branched into four and connected to four neighboring pixel lines. Although some of the branch lines are omitted in the figure, the N-2 scan line (SN-2), N+1 scan line (SN+1), and N+2 scan line (SN+2) are also four gate lines. branches out into fields.

27A to 27D are diagrams showing pixel circuits of a display device and a driving method thereof according to a third embodiment of the present invention. In this embodiment, the 4N-1 to 4N+2 pixel lines [(4N-1)th line, (4N)th line, (4N+1)th line, (4N+2)th line] are the N-th pixel lines. This is an example of initialization simultaneously in response to a scan signal [SCAN(N)]. The third embodiment of the present invention is not limited to this. For example, when the gates of the initialization switch elements (T16-51 to T16-54) are connected to the N-1 scan line (SN-1) as in the above-described embodiments, the 4N+2 pixel lines [(4N-1)th line, (4N)th line, (4N+1)th line, (4N+2)th line] simultaneously responds to the N-1th scan signal [SCAN(N-1)] Can be initialized.

In each of the pixels of the 4N-1th pixel line [(4N-1)th line] shown in FIG. 27A, the gates of the first and second switch elements T11 and T12 transmit the N-1th scan signal [SCAN (N-1)] is connected to the applied N-1 scan line (SN-1). The first and second switch elements T11 are turned on in response to the gate-on voltage VGL of the N-1 scan signal [SCAN(N-1)].

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element (T15) is connected to the N-2th scan line (SN-2) to which the N-2th scan signal [SCAN(N-2)] is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-2th scan signal [SCAN(N-2)]. The gate of the initialization switch element (T16-51) is connected to the Nth scan line (SN) to which the Nth scan signal [SCAN(N)] is applied. The initialization switch element (T16-51) is turned on in response to the gate-on voltage (VGL) of the Nth scan signal [SCAN(N)].

In each of the pixels of the 4N pixel line [(4N)th line] shown in FIG. 27B, the gate of the first switch element T11, the gate of the second switch element T12, and the initialization switch element T16-52 ) is connected to the Nth scan line (SN) to which the Nth scan signal [SCAN(N)] is applied. The first switch element T11, the second switch element T12, and the initialization switch element T16-52 are turned on in response to the gate-on voltage VGL of the Nth scan signal [SCAN(N)].

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the N-1th scan line SN-1 to which the N-1th scan signal [SCAN(N-1)] is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-1 scan signal [SCAN(N-1)].

In each of the pixels of the 4N+1th pixel line [(4N+1)th line] shown in FIG. 27C, the gates of the first and second switch elements T11 and T12 transmit the N+1th scan signal [SCAN( N+1)] is connected to the applied N+1 scan line (SN+1). The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the N+1 scan signal [SCAN(N+1)].

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gates of the fifth switch element T15 and the initialization switch element T16-53 are connected to the Nth scan line SN to which the Nth scan signal [SCAN(N)] is applied. The fifth switch element T15 and the initialization switch element T16-53 are turned on in response to the gate-on voltage VGL of the Nth scan signal [SCAN(N)].

In each of the pixels of the 4N+2th pixel line [(4N+2)th line] shown in FIG. 27D, the gates of the first and second switch elements T11 and T12 receive the N+2th scan signal [SCAN (N+2)] is connected to the applied N+2 scan line (SN+2). The first and second switch elements T11 are turned on in response to the gate-on voltage VGL of the N+2 scan signal [SCAN(N+2)].

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line (EML) to which the shared EM signal (EM) is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the N+1 scan line SN+1 to which the N+1 scan signal [SCAN(N+1)] is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N+1 scan signal [SCAN(N+1)]. The gate of the initialization switch element (T16-51) is connected to the Nth scan line (SN) to which the Nth scan signal [SCAN(N)] is applied. The initialization switch element (T16-51) is turned on in response to the gate-on voltage (VGL) of the Nth scan signal [SCAN(N)].

The above-described embodiments can be applied singly or combined.

Various embodiments of the display device of the present invention can be described as follows.

Example 1: A display device includes a data line (DL) to which a data voltage is applied; A shared EM line (EML) to which a shared EM signal is applied; a first scan line (SN-2) to which a first scan signal (SCAN(N-2)) is applied; a second scan line (SN-1) to which a second scan signal (SCAN(N-1)) generated following the first scan signal is applied; a third scan line (SN) to which a third scan signal (SCAN(N)) generated following the second scan signal is applied; a first pixel circuit ((2N-1)th line pixel) connected to the data line, the shared EM line, the first scan line, and the second scan line; and a second pixel circuit ((2N)th line pixel) connected to the data line, the shared EM line, the second scan line, and the third scan line.

Each of the first and second pixel circuits includes a driving element (DT) including a gate connected to a capacitor (Cst); a light emitting element (EL) that emits light by a current flowing through the driving element; and an initialization switch (T16) that applies a predetermined initialization voltage to the anode of the light emitting device in response to one of the scan signals.

Pulses of the first scan signal, pulses of the second scan signal, and pulses of the third scan signal are generated within the pulse duration of the shared EM signal.

The same scan signal is applied to the gates of the initialization switches of the first and second pixel circuits, so that the initialization voltage is simultaneously applied to the light emitting devices of the first and second pixel circuits.

Example 2: A gate of each of the initialization switch of the first pixel circuit and the initialization switch of the second pixel circuit may be connected to the second scan line.

Embodiment 3: The first pixel circuit includes a 1-1 switch element having a gate connected to the second scan line, a first electrode connected to a 1-2 node, and a second electrode connected to a 1-3 node; a 1-2 switch element having a gate connected to the second scan line, a first electrode connected to a 1-5 node, and a second electrode connected to the data line; a 1-3 switch element having a gate connected to the shared EM line, a first electrode connected to the 1-1 node to which a pixel driving voltage is applied, and a second electrode connected to the 1-5 node; A 1-4 switch having a gate connected to the shared EM line, a first electrode connected to the 1-3 node, and a second electrode connected to the anode of the light emitting element of the first pixel circuit via the 1-4 node. device; And it may further include a 1-5 switch element having a gate connected to the first scan line, a first electrode connected to the 1-2 node, and a second electrode to which the initialization voltage is applied.

The initialization switch of the first pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the first to fourth nodes. The capacitor of the first pixel circuit is connected between the 1-1 node and the 1-2 node.

The driving element of the first pixel circuit further includes a first electrode connected to the 1-5 node and a second electrode connected to the 1-3 node.

Embodiment 4: The second pixel circuit includes a 2-1 switch element having a gate connected to the third scan line, a first electrode connected to a 2-2 node, and a second electrode connected to a 2-3 node; a 2-2 switch element having a gate connected to the third scan line, a first electrode connected to a 2-5 node, and a second electrode connected to the data line; a 2-3 switch element having a gate connected to the shared EM line, a first electrode connected to the 2-1 node to which the pixel driving voltage is applied, and a second electrode connected to the 2-5 node; a gate connected to the shared EM line, a first electrode connected to a 2-3 node, and a 2-4 switch element connected to the anode of the light emitting element of the second pixel circuit via the 2-4 node; and a 2-5 switch element having a gate connected to the second scan line, a first electrode connected to the 2-2 node, and a second electrode to which the initialization voltage is applied.

The initialization switch of the second pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the 2-4 node. The capacitor of the second pixel circuit is connected between the 2-1 node and the 2-2 node.

The driving element of the second pixel circuit further includes a first electrode connected to the 2-5 node and a second electrode connected to the 2-3 node.

Example 5: When the pulse of the second scan signal is generated, the data voltage compensated for the threshold voltage of the driving element is applied to the 1-2 node, and the initialization voltage is applied to the 1-4 node at the same time. It can be. When the pulse of the second scan signal is generated, the initialization voltage may be applied to the 2-2 node and the 2-4 node.

Example 6: When the second pixel circuit generates a pulse of the third scan signal, the first pixel circuit may maintain its previous state. When a pulse of the third scan signal is generated, a data voltage compensated for the threshold voltage of the driving element may be applied to the 2-2 node of the second pixel circuit.

Example 7: The display device includes a fourth scan line (SN+1) to which a fourth scan signal (SCAN(N+1)) generated following the third scan signal is applied; and a third pixel circuit ((3N+1)th line pixel) connected to the data line, the shared EM line, the second scan line, the third scan line, and the fourth scan line. there is.

The third pixel circuit includes a 3-1 switch element having a gate connected to the fourth scan line, a first electrode connected to a 3-2 node, and a second electrode connected to the 3-3 node; a 3-2 switch element having a gate connected to the fourth scan line, a first electrode connected to the 3-5 node, and a second electrode connected to the data line; a 3-3 switch element having a gate connected to the shared EM line, a first electrode connected to the 3-1 node to which the pixel driving voltage is applied, and a second electrode connected to the 3-5 node; a gate connected to the shared EM line, a first electrode connected to a 3-3 node, and a 3-4 switch element connected to the anode of the light emitting element of the second pixel circuit via the 3-4 node; and a 3-5 switch element having a gate connected to the third scan line, a first electrode connected to the 3-2 node, and a second electrode to which the initialization voltage is applied.

The initialization switch of the third pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the 3-4 nodes. The capacitor of the third pixel circuit is connected between the 3-1 node and the 3-2 node.

The driving element of the third pixel circuit further includes a first electrode connected to the 3-5 node and a second electrode connected to the 3-3 node.

Various embodiments of a method of driving a display device according to an embodiment of the present invention can be described as follows.

Example 1: The driving method includes generating a shared EM signal; sequentially generating pulses of a first scan signal, pulses of a second scan signal, and pulses of a third scan signal within the pulse duration of the shared EM signal; and simultaneously initializing pixels of at least two pixel lines sharing the shared EM signal at any one pulse timing of the pulse of the first scan signal, the pulse of the second scan signal, and the pulse of the third scan signal. Includes.

Example 2: The step of simultaneously initializing the pixels of the at least two pixel lines includes simultaneously applying a predetermined initialization voltage to the anode of the light emitting device disposed in each of the pixels of the at least two pixel lines sharing the shared EM signal. It can be included.

Example 3: The driving method may further include sequentially scanning the pixel lines using the scan signals.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

100: display panel 120: gate driver
200: Host system 300: Drive IC
DL: data line EML: shared EM line
SN-2 to SN+1: Scan lines

Claims (10)

a data line (DL) to which a data voltage is applied;
A shared EM line (EML) to which a shared EM signal is applied;
a first scan line (SN-2) to which a first scan signal (SCAN(N-2)) is applied;
a second scan line (SN-1) to which a second scan signal (SCAN(N-1)) generated following the first scan signal is applied;
a third scan line (SN) to which a third scan signal (SCAN(N)) generated following the second scan signal is applied;
a first pixel circuit ((2N-1)th line pixel) connected to the data line, the shared EM line, the first scan line, and the second scan line; and
A second pixel circuit ((2N)th line pixel) connected to the data line, the shared EM line, the second scan line, and the third scan line,
Each of the first and second pixel circuits,
a driving element (DT) including a gate connected to a capacitor (Cst);
a light emitting element (EL) that emits light by a current flowing through the driving element; and
An initialization switch (T16) that applies a predetermined initialization voltage to the anode of the light emitting device in response to one of the scan signals,
Pulses of the first scan signal, pulses of the second scan signal, and pulses of the third scan signal are generated within the pulse duration of the shared EM signal,
A display device in which the same scan signal is applied to the gates of the initialization switches of the first and second pixel circuits and the initialization voltage is simultaneously applied to the light emitting elements of the first and second pixel circuits. According to claim 1,
A display device wherein gates of each of the initialization switch of the first pixel circuit and the initialization switch of the second pixel circuit are connected to the second scan line. According to claim 2,
The first pixel circuit is,
a 1-1 switch element having a gate connected to the second scan line, a first electrode connected to a 1-2 node, and a second electrode connected to a 1-3 node;
a 1-2 switch element having a gate connected to the second scan line, a first electrode connected to a 1-5 node, and a second electrode connected to the data line;
a 1-3 switch element having a gate connected to the shared EM line, a first electrode connected to the 1-1 node to which a pixel driving voltage is applied, and a second electrode connected to the 1-5 node;
A 1-4 switch having a gate connected to the shared EM line, a first electrode connected to the 1-3 node, and a second electrode connected to the anode of the light emitting element of the first pixel circuit via the 1-4 node. device; and
It further includes a 1-5 switch element having a gate connected to the first scan line, a first electrode connected to the 1-2 node, and a second electrode to which the initialization voltage is applied,
The initialization switch of the first pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the 1-4 nodes,
The capacitor of the first pixel circuit is connected between the 1-1 node and the 1-2 node,
The driving element of the first pixel circuit is,
A display device further comprising a first electrode connected to the 1-5 node and a second electrode connected to the 1-3 node. According to claim 3,
The second pixel circuit is,
a 2-1 switch element having a gate connected to the third scan line, a first electrode connected to the 2-2 node, and a second electrode connected to the 2-3 node;
a 2-2 switch element having a gate connected to the third scan line, a first electrode connected to a 2-5 node, and a second electrode connected to the data line;
a 2-3 switch element having a gate connected to the shared EM line, a first electrode connected to the 2-1 node to which the pixel driving voltage is applied, and a second electrode connected to the 2-5 node;
a gate connected to the shared EM line, a first electrode connected to a 2-3 node, and a 2-4 switch element connected to the anode of the light emitting element of the second pixel circuit via the 2-4 node; and
A 2-5 switch element having a gate connected to the second scan line, a first electrode connected to the 2-2 node, and a second electrode to which the initialization voltage is applied,
The initialization switch of the second pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the 2-4 node,
The capacitor of the second pixel circuit is connected between the 2-1 node and the 2-2 node,
The driving element of the second pixel circuit is,
A display device further comprising a first electrode connected to the 2-5 node and a second electrode connected to the 2-3 node. According to claim 4,
When the pulse of the second scan signal is generated, a data voltage compensated for the threshold voltage of the driving element is applied to the 1-2 node, and at the same time, the initialization voltage is applied to the 1-4 node,
A display device in which the initialization voltage is applied to the 2-2 node and the 2-4 node when a pulse of the second scan signal is generated. According to claim 5,
The second pixel circuit is,
When the pulse of the third scan signal is generated, the first pixel circuit maintains its previous state,
A display device in which a data voltage compensated for the threshold voltage of the driving element is applied to the 2-2 node of the second pixel circuit when a pulse of the third scan signal is generated. According to claim 4,
a fourth scan line (SN+1) to which a fourth scan signal (SCAN(N+1)) generated following the third scan signal is applied; and
Further comprising a third pixel circuit ((3N+1)th line pixel) connected to the data line, the shared EM line, the second scan line, the third scan line, and the fourth scan line,
The third pixel circuit is,
a 3-1 switch element having a gate connected to the fourth scan line, a first electrode connected to the 3-2 node, and a second electrode connected to the 3-3 node;
a 3-2 switch element having a gate connected to the fourth scan line, a first electrode connected to the 3-5 node, and a second electrode connected to the data line;
a 3-3 switch element having a gate connected to the shared EM line, a first electrode connected to the 3-1 node to which the pixel driving voltage is applied, and a second electrode connected to the 3-5 node;
a gate connected to the shared EM line, a first electrode connected to a 3-3 node, and a 3-4 switch element connected to the anode of the light emitting element of the second pixel circuit via the 3-4 node; and
A 3-5 switch element having a gate connected to the third scan line, a first electrode connected to the 3-2 node, and a second electrode to which the initialization voltage is applied,
The initialization switch of the third pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the 3-4 nodes,
The capacitor of the third pixel circuit is connected between the 3-1 node and the 3-2 node,
The driving element of the third pixel circuit is,
A display device further comprising a first electrode connected to the 3-5 node and a second electrode connected to the 3-3 node. generating a shared EM signal;
sequentially generating pulses of a first scan signal, pulses of a second scan signal, and pulses of a third scan signal within the pulse duration of the shared EM signal; and
Simultaneously initializing pixels of at least two pixel lines sharing the shared EM signal at any one pulse timing of the pulse of the first scan signal, the pulse of the second scan signal, and the pulse of the third scan signal. Includes,
The step of simultaneously initializing pixels of at least two pixel lines includes:
A method of driving a display device comprising simultaneously applying a predetermined initialization voltage to an anode of a light emitting device disposed in each of pixels of at least two pixel lines sharing the shared EM signal. delete According to claim 8,
A method of driving a display device further comprising sequentially scanning the pixel lines using the scan signals.