KR20230060135A - Apparatus for generating light-emittion control signal and operating method thereof - Google Patents

Abstract

The present invention relates to a signal generating apparatus for generating a light emission control signal and an operating method thereof. The signal generating device according to one embodiment includes: a first signal generating unit for receiving a first clock, a second clock having a phase opposite to the first clock, and an (n-1)th light emission control signal applied through an (n-1)th light emission control line (where n is a positive integer), and generating a first gate signal based on the first clock, the second clock, and the (n-1)th light emission control signal; a second signal generating unit for receiving the (n-1)th light emission control signal, and an enable clock having the same pulse width and phase as one of the first clock and the second clock, and generating a second gate signal based on the (n-1)th light emission control signal and the enable clock; and a light emission control signal generating unit for generating a target light emission control signal applied through an n-th light emission control line based on the first gate signal and the second gate signal.

Description

Signal generating device for generating light emission control signal and operation method thereof

The present invention relates to a signal generating device for generating an emission control signal and an operation method thereof, and more particularly, to a technical concept of generating an emission control signal (EM) used in a pixel driving circuit of an organic light emitting display device.

1A to 1B are diagrams illustrating a pixel driving circuit of an organic light emitting display device.

Referring to FIGS. 1A and 1B , the pixel driving circuit 110 of the organic light emitting display device is a circuit provided in each of a plurality of pixels formed in an area where a plurality of row lines and column lines intersect. It is typically implemented with 6 transistors (T1 to T6) and 1 capacitor, that is, a 6T1C structure, and is driven based on control signals (SCAN, INIT, and EM) input to each transistor as shown in reference numeral 120.

Among them, the emission control signal EM may be used to prevent light from being generated during the compensation period of the pixel driving circuit 110 .

Specifically, as shown in FIG. 1A, in the p-type TFT-based pixel driving circuit 110, the emission control signal EM is controlled to have a high level in the initialization and threshold voltage compensation section, and the n-type TFT-based pixel driving circuit 110 In the pixel driving circuit of , emission of light from a corresponding pixel may be blocked by controlling the emission control signal EM to have a low level in the initialization and threshold voltage compensation section.

In addition, the light emission control signal (EM) can play a role of adjusting the brightness by adjusting the light generation period, and even if the same current flows to the OLED, the brightness is adjusted by adjusting the high pulse period of the light emission control signal (EM). can do. In other words, the emission control signal EM can be easily used even when adjusting the luminance of the display according to the ambient illumination.

Accordingly, the organic light emitting display device requires a signal generator having a shift register characteristic of shifting by one line time for each of a plurality of row lines, and at the same time easily varying and outputting the pulse width of the emission control signal EM.

However, the conventional signal generating device for generating the emission control signal EM includes a circuit for controlling the pulse width of the emission control signal EM to be an odd multiple of the line time, and a circuit for controlling the pulse width to an even multiple of the line time. There is a problem that the circuit configuration of the liver is different.

That is, the conventional signal generating device can selectively control the pulse width of the emission control signal EM to either an odd multiple or an even multiple of the line signal, so that the user controls the emission control signal EM with a desired pulse width. However, there is a limitation, and thus there is a problem that the brightness control of the display device based on the emission control signal (EM) is also restricted.

Korean Patent Publication No. 10-2021-0007508, "Display device and its driving method" Korean Patent Publication No. 10-2021-0040727, "Display device and its driving method"

An object of the present invention is to provide a signal generating device and operation method for generating a light emission control signal having a pulse width of an arbitrary multiple regardless of whether the line time is an odd or even multiple.

In addition, the present invention is intended to provide a signal generating device and an operating method for generating a light emission control signal having an arbitrary multiple of pulse width with a smaller number of transistors compared to the prior art.

A signal generating device according to an embodiment of the present invention is applied through a first clock, a second clock having a phase opposite to the first clock, and an n-1th (where n is a positive integer) emission control line. - A first signal generator for receiving a 1st light emission control signal and generating a first gate signal based on the first clock, the second clock and the n-1th light emission control signal; Second signal generation for receiving an enable clock having the same pulse width and phase as either one of the first clock and the second clock and generating a second gate signal based on the n-1th light emission control signal and the enable clock and a light emitting control signal generator configured to generate a target light emitting control signal applied through the nth light emitting control line based on the first gate signal and the second gate signal.

According to one side, the target light emission control signal has the same pulse width as the n-1th light emission control signal, and in contrast to the n-1th light emission control signal, at least one of the first clock, the second clock, and the enable clock. The signal may be delayed by the line time corresponding to the pulse width of the clock.

According to one side, the first signal generator may include a first transistor receiving a second clock and an n−1 th light emission control signal, and a second transistor electrically connected to the first transistor and receiving a first clock. .

According to one side, the first signal generator may receive an n−1 th light emission control signal through a gate terminal of a first transistor and receive a first clock through a gate terminal of a second transistor.

According to one side, the second signal generator includes a seventh transistor for receiving the n-1th light emission control signal, an eighth transistor electrically connected to the seventh transistor, a ninth transistor for receiving the n-1th light emission control signal, and a second signal generating unit. A tenth transistor electrically connected to the ninth transistor and receiving an enable clock may be included.

According to one side, the second signal generator may receive the n−1 th light emission control signal through the gate terminals of the seventh and eighth transistors, respectively.

According to one side, the second signal generating unit may be connected to a node electrically connecting the gate terminal of the tenth transistor to the seventh transistor and the eighth transistor.

According to one side, the light emitting control signal generator includes a third transistor receiving a first gate signal, a fourth transistor electrically connected to the third transistor and receiving a second gate signal, and a gate terminal of the third transistor and the fourth transistor. It may include a fifth transistor electrically connected to the node electrically connected to and a sixth transistor electrically connected to the fifth transistor and receiving the second gate signal.

According to one side, the emission control signal generating unit may receive the first gate signal through the gate terminal of the third transistor and receive the second gate signal through the gate terminals of the fourth and sixth transistors, respectively.

According to one side, the light emitting control signal generator may further include a coupling capacitor provided between a node electrically connecting the third transistor and the fourth transistor and the n+1th light emitting control line.

In a signal generation method according to an embodiment of the present invention, in a first signal generator, a first clock, a second clock having a phase opposite to the first clock, and an n-1th (where n is a positive integer) emit light. Receiving an n-1 th light emission control signal applied through a control line, generating a first gate signal in a first signal generator based on a first clock, a second clock, and an n-1 th light emission control signal receiving, in a second signal generator, an enable clock having the same pulse width and phase as the n-1 th light emission control signal and any one of the first and second clocks, the second signal Generating, in a generator, a second gate signal based on the n-1th light emission control signal and an enable clock; and In the light emission control signal generator, controlling the nth light emission based on the first gate signal and the second gate signal. A step of generating a target emission control signal applied through a line may be included.

According to one embodiment, the present invention can generate a light emission control signal having a pulse width of an arbitrary multiple regardless of whether the line time is an odd or even multiple.

According to one embodiment, the present invention can generate a light emission control signal having a pulse width of an arbitrary multiple with a smaller number of transistors compared to conventional technologies.

1A to 1B are diagrams illustrating a pixel driving circuit of an organic light emitting display device.
2 is a diagram illustrating a signal generating device according to an exemplary embodiment.
3A to 3C are diagrams illustrating a first implementation example of a signal generating device according to an embodiment.
4A to 4C are diagrams illustrating a second embodiment of a signal generating device according to an embodiment.
5 is a diagram illustrating a signal generation method according to an embodiment.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification are only illustrated for the purpose of explaining the embodiments according to the concept of the present invention, and the embodiments according to the concept of the present invention These may be embodied in various forms and are not limited to the embodiments described herein.

Embodiments according to the concept of the present invention can apply various changes and can have various forms, so the embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosures, and includes modifications, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various elements, but elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one element from another element, for example, a first element may be termed a second element, and similar In short, the second component may also be referred to as the first component.

It is understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. It should be. On the other hand, when an element is referred to as “directly connected” or “directly connected” to another element, it should be understood that no other element exists in the middle. Expressions describing the relationship between components, such as "between" and "directly between" or "directly adjacent to" should be interpreted similarly.

Terms used in this specification are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "have" are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, but one or more other features or numbers, It should be understood that the presence or addition of steps, operations, components, parts, or combinations thereof is not precluded.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in this specification, it should not be interpreted in an ideal or excessively formal meaning. don't

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the patent application is not limited or limited by these examples. Like reference numerals in each figure indicate like elements.

2 is a diagram illustrating a signal generating device according to an exemplary embodiment.

Referring to FIG. 2 , the signal generating device 200 according to an exemplary embodiment may generate a light emission control signal having a pulse width of an arbitrary multiple regardless of whether the line time is an odd multiple or an even multiple.

In addition, the signal generating device 200 can generate a light emission control signal having a pulse width of an arbitrary multiple using a smaller number of transistors compared to the conventional technology.

To this end, the signal generating device 200 may include a first signal generating unit 210, a second signal generating unit 220, and an emission control signal generating unit 230, and the first signal generating unit 210 ), the second signal generator 220 and the emission control signal generator 230 may be implemented with 10 transistors and 1 capacitor.

The first signal generator 210 according to an embodiment includes a first clock (CLK), a second clock (CLKB) having a phase opposite to the first clock (CLK), and an n−1 (where n is a positive number). An integer of) may receive an n−1 th emission control signal EM[n−1] applied through the emission control line.

In addition, the first signal generator 210 may generate a first gate signal based on the first clock CLK, the second clock CLKB, and the n−1 th emission control signal EM[n−1]. can

For example, the first clock (CLK) and the second clock (CLKB) may be clock signals having phases opposite to each other, and the pulse width may be formed corresponding to a preset line time. Each of the two clocks CLKB may be provided from a timing controller of the organic light emitting diode display.

The second signal generating unit 220 according to an embodiment may be configured to clock the n−1 th light emission control signal EM[n−1], and any one of the first clock CLK and the second clock CLKB. An enable clock (CLKE) having the same pulse width and phase may be received.

Also, the second signal generator 220 may generate a second gate signal based on the n−1 th emission control signal EM[n−1] and the enable clock CLKE.

The emission control signal generator 230 according to an exemplary embodiment may generate a target emission control signal EM[n] applied through the n-th emission control line based on the first gate signal and the second gate signal. .

For example, the target emission control signal EM[n] has the same pulse width as the n-1 th emission control signal EM[n-1], and the n-1 th emission control signal EM[n-1]. 1]), it may be a signal delayed by a single line time.

Also, the enable clock CLKE may be formed with a pulse width corresponding to the line time, similar to the first clock CLK and the second clock CLKB, and the pulse width of the target emission control signal EM[n]. It may be formed in the same phase as any one of the first clock (CLK) and the second clock (CLKB) according to the size of .

Specifically, when the pulse width of the emission control signal EM[n] is an even multiple of the line time, the timing controller converts the second clock CLKB into an enable clock CLKE through a switching operation, and the second signal generator. 220, and when the pulse width of the emission control signal EM[n] is an odd multiple of the line time, a second signal is generated by using the first clock CLK as an enable clock CLKE through a switching operation. section 220.

That is, the signal generating device 200 according to an embodiment uses an enable clock (CLKE) provided only by a switching operation of a timing controller without additional power or circuitry to determine whether the line time is an odd or even multiple. Regardless, the emission control signal EM[n] having a pulse width of an arbitrary multiple may be generated.

The signal generating device 200 according to an embodiment will be described in more detail with reference to FIGS. 3A to 4C.

3A to 3C are diagrams illustrating a first implementation example of a signal generating device according to an embodiment.

Referring to FIGS. 3A to 3C , reference numeral 310 shows a circuit diagram of the signal generating device according to the first embodiment, and reference numeral 320 indicates an even multiple of a line time in the signal generating device according to the first embodiment. A timing diagram for generating a light emission control signal having a pulse width is shown. Reference numeral 330 is a timing diagram for generating a light emission control signal having a pulse width of an odd multiple of a line time in the signal generating device according to the first embodiment. shows

Referring to reference numeral 310, the signal generator according to the first embodiment may include a first signal generator 311, a second signal generator 312, and an emission control signal generator 313. The first signal generator 311, the second signal generator 312, and the emission control signal generator 313 may be implemented with 10 n-type TFTs and 1 capacitor.

The first signal generator 311 is electrically connected to the first transistor N1 receiving the second clock CKLB and the n−1 th emission control signal EM[n−1] and the first transistor N1. A second transistor N1 connected to and receiving the first clock CLK may be included.

Specifically, the first signal generator 311 receives the n−1 th emission control signal EM[n−1] through the gate terminal of the first transistor N1, and the gate of the second transistor N2. The first clock CLK may be received through the terminal, where the n−1 th emission control signal EM[n−1] may be received when the first clock CLK has a high level.

In addition, the first signal generator 311 receives the second clock CKLB through the drain terminal of the first transistor N1 and electrically connects the first transistor N1 and the second transistor N2. A first gate signal may be output through the node A, wherein the first gate signal has a high level or a low level according to the respective switching operations of the first transistor N1 and the second transistor N2. can have

Meanwhile, the source terminal of the second transistor N2 may be connected to a second voltage line to which the low level voltage VGL is applied. For example, the second voltage line may be a ground (GND) line, but is not limited thereto. no.

The second signal generator 312 includes a seventh transistor N7 receiving the n−1 th emission control signal EM[n−1] and an eighth transistor N8 electrically connected to the seventh transistor N7. ), a ninth transistor N9 receiving the n-1th light emission control signal EM[n-1], and a 10th transistor electrically connected to the ninth transistor N9 and receiving the enable clock CLKE. (N10) may be included.

Specifically, the second signal generator 312 receives the n−1 th emission control signal EM[n−1] through the gate terminals of the seventh and eighth transistors N7 and N8, respectively. The enable clock CLKE may be received through the drain terminal of the tenth transistor N10.

Also, in the second signal generator 312 , the gate terminal of the tenth transistor N10 may be connected to a node electrically connecting the seventh transistor N7 and the eighth transistor N8 .

In addition, the second signal generator 312 may output a second gate signal through a node QB electrically connecting the ninth transistor N9 and the tenth transistor N10, wherein the second gate signal is Each of the 7th transistor N7 to 10th transistor N10 may have a high level or a low level according to a switching operation.

Meanwhile, the source terminal of each of the seventh transistor N7 and the ninth transistor N9 is connected to the second voltage line, and the drain terminal of the eighth transistor N8 has a first voltage VGH applied thereto. It may be connected to a voltage line, and for example, the first voltage line may be a power supply voltage (VDD) line, but is not limited thereto.

Also, the eighth transistor N8 may be a diode connected transistor.

The emission control signal generator 313 includes a third transistor N3 receiving a first gate signal, a fourth transistor N4 electrically connected to the third transistor N3 and receiving a second gate signal, and a gate terminal. A fifth transistor N5 electrically connected to a node Q electrically connecting the third transistor N3 and the fourth transistor N4 and electrically connected to the fifth transistor N5 and receiving a second gate signal. It may include a sixth transistor (N6) to.

Specifically, the emission control signal generator 313 receives the first gate signal through the gate terminal of the third transistor N3, and through the gate terminals of the fourth and sixth transistors N4 and N6, respectively. A second gate signal may be received. In other words, the gate terminal of the third transistor N3 may be connected to the node A, and the gate terminals of the fourth and sixth transistors N4 and N6 may be connected to the node QB.

In addition, the emission control signal generator 313 may generate and output a target emission control signal EM[n] through a node electrically connecting the fifth transistor N5 and the sixth transistor N6, Here, the target emission control signal EM[n] has the same pulse width as the n−1 th emission control signal EM[n−1] according to the switching operations of the third to sixth transistors N3 to N6 respectively. and can be formed/output as a signal delayed by the line time.

For example, the emission control signal generation unit 313 may output the target emission control signal EM[n] to each pixel driving circuit connected to the nth emission control line.

Meanwhile, the drain terminals of the third and fifth transistors N3 and N5 are connected to the first voltage line, and the source terminals of the fourth and sixth transistors N4 and N6 are connected to the second voltage line. can

According to one side, the emission control signal generator 313 includes a coupling capacitor (C) provided between the node Q and the n+1th emission control line to which the n+1th emission control signal EM[n+1] is applied. ), and the coupling capacitor C increases the voltage of the node Q through capacitive coupling to increase the level of the target emission control signal EM[n] to a high level voltage (VGH).

Hereinafter, the operation process of the signal generator according to the first embodiment will be described through timing diagrams shown at reference numerals 320 and 330 .

When the signal generating device according to the first embodiment generates a target emission control signal EM[n] having a pulse width of an even number of times the line time, node A is at a low level in section (1) of reference numeral 320. and since the node QB is maintained at a high level, the node Q and the target emission control signal EM[n] may be maintained at a low level.

In period (2) of reference numeral 320, node A starts to become high level according to the second clock (CLKB), and node Q is one line time later than the n-1 th emission control signal (EM[n-1]). high level, and when the next n+1 th emission control signal (EM[n+1]) goes up to high level, the node Q rises to a higher voltage due to the coupling operation through the coupling capacitor, Accordingly, in period (2), since the fifth transistor N5, which is a pull-up transistor, is turned on, a high level target emission control signal EM[n] may be output.

In section (3) of reference numeral 320, since the enable clock (CLKE) has the same waveform as the second clock (CLKB), after the n-1th emission control signal (EM[n-1]) drops to the low level, The node QB rises to a high level after one line time, and this causes the node Q and the target emission control signal EM[n] to fall to a low level after one line time, and through this, the first embodiment The signal generating device according to the present invention may output a target emission control signal EM[n] delayed by one line time compared to the n−1 th emission control signal EM[n−1].

In the case of generating the target emission control signal EM[n] having a pulse width of an odd multiple of the line time, the signal generating device according to the first embodiment may operate according to the timing diagram of reference numeral 330, where The operation process according to reference numeral 330 is the same as the operation process described above through reference numeral 320 except that the enable clock CLKE and the first clock CLK are the same clock, so the contents described through reference numeral 320 A description overlapping with the above will be omitted.

4A to 4C are diagrams illustrating a second embodiment of a signal generating device according to an embodiment.

Referring to FIGS. 4A to 4C , reference numeral 410 denotes a circuit diagram of the signal generator according to the second embodiment, and reference numeral 420 denotes an even multiple of a line time in the signal generator according to the second embodiment. A timing diagram for generating a light emission control signal having a pulse width is shown. Reference numeral 430 is a timing diagram for generating a light emission control signal having a pulse width of an odd multiple of a line time in the signal generating device according to the second embodiment. shows

Referring to reference numeral 410, the signal generator according to the second embodiment may include a first signal generator 411, a second signal generator 412, and an emission control signal generator 413. The 1 signal generator 411, the second signal generator 412, and the emission control signal generator 413 may be implemented with 10 p-type TFTs and 1 capacitor.

The first signal generator 411 is electrically connected to the first transistor P1 receiving the second clock CKLB and the n−1 th emission control signal EM[n−1] and the first transistor P1. A second transistor P1 connected to and receiving the first clock CLK may be included.

Specifically, the first signal generator 411 receives the n−1 th light emission control signal EM[n−1] through the gate terminal of the first transistor P1, and the gate of the second transistor P2. The first clock CLK may be received through the terminal.

In addition, the first signal generator 311 receives the second clock CKLB through the source terminal of the first transistor P1 and electrically connects the first transistor P1 and the second transistor P2. A first gate signal may be output through the node A, wherein the first gate signal has a high level or a low level according to the respective switching operations of the first transistor P1 and the second transistor P2. can have

Meanwhile, a drain terminal of the second transistor P2 may be connected to a first voltage line to which a high level voltage VGH is applied.

The second signal generator 412 includes a seventh transistor P7 receiving the n−1 th emission control signal EM[n−1] and an eighth transistor P8 electrically connected to the seventh transistor P7. ), a ninth transistor P9 receiving the n-1th light emission control signal EM[n-1], and a 10th transistor electrically connected to the ninth transistor P9 and receiving the enable clock CLKE. (P10) may be included.

Specifically, the second signal generator 412 receives the n−1 th emission control signal EM[n−1] through the gate terminals of the seventh and eighth transistors P7 and P8, The enable clock CLKE may be received through the source terminal of the tenth transistor P10 .

Also, in the second signal generator 412 , the gate terminal of the tenth transistor P10 may be connected to a node electrically connecting the seventh transistor P7 and the eighth transistor P8 .

In addition, the second signal generator 412 may output a second gate signal through a node QB electrically connecting the ninth transistor P9 and the tenth transistor P10, where the second gate signal is Each of the 7th transistor P7 to 10th transistor P10 may have a high level or a low level according to a switching operation.

Meanwhile, the drain terminal of each of the seventh transistor P7 and the ninth transistor P9 is connected to the first voltage line, and the source terminal of the eighth transistor P8 is connected to the second voltage to which the low level voltage VGL is applied. It can be connected with a voltage line. Also, the eighth transistor P8 may be a diode-connected transistor.

The light emitting control signal generator 413 includes a third transistor P3 receiving a first gate signal, a fourth transistor P4 electrically connected to the third transistor P3 and receiving a second gate signal, and a gate terminal. A fifth transistor P5 electrically connected to a node Q electrically connecting the third transistor P3 and the fourth transistor P4 and electrically connected to the fifth transistor P5 and receiving a second gate signal It may include a sixth transistor (P6) to.

Specifically, the light emitting control signal generator 413 receives the first gate signal through the gate terminal of the third transistor P3, and receives the first gate signal through the gate terminals of the fourth and sixth transistors P4 and P6, respectively. A second gate signal may be received. In other words, the gate terminal of the third transistor P3 may be connected to the node A, and the gate terminals of the fourth and sixth transistors P4 and P6 may be connected to the node QB.

In addition, the emission control signal generator 413 may generate and output a target emission control signal EM[n] through a node electrically connecting the fifth transistor P5 and the sixth transistor P6, Here, the target emission control signal EM[n] has the same pulse width as the n−1 th emission control signal EM[n−1] according to the respective switching operations of the third to sixth transistors P3 to P6. and can be formed/output as a signal delayed by the line time.

For example, the emission control signal generator 413 may output the target emission control signal EM[n] to each pixel driving circuit connected to the n-th row line, and the pixel driving circuit may output the target emission control signal EM When [n]) is at a high level, light may be controlled not to be generated.

Meanwhile, source terminals of the third and fifth transistors P3 and P5 are connected to the second voltage line, and drain terminals of the fourth and sixth transistors P4 and P6 are connected to the first voltage line. can

According to one side, the emission control signal generator 413 includes a coupling capacitor (C) provided between the node Q and the n+1 th emission control line to which the n+1 th emission control signal EM[n+1] is applied. ), and the coupling capacitor C increases the voltage of the node Q through capacitive coupling so that the level of the target emission control signal EM[n] is reduced to a low level voltage (VGL).

Hereinafter, the operation process of the signal generating apparatus according to the first embodiment will be described through timing diagrams shown at reference numerals 420 and 430 .

When the signal generating device according to the second embodiment generates a target emission control signal EM[n] having a pulse width of an even number of times the line time, node A is at a high level in section (1) of reference numeral 420. and since the node QB is maintained at the low level, the node Q and the target emission control signal EM[n] may be maintained at the high level.

In period (2) of reference numeral 420, node A starts to become low level according to the second clock (CLKB), and node Q is one line time later than the n-1 th emission control signal (EM[n-1]). becomes low level, and when the next n+1th emission control signal (EM[n+1]) goes up to low level, the node Q drops to a lower voltage due to the coupling operation through the coupling capacitor. In period (2), since the fifth transistor N5 is turned on, a low level target emission control signal EM[n] may be output.

In section (3) of reference numeral 420, since the enable clock (CLKE) has the same waveform as the second clock (CLKB), after the n-1th emission control signal (EM[n-1]) increases to a high level, The node QB drops to a low level after one line time, which causes the node Q and the target emission control signal EM[n] to rise to a high level after one line time, and through this, the second embodiment The signal generating device according to the present invention may output a target emission control signal EM[n] delayed by one line time compared to the n−1 th emission control signal EM[n−1].

In the case of generating the target emission control signal EM[n] having a pulse width of an odd multiple of the line time, the signal generating device according to the second embodiment may operate according to the timing diagram of reference numeral 430, where The operation process according to reference numeral 430 is the same as the operation process described above through reference numeral 420 except that the enable clock CLKE and the first clock CLK are the same clock, so the contents described through reference numeral 420 A description overlapping with the above will be omitted.

5 is a diagram illustrating a signal generation method according to an embodiment.

In other words, FIG. 5 is a view for explaining an operation method of the signal generating device according to the embodiment described through FIGS. 2 to 4C, and among the contents described through FIG. 2 to FIG. 4C below, A description overlapping with the above will be omitted.

Referring to FIG. 5, in step 510, the signal generation method according to the embodiment includes a first signal generator, a first clock, a second clock having a phase opposite to the first clock, and an n−1 (where n is a positive integer) an n-1th light emission control signal applied through the light emission control line may be received.

Next, in step 520, the signal generating method according to the embodiment may generate a first gate signal based on the first clock, the second clock, and the n−1 th light emission control signal in the first signal generating unit. .

Next, in step 530, the signal generation method according to the embodiment generates the same pulse width and phase as the n-1 th light emission control signal and any one of the first clock and the second clock in the second signal generator. can receive an enable clock having Here, step 530 of the signal generation method according to an embodiment may be performed at the same time as step 510 .

Next, in step 540, the second signal generator may generate a second gate signal based on the n−1 th light emission control signal and the enable clock.

Next, in step 550, the emission control signal generation unit generates a target emission control signal applied through the n-th emission control line based on the first gate signal and the second gate signal. can

According to one side, the target light emission control signal has the same pulse width as the n-1th light emission control signal, and in contrast to the n-1th light emission control signal, at least one of the first clock, the second clock, and the enable clock. It may be a signal delayed by the line time corresponding to the pulse width of the clock.

As a result, using the present invention, it is possible to generate an emission control signal having a pulse width of an arbitrary multiple regardless of whether the line time is an odd or even multiple.

In addition, if the present invention is used, a light emission control signal having a pulse width of an arbitrary multiple can be generated with a smaller number of transistors compared to the conventional technology.

As described above, although the embodiments have been described with limited drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in a different order than the described method, and/or the described devices, structures, devices, circuits, etc., may be combined or combined in a different form than the described method, or other components Or even if it is replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

200: signal generating device 210: first signal generating unit
220: second signal generator 230: emission control signal generator

Claims (11)

Receiving a first clock, a second clock having a phase opposite to the first clock, and an n-1 th light emission control signal applied through an n-1 th light emission control line (where n is a positive integer); a first signal generator configured to generate a first gate signal based on the first clock, the second clock, and the n−1 th light emission control signal;
An enable clock having the same pulse width and phase as the n-1 th light emission control signal and one of the first clock and the second clock is received, and the n-1 th light emission control signal and the phosphor a second signal generator configured to generate a second gate signal based on an enable clock; and
An emission control signal generator configured to generate a target emission control signal applied through an nth emission control line based on the first gate signal and the second gate signal.
A signal generating device comprising a. According to claim 1,
The target emission control signal,
The pulse width of at least one of the first clock, the second clock, and the enable clock has the same pulse width as the n-1 th light emission control signal and is comparable to the n-1 th light emission control signal. A signal delayed by the line time corresponding to
signal generator. According to claim 1,
The first signal generator,
a first transistor receiving the second clock and the n−1 th light emission control signal; and
A second transistor electrically connected to the first transistor and receiving the first clock
A signal generating device comprising a. According to claim 3,
The first signal generator,
Receiving the n−1 th light emission control signal through the gate terminal of the first transistor and receiving the first clock through the gate terminal of the second transistor
signal generator. According to claim 1,
The second signal generator,
a seventh transistor to receive the n−1 th light emission control signal;
an eighth transistor electrically connected to the seventh transistor;
a ninth transistor receiving the n−1 th light emission control signal; and
A tenth transistor electrically connected to the ninth transistor and receiving the enable clock
A signal generating device comprising a. According to claim 5,
The second signal generator,
Receiving the n−1 th light emission control signal through gate terminals of the seventh transistor and the eighth transistor, respectively
signal generator. According to claim 5,
The second signal generator,
A gate terminal of the tenth transistor is connected to a node electrically connecting the seventh transistor and the eighth transistor.
signal generator. According to claim 1,
The emission control signal generator,
a third transistor receiving the first gate signal;
a fourth transistor electrically connected to the third transistor and receiving the second gate signal;
A fifth transistor having a gate terminal electrically connected to a node electrically connecting the third transistor and the fourth transistor; and
A sixth transistor electrically connected to the fifth transistor and receiving the second gate signal.
signal generator. According to claim 8,
The emission control signal generator,
Receiving the first gate signal through a gate terminal of the third transistor, and receiving the second gate signal through gate terminals of each of the fourth and sixth transistors
signal generator. According to claim 8,
The emission control signal generator,
a coupling capacitor provided between a node electrically connecting the third transistor and the fourth transistor and an n+1 th light emitting control line;
Signal generating device further comprising a. In the first signal generator, the n-1th light emission is applied through a first clock, a second clock having a phase opposite to the first clock, and an n-1th (where n is a positive integer) emission control line. receiving a control signal;
generating, by the first signal generator, a first gate signal based on the first clock, the second clock, and the n−1 th light emission control signal;
receiving, by a second signal generator, an enable clock having the same pulse width and phase as the n−1 th light emission control signal and one of the first clock and the second clock;
generating, by the second signal generator, a second gate signal based on the n-1 th light emission control signal and the enable clock; and
Generating, in a light emitting control signal generator, a target light emitting control signal applied through an nth light emitting control line based on the first gate signal and the second gate signal;
Signal generation method comprising a.

Images