KR20210040727A - Display device and driving method thereof - Google Patents

Abstract

A display device and a driving method thereof are disclosed. This display device sequentially generates a pulse of a first scan signal, a pulse of a second scan signal, and a pulse of a third scan signal within a pulse duration time of a shared EM signal and simultaneously initializes pixels of at least two pixel lines which share the shared EM signal at a pulse timing of any one of the scan signals.

Description

Display device and its driving method {DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to a display device for real-time variable initialization voltage of pixels and a driving method thereof.

Electroluminescent displays are roughly classified into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. An organic light emitting diode display of an active matrix type includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has a high response speed and high luminous efficiency, luminance, and viewing angle. There is an advantage. In an organic light-emitting display device, a light-emitting diode device (referred to as an Organic Light Emitting Diode, OLED") is formed on each of the pixels. The organic light-emitting display device has a fast response speed and excellent luminous efficiency, luminance, and viewing angle. Since gradations can be expressed in full black, the contrast ratio and color reproduction rate are excellent.

The organic light emitting display device does not require a backlight unit, and may be implemented on a plastic substrate, a thin glass substrate, or a metal substrate, which is a flexible material. Therefore, the flexible display can be implemented as an organic light emitting display device.

Pixels of an organic light emitting diode display include an OLED, a driving element that drives the OLED by controlling a current flowing through the OLED according to the gate-source voltage (Vgs), and a storage capacitor that maintains the gate voltage of the driving element.

The driving element may be implemented as a transistor. In order to make the image quality of the entire screen of the OLED display uniform, the driving element must have uniform electrical characteristics among all pixels. However, due to process variation and device characteristic variation caused in the manufacturing process of the display panel, there may be a difference in electrical characteristics of the driving element between pixels, and this difference may increase as the driving time of the pixels elapses. In order to compensate for variations in electrical characteristics of the driving element between pixels, an internal compensation technology and/or an external compensation technology may be applied to the OLED display.

In the internal compensation technology, a threshold voltage of a driving element is sensed for each sub-pixel using an internal compensation circuit embedded in each of the pixels, and the data voltage is compensated by the threshold voltage. The external compensation technology uses an external compensation circuit to sense a current or voltage of a driving element that changes according to electrical characteristics of the driving elements in real time. The external compensation technology modulates pixel data (digital data) of an input image as much as the electrical characteristic variation (or change) of the driving element sensed for each pixel, thereby compensating the electrical characteristic variation (or change) of the driving element in each of the pixels in real time.

In an organic light emitting diode display, luminance deviation may occur between pixels according to a structure of a display panel or a driving method. For example, luminance deviation may occur between pixel lines.

It is an object of the present invention to solve the aforementioned necessities and/or problems.

The present invention provides a display device capable of reducing luminance deviation between pixels and a driving method thereof.

The subject of the present invention is not limited to the problems mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

The display device of the present invention comprises: a data line to which a data voltage is applied; A shared EM line to which a shared EM signal is applied; A first scan line to which a first scan signal is applied; A second scan line to which a second scan signal generated subsequent to the first scan signal is applied; A third scan line to which a third scan signal generated subsequent to the second scan signal is applied; A first pixel circuit connected to the data line, the shared EM line, the first scan line, and the second scan line; And a second pixel circuit connected to the data line, the shared EM line, the second scan line, and the third scan line.

Each of the first and second pixel circuits includes a driving element including a gate connected to a capacitor; A light-emitting element that emits light by a current flowing through the driving element; And an initialization switch for applying a predetermined initialization voltage to the anode of the light emitting device in response to any one of the scan signals.

A pulse of the first scan signal, a pulse of the second scan signal, and a pulse of the third scan signal are generated within the pulse duration of the shared EM signal.

The same scan signal is applied to gates of the initialization switch of the first and second pixel circuits, so that the initialization voltage is simultaneously applied to the light emitting devices of the first and second pixel circuits.

The method of driving the display device includes generating a shared EM signal; Sequentially generating a pulse of a first scan signal, a pulse of a second scan signal, and a pulse of a third scan signal within the pulse duration of the shared EM signal; And simultaneously initializing pixels of at least two pixel lines sharing the shared EM signal at a pulse timing of any one of the pulse of the first scan signal, the pulse of the second scan signal, and the pulse of the third scan signal. Includes.

According to the present invention, the number of output channels of the gate driver can be reduced by connecting the gate signal lines to neighboring pixel lines so that the gate signal lines to which the gate signal is applied are shared with the neighboring pixel lines.

The present invention minimizes luminance deviation between pixels due to a difference in initialization timing between neighboring pixel lines by connecting a gate of a switch device for initializing a node connected to an anode of a light emitting device in adjacent pixel lines to the same scan line. It can be done, and luminance uniformity can be improved in low gradations.

According to the present invention, the luminance of the light emitting device is reduced in the initialization step, so that the luminance of the black gray scale may be lowered.

The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram showing a display device according to an exemplary embodiment of the present invention.
2 is a diagram illustrating an example of arrangement of pentile pixels.
3 is a diagram showing an example of real pixel arrangement.
4 is a block diagram showing the configuration of the drive IC shown in FIG. 1.
5 is a diagram schematically showing a pixel circuit of the present invention.
6 is a circuit diagram showing a pixel circuit including an internal compensation circuit.
7A to 9B are diagrams showing the operation of the pixel circuit shown in FIG. 6 step by step.
10 is a diagram illustrating an example in which gate signal lines are shared between neighboring pixel lines.
11A to 12B are diagrams illustrating an initialization step of neighboring pixels in a display device in which gate signal lines are shared between neighboring pixel lines.
13A and 13B are diagrams illustrating parasitic capacitance between a third gate line and a fourth node in pixel circuits of neighboring pixel lines to which gate signal lines are shared.
14A and 14B are diagrams showing a gate signal and a fourth node voltage in pixel circuits of neighboring pixel lines in which gate signal lines are shared.
15A and 15B are diagrams illustrating a current flowing through a light emitting device in pixel circuits of neighboring pixel lines in which gate signal lines are shared.
16A to 20B are diagrams illustrating pixel circuits and a driving method of the display device according to the first exemplary embodiment of the present invention.
21A and 21B are flowcharts illustrating a method of initializing pixel circuits of neighboring pixel lines to which gate signal lines are shared in the display device according to the first exemplary embodiment of the present invention.
22A and 22B are simulation results diagrams showing effects of the display device according to the first exemplary embodiment of the present invention.
23 is a diagram illustrating an example in which gate signal lines are shared between neighboring pixel lines in the display device according to the second exemplary embodiment of the present invention.
24A to 25C are diagrams illustrating pixel circuits and a driving method of the display device according to the second exemplary embodiment of the present invention.
26 is a diagram illustrating an example in which gate signal lines are shared between neighboring pixel lines in the display device according to the third embodiment of the present invention.
27A to 27D are diagrams showing pixel circuits and a driving method of the display device according to the third exemplary embodiment of the present invention.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the present embodiments are intended to complete the disclosure of the present invention, and common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. The same reference numerals refer to the same elements throughout the specification. In addition, in describing the present invention, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When'include','have','consists of' and the like mentioned in the present specification are used, other parts may be added unless'only' is used. In the case of expressing the constituent elements in the singular, it includes the case of including the plural unless specifically stated otherwise.

In interpreting the constituent elements, it is interpreted as including an error range even if there is no explicit description.

In the case of a description of the positional relationship, for example, if the positional relationship of the two parts is described as'on the top','on the top of the ~','the bottom of the','the next to the', etc.,'right' Or, unless'direct' is used, one or more other parts may be located between the two parts.

In the description of the embodiments, first, second, and the like are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be a second component within the technical idea of the present invention.

The same reference numerals refer to the same elements throughout the specification.

Features of the various embodiments may be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

In the display device of the present invention, the pixel circuit and the gate driver may include a plurality of transistors. Transistors may be implemented as an oxide TFT (Thin Film Transistor) including an oxide semiconductor, an LTPS TFT including a Low Temperature Poly Silicon (LTPS), or the like. Each of the transistors may be implemented as a p-channel MOSFET (metal-oxide-semiconductor field effect transistor) or a transistor having an n-channel MOSFET structure. In the embodiment, the transistors of the pixel circuit are described based on an example in which the transistors are implemented as p-channel transistors, but the present invention is not limited thereto.

The transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit from the transistor. In the transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In the n-channel transistor, the direction of current flows from the drain to the source. In the case of the p-channel transistor PMOS, since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may be changed according to the applied voltage. Therefore, the invention is not limited due to the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal swings between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, while it is turned off in response to the gate-off voltage. In the case of an n-channel transistor, a gate-on voltage may be a gate high voltage (VGH), and a gate-off voltage may be a gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be the gate low voltage VGL, and the gate-off voltage may be the gate high voltage VGH.

In the following embodiments, the pixel circuit will be described centering on an example implemented with p-channel transistors, but the present invention is not limited thereto. In an embodiment, "VGL" is a gate-on voltage of a scan signal, "VGH" is a gate-off voltage of a scan signal, "VEL" is a light emission control signal (hereinafter referred to as "EM signal"), and "VEH" is an EM signal. Denotes the gate-off voltage of each.

Each of the pixels of the present invention senses a threshold voltage of the driving element in a sensing step defined by a light-emitting element, a driving element that controls a current flowing through the light-emitting element according to a voltage between a gate and a source, and a pulse of the scan signal. It includes an internal compensation circuit to supply to the capacitor. The internal compensation circuit includes a capacitor connected to the gate of the driving element, and one or more switch elements connecting the capacitor, the driving element, and the light emitting element. The internal compensation circuit may include the capacitor shown in FIG. 6 and a plurality of switch elements.

The display device of the present invention includes a driving device for driving pixels. The driving device may limit the maximum luminance of pixel data by receiving a brightness value DBV input from the outside and changing the data voltage and the low potential power supply voltage ELVSS according to the brightness value. The driving device may change the initialization voltage Vini in real time based on one or more of a low-potential power supply voltage ELVSS that varies according to a gray level of pixel data and a brightness value, and a threshold value of a driving element of the pixels. The drive device is described as the drive IC 300 in the following embodiment.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 4, the display device of the present invention includes a display panel 100 and display panel driving units 120 and 300.

The display panel driving units 120 and 300 write pixel data of an input image to pixels of a screen to display an image on the screen. The display panel drivers 120 and 300 provide a gate driver 120 that supplies a gate signal to the gate lines GL1 to GL2 of the display panel 100, and the pixel data is referred to as a voltage of a data signal (hereinafter, referred to as a "data voltage"). A data driving unit 306 that converts the data to data lines and supplies them to data lines through data output channels, and a timing controller 303 that controls operation timings of the data driving unit 306 and the gate driving unit 120. The data driver 306 and the timing controller 303 may be integrated in a drive integrated circuit (IC) 300.

The screen of the display panel 100 is a pixel in which data lines DL1 to DL6, gate lines GL1 and GL2 crossing the data lines DL1 to DL6, and pixels P are arranged in a matrix form. It includes an array (AA). The pixels P are disposed in the pixel array AA in a matrix form defined by the data lines DL1 to DL6 and the gate lines GL1 and GL2. The pixels P display an image by applying a pixel data voltage.

Each of the pixels P includes sub-pixels having different colors for color implementation. The sub-pixels include red (Red, hereinafter referred to as “R sub-pixel”), green (Green, hereinafter referred to as “G sub-pixel”), and blue (blue, hereinafter referred to as “B sub-pixel”). Although not shown, a white sub-pixel may be further included. Hereinafter, the pixel can be interpreted as a sub-pixel.

Each of the sub-pixels may include an internal compensation circuit that senses an electrical characteristic of a driving element, for example, a threshold voltage, to compensate for a gate voltage of the driving element.

The pixels P may be arranged as a real color pixel and a pentile pixel. The pentile pixel uses a preset pentile pixel rendering algorithm to drive two sub-pixels of different colors as one pixel P as shown in FIG. 2 to achieve a higher resolution than a real color pixel. Can be implemented. The pentile pixel rendering algorithm compensates for insufficient color expression in each of the pixels P with the color of light emitted from adjacent pixels.

In the case of a real color pixel, one pixel P is composed of R, G, and B subpixels as shown in FIG. 3.

When the resolution of the pixel array AA is n*m, the pixel array AA includes n pixel columns and m pixel lines crossing the pixel column. 2 and 3, #1 and #2 denote pixel line numbers. The pixel column includes pixels arranged along the Y-axis direction. The pixel line includes pixels arranged along the X-axis direction. One horizontal period 1H is a time obtained by dividing one frame period by the number of m pixel lines. The gate driver 120 may sequentially output the gate signal from the first pixel line to the m-th pixel line to perform progressive scan of the pixels line by line. Pixels of one pixel line may operate through initialization, sensing, and data writing within one horizontal period 1H.

The pixel array AA of the display panel 100 may be formed on a glass substrate, a metal substrate, or a plastic substrate. In the case of a plastic OLED panel, a pixel array (AA) is formed on a plastic substrate to be implemented as a flexible panel. The plastic OLED panel includes a pixel array (AA) on an organic thin film bonded on a back plate. A touch sensor array may be formed on the pixel array AA.

The back plate may be a polyethylene terephthalate (PET) substrate. An organic thin film is formed on the back plate. A pixel array AA and a touch sensor array may be formed on the organic thin film. The back plate blocks moisture permeation toward the organic thin film so that the pixel array AA is not exposed to humidity. The organic thin film may be a thin PI (Polyimide) film substrate. A multi-layered buffer layer may be formed of an insulating material (not shown) on the organic thin film. Wires for supplying power or signals applied to the pixel array AA and the touch sensor array may be formed on the organic thin film.

The gate driver 120 may be mounted together with the pixel array AA on the substrate of the display panel 100. The gate driver 120 formed directly on the substrate of the display panel 100 is known as a gate in panel (GIP) circuit.

The gate driver 120 may be disposed on one of the left and right bezels of the display panel 100 to supply a gate signal to the gate lines GL1 and GL2 in a single feeding method. In the case of the single feeding method, one of the two gate driving units 120 in FIG. 1 is not required.

The gate driver 120 may be disposed on each of the left and right bezels of the display panel 100 to supply a gate signal to the gate lines GL1 and GL2 in a double feeding method. In the case of the double feeding method, gate signals may be simultaneously applied at both ends of one gate line.

The gate driver 120 is driven according to the gate timing signal supplied from the drive IC 300 using a shift register to supply the gate signals GATE1 and GATE2 to the gate lines GL1 and GL2. The shift register may sequentially supply the gate signals GATE1 and GATE2 to the gate lines GL1 and GL2 by shifting the gate signals GATE1 and GATE2. The gate signals GATE1 and GATE2 may include scan signals [SCAN(N-1), SCAN(N)], EM signals [EM(N)] and the like shown in FIGS. 6 and 7.

The drive IC 300 may output a gate timing signal for controlling the gate driver 120 through gate timing signal output channels. The gate timing signal may include a start signal input to the shift register and a shift clock. The drive IC 300 is connected to the data lines DL1 to DL6 through data output channels to supply the data voltage Vdata to the data lines DL1 to DL6.

The drive IC 300 may be connected to the host system 200, the first memory 301, and the display panel 100 as shown in FIG. 4. The drive IC 300 may include a data operation unit 308, a timing controller 303, and a data driver 306. The drive IC 300 may further include a second memory 302, a gamma compensation voltage generator 305, a power supply unit 304, a level shifter 307, and the like.

The timing controller 303 provides pixel data PDATA of an input image received from the host system 200 to the data driver 306. The timing controller 303 generates a gate timing signal for controlling the gate driver 120 and a source timing signal for controlling the data driver 306 to control the operation timing of the gate driver 120 and the data driver 306. Can be controlled.

The drive IC 300 may generate gate timing signals for driving the gate driver 120 through the timing controller 303 and the level shifter 307. The gate timing signal includes a gate timing signal such as a start pulse (VST) and a shift clock (GCLK), and a gate voltage such as a gate-on voltage (VGL) and a gate-off voltage (VGH). The start pulse VST and the shift clock GCLK swing between the gate-on voltage VGL and the gate-off voltage VGH.

The data operation unit 308 includes a receiving unit for receiving pixel data input as a digital signal from the host system 200, and a data operation unit for improving image quality by modulating pixel data input through the receiving unit using a preset image quality algorithm. The data operation unit 308 is a data restoration unit that decodes and restores compressed pixel data, an optical compensation unit that adds a preset optical compensation value to the pixel data, and calculates an average image level (APL) of the input image to obtain luminance. And a luminance adjustment unit that controls power consumption and the like. The optical compensation value may be set as a value for correcting the luminance of each pixel data based on the luminance of the screen measured based on the camera image captured in the manufacturing process.

The data driver 306 converts the pixel data (digital signal) received from the timing controller 303 into a gamma compensation voltage using a digital to analog converter (hereinafter referred to as “DAC”) to convert the data voltage ( Vdata). The data voltage Vdata output from the data driver 306 is supplied to the data lines DL1 to DL6 of the pixel array AA through an output buffer connected to the data channel of the drive IC 300.

The gamma compensation voltage generator 305 distributes the gamma reference voltage from the power supply unit 304 through a divider circuit to generate a gamma compensation voltage for each gray level. The gamma compensation voltage is an analog voltage in which a voltage is set for each gray level of pixel data. The gamma compensation voltage output from the gamma compensation voltage generator 305 is provided to the data driver 306.

The level shifter 307 converts a low level voltage of the gate timing signal received from the timing controller 303 into a gate-on voltage VGL, and converts a high level voltage of the gate timing signal. It converts to a gate-off voltage (VGH). The level shifter 307 outputs the gate timing signal and the gate voltages VGH and VGL through the gate timing signal output channels and supplies them to the gate driver 120.

The power supply unit 304 generates power required for driving the pixel array AA of the display panel 100, the gate driver 120, and the drive IC 300 using a DC-DC converter. . The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply unit 304 adjusts the DC input voltage from the host system 200 to provide a gamma reference voltage and a gate-on voltage (VGL). DC power such as a gate-off voltage VGH, a pixel driving voltage ELVDD, a low-potential power voltage ELVSS, and an initialization voltage Vini may be generated.

The gamma reference voltage is supplied to the gamma compensation voltage generator 305. The gate-on voltage VGL and the gate-off voltage VGH are supplied to the level shifter 307 and the gate driver 120. Pixel power, such as the pixel driving voltage ELVDD, the low-potential power voltage ELVSS, and the initialization voltage Vini, is commonly supplied to the pixels P.

The gate voltage may be set as VGH = 15V, VEH = 13V, VGL = -6V, and VEL = -6V, but is not limited thereto. The pixel power may be set to ELVDD = 13V and ELVSS = 0V, but is not limited thereto. The voltage range of the data voltage Vdata determined by the gamma reference voltage may be Vdata = 0 to 5V, but is not limited thereto. The initialization voltage Vini is set to a DC voltage lower than the data voltage Vdata and lower than the threshold voltage of the light emitting element EL to suppress the light emission of the light emitting element EL and initialize main nodes of the pixels.

The second memory 302 stores a compensation value, register setting data, and the like received from the first memory 301 when power is supplied to the drive IC 300. The compensation value can be applied to various algorithms with improved image quality. The compensation value may include an optical compensation value.

The register setting data defines the operation and waveform timing of the data driver 306, the timing controller 303, the gamma compensation voltage generator 305, and the power supply unit 34, the output voltage level of the power supply unit 34, and the like. The first memory 301 may include a flash memory. The second memory 302 may include static RAM (SRAM).

The host system 200 may be any one of a TV (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile system, and a wearable system.

In a mobile system, the host system 200 may be implemented as an application processor (AP). In a mobile system, the host system 200 may transmit pixel data of an input image to the drive IC 300 through a Mobile Industry Processor Interface (MIPI). The host system 200 may be connected to the drive IC 300 through a flexible printed circuit, for example, a flexible printed circuit (FPC) 310.

5 is a diagram schematically showing a pixel circuit of the present invention.

Referring to FIG. 5, the pixel circuit may include first to third circuit parts 10, 20, and 30 and first to third connection parts 12, 23, and 13. One or more components may be omitted or added in this pixel circuit.

The first circuit unit 10 supplies the pixel driving voltage ELVDD to the driving element DT. The driving element DT may be implemented as a transistor including a gate DRG, a source DRS, and a drain DRD. The second circuit unit 20 charges the capacitor Cst connected to the gate DRG of the driving element DT and maintains the voltage of the capacitor Cst for one frame period. The third circuit unit 30 converts the current into light by providing the current supplied from the pixel driving voltage ELVDD to the light emitting device EL through the driving device DT.

The third circuit unit 30 may be connected to a sensing unit that senses a change in an electrical characteristic or a threshold voltage of the driving element DT in real time.

The first connection part 12 connects the first circuit part 10 and the second circuit part 20 to each other. The second connection part 23 connects the second circuit part 20 and the third circuit part 30 to each other. The third connection part 13 connects the third circuit part 30 and the first circuit part 10 to each other. Each of the first connection part 12, the second connection part 23, and the third connection part 13 may include one or more transistors and wires.

The internal compensation circuit may be connected to the circuit units 10, 20, and 30 and the connection units 12, 23 and 13.

The pixel circuit may be implemented as a pixel circuit including an internal compensation circuit as shown in FIG. 6. The internal compensation circuit illustrated in FIG. 6 may operate by being divided into an initialization step (Ti), a sensing step (Ts), and a light emitting step (Tem).

The pixel circuit illustrated in FIG. 6 exemplifies an arbitrary sub-pixel circuit belonging to an Nth (N is a natural number) pixel line. The pixel circuit includes an internal compensation circuit that senses the threshold voltage Vth of the driving element DT and compensates the gate voltage of the driving element DT by the threshold voltage Vth.

As shown in FIG. 6, the display panel 100 includes a first power line VDDL for supplying the pixel driving voltage ELVDD to the pixels P and the low potential power voltage ELVSS to the pixels P. A second power line VSSL to be supplied to and a third power line INIL for supplying the initialization voltage Vini to the pixels P may be further included.

Referring to FIG. 6, the pixel circuit includes a light emitting element EL, a plurality of transistors T11 to T16 and DT, a capacitor Cst, and the like.

The transistors T11 to T16 and DT may be implemented as p-channel transistors. The transistors T11 to T16 and DT may be divided into switch elements T11 to T16 and a driving element DT.

Gate signals such as an N-1th scan signal [SCAN(N-1)], an Nth scan signal [SCAN(N)], and an EM signal [EM(N)] may be applied to the pixel circuit. The pulse of the N-1th scan signal [SCAN(N-1)] is synchronized with the data voltage Vdata of the N-1th pixel line. The pulse of the Nth scan signal [SCAN(N)] is synchronized with the data voltage Vdata of the Nth pixel line. The pulse of the Nth scan signal [SCAN(N)] is generated with the same pulse width as the N-1th scan signal SCAN(N-1), and the pulse of the N-1th scan signal [SCAN(N-1)] It occurs later than the pulse. The pulse width of the scan signals [SCAN(N-1), SCAN(N)] may be set to one horizontal period (1H).

The capacitor Cst is connected between the first node n11 and the second node n12. The pixel driving voltage ELVDD is supplied to the pixels P through the first power line VDDL. The first node n11 is connected to the first power line VDDL, the first electrode of the third switch element T13, and the first electrode of the capacitor Cst.

The second node n12 is connected to the second electrode of the capacitor Cst, the gate of the driving element DT, the first electrode of the first switch element T11, and the first electrode of the fifth switch element T15. do.

The first switch element T11 is turned on according to the gate-on voltage VGL of the N-th scan signal SCAN(N) to connect the gate of the driving element DT and the second electrode. The first switch element T11 includes a gate connected to the second gate line SN, a first electrode connected to the second node n12, and a second electrode connected to the third node n13. The third node n13 is connected to the second electrode of the driving element DT, the second electrode of the first switch element T11, and the first electrode of the fourth switch element T14. The Nth scan signal SCAN(N) is supplied to the pixels P through the second gate line SN.

The first switch element T11 is turned on only for one horizontal period 1H in which the Nth scan signal [SCAN(N)] is generated as the gate-on voltage VGL in one frame period, and then during one frame period. Stay off. Accordingly, the first switch element T11 may be implemented as a transistor having a dual gate structure capable of reducing leakage current as illustrated in FIG. 6, but is not limited thereto.

The second switch element T12 is turned on according to the gate-on voltage VGL of the Nth scan signal SCAN(N) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switch element T12 includes a gate connected to the second gate line SN, a first electrode connected to the fifth node n15, and a second electrode connected to the data line 131. The fifth node n15 is connected to the first electrode of the driving element DT, the first electrode of the second switch element T12, and the second electrode of the third switch element T13.

The third switch element T13 supplies the pixel driving voltage ELVDD to the first electrode of the driving element DT in response to the EM signal EM(N). The EM signal [EM(N)] is supplied to the pixels P through the third gate line EML. The third switch element T13 includes a gate connected to the third gate line EML, a first electrode connected to the first power line VDDL via the first node n11, and the fifth node n15. And a second electrode.

The fourth switch element T14 is turned on according to the gate-on voltage VEL of the EM signal [EM(N)] to connect the second electrode of the driving element DT to the anode of the light emitting element EL. The gate of the fourth switch element T14 is connected to the third gate line EML. The first electrode of the fourth switch element T14 is connected to the second electrode of the driving element DT via a third node n13, and the second electrode of the fourth switch element T14 is a fourth node ( It is connected to the anode of the light-emitting element EL via n14). The fourth node n14 is connected to the anode of the light emitting element EL, the second electrode of the fourth switch element T14, and the second electrode of the sixth switch element T16.

The fifth switch element T15 is turned on according to the gate-on voltage VEL of the N-1th scan signal [SCAN(N-1)] to connect the second node n12 to the third power line INIL. By connecting, the capacitor Cst and the gate of the driving element DT are initialized during the initialization step Ti. The N-1th scan signal SCAN(N-1) is supplied to the pixels P through the first gate line SN-1. The initialization voltage Vini is supplied to the pixels P through the third power line INIL. The fifth switch element T15 includes a gate connected to the first gate line SN-1 to which the N-1th scan signal [SCAN(N-1)] is applied, a first electrode connected to the second node n12, And a second electrode connected to the third power line INIL.

The fifth switch element T15 may be implemented as a transistor having a dual gate structure capable of reducing leakage current because the off period is long, but is not limited thereto.

The sixth switch element T16 is turned on according to the gate-on voltage VGL of the N-th scan signal [SCAN(N)] to connect the third power line INIL to the light emitting element EL in the sensing step Ts. Connect to the anode of. During the sensing step Ts, the anode voltage of the light emitting element EL is the initialization voltage Vini. In the sensing step Ts, the light emitting element EL does not emit light because the voltage between the anode and the cathode is less than its threshold voltage. The sixth switch element T16 includes a gate connected to the second gate line SN, a first electrode connected to the third power line INIL, and a second electrode connected to the fourth node n14.

The driving element DT drives the light emitting element EL by controlling the current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the second node n12, a first electrode connected to the fifth node n15, and a second electrode connected to the third node n13.

The internal compensation circuit operation of the pixel circuit is an initialization step (Ti) in which main nodes of the pixel circuit are initialized, a sensing step in which a threshold voltage of the driving element DT is sensed and the gate voltage of the driving element DT is compensated by this threshold voltage. (Ts) and a current flowing according to the gate-source voltage Vgs of the driving device DT may be divided into a light emitting step Tem in which the light emitting device EL emits light.

7A to 9B are diagrams showing the operation of the pixel circuit shown in FIG. 6 step by step. 7A is a diagram illustrating a current path flowing through a pixel circuit in an initialization step (Ti). 8A is a diagram illustrating a current path flowing through a pixel circuit in a sensing step Ts. The sensing step Ts may be interpreted as a programming step or a data writing step. 9A is a diagram illustrating a current path flowing through a pixel circuit during a light emission step Tem. The light emission step Tem may be interpreted as a display driving step. 7B, 8B, and 9B are waveform diagrams showing a gate signal applied to the pixel circuit shown in FIG. 6.

7A and 7B, the voltage of the N-1 th scan signal SCAN(N-1) in the initialization step Ti is the gate-on voltage VGL. The fifth switch element T15 is turned on in the initialization step Ti so that the voltage of the second node n12 is discharged to the initialization voltage Vini. As a result, in the initialization step Ti, the capacitor Cst and the gate voltage of the driving element DT are initialized to the initialization voltage Vini.

8A and 8B, the voltage of the Nth scan signal [SCAN(N)] in the sensing step Ts is the gate-on voltage VGL. The first, second, and sixth switch elements T11, T12, and T16 are turned on in the sensing step Ts. At this time, the data voltage Vdata is applied to the second node n12, and the voltage of the second node n12 changes from Vini to Vdata-|Vth|. The data voltage Vdata compensated by the threshold voltage Vth of the driving element DT sensed in the sensing step Ts is charged in the capacitor Cst and applied to the gate of the driving element DT. Therefore, even if there is a variation in the threshold voltage Vth of the driving element DT or a change in the threshold voltage Vth between pixels, the gate voltage of the driving element DT can be compensated by the threshold voltage Vth. have.

9A and 9B, the voltage of the EM signal [EM(N)] is changed to the gate-on voltage VEL in the light emission step Tem. The third and fourth switch elements T13 and T14 are turned on in the light emission step Tem. During the light-emitting step Temp, current flows through the driving element DT through the light-emitting element EL, so that the light-emitting element EL may emit light.

The amount of current flowing through the light emitting element EL is adjusted according to the gate-source voltage Vgs of the driving element DT. The voltage Vgs between the gate and the source of the driving element DT is Vgs = Vdata-|Vth|-ELVDD during the light emission step Temp. In order to accurately express the low gradation luminance, the EM signal [EM(N)] is between the gate-on voltage (VEL) and the gate-off voltage (VEH) at a predetermined duty ratio during the light emission step (Tem) It can be transitioned.

In order to reduce the number of output channels of the gate driver 120, a method of sharing gate signal lines to which a gate signal is applied to neighboring pixel lines as shown in the example of FIG. 10 may be considered.

In the example of FIG. 10, (2N-1)th line is a 2N-1 pixel line, "(2N)th line" is a 2N pixel line, and "(2N+1)th line" is a 2N+1 pixel line. , "(2N+2)th line" denotes a 2N+2 pixel line, respectively.

Each of the gate signal lines EML, SN-2, SN-1, and SN is connected 1:1 to each of the output channels of the gate driver 120. In addition, each of the gate signal lines EML, SN-2, SN-1, and SN is divided into two and connected to two adjacent pixel lines.

The 2N-1th pixel line [(2N-1)th line] is a gate such as an N-2th scan line SN-2, an N-1th scan line SN-1, and a shared EM line EML. It is connected to the signal wires. The 2Nth pixel line [(2N)th line] is connected to gate signal lines such as the N-1th scan line SN-1, the Nth scan line SN, and the shared EM line EML. Accordingly, the shared EM line EML is connected to the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line [(2N)th line]. Also, the N-1th scan line SN-1 is shared with the 2N-1th pixel line [(2N-1)th line] and the 2Nth pixel line [(2N)th line]. The Nth scan line SN is shared with the 2Nth pixel line [(2N)th line] and the 2N+1th pixel line [(2N+1)th line].

In a display device in which gate signal lines are shared between neighboring pixel lines, a fourth node n14, that is, a light emitting element ( The turn-on timing of the initialization switch element T16 for initializing the anode of EL) may be changed. In this case, in the initialization step Ti, the voltage of the fourth node n14 increases, and a current flows through the light emitting element EL, so that a difference in luminance may be seen in neighboring pixel lines. This will be described in conjunction with FIGS. 11A to 15B.

11A to 12B are diagrams illustrating an initialization step of neighboring pixels in a display device in which gate signal lines are shared between neighboring pixel lines.

11A and 11B, the pulse of the shared EM signal EM may be generated for 3 horizontal periods or more. In the case of FIGS. 11A and 11B, the pulse of the shared EM signal is an example in which a pulse width of approximately 4 horizontal periods is generated within t1 to t5.

The pixels of the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line [(2N)th line] receive the shared EM signal EM. The pulse of the shared EM signal EM is generated as a gate-off voltage VEL. In the pulse duration of the shared EM signal EM, the pulse of the N-2th scan signal [SCAN(N-2)], the pulse of the N-1th scan signal [SCAN(N-1)], and A pulse of the Nth scan signal [SCAN(N)] is generated. The pulses of the scan signals [SCAN(N-2), SCAN(N-1), SCAN(N)] are generated as a gate-on voltage VGL, and are sequentially shifted by a shift register.

The shared EM signal (EM) is 4 horizontal periods, the shared EM signal (EM) is inverted to the gate-off voltage (VEH) at t1, maintains the gate-off voltage (VEH) during t2 to t4, and then the gate-on voltage ( VEL) can be generated as a pulse having a pulse width of approximately 4 horizontal periods. The N-2th scan signal [SCAN(N-2)] is inverted to the gate-on voltage VGL at t2 and is generated as a pulse having a pulse width of 1 horizontal period 1H. The N-1th scan signal [SCAN(N-1)] is inverted to the gate-on voltage VGL at t3 and is generated as a pulse having a pulse width of 1 horizontal period 1H. The Nth scan signal [SCAN(N)] is inverted to the gate-on voltage VGL at t4 and is generated as a pulse having a pulse width of one horizontal period (1H).

The initialization step Ti is different between the pixels of the 2N-1th pixel line [(2N-1)th line] and the 2N-1th pixel line [(2N)th line]. Hereinafter, the sixth switch element T16 for initializing the fourth node n14 in the initialization step Ti is referred to as "initialization switch element".

The pixels of the 2N-1th pixel line [(2N-1)th line] are the shared EM signal EM, the N-2th scan signal [SCAN(N-2)], and the Nth as shown in FIG. 11A. -1 Receive gate signal such as scan signal [SCAN(N-1)]. The initializing step (Ti) of these pixels is carried out at t3. The initialization switch elements T16-11 of the 2N-1th pixel line [(2N-1)th line] are turned in response to the pulse of the N-1th scan signal [SCAN(N-1)] input to t3. -Is turned on to initialize the fourth node (n14) to Vini.

The pixels of the 2Nth pixel line [(2N)th line] are as shown in FIG. 11B, the shared EM signal EM, the N-1th scan signal [SCAN(N-1)], and the Nth scan signal [SCAN It receives a gate signal such as (N)]. The initializing step (Ti) of these pixels is carried out at t4. The initialization switch elements T16-12 of the 2N-th pixel line [(2N)th line] are turned on in response to the pulse of the N-th scan signal [SCAN(N)] input to t4, and are turned on to the fourth node n14. ) To Vini.

12A and 12B, gates of the initialization switch elements T16-21 of the 2N-1th pixel line [(2N-1)th line] are connected to the N-2th scan line SN-2. I can. Gates of the initialization switch elements T16-22 of the 2Nth pixel line [(2N)th line] may be connected to the N-1th scan line SN-1. In this case, the initialization switch elements T16-21 and T16-22 may be turned on in response to a scan signal input first among scan signals sequentially input within the pulse duration of the shared EM signal EM.

The pixels of the 2N-1th pixel line [(2N-1)th line] are the shared EM signal EM, the N-2th scan signal [SCAN(N-2)], and the Nth as shown in FIG. 12A. -1 Receive gate signal such as scan signal [SCAN(N-1)]. The initializing step (Ti) of these pixels is carried out at t2. The initialization switch elements T16-21 of the 2N-1th pixel line [(2N-1)th line] are turned in response to the pulse of the N-2th scan signal [SCAN(N-2)] input to t2. -Is turned on to initialize the fourth node (n14) to Vini.

As shown in FIG. 12B, the pixels of the 2Nth pixel line [(2N)th line] are the shared EM signal EM, the N-1th scan signal [SCAN(N-1)], and the Nth scan signal [SCAN. It receives a gate signal such as (N)]. The initializing step (Ti) of these pixels is carried out at t3. The initialization switch elements T16-22 of the 2N-th pixel line [(2N)th line] are turned on in response to the pulse of the N-1th scan signal [SCAN(N-1)] input to t3. 4 Initialize node n14 to Vini.

A parasitic capacitance Cpar may exist between the shared EM line EML and the fourth node n14 as shown in FIGS. 13A and 13B. When the voltage of the shared EM signal EM rises to t1, the voltage Vini of the fourth node n14 increases due to the parasitic capacitance Cpar, thereby causing an increase in the anode voltage of the light emitting element EL. In this case, a current flows through the light emitting device OLED, so that weak light may be seen from the light emitting device OLED. In this case, the voltage of the fourth node n14 is simultaneously increased in neighboring pixel lines, but a difference in luminance between the pixel lines may be seen due to a time difference in the initialization step Ti.

14A and 14B are diagrams showing a gate signal and a fourth node voltage in pixel circuits of neighboring pixel lines in which gate signal lines are shared.

14A and 14B, when the voltage of the shared EM signal EM increases, referring to FIGS. 14A and 14B, the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line In the pixels of the [(2N1)th line], the voltage Vn14 of the fourth node n14 simultaneously increases due to the parasitic capacitance Cpar. Subsequently, in the pixels of the 2N-1 pixel line [(2N-1)th line], the voltage Vn14 of the fourth node n14 is equal to the pulse of the N-1th scan signal [SCAN(N-1)]. After being lowered when generated, the voltage Vn14 of the fourth node n14 in the pixels of the 2N pixel line [(2N)th line] is lowered when the pulse of the Nth scan signal [SCAN(N)] is generated. .

Due to the time difference in the initialization step Ti, the amount of charge accumulated at the fourth node n14 in the pixels of the 2N-1 pixel line [(2N-1)th line] is the 2N pixel line [(2N)th line]. ] More than the pixels. As a result, as shown in FIGS. 15A and 15B, the luminance of the 2N-1 pixel line [(2N-1)th line] is higher than that of the 2N-th pixel line [(2N)th line].

The present invention can reduce a difference in luminance between neighboring pixel lines and suppress an increase in luminance of a black gradation by simultaneously performing an initialization step of neighboring pixel lines shared by gate signal lines.

The 2N-1 pixel line [(2N-1)th line] may include a first pixel circuit, and the 2N-th pixel line [(2N)th line] may include a second pixel circuit. The first and second pixel circuits may be adjacent to each other up and down to share one data line DL. The first pixel circuit may be connected to a data line DL, a shared EM line to which a shared EM signal is applied, a first scan line to which a first scan signal is applied, and a second scan line to which a second scan signal is applied. The second pixel circuit may be connected to the data line DL, the shared EM line, the second scan line, and a third scan line to which a third scan signal is applied. In FIGS. 16A to 20B, the first scan signal may be interpreted as SCAN(N-2), the second scan signal may be interpreted as SCAN(N-1), and the third scan signal may be interpreted as SCAN(N).

A pulse of the first scan signal, a pulse of the second scan signal, and a pulse of the third scan signal may be generated within the pulse duration of the shared EM signal.

Each of the first and second pixel circuits includes a capacitor Cst connected between a first node n11 and a second node n12, a driving element DT including a gate connected to the second node n12, and It may include a light-emitting element EL that emits light by a current flowing through the driving element DT. When a pulse of the second scan signal is generated, anode voltages of the light emitting elements EL may be simultaneously initialized in the first and second pixel circuits.

The first and second pixel circuits have substantially the same circuit configuration, except that the connection relationship between the scan lines and the switch elements is different. For convenience, if the components of the first pixel circuit are divided into 1-X and the components of the second pixel circuit are divided into 2-X, the components of the first pixel circuit and the second pixel circuit can be arranged as follows.

The first pixel circuit includes a first electrode having a gate connected to the second scan line SN-1, a first electrode connected to the 1-2th node n12, and a second electrode connected to the 1-3th node n13. -1 switch element T11; 1-2 switch element T12 having a gate connected to the second scan line SN-1, a first electrode connected to the 1-5th node n15, and a second electrode connected to the data line DL ; A gate connected to the shared EM line EML, a first electrode connected to the 1-1 node n11 to apply a pixel driving voltage ELVDD, and a second electrode connected to the 1-5 node n15 A 1-3th switch element T13 having a; The gate connected to the shared EM line EML, the first electrode connected to the 1-3th node n13, and the second connected to the anode of the light emitting element of the first pixel circuit via the 1-4th node n14 A 1-4th switch element (n14) having an electrode; A 1-5 switch element having a gate connected to the first scan line SN-2, a first electrode connected to the 1-2 node n12, and a second electrode to which an initialization voltage Vini is applied ( T15); And a gate connected to the second scan line SN-1, a first electrode to which the initialization voltage Vini is applied, and a 1-6th switch element T16-31 connected to the 1-4th node n14. ). The capacitor Cst of the first pixel circuit is connected between the first-first node n11 and the first-second node n12.

The second pixel circuit has a gate connected to the third scan line SN, a first electrode connected to a node 2-2 (n12), and a second electrode connected to a node 2-3 (n13). -1 switch element T11; A 2-2 switch element T12 having a gate connected to the third scan line SN, a first electrode connected to the 2-5th node n15, and a second electrode connected to the data line DL; A gate connected to the shared EM line EML, a first electrode connected to the 2-1 node n11 to which the pixel driving voltage ELVDD is applied, and a second electrode connected to the 2-5 node n15 A 2-3rd switch element T13 having an electrode; A gate connected to the shared EM line (EML), a first electrode connected to a node 2-3 (n13), and a second electrode connected to the anode of the light emitting device of the second pixel circuit via the node 2-4 (n14). 2-4 switch element T14; A 2-5 switch element having a gate connected to the second scan line SN-1, a first electrode connected to the 2-2 node n12, and a second electrode to which the initialization voltage Vini is applied. (T15); And a gate connected to the second scan line SN-1, a first electrode to which the initialization voltage Vini is applied, and a 2-6th switch element T16-32 connected to the 2-4 node n14. ).

The configuration and effects of the first and second pixel circuits will be described in detail with reference to FIGS. 16A to 21B.

16A to 20B are diagrams illustrating pixel circuits and a driving method of the display device according to the first exemplary embodiment of the present invention. In the pixel circuits shown in FIGS. 16A to 20B, the same reference numerals are assigned to portions that are substantially the same as those of FIG. 6, and detailed descriptions thereof will be omitted. Transistors shaded in FIGS. 16A to 20B are transistors except for the initialization switch element T16. Arrows indicate current flow.

Each pixel circuit of each of the pixels of the 2N-1 pixel line [(2N-1)th line] includes a light emitting element EL and a plurality of transistors as shown in FIGS. 16A, 17A, 18A, and 19A. S (T11 to T16-31, DT), a capacitor (Cst), and the like. The transistors T11 to T16-31 and DT may be divided into switch elements T11 to T16-31 and a driving element DT.

16A, 17A, 18A, and 19A, the gate of the first switch element T11, the gate of the second switch element T12, and the gate of the initialization switch element T16-31 are Nth. It is connected to the N-1th scan line SN-1 to which the -1 scan signal SCAN(N-1) is applied. The first switch element T11, the second switch element T12, and the initialization switch element T16-31 are turned in response to the gate-on voltage VGL of the N-1th scan signal [SCAN(N-1)]. -It's on.

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the N-2th scan line SN-2 to which the N-2th scan signal SCAN(N-2) is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-2th scan signal SCAN(N-2).

The pixel circuit of each of the pixels of the 2N pixel line [(2N)th line] includes a light emitting element EL and a plurality of transistors T11 to as shown in FIGS. 16B, 17B, 18B, and 19B. T16-32, DT), capacitors (Cst), etc. are included. The transistors T11 to T16-32 and DT may be divided into switch elements T11 to T16-32 and a driving element DT.

16B, 17B, 18B, and 19B, the gates of the first and second switch elements T11 and T12 are the Nth scan lines SN to which the Nth scan signals [SCAN(N)] are applied. ). The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the Nth scan signal SCAN(N).

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 and the gate of the initialization switch element T16-32 are the N-1th scan line SN-1 to which the N-1th scan signal [SCAN(N-1)] is applied Is connected to The fifth switch element T15 and the initialization switch element T16-32 are turned on in response to the gate-on voltage VGL of the N-1th scan signal SCAN(N-1).

16A and 16B illustrate the operations of pixels of the 2N-1th pixel line [(2N-1)th line] and the 2Nth pixel line [(2N)th line] at time t1.

Referring to FIGS. 16A and 16B, in the light emitting step Temp of the 2N-1 pixel line [(2N-1)th line] and the 2N pixel line [(2N)th line], the driving element DT is Current flows through the light emitting element EL according to the gate-source voltage Vgs. When the shared EM signal EM is generated as a pulse of the gate-off voltage VEH at the time t1, the third and fourth switch elements T13 and 14 are turned off, so that no current flows through the light emitting element EL. .

17A and 17B illustrate operations of pixels of the 2N-1th pixel line [(2N-1)th line] and the 2Nth pixel line [(2N)th line] at t2.

The pulse of the N-2th scan signal [SCAN(N-2)] is applied to the 2N-1th pixel line [(2N-1)th line] as a gate-on voltage VGL at a time point t2, as shown in FIG. 17A. . At this time, the fifth switch element T15 is turned on in the pixels of the 2N-1 pixel line [(2N-1)th line], and Vini is applied to the second node n12 so that the capacitor Cst and the The gate of the driving element DT is initialized to Vini.

In the pixels of the 2N pixel line [(2N)th line], all the transistors T1 to T16-32, DT are shared with the scan signals [SCNA(N-1), SCAN(N)] as shown in FIG. 17B. Since the EM signal EM is the gate-off voltage VGH and VEH, it is turned off at the time t2.

18A and 18B illustrate operations of pixels of the 2N-1th pixel line [(2N-1)th line] and the 2Nth pixel line [(2N)th line] at t3.

18A and 18B, pixels of a 2N-1 pixel line [(2N-1)th line] and a 2N pixel line [(2N)th line] are an N-1th scan signal applied at a time point t3. It operates as a synchronization initialization step (Ti) according to the pulse of the gate-on voltage (VGL) of [SCAN(N-1)]. At the same time, the sensing step Ts is performed in the pixels of the 2N-1 pixel line [(2N-1)th line] so that the data voltage Vdata is applied to the second node n2 to be applied to the capacitor Cst. The data voltage Vdata compensated by the threshold voltage Vth of the driving element DT is charged.

The pulse of the N-1th scan signal [SCAN(N-1)] is applied to the 2N-1th pixel line [(2N-1)th line] as a gate-on voltage VGL at a time point t3, as shown in FIG. 18A. . At this time, the first switch element T11, the second switch element T12, and the initialization switch element T16-31 are turned on in the pixels of the 2N-1 pixel line [(2N-1)th line]. As a result, Vini is applied to the fourth node n14 so that the anode of the light emitting element EL is initialized to Vini. At the same time, the data voltage Vdata is applied to the second node n12 through the second switch element T12 and the first and second electrodes of the driving element DT. At this time, the voltage of the second node n2 changes to Vdata-|Vth|.

The pulse of the N-1th scan signal [SCAN(N-1)] is applied to the 2Nth pixel line [(2N)th line] with the gate-on voltage VGL at the time t3, as shown in FIG. 18B. At this time, the fifth switch element T15 and the initialization switch element T16-32 are turned on in the pixels of the 2N pixel line [(2N)th line], so that the second node n2 and the fourth node ( Vini is applied to n14). As a result, the capacitor Cst, the gate of the driving element DT, and the anode of the light emitting element EL are initialized to Vini.

19A and 19B illustrate operations of pixels of the 2N-1th pixel line [(2N-1)th line] and the 2Nth pixel line [(2N)th line] at t4.

19A and 19B, gate signals [SCAN(N-2) and SCAN(N-1) applied to pixels of the 2N-1 pixel line [(2N-1)th line] at time t4 , EM] are all gate-off voltages. Accordingly, the transistors T11 to T16-31 and DT of the 2N-1 pixel line [(2N-1)th line] are maintained in an off state, and thus the 2N-1 pixel line [(2N-1)th line] The pixels of the are retained in their previous state.

The pixels of the 2Nth pixel line [(2N)th line] perform the sensing step Ts according to the pulse of the gate-on voltage VGL of the Nth scan signal [SCAN(N)] applied at the time t4. In the sensing step Ts, the data voltage Vdata in the pixels of the second N pixel line [(2N)th line] is the second switch element T12 and the first electrode and the second electrode of the driving element DT. It is applied to the second node (n12) through. At this time, the voltage of the second node n2 changes to Vdata-|Vth|.

20A and 20B illustrate operations of pixels of the 2N-1th pixel line [(2N-1)th line] and the 2Nth pixel line [(2N)th line] at t5.

20A and 20B, a shared EM signal EM applied to pixels of a 2N-1 pixel line [(2N-1)th line] and a 2N pixel line [(2N)th line] is t5. At this point, it is inverted to the gate-on voltage VEL, and the light emission step Tem starts. In the light emission step Tem, the third and fourth switch elements T13 and 14 are turned on so that a current flows through the light emitting element EL. At this time, the gate-source voltage Vgs of the driving element DT is Vgs = Vdata-|Vth|-ELVDD.

As described above, a method of driving a display device according to an embodiment of the present invention includes the steps of generating a shared EM signal EM, and a first scan signal [S( N-2)], a second scan signal [S(N-1)], and a third scan signal [S(N)] in sequence, and the first scan signal [ S(N-2)], the second scan signal [S(N-1)], and the third scan signal [S(N)]. And simultaneously initializing pixels [(2N-1)th line pixel, (2N)th line pixel] of at least two pixel lines sharing the signal EM.

The initialization voltage Vini is simultaneously applied to the anode of the light emitting element EL disposed in each of the pixels [(2N-1)th line pixel, (2N)th line pixel] of at least two pixel lines sharing the shared EM signal. It is authorized.

The pixels [(2N-1)th line pixel, (2N)th line pixel] of the pixel lines are generated by the scan signals [S(N-2), S(N-1), S(N)]. It is sequentially scanned line by line.

21A and 21B are flowcharts illustrating a method of initializing pixel circuits of neighboring pixel lines to which gate signal lines are shared in the display device according to the first exemplary embodiment of the present invention.

21A and 21B, the N-2th scan signal [SCAN(N-2)], the N-1th scan signal [SCAN(N-1)] within the pulse duration of the shared EM signal EM, The Nth scan signal [SCAN(N)] is sequentially generated (S11 to S13). The 2N-1th pixel line [(2N-1)th line] is the shared EM signal (EM), the N-2th scan signal [SCAN(N-2)], and the N-1th scan signal [SCAN(N-1) )], etc., and the fourth node n14 is initialized at the pulse timing of the N-1th scan signal [SCAN(N-1)] (S15). At the same time, the 2N pixel line [(2N)th line] is the gate of the shared EM signal (EM), the N-1th scan signal [SCAN(N-1)], and the Nth scan signal [SCAN(N)]. Upon receiving the signal, the fourth node n14 is initialized at the pulse timing of the N-1th scan signal SCAN(N-1) (S15).

As can be seen from the simulation results of FIGS. 22A and 22B, the display device of the present invention has the same time from when the shared EM signal EM rises to the start of the initialization step Ti. The current (iel) is substantially the same. As a result, the luminance of the light emitting element EL is reduced in the initialization step (Ti), thereby reducing the increase in the luminance of the black gradation, as well as minimizing the luminance deviation between neighboring pixel lines to which the shared EM signal EM is applied. Can be.

In the display device according to the second embodiment of the present invention, a shared EM signal is applied to three neighboring pixel lines.

In the example of FIG. 23, (3N-1)th line is a 3N-1 pixel line, "(3N)th line" is a 3N pixel line, and "(3N+1)th line" is a 3N+1 pixel line. Respectively.

Each of the gate signal lines EML, SN-2, SN-1, and SN is connected 1:1 to each of the output channels of the gate driver 120. In addition, each of the gate signal lines EML, SN-2, SN-1, and SN is divided into three and connected to three neighboring pixel lines. Although some of the branch lines are omitted in the drawing, the N-2th scan line SN-2, the Nth scan line SN, and the N+1th scan line SN+1 are also branched into three gate lines. .

The 3N-1th pixel line [(3N-1)th line] may include a first pixel circuit, and the 3N-th pixel line [(3N)th line] may include a second pixel circuit. The 3N+1 pixel line [(3N+1)th line] may include a third pixel circuit.

The first to third pixel circuits may be adjacent to each other up and down to share one data line DL.

N-2th scan signal [SCAN(N-2)], N-1th scan signal [SCAN(N-1)], Nth scan signal [SCAN(N)], N+1th scan signal [SCAN( N+1)] as a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal, respectively, in the embodiments shown in FIGS. 24A to 24C, the first to third pixel circuits The configuration can be defined as:

The first to third pixel circuits have substantially the same circuit configuration, only the connection relationship between the scan lines and the switch elements is different. For convenience, if the components of the first pixel circuit are divided into 1-X, the components of the second pixel circuit are divided into 2-X, and the components of the third pixel circuit are divided into 3-X, the first, second, and third The components of the pixel circuit can be organized as follows.

As shown in FIG. 24A, the first pixel circuit is connected to the gate connected to the second scan line SN-1, the first electrode connected to the 1-2 node n12, and the 1-3 node n13. A 1-1st switch element T11 having a connected second electrode; 1-2 switch element T12 having a gate connected to the second scan line SN-1, a first electrode connected to the 1-5th node n15, and a second electrode connected to the data line DL ; A gate connected to the shared EM line EML, a first electrode connected to the 1-1 node n11 to apply a pixel driving voltage ELVDD, and a second electrode connected to the 1-5 node n15 A 1-3th switch element T13 having a; The gate connected to the shared EM line EML, the first electrode connected to the 1-3th node n13, and the second connected to the anode of the light emitting element of the first pixel circuit via the 1-4th node n14 A 1-4th switch element (n14) having an electrode; And a gate connected to the first scan line SN-2, a first electrode connected to the 1-2 node n12, and a second electrode to which an initialization voltage Vini is applied. (T15); And a gate connected to the second scan line SN-1, a first electrode to which the initialization voltage Vini is applied, and a 1-6th switch element T16-41 connected to the 1-4th node n14. ).

As shown in FIG. 24B, the second pixel circuit includes a gate connected to the third scan line SN, a first electrode connected to a 2-2 node n12, and a 2-3 node n13. A 2-1 switch element T11 having a second electrode; A 2-2 switch element T12 having a gate connected to the third scan line SN, a first electrode connected to the 2-5th node n15, and a second electrode connected to the data line DL; A gate connected to the shared EM line EML, a first electrode connected to the 2-1 node n11 to which the pixel driving voltage ELVDD is applied, and a second electrode connected to the 2-5 node n15 A 2-3rd switch element T13 having an electrode; A gate connected to the shared EM line (EML), a first electrode connected to a node 2-3 (n13), and a second electrode connected to the anode of the light emitting device of the second pixel circuit via the node 2-4 (n14). 2-4 switch element T14; A 2-5 switch element having a gate connected to the second scan line SN-1, a first electrode connected to the 2-2 node n12, and a second electrode to which the initialization voltage Vini is applied. (T15); And a gate connected to the second scan line SN-1, a first electrode to which the initialization voltage Vini is applied, and a 2-6th switch element T16-42 connected to the 2-4th node n14. ).

The third pixel circuit includes a gate connected to the fourth scan line SN+1, a first electrode connected to a 3-2 node n12, and a 3-3 node n13, as shown in FIG. 24C. A 3-1 switch element T11 having a second electrode connected to the second electrode; A 3-2 switch element T12 having a gate connected to the fourth scan line SN+1, a first electrode connected to the 3-5th node n15, and a second electrode connected to the data line DL. ); A gate connected to the shared EM line EML, a first electrode connected to the 3-1 node n11 to which the pixel driving voltage ELVDD is applied, and a second electrode connected to the 3-5 node n15 A 3-3 switch element T13 having an electrode; A gate connected to the shared EM line EML, a first electrode connected to the 3-3 node n13, and a first electrode connected to the anode of the light emitting device of the second pixel circuit via the 3-4 node n14. 3-4 switch element T14; A 3-5th switch element T15 having a gate connected to the third scan line SN, a first electrode connected to the 3-2th node n12, and a second electrode to which the initialization voltage Vini is applied. ); And a gate connected to the second scan line SN-1, a first electrode to which the initialization voltage Vini is applied, and a second electrode connected to the 3-4th node n14. It includes elements T16-43.

The configuration and effect of the first to third pixel circuits will be described in detail with reference to FIGS. 24A to 24C.

24A to 25C are diagrams illustrating pixel circuits and a driving method of the display device according to the second exemplary embodiment of the present invention.

In each of the pixels of the 3N-1 pixel line [(3N-1)th line] shown in FIG. 24A, the gate of the first switch element T11, the gate of the second switch element T12, and the initialization switch element The gate of the (T16-41) is connected to the N-1th scan line SN-1 to which the N-1th scan signal [SCAN(N-1)] is applied. The first switch element T11, the second switch element T12, and the initialization switch element T16-41 are turned in response to the gate-on voltage VGL of the N-1th scan signal [SCAN(N-1)]. -It's on.

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the N-2th scan line SN-2 to which the N-2th scan signal SCAN(N-2) is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-2th scan signal SCAN(N-2).

In each of the pixels of the 3N pixel line [(3N)th line] shown in FIG. 24B, the gates of the first and second switch elements T11 and T12 are applied to the Nth scan signal [SCAN(N)]. It is connected to the Nth scan line SN. The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the Nth scan signal SCAN(N).

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 and the gate of the initialization switch element T16-42 are the N-1th scan line SN-1 to which the N-1th scan signal [SCAN(N-1)] is applied Is connected to The fifth switch element T15 and the initialization switch element T16-42 are turned on in response to the gate-on voltage VGL of the N-1th scan signal SCAN(N-1).

In each of the pixels of the 3N+1 pixel line [(3N+1)th line] shown in FIG. 24C, the gates of the first and second switch elements T11 and T12 are the N+1th scan signal [SCAN( N+1)] is connected to the N+1th scan line SN+1 to which it is applied. The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the N+1th scan signal SCAN(N+1).

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the Nth scan line SN to which the Nth scan signal SCAN(N) is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the Nth scan signal SCAN(N). The gate of the initialization switch element T16-43 is connected to the N-1th scan line SN-1 to which the N-1th scan signal SCAN(N-1) is applied. The initialization switch elements T16-43 are turned on in response to the gate-on voltage VGL of the N-1th scan signal SCAN(N-1).

In the display device according to the second embodiment of the present invention, the first to third pixel circuits are formed in response to a pulse of a third scan signal, that is, an Nth scan signal [SCAN(N)], as shown in FIGS. 25A to 25C. Four nodes (n14) can be initialized at the same time.

In each of the pixels of the 3N pixel line [(3N-1)th line] shown in FIG. 25A, the gates of the first and second switch elements T11 and T12 are the N-1th scan signal [SCAN(N- 1)] is connected to the N-1th scan line SN-1 to which it is applied. The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the N-1th scan signal SCAN(N-1).

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the N-2th scan line SN-2 to which the N-2th scan signal SCAN(N-2) is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-2th scan signal SCAN(N-2).

The gate of the initialization switch element T16-41 is connected to the Nth scan line SN to which the Nth scan signal SCAN(N) is applied. The initialization switch elements T16-41 are turned on in response to the gate-on voltage VGL of the Nth scan signal SCAN(N).

In each of the pixels of the 3N pixel line [(3N)th line] shown in FIG. 25B, the gates of the first switch element T11, the second switch element T12, and the initialization switch element T16-42 are It is connected to the Nth scan line SN to which the N scan signal [SCAN(N)] is applied. The first switch element T11, the second switch element T12, and the initialization switch element T16-42 are turned on in response to the gate-on voltage VGL of the Nth scan signal SCAN(N).

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the N-1th scan line SN-1 to which the N-1th scan signal SCAN(N-1) is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-1th scan signal SCAN(N-1).

In each of the pixels of the 3N+1 pixel line [(3N+1)th line] shown in FIG. 25C, the gates of the first and second switch elements T11 and T12 are the N+1th scan signals [SCAN( N+1)] is connected to the N+1th scan line SN+1 to which it is applied. The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the N+1th scan signal SCAN(N+1).

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

Gates of the fifth switch element T15 and the initialization switch elements T16-43 are connected to the Nth scan line SN to which the Nth scan signal [SCAN(N)] is applied. The fifth switch element T15 and the initialization switch element T16-43 are turned on in response to the gate-on voltage VGL of the Nth scan signal [SCAN(N)].

26 is a diagram illustrating an example in which gate signal lines are shared between neighboring pixel lines in the display device according to the third embodiment of the present invention.

In the display device according to the third embodiment of the present invention, a shared EM signal is applied to four adjacent pixel lines.

In the example of FIG. 26, (4N-1)th line is a 4N-1th pixel line, "(4N)th line" is a 4Nth pixel line, and "(4N+1)th line" is a 4N+1th pixel line. , &Quot;(4N+2)th line" denotes a 4N+2th pixel line, respectively.

Each of the gate signal lines EML, SN-2, SN-1, SN, SN+1, and SN+2 is 1:1 connected to each of the output channels of the gate driver 120. In addition, each of the gate signal lines EML, SN-2, SN-1, SN, SN+1, and SN+2 is divided into four and connected to four neighboring pixel lines. Although some of the branch lines are omitted in the drawing, the N-2th scan line SN-2, the N+1th scan line SN+1, and the N+2th scan line SN+2 are also four gate lines. Branches into.

27A to 27D are diagrams showing pixel circuits and a driving method of the display device according to the third exemplary embodiment of the present invention. In this embodiment, the 4N-1 to 4N+2 pixel lines [(4N-1)th line, (4N)th line, (4N+1)th line, (4N+2)th line] are the Nth line. This is an example of simultaneous initialization in response to the scan signal [SCAN(N)]. The third embodiment of the present invention is not limited thereto. For example, as in the above-described embodiments, when the gates of the initialization switch elements T16-51 to T16-54 are connected to the N-1th scan line SN-1, the 4N+2 pixel lines [(4N-1)th line, (4N)th line, (4N+1)th line, (4N+2)th line] simultaneously responds to the N-1th scan signal [SCAN(N-1)] Can be initialized.

In each of the pixels of the 4N-1th pixel line [(4N-1)th line] shown in FIG. 27A, the gates of the first and second switch elements T11 and T12 are the N-1th scan signal [SCAN] (N-1)] is connected to the N-1 th scan line SN-1 to which it is applied. The first and second switch elements T11 are turned on in response to the gate-on voltage VGL of the N-1th scan signal SCAN(N-1).

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the N-2th scan line SN-2 to which the N-2th scan signal SCAN(N-2) is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-2th scan signal SCAN(N-2). The gate of the initialization switch element T16-51 is connected to the Nth scan line SN to which the Nth scan signal SCAN(N) is applied. The initialization switch elements T16-51 are turned on in response to the gate-on voltage VGL of the Nth scan signal SCAN(N).

In each of the pixels of the 4N pixel line [(4N)th line] shown in FIG. 27B, the gate of the first switch element T11, the gate of the second switch element T12, and the initialization switch element T16-52 The gate of) is connected to the Nth scan line SN to which the Nth scan signal SCAN(N) is applied. The first switch element T11, the second switch element T12, and the initialization switch element T16-52 are turned on in response to the gate-on voltage VGL of the Nth scan signal SCAN(N).

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the N-1th scan line SN-1 to which the N-1th scan signal SCAN(N-1) is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N-1th scan signal SCAN(N-1).

In each of the pixels of the 4N+1 pixel line [(4N+1)th line] shown in FIG. 27C, the gates of the first and second switch elements T11 and T12 are the N+1th scan signals [SCAN( N+1)] is connected to the N+1th scan line SN+1 to which it is applied. The first and second switch elements T11 and T12 are turned on in response to the gate-on voltage VGL of the N+1th scan signal SCAN(N+1).

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

Gates of the fifth switch element T15 and the initialization switch elements T16-53 are connected to the Nth scan line SN to which the Nth scan signal [SCAN(N)] is applied. The fifth switch element T15 and the initialization switch element T16-53 are turned on in response to the gate-on voltage VGL of the Nth scan signal [SCAN(N)].

In each of the pixels of the 4N+2 pixel line [(4N+2)th line] shown in FIG. 27D, the gates of the first and second switch elements T11 and T12 are N+2th scan signals [SCAN]. (N+2)] is connected to the N+2th scan line SN+2 to which it is applied. The first and second switch elements T11 are turned on in response to the gate-on voltage VGL of the N+2th scan signal SCAN(N+2).

Gates of the third and fourth switch elements T13 and 14 are connected to the shared EM line EML to which the shared EM signal EM is applied. The third and fourth switch elements T13 and T14 are turned on in response to the gate-on voltage VEL of the shared EM signal EM.

The gate of the fifth switch element T15 is connected to the N+1th scan line SN+1 to which the N+1th scan signal SCAN(N+1) is applied. The fifth switch element T15 is turned on in response to the gate-on voltage VGL of the N+1th scan signal SCAN(N+1). The gate of the initialization switch element T16-51 is connected to the Nth scan line SN to which the Nth scan signal SCAN(N) is applied. The initialization switch elements T16-51 are turned on in response to the gate-on voltage VGL of the Nth scan signal SCAN(N).

The above-described embodiments may be applied alone or in combination.

Various embodiments of the display device of the present invention may be described as follows.

Embodiment 1: A display device includes a data line DL to which a data voltage is applied; A shared EM line (EML) to which a shared EM signal is applied; A first scan line SN-2 to which a first scan signal SCAN(N-2) is applied; A second scan line SN-1 to which a second scan signal SCAN(N-1) generated subsequent to the first scan signal is applied; A third scan line SN to which a third scan signal SCAN(N) generated subsequent to the second scan signal is applied; A first pixel circuit ((2N-1)th line pixel) connected to the data line, the shared EM line, the first scan line, and the second scan line; And a second pixel circuit ((2N)th line pixel) connected to the data line, the shared EM line, the second scan line, and the third scan line.

Each of the first and second pixel circuits includes a driving element DT including a gate connected to a capacitor Cst; A light-emitting element EL that emits light by a current flowing through the driving element; And an initialization switch T16 for applying a predetermined initialization voltage to the anode of the light emitting device in response to any one of the scan signals.

A pulse of the first scan signal, a pulse of the second scan signal, and a pulse of the third scan signal are generated within the pulse duration of the shared EM signal.

The same scan signal is applied to gates of the initialization switch of the first and second pixel circuits, so that the initialization voltage is simultaneously applied to the light emitting devices of the first and second pixel circuits.

Embodiment 2: The gates of the initialization switch of the first pixel circuit and the initialization switch of the second pixel circuit may be connected to the second scan line.

Embodiment 3: The first pixel circuit includes: a 1-1 switch element having a gate connected to the second scan line, a first electrode connected to a node 1-2, and a second electrode connected to a node 1-3; A 1-2 switch element having a gate connected to the second scan line, a first electrode connected to a node 1-5, and a second electrode connected to the data line; A 1-3th switch element having a gate connected to the shared EM line, a first electrode connected to a 1-1 node to which a pixel driving voltage is applied, and a second electrode connected to the 1-5 node; A 1-4 switch having a gate connected to the shared EM line, a first electrode connected to a node 1-3, and a second electrode connected to an anode of the light emitting element of the first pixel circuit via a node 1-4 device; And a 1-5th switch element having a gate connected to the first scan line, a first electrode connected to the 1-2th node, and a second electrode to which the initialization voltage is applied.

The initialization switch of the first pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the nodes 1-4. The capacitor of the first pixel circuit is connected between the first-first node and the first-second node.

The driving element of the first pixel circuit further includes a first electrode connected to the node 1-5 and a second electrode connected to the node 1-3.

Embodiment 4: The second pixel circuit comprises: a 2-1 switch element having a gate connected to the third scan line, a first electrode connected to a node 2-2, and a second electrode connected to a node 2-3; A 2-2 switch element having a gate connected to the third scan line, a first electrode connected to a node 2-5, and a second electrode connected to the data line; A 2-3rd switch element having a gate connected to the shared EM line, a first electrode connected to a node 2-1 to which the pixel driving voltage is applied, and a second electrode connected to the node 2-5; A gate connected to the shared EM line, a first electrode connected to a node 2-3, and a switch device 2-4 connected to an anode of the light emitting device of the second pixel circuit via a node 2-4; And a 2-5th switch element having a gate connected to the second scan line, a first electrode connected to the 2-2 node, and a second electrode to which the initialization voltage is applied.

The initialization switch of the second pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the node 2-4. The capacitor of the second pixel circuit is connected between the 2-1 node and the 2-2 node.

The driving element of the second pixel circuit further includes a first electrode connected to the node 2-5 and a second electrode connected to the node 2-3.

Example 5: When the pulse of the second scan signal is generated, a data voltage compensated for the threshold voltage of the driving element is applied to the node 1-2 and the initialization voltage is applied to the node 1-4. Can be. When the pulse of the second scan signal is generated, the initialization voltage may be applied to the node 2-2 and the node 2-4.

Embodiment 6: In the second pixel circuit, when the pulse of the third scan signal is generated, the first pixel circuit may maintain a previous state. When the pulse of the third scan signal is generated, a data voltage compensated for the threshold voltage of the driving element may be applied to the node 2-2 of the second pixel circuit.

Embodiment 7: The display device includes: a fourth scan line SN+1 to which a fourth scan signal SCAN(N+1) generated subsequent to the third scan signal is applied; And a third pixel circuit ((3N+1)th line pixel) connected to the data line, the shared EM line, the second scan line, the third scan line, and the fourth scan line. have.

The third pixel circuit includes: a 3-1 switch element having a gate connected to the fourth scan line, a first electrode connected to a node 3-2, and a second electrode connected to a node 3-3; A 3-2 switch element having a gate connected to the fourth scan line, a first electrode connected to a node 3-5, and a second electrode connected to the data line; A 3-3 switch element having a gate connected to the shared EM line, a first electrode connected to the 3-1 node to which the pixel driving voltage is applied, and a second electrode connected to the 3-5 node; A gate connected to the shared EM line, a first electrode connected to a node 3-3, and a switch device 3-4 connected to an anode of the light emitting device of the second pixel circuit via a node 3-4; And a 3-5th switch element having a gate connected to the third scan line, a first electrode connected to the 3-2 node, and a second electrode to which the initialization voltage is applied.

The initialization switch of the third pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the 3-4 node. The capacitor of the third pixel circuit is connected between the 3-1 node and the 3-2 node.

The driving element of the third pixel circuit further includes a first electrode connected to the 3-5 node and a second electrode connected to the 3-3 node.

Various embodiments of a method of driving a display device according to an embodiment of the present invention may be described as follows.

Embodiment 1: The driving method comprises the steps of generating a shared EM signal; Sequentially generating a pulse of a first scan signal, a pulse of a second scan signal, and a pulse of a third scan signal within the pulse duration of the shared EM signal; And simultaneously initializing pixels of at least two pixel lines sharing the shared EM signal at a pulse timing of any one of the pulse of the first scan signal, the pulse of the second scan signal, and the pulse of the third scan signal. Includes.

Embodiment 2: The step of simultaneously initializing pixels of the at least two pixel lines includes simultaneously applying a predetermined initialization voltage to an anode of a light emitting device disposed on each of pixels of at least two pixel lines sharing the shared EM signal Can include.

Embodiment 3: The driving method may further include sequentially scanning the pixel lines by the scan signals.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Accordingly, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

100: display panel 120: gate driver
200: host system 300: drive IC
DL: data line EML: shared EM line
SN-2 to SN+1: scan line

Claims (10)

A data line DL to which a data voltage is applied;
A shared EM line (EML) to which a shared EM signal is applied;
A first scan line SN-2 to which a first scan signal SCAN(N-2) is applied;
A second scan line SN-1 to which a second scan signal SCAN(N-1) generated subsequent to the first scan signal is applied;
A third scan line SN to which a third scan signal SCAN(N) generated subsequent to the second scan signal is applied;
A first pixel circuit ((2N-1)th line pixel) connected to the data line, the shared EM line, the first scan line, and the second scan line; And
A second pixel circuit ((2N)th line pixel) connected to the data line, the shared EM line, the second scan line, and the third scan line,
Each of the first and second pixel circuits,
A driving element DT including a gate connected to the capacitor Cst;
A light-emitting element EL that emits light by a current flowing through the driving element; And
And an initialization switch (T16) for applying a predetermined initialization voltage to the anode of the light emitting device in response to any one of the scan signals,
The pulse of the first scan signal, the pulse of the second scan signal, and the pulse of the third scan signal are generated within the pulse duration of the shared EM signal,
A display device in which the same scan signal is applied to the gates of the initialization switch of the first and second pixel circuits to simultaneously apply the initialization voltage to the light emitting elements of the first and second pixel circuits. The method of claim 1,
A display device in which gates of an initialization switch of the first pixel circuit and an initialization switch of the second pixel circuit are connected to the second scan line. The method of claim 2,
The first pixel circuit,
A first-first switch element having a gate connected to the second scan line, a first electrode connected to a node 1-2, and a second electrode connected to a node 1-3;
A 1-2 switch element having a gate connected to the second scan line, a first electrode connected to a node 1-5, and a second electrode connected to the data line;
A 1-3th switch element having a gate connected to the shared EM line, a first electrode connected to a 1-1 node to which a pixel driving voltage is applied, and a second electrode connected to the 1-5 node;
A 1-4 switch having a gate connected to the shared EM line, a first electrode connected to a node 1-3, and a second electrode connected to an anode of the light emitting element of the first pixel circuit via a node 1-4 device; And
Further comprising a 1-5 switch element having a gate connected to the first scan line, a first electrode connected to the 1-2 node, and a second electrode to which the initialization voltage is applied,
The initialization switch of the first pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the nodes 1-4,
The capacitor of the first pixel circuit is connected between the 1-1 node and the 1-2 node,
The driving element of the first pixel circuit,
A display device further comprising: a first electrode connected to the 1-5th node and a second electrode connected to the 1-3th node. The method of claim 2,
The second pixel circuit,
A 2-1 switch element having a gate connected to the third scan line, a first electrode connected to a node 2-2, and a second electrode connected to a node 2-3;
A 2-2 switch element having a gate connected to the third scan line, a first electrode connected to a node 2-5, and a second electrode connected to the data line;
A 2-3rd switch element having a gate connected to the shared EM line, a first electrode connected to a node 2-1 to which the pixel driving voltage is applied, and a second electrode connected to the node 2-5;
A gate connected to the shared EM line, a first electrode connected to a node 2-3, and a switch device 2-4 connected to an anode of the light emitting device of the second pixel circuit via a node 2-4; And
A 2-5 switch element having a gate connected to the second scan line, a first electrode connected to the 2-2 node, and a second electrode to which the initialization voltage is applied,
The initialization switch of the second pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the node 2-4,
The capacitor of the second pixel circuit is connected between the 2-1 node and the 2-2 node,
The driving element of the second pixel circuit,
The display device further comprises a first electrode connected to the 2-5 node and a second electrode connected to the 2-3 node. The method of claim 4,
When a pulse of the second scan signal is generated, a data voltage compensated for the threshold voltage of the driving element is applied to the node 1-2, and the initialization voltage is applied to the node 1-4,
When a pulse of the second scan signal is generated, the initialization voltage is applied to the node 2-2 and the node 2-4. The method of claim 5,
The second pixel circuit,
When the pulse of the third scan signal is generated, the first pixel circuit maintains the previous state,
When a pulse of the third scan signal is generated, a data voltage compensated for the threshold voltage of the driving element is applied to the node 2-2 of the second pixel circuit. The method of claim 4,
A fourth scan line SN+1 to which a fourth scan signal SCAN(N+1) generated subsequent to the third scan signal is applied; And
A third pixel circuit ((3N+1)th line pixel) connected to the data line, the shared EM line, the second scan line, the third scan line, and the fourth scan line,
The third pixel circuit,
A 3-1 switch element having a gate connected to the fourth scan line, a first electrode connected to a node 3-2, and a second electrode connected to a node 3-3;
A 3-2 switch element having a gate connected to the fourth scan line, a first electrode connected to a node 3-5, and a second electrode connected to the data line;
A 3-3 switch element having a gate connected to the shared EM line, a first electrode connected to the 3-1 node to which the pixel driving voltage is applied, and a second electrode connected to the 3-5 node;
A gate connected to the shared EM line, a first electrode connected to a node 3-3, and a switch device 3-4 connected to an anode of the light emitting device of the second pixel circuit via a node 3-4; And
A 3-5th switch element having a gate connected to the third scan line, a first electrode connected to the 3-2 node, and a second electrode to which the initialization voltage is applied,
The initialization switch of the third pixel circuit includes a first electrode to which the initialization voltage is applied, and a second electrode connected to the 3-4 node,
The capacitor of the third pixel circuit is connected between the 3-1 node and the 3-2 node,
The driving element of the third pixel circuit,
The display device further includes a first electrode connected to the 3-5 node and a second electrode connected to the 3-3 node. Generating a shared EM signal;
Sequentially generating a pulse of a first scan signal, a pulse of a second scan signal, and a pulse of a third scan signal within the pulse duration of the shared EM signal; And
Simultaneously initializing pixels of at least two pixel lines sharing the shared EM signal at a pulse timing of any one of the pulse of the first scan signal, the pulse of the second scan signal, and the pulse of the third scan signal. Driving method of a display device including. The method of claim 8,
Initializing the pixels of the at least two pixel lines at the same time,
And simultaneously applying a predetermined initialization voltage to an anode of a light emitting device disposed on each of pixels of at least two pixel lines sharing the shared EM signal. The method of claim 8,
And sequentially scanning the pixel lines by the scan signals.

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