KR102608779B1 - Display panel and driving method thereof - Google Patents

Abstract

The present invention relates to a display device and a method of driving the same, and relates to a display device and a method of driving the same. The pixel data voltage is changed by using switch elements of a demultiplexer or separate switch elements for charge sharing connected between the output channels of the data driver and the data lines of the pixel array. Before the data lines are sequentially charged, the data lines are connected to each other to perform charge sharing of the data lines.

Description

Display device and its driving method {DISPLAY PANEL AND DRIVING METHOD THEREOF}

The present invention relates to a display device in which a demultiplexer (DEMUX) is disposed between a data driver and data lines, and a method of driving the same.

Plate display devices include Liquid Crystal Display (LCD), Electroluminescence Display (Electroluminescence Display), Field Emission Display (FED), and Plasma Display Panel (PDP).

Electroluminescent displays are divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness, and viewing angle. There is an advantage.

OLED, an organic light emitting display device, includes an organic compound layer formed between an anode and a cathode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL) may be included. When voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emitting layer (EML) to form excitons, and as a result, the emitting layer (EML) emits visible light. is released.

Each pixel of a display device is divided into a number of sub-pixels of different colors to implement color, and each of the sub-pixels includes a transistor used as a switch element or driving element. These transistors can be implemented as TFTs (Thin Film Transistors).

The driving circuit of the display device writes pixel data of the input image into pixels. The driving circuit of the flat panel display device includes a data driver that supplies a data signal to the data lines, and a gate driver that supplies a gate signal (or scan signal) to the gate lines (or scan lines). A demultiplexer (DEMUX) may be placed between the data driver and the data lines. The demultiplexer connects one channel of the data driver between a plurality of data lines and distributes the data voltage output from one channel of the data driver to the plurality of data lines in time division, thereby reducing the number of channels of the data driver.

The number of channels in the data driver can be reduced by using a demultiplexer, but the charging time for one pixel may be insufficient due to the demultiplexer. For example, when one channel of the data driver is connected to two data lines through a demultiplexer, the charging time of the pixels is reduced by about half because the data voltage is sequentially applied to the two data lines within one horizontal period. . In such a display device, when the voltage difference between data lines increases, a large difference in luminance may occur between neighboring pixels.

The low-potential power supply voltage (VSS) is a base voltage commonly applied to the cathode of the OLED in the pixels. The cathode of OLED is coupled to the data line through parasitic capacitance. Therefore, when the transition difference between pixel data to be written to the subpixels increases and the transition width of the voltage applied to the data line increases, a ripple in the low-potential power supply voltage (VSS) of the pixels is generated and the low-potential power supply voltage increases. Voltage (VSS) may fluctuate. When the low-potential power supply voltage (VSS) changes like this, changes in luminance and crosstalk of pixels can be seen.

Therefore, the present invention provides a display device in which a demultiplexer is disposed between a data driver and data lines, and a display device that can achieve effects such as reduced power consumption, reduced coupling ripple, and reduced ON time of the demultiplexer, and its driving. Provides a method.

A display device according to an embodiment of the present invention uses a data driver that outputs a data voltage through first and second channels, and 1-1 and 2-1 switch elements to output a data voltage through the first channel. The data voltage output through the second channel is distributed to the third and fourth data lines using a first demultiplexer, 1-2 and 2-2 switch elements that distribute the voltage to the first and second data lines. It includes a second demultiplexer for distribution, and a control unit for controlling switch on/off timing of the first and second demultiplexers.

All switch elements of the first and second demultiplexers are simultaneously turned on for a first time to connect the first and second data lines. At a second time, the 1-1 and 1-2 switch elements are simultaneously turned on so that the first channel is connected to the first data line and the second channel is connected to the third data line. At a third time, the 2-1 and 2-2 switch elements are simultaneously turned on so that the first channel is connected to the second data line and the second channel is connected to the fourth data line.

A display device according to another embodiment of the present invention uses a data driver that outputs a data voltage through first and second channels, and 1-1 and 2-1 switch elements to output data through the first channel. The data voltage output through the second channel is distributed to the third and fourth data lines using a first demultiplexer that distributes the voltage to the first and second data lines, and 1-2 and 2-2 switch elements. It includes a second demultiplexer that distributes, a charge sharing unit that selectively connects the first and second channels, and a control unit that controls switch on/off timing of the first and second demultiplexers and the charge sharing unit.

All switch elements of the first and second demultiplexers and switch elements of the charge sharing unit are simultaneously turned on for a first time, so that the first channel and the second channel are connected, and the data lines are connected to the first and second channels. Connected to 2 channels.

A display device according to another embodiment of the present invention uses a data driver that outputs a data voltage through first and second channels, and 1-1 and 2-1 switch elements to output data voltage through the first channel. A first demultiplexer distributes the data voltage to the first and second data lines, and the data voltage output through the second channel is distributed to the third and fourth data lines using 1-2 and 2-2 switch elements. It includes a second demultiplexer that distributes data to the data lines, a charge sharing unit that selectively connects the data lines, and a control unit that controls switch on/off timing of the first and second demultiplexers and the charge sharing unit.

The switch elements of the charge sharing unit are simultaneously turned on for a first time so that the data lines are connected through the switch elements of the charge sharing unit.

A display device according to another embodiment of the present invention includes a data driver that outputs a data voltage through first and second channels; a charge sharing unit selectively connecting a first data line connected to the first channel and a second data line connected to the second channel; and a control unit that controls switch on/off timing of the charge sharing unit.

The switch elements of the charge sharing unit are simultaneously turned on for a first time, and the data lines are connected through the switch elements of the charge sharing unit, and then turned off for a second and third time. At a second time, the first data voltage from the first channel is stored in the first data line. At a third time, a second data voltage from the second channel is stored in the second data line.

A method of driving a display device according to an embodiment of the present invention includes the steps of turning on all switch elements of the first and second demultiplexers simultaneously for a first time to connect the first and second data lines. , At a second time, the 1-1 and 1-2 switch elements are simultaneously turned on so that the first channel is connected to the first data line and the second channel is connected to the third data line. Step, and at a third time, the 2-1 and 2-2 switch elements are simultaneously turned on so that the first channel is connected to the second data line and the second channel is connected to the fourth data line. Includes connecting steps.

A method of driving a display device according to another embodiment of the present invention is such that all the switch elements of the first and second demultiplexers and the switch elements of the charge sharing unit are simultaneously turned on at a first time to connect the first channel and the second demultiplexer. A step in which two channels are connected and the data lines are connected to the first and second channels, and at a second time, the 1-1 and 1-2 switch elements are turned on simultaneously so that the first channel is connected to the first and second channels. Connecting the second channel to the third data line at the same time as being connected to the first data line, and at a third time, the 2-1 and 2-2 switch elements are simultaneously turned on to connect the first channel This includes connecting the second channel to the fourth data line at the same time as it is connected to the second data line.

A method of driving a display device according to another embodiment of the present invention includes the steps of simultaneously turning on the switch elements of the charge sharing unit at a first time and connecting the data lines through the switch elements of the charge sharing unit at a second time. The 1-1 and 1-2 switch elements are simultaneously turned on so that the first channel is connected to the first data line and the second channel is connected to the third data line, and At 3 hours, the 2-1 and 2-2 switch elements are simultaneously turned on so that the first channel is connected to the second data line and the second channel is connected to the fourth data line. Includes.

A method of driving a display device according to another embodiment of the present invention includes the steps of simultaneously turning on the switch elements of the charge sharing unit for a first time and connecting the data lines through the switch elements of the charge sharing unit. , and after the switch elements of the charge sharing unit are turned off and the first data voltage from the first channel at a second time is stored in the first data line, the second data from the second channel at a third time and storing a voltage on the second data line.

The present invention uses switch elements of a demultiplexer connected between the output channels of the data driver and the data lines of the pixel array, or separate switch elements for charge sharing, before the pixel data voltage is sequentially charged to the data lines. The data lines are connected to each other so that the voltage of the data lines is set to the average voltage of the data lines through charge sharing of the data lines. As a result, the present invention can achieve effects such as reduced power consumption, reduced coupling ripple, and reduced ON time of the demultiplexer in a display device in which a demultiplexer is disposed between a data driver and data lines.

1 is a block diagram showing a display device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a charge share circuit applied to the display device shown in FIG. 1.
3 and 4 are circuit diagrams showing examples of pixel circuits applicable to the present invention.
Figure 5 is a circuit diagram showing an example in which two left and right neighboring subpixels share one output buffer of the data driver.
FIG. 6 is a waveform diagram showing driving signals of the subpixels shown in FIG. 5.
Figures 7 and 8 are diagrams showing the connection structure of the data driver, demultiplexer, and pixel array according to the first embodiment of the present invention.
FIG. 9 is a diagram quantitatively showing the transition width when charge sharing is not performed when displaying a yellow image as in FIG. 8.
Figure 10 is a waveform diagram showing the charge share section (t1).
Figure 11 is a waveform diagram showing the charge sharing method according to the first embodiment of the present invention.
FIG. 12 is a diagram quantitatively showing the charge share effect of the first embodiment when displaying a yellow image as shown in FIG. 8.
FIG. 13 is a waveform diagram showing voltages of some data lines in the pixel array shown in FIG. 8.
Figure 14 is a diagram showing a charge share circuit connected between channels of the data driver.
Figures 15a and 15b are waveform diagrams showing the charge sharing method according to the second embodiment of the present invention.
Figure 16 is a diagram showing a charge share circuit disposed on the substrate of the display panel.
Figure 17 is a waveform diagram showing the charge sharing method according to the third embodiment of the present invention.
FIG. 18 is a diagram quantitatively showing the charge share effect of the third embodiment when displaying a yellow image as shown in FIG. 8.
FIG. 19 is a diagram showing another example of a charge share circuit disposed on a display panel substrate.
Figure 20 is a waveform diagram showing the charge sharing method according to the fourth embodiment of the present invention.
FIG. 21 is a diagram quantitatively showing the charge share effect of the fourth embodiment when displaying a yellow image as shown in FIG. 8.
FIG. 22 is a diagram showing an example of a charge sharing circuit disposed on a substrate of a display panel without a demultiplexer.
Figure 23 is a waveform diagram showing the charge sharing method according to the fifth embodiment of the present invention.
FIG. 24 is a diagram showing another example of a charge share circuit disposed on a display panel substrate.
Figure 25 is a waveform diagram showing the charge sharing method according to the sixth embodiment of the present invention.
FIG. 26 is a diagram quantitatively showing the charge share effect of the sixth embodiment when displaying a yellow image as shown in FIG. 8.
FIGS. 27A to 30B are diagrams showing in detail a driving method including a charge sharing section in neighboring subpixels that include the pixel circuit shown in FIG. 3 and share an output buffer.
FIGS. 31A to 35B are diagrams showing in detail a driving method including a charge sharing section in neighboring subpixels that include the pixel circuit shown in FIG. 4 and share an output buffer.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. Only the embodiments are intended to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “comprises,” “includes,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two components is described as 'on top', 'on top', 'on the bottom', 'next to ~', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the display device of the present invention, each of the pixel circuit and the gate driver may include a plurality of transistors and be formed directly on the substrate of the display panel. A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal and charge share control signal (hereinafter referred to as “CS”) may swing between the gate on voltage and the gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate on voltage, while the transistor is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage (Gate High Voltage, VGH), and the gate-off voltage may be the gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be the gate low voltage (VGL) and the gate-off voltage may be the gate high voltage (VGH).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings. In the following embodiments, the description will focus on an organic light emitting display device including an organic light emitting material. The technical idea of the present invention is not limited to organic light emitting display devices, but can be applied to inorganic light emitting display devices including inorganic light emitting materials.

The present invention uses a demultiplexer (DEMUX) to time-divide the data voltage output through one channel of the data driver to N (N is a positive integer of 2 or more) data lines.

1 to 4, an electroluminescent display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit for writing data into the pixels 101 of the display panel 100. Includes.

The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 that intersect the data lines 103, and pixels arranged in a matrix form. The pixel array includes multiple pixel lines (L1 to Ln). A pixel line includes pixels arranged in 1 line in the pixel array of the display panel 100. When the resolution of the pixel array is m*n, the pixel array includes n pixel lines (L1 to Ln). Pixels placed on one pixel line share gate lines. Subpixels 101 arranged in one pixel line are connected to different data lines 102. Subpixels arranged vertically along the data line direction share the same data line.

Each of the pixels is divided into a red subpixel (hereinafter referred to as “R subpixel”), a green subpixel (hereinafter referred to as “G subpixel”), and a blue subpixel (hereinafter referred to as “B subpixel”) for color implementation. can be divided. Each of the pixels may further include a white subpixel. Each of the subpixels 101 includes a pixel circuit. Hereinafter, pixel may be interpreted as having the same meaning as subpixel.

The pixel circuit includes a light emitting element, a driving element, one or more switch elements, and a capacitor, such as the examples in Figures 3 and 4. The driving element and switch element can be implemented as a TFT (Thin Film Transistor). It should be noted that the pixel circuit is not limited to FIGS. 3 and 4. For example, Figures 3 and 4 may illustrate a pixel circuit implemented based on a p-channel TFT, but the pixel circuit may also be implemented as a pixel circuit based on a known n-channel TFT. The pixel circuit is connected to the data line 102 and the gate line 103.

As shown in FIGS. 3 and 4, the display panel 100 includes a first power line 61 for supplying a pixel driving voltage (VDD) to the subpixels 101, and a reference voltage (61) for initializing the pixel circuit. It may further include a second power line 62 for supplying Vref) to the subpixels 101 and a VSS electrode for supplying a low-potential power supply voltage (VSS) to the pixels. The power lines 61 and 62 and the VSS electrode are connected to a power circuit not shown.

Touch sensors may be disposed on the display panel 100. Touch input can be sensed using separate touch sensors or sensed through pixels. Touch sensors can be implemented as on-cell type or add-on type touch sensors placed on the screen of the display panel or embedded in the pixel array. You can.

The display panel driving circuit includes a data driver 110 and a gate driver 120. The display panel driving circuit further includes a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

The display panel driving circuit writes pixel data (digital data) of the input image to the pixels of the display panel 100 under the control of a timing controller (Timing controller, TCON) 130. The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensors. The touch sensor driver is omitted in FIG. 1. In a mobile device, the display panel driving circuit, timing controller 130, and power circuit can be integrated into one drive IC (Integrated Circuit).

The display panel driving circuit may operate in a low-speed driving mode. The low-speed driving mode can be set to analyze the input image and reduce power consumption of the display device when the input image does not change by a preset number of frames. In other words, the low-speed driving mode can reduce power consumption by controlling the data writing cycle of pixels to be long by lowering the refresh rate of pixels when a still image is input for more than a certain period of time. The low-speed drive mode is not limited to when a still image is input. For example, when the display device operates in standby mode or when a user command or input image is not input to the display panel driving circuit for more than a predetermined period of time, the display panel driving circuit may operate in a low-speed driving mode.

The data driver 110 uses a DAC (Digital to Analog Converter) to convert the pixel data (digital data) of the input image received from the timing controller 130 every frame period into a gamma compensation voltage and the voltage of the data signal (hereinafter referred to as , called “data voltage”, Vdata) is generated. The data voltage Vdata is output through the output buffer AMP from each of the channels (CH1 and CH2 in FIG. 2) of the data driver 110.

The demultiplexer array 112 is disposed between the data driver 110 and the data lines 102 using a plurality of switch elements (M1 and M2 in FIG. 2) to generate a data voltage (Vdata) output from the data driver 110. ) is time-divided and distributed to the data lines 102.

The output buffer (AMP) connected to one channel in the data driver 110 may be connected to neighboring data lines 1021 to 1024 through the demultiplexer array 112, as shown in FIG. 2. The demultiplexer array 112 includes multiple demultiplexers 21 and 22 as shown in FIG. 2 .

The demultiplexers 21 and 22 may be 1:N demultiplexers with one input node and N output nodes (N is two or more positive integers). The demultiplexers 21 and 22 of the demultiplexer array 112 are illustrated as 1:2 demultiplexers in FIG. 2, but are not limited thereto. For example, each of the demultiplexers 21 and 22 of the demultiplexer array 112 is implemented as a 1:3 demultiplexer, so that one channel can be sequentially connected to three data lines in the data driver 110. The demultiplexer array 112 may be formed directly on the substrate of the display panel 100 or may be integrated into one drive IC together with the data driver 110.

Capacitors 51 to 54 are connected to each of the data lines 1021 to 1024, as shown in FIG. 2. The capacitors 51 to 54 sample and store the data voltage Vdata applied to the data lines 1021 to 1024 through the demultiplexers 21 and 22. The data voltage Vdata stored in the capacitors 51 to 54 is supplied to the pixel circuit of the subpixels 101. The capacitors 51 to 54 may be implemented as parasitic capacitances of the data lines 1021 to 1024 or as separate capacitors formed with a predetermined design value.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed directly on the bezel area (Bezel, BZ) of the display panel 100 along with the TFT array of the pixel array. The gate driver 120 outputs a gate signal to the gate lines 103 under the control of the timing controller 130. The gate driver 120 can sequentially supply the signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signal may include a scan signal for selecting pixels of a line on which data will be written, and an emission control signal (hereinafter referred to as an “EM signal”) that defines the emission time of the pixels charged with the data voltage.

The gate driver 120 may include a first gate driver 121 and a second gate driver 122. The first gate driver 121 outputs a scan signal and sequentially shifts the scan signal according to the shift clock. The second gate driver 122 outputs the EM signal EM and sequentially shifts the EM signal EM according to the shift clock. In the case of a model without a bezel, switch elements constituting the first and second gate drivers 121 and 122 may be distributed in a pixel array.

The timing controller 130 receives digital video data (DATA) of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and a data enable signal (DE in FIG. 6). Since the vertical period and horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync) can be omitted. The data enable signal (DE) has a period of 1 horizontal period (1H). The host system may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, and a mobile device system.

The timing controller 130 multiplies the input frame frequency by i times and controls the operation timing of the display panel drivers 110, 112, and 120 with a frame frequency of input frame frequency x i (i is a positive integer greater than 0) Hz. You can. The input frame frequency is 60Hz in the NTSC (National Television Standards Committee) method and 50Hz in the PAL (Phase-Alternating Line) method. The timing controller 130 may lower the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower the refresh rate of pixels in a low-speed driving mode.

The timing controller 130 controls the data timing control signal for controlling the operation timing of the data driver 110 and the operation timing of the demultiplexer array 112 based on the timing signals (Vsync, Hsync, DE) received from the host system. MUX signals (MUX1, MUX2) for this purpose and a gate timing control signal for controlling the operation timing of the gate driver 120 are generated. The data timing signal includes a source output enable signal (Source output enable, SOE) shown in FIG. 7. The data driver 110 simultaneously outputs the data voltage (Vdata) during the low logic section between pulses of the source output enable signal (SOE) in each channel, while the data voltage (Vdata) of the source output enable signal (SOE) is simultaneously output. The data voltage (Vdata) is not output in the pulse, that is, high logic section.

The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120. The level shifter converts the low level voltage of the gate timing control signal to the gate low voltage (VGL) and the high level voltage of the gate timing control signal to the gate high voltage (VGH). .

The present invention uses the switch elements (M1, M2) of the demultiplexer array 112 to connect the channels of the data driver 110 or between the data lines 1021 to 1024 during the charge share period set before the charging period of the data lines. Charge share can be implemented. Additionally, the present invention can use a separate charge share circuit to perform charge share during a charge share period set before the charging period (t2, t3) of the data lines. Hereinafter, the first time t1 represents a charge share period, and the second and third times t2 and t3 represent charging periods of data lines in which data voltages are sequentially charged to neighboring data lines.

When the channels (CH1 to CH4) of the data driver 110 are connected or the data lines (1021 to 1024) are connected, the voltages of the channels (CH1 to CH4) or the data lines (1021 to 1024) are averaged to produce a data voltage. After the transition width of (Vdata) is reduced, it can rise to the target voltage of the pixel data in a short period of time, resulting in effects such as reduced power consumption, reduced coupling ripple, and reduced ON time of the demultiplexer. You can get it.

As shown in FIG. 2, it may include a charge share circuit disposed within the drive IC including the data driver 100 or on the display panel 100. The charge sharing circuit may include a charge sharing unit 41 connected between the data driver 110 and the input nodes of the demultiplexer array 112. Additionally, the charge sharing circuit may include a charge sharing unit 42 connected between the output nodes of the demultiplexer array 112 and the data lines 1021 to 1024.

The charge sharing units 41 and 42 connect the channels CH1 and CH2 of the data driver 102 before the switch elements M1 and M2 of the demultiplexer array 112 are turned on. Consumption is achieved by connecting the data lines (1021 to 1024) to reduce the transition width of the data voltage (Vdata) between the odd pixel lines (L1, L3,...Ln-1) and the even pixel lines (L2, L4,...Ln). It is possible to obtain effects such as power reduction, coupling ripple reduction, and ON time reduction of the demultiplexer switches (M1, M2).

When the switch elements of the charge sharing unit 41 are turned on, the channels (CH1, CH2) of the data driver 112 connected to the switch elements are connected to each other, and the voltages of the data lines connected to the channels are averaged. The transition width of the data voltage (Vdata) may be reduced. When the switch elements of the charge sharing unit 42 are turned on, the data lines connected to the switch elements are connected to each other and the voltages of the data lines are averaged, thereby reducing the transition width of the data voltage Vdata.

3 and 4 are circuit diagrams showing examples of pixel circuits applicable to embodiments of the present invention. The pixel circuits shown in FIGS. 3 and 4 are examples of an internal compensation circuit that senses the threshold voltage (Vth) of the driving element and compensates the data voltage (Vdata) by the threshold voltage (Vth). The internal compensation circuit is built into each pixel circuit and samples the threshold voltage of the driving element, which changes according to the electrical characteristics of the driving element in each pixel circuit, and compensates the data voltage in real time by the threshold voltage of the driving element. It should be noted that the present invention is not limited to the pixel circuit shown in Figures 3 and 4. For example, the pixel circuit of the present invention can be applied as an internal compensation circuit that senses the mobility (μ) of the driving element and compensates the data voltage (Vdata) by the mobility.

Referring to FIG. 3, an example of a pixel circuit includes a light emitting element (EL), a plurality of transistors (T1 to T5, DT), a capacitor (Cst), etc. The transistors T1 to T5 and DT may be implemented as p-channel transistors (PMOS) as shown in FIG. 3, but are not limited thereto. The transistors T1 to T5 include switch elements T1 and T5 and a driving element DT.

The switch elements (T1 to T5) are turned on/off according to the gate signal from the gate lines (31 to 33) to initialize the pixel circuit, and then connect the source and drain of the driving element (DT) to generate the data voltage (Vdata). is supplied to the capacitor (Cst). And the switch elements (T1 to T5) switch the current pass between the driving element (DT) and the light emitting element (DT). When the gate and drain of the driving element (DT) are connected, the driving element (DT) operates in the form of a diode, so that the gate-source voltage of the driving element (DT) rises to the threshold voltage of the driving element (DT), The threshold voltage of DT) is sampled on the capacitor (Cst).

The light emitting element (EL) can be implemented as OLED. OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the fourth and fifth switch elements (T4 and T5) through the fourth node (n4). The cathode of the OLED is connected to the VSS electrode to which a low-potential power supply voltage (VSS) is applied. The driving element (DT) supplies current to the OLED to drive the OLED. OLED emits light with a current controlled by the driving element (DT) according to the data voltage (Vdata). The current path of the OLED is switched by the fourth switch element (T4).

The capacitor Cst is connected between the first node n1 and the second node n2. The first node n1 is connected to the second electrode of the first switch element T1, the first electrode of the third switch element T3, and the first electrode of the capacitor Cst. The second node n2 is connected to the second electrode of the capacitor Cst, the gate of the driving element DT, and the first electrode of the second switch element T2. The compensated data voltage (Vdata) is charged to the capacitor (Cst) by the threshold voltage (Vth) of the sampled driving element (DT). Therefore, since the data voltage Vdata in each of the subpixels 101 is compensated by the threshold voltage Vth of the driving element DT, the threshold voltage deviation of the driving element DT in the subpixels 101 is compensated. It can be.

The first switch element T1 supplies the data voltage Vdata to the first node n1 in response to the first scan signal SCAN1. The first switch element T1 includes a gate connected to the first gate line 31, a first electrode connected to the data line 21, and a second electrode connected to the first node n1. The first scan signal SCAN1 is applied to the subpixels 101 through the first gate line 31. The first scan signal (SCAN1) is generated as a pulse of the gate-on voltage (VGL), the data voltage (Vdata) is applied to the capacitor (Cst), and the threshold voltage of the driving element (DT) is applied to the capacitor. Defines the sampling time in (Cst). The pulse width of the first scan signal SCAN1 may be set to 1 horizontal period (1H) or less as shown in FIG. 6.

The second switch element T2 connects the gate of the driving element DT to the second electrode in response to the second scan signal SCAN2, thereby causing the driving element DT to operate as a diode. The second switch element T2 includes a gate connected to the second gate line 32, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The pulse of the second scan signal SCAN2 is inverted to the gate-on voltage before the first scan signal SCAN1 and is inverted to the gate-off voltage at the same time as the first scan signal SCAN1. The pulse width of the second scan signal SCAN2 may be set to 1 horizontal period (1H) or less.

The third switch element T3 supplies a predetermined reference voltage (Vref) to the first node (n1) in response to the EM signal (EM). The reference voltage Vref is supplied to the subpixels 101 through the second power line 62. The third switch element T3 includes a gate connected to the third gate line 33, a first electrode connected to the first node n1, and a second electrode connected to the second power line 62. The EM signal (EM) defines the on/off time of the light emitting element (EL). The pulse of the EM signal (EM) may be generated as a gate-off voltage to block light emission of the light emitting element (EL). The EM signal EM is inverted to the gate-off voltage when the first scan signal (SCAN1) is inverted to the gate-on voltage, and the gate-on voltage is inverted after the first and second scan signals (SCAN1 and SCAN2) are inverted to the gate-off voltage. It can be inverted into voltage.

The fourth switch element T4 switches the current path of the light emitting element EL in response to the EM signal EM. The gate of the fourth switch element T4 is connected to the third gate line 33. The first electrode of the fourth switch element T4 is connected to the third node n3, and the second electrode of the fourth switch element T4 is connected to the fourth node n4.

The fifth switch element T5 supplies the reference voltage Vref to the fourth node n4 connected to the anode of the light emitting element EL in response to the second scan signal SCAN2. The fifth switch element T5 includes a gate connected to the second gate line 32, a first electrode connected to the second power line 62, and a second electrode connected to the fourth node n4.

The driving element DT drives the light emitting element EL by controlling the current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the second node n2, a first electrode connected to the first power line 61, and a second electrode connected to the third node n3. The pixel driving voltage (VDD) is supplied to the pixels through the first power line 61.

Referring to FIG. 4, another example of a pixel circuit includes a light emitting element (EL), a plurality of TFTs (T11 to T16, DT), a capacitor (Cst), etc. The TFTs (T11 to T16, DT) may be implemented as p-channel TFTs (PMOS), but are not limited to this. The gate signal applied to this pixel circuit includes the N-1th scan signal (SCAN(N-1)), the Nth scan signal (SCAN(N)), and the EM signal (EM(N)). N is a positive integer. The N-1th scan signal (SCAN(N-1)) is synchronized with the data voltage (Vdata) of the N-1th pixel line, and the Nth scan signal (SCAN(N)) is the data voltage (Vdata) of the Nth pixel line. Vdata). The Nth scan signal (SCAN(N)) is generated with the same pulse width as the N-1th scan signal (SCAN(N-1)) and is shifted from the N-1th scan signal (SCAN(N-1)).

The capacitor Cst is connected between the first node n1 and the second node n2. The pixel driving voltage (VDD) is supplied to the pixel circuit through the first power line 61. The first node n1 is connected to the first power line 61, the first electrode of the third switch element T13, and the first electrode of the capacitor Cst. The second node n2 is connected to the second electrode of the capacitor Cst, the gate of the driving element DT, the first electrode of the first switch element T11, and the first electrode of the fifth switch element T15. do.

The first switch element T11 connects the gate of the driving element DT to the second electrode in response to the Nth scan signal SCAN(N). The first switch element T11 includes a gate connected to the first gate line 34, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The Nth scan signal SCAN(N) is applied to the pixel circuit through the first gate line 34. The third node n3 is connected to the gate of the driving element DT, the second electrode of the first switch element T11, and the first electrode of the fourth switch element T14.

The second switch element T12 applies the data voltage Vdata to the first electrode of the driving element DT in response to the Nth scan signal SCAN(N). The second switch element T12 includes a gate connected to the first gate line 34, a first electrode connected to the fifth node n5, and a second electrode connected to the data line 1021. The fifth node n5 is connected to the first electrode of the driving element DT, the first electrode of the second switch element T12, and the second electrode of the third switch element T13.

The third switch element T13 applies the pixel driving voltage VDD to the first electrode of the driving element DT in response to the EM signal EM(N). The third switch element T13 includes a gate connected to the third gate line 36, a first electrode connected to the first power line 61, and a second electrode connected to the fifth node n5. The EM signal EM(N) is applied to the pixel circuit through the third gate line 36.

The fourth switch element T14 connects the second electrode of the driving element DT to the anode of the light emitting element EL in response to the EM signal EM(N). The gate of the fourth switch element T14 is connected to the third gate line 36. The first electrode of the fourth switch element T14 is connected to the third node n3, and the second electrode of the fourth switch element T14 is connected to the fourth node n4. The fourth node n4 is connected to the anode of the light emitting element EL, the second electrode of the fourth switch element T14, and the second electrode of the sixth switch element T16.

The fifth switch element T15 connects the second node n2 to the second power line 62 in response to the N-1 scan signal SCAN(N-1). The reference voltage Vini is applied to the pixel circuit through the second power line 62. The fifth switch element T15 includes a gate connected to the second gate line 35, a first electrode connected to the second node n2, and a second electrode connected to the second power line 62.

The sixth switch element T16 connects the second power line 62 to the anode of the light emitting element EL in response to the Nth scan signal SCAN(N). The sixth switch element T16 includes a gate connected to the first gate line 34, a first electrode connected to the second power line 62, and a second electrode connected to the anode of the light emitting element EL.

The driving element DT drives the light emitting element EL by controlling the current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the second node n2, a first electrode connected to the fifth node n5, and a second electrode connected to the third node n3.

VDD, VSS, and Vini may be direct current voltages of VDD = 7V~8V, VSS = 0V, and Vini = 1V, but are not limited thereto. Vdata may be a voltage between 0V and 5V output from the data driver 110, but is not limited to this.

In the display device of the present invention, as shown in FIG. 5, two left and right neighboring subpixels 101A and 101B on the N-th pixel line share one output buffer (AMP) to provide the channel of the data driver 110. The number can be reduced.

FIG. 6 is a waveform diagram showing driving signals of the subpixels shown in FIG. 5. In FIG. 6, “x” is an invalid section in which the data voltage (Vdata) of pixel data is not output from the data driver 110.

Referring to FIGS. 5 and 6 , in the first step (S1), a first MUX signal (MUX1) that is synchronized with the first pixel data voltage (D1(N)) is generated. In the first step (S1), the first switch element (M1) of the demultiplexer is turned on so that the output buffer (AMP) is connected to the first data line (1021). At this time, the first pixel data voltage D1(N) is stored in the capacitor 51 of the first data line 1021.

In the second step (S2), a second MUX signal (MUX2) that is synchronized with the second pixel data voltage (D2(N)) is generated. In the second step (S2), the second switch element (M2) of the demultiplexer is turned on so that the output buffer (AMP) is connected to the second data line (1022). At this time, the second pixel data voltage D2(N) is stored in the capacitor 52 of the second data line 1022.

In the third step (S3), the second scan signal (SCAN2(N)) is inverted to the gate-on voltage and the second and fifth switch elements (T2, T5) are turned on to turn on the first and fourth nodes ( n1, N4) are initialized to the reference voltage (Vref). In the third step (S2), the MUX signals (MUX1, MUX2) are inverted to the gate-off voltage so that the switch elements (M1, M2) of the demultiplexer are turned off.

In the fourth step (S4), while the second and fifth switch elements T2 and T5 are maintained in the on state, the first scan signal SCAN1(N) is inverted to the gate-on voltage to switch the first switch element T2 and T5. (T1) is turned on, the data voltage (Vdata) is applied to the capacitor (Cst), and the threshold voltage of the driving element (DT) is applied to the capacitor (Cst). Accordingly, in the fourth step (S4), the data voltage (Vdata) compensated by the threshold voltage of the driving element (DT) is sampled in the capacitor (Cst). At this time, the threshold voltage (Vth) of the driving element (DT) in the subpixels (101A, 101B) is sampled simultaneously, and the driving element (DT) for driving the light emitting element (EL) of the subpixels (101A, 101B) is sampled simultaneously. ) The gate-source voltage is set.

In the fifth step (S5), the EM signal (EM(N)) is inverted to the gate-on voltage, and the current generated according to the voltage between the gate and source of the driving element (DT) flows to the light emitting element (EL). EL) emits light.

Figures 7 and 8 are diagrams showing the connection structure of the data driver, demultiplexer, and pixel array according to the first embodiment of the present invention. 7 and 8, R, G, and B are the colors of the subpixels, and the numbers “255” and “0” in the subpixels 101 are the gray scale level of the pixel data. For example, R (255) represents an R subpixel and R pixel data with a grayscale value of 255.

Referring to FIGS. 7 and 8 , each of the channels CH1 to CH6 of the data driver 110 includes an output switch element S1 connected between the output buffer AMP and the demultiplexer array 112. The output switch element S1 is turned on during the low logic period between high logic pulses of the source output enable signal SOE from the timing controller 130 to supply the data voltage Vdata to the input of the demultiplexer array 112. Supply to nodes. On the other hand, the output switch element (S1) is turned off during the high logic pulse section of the source output enable signal (SOE) to set the data voltage (Vdata) between the data voltage (Vdata) and the input node of the demultiplexer array (112). Block it. In Figure 8, the turned-on output switch element S1 is omitted.

The color arrangement of the pixel array shown in FIG. 7 is an example of a pentile pixel arrangement, but the present invention is not limited thereto. In the pixel array of Pendo 7, subpixels ( 1O1) can be deployed. The subpixels 1O1 may be arranged in the order of B subpixel, G subpixel, R subpixel, and G subpixel from left to right in the even-numbered pixel lines L2, L4, and Ln. In the case of pentile pixel arrangement, two neighboring sub-pixels may form one pixel. The tile pixel rendering algorithm compensates for the lack of color expression in each pixel with the color of light emitted from adjacent pixels.

The example in FIG. 7 is an example in which a pixel array represents a white image. In a white image, the grayscale value of the pixel date in each of the R subpixel, G subpixel, and B subpixel is white grayscale, that is, 255. The example in FIG. 8 is an example in which a pixel array represents a yellow image. In a yellow image, the gray level value of pixel data in the R subpixel and G subpixel is 255, while the gray level value of B pixel data written in the B subpixel is 0, which is the black gray level value.

If charge sharing is not performed, the data voltage charge amount of subpixels may decrease depending on the pixel data of the input image, and the charge amount difference between neighboring subpixels or between pixel columns may increase, resulting in uneven luminance. Additionally, if charge sharing is not performed, the data transition width between neighboring pixel lines may increase, causing coupling ripple, especially VSS ripple, to cause uneven luminance between pixel lines.

When displaying a yellow image on a pixel array as shown in FIG. 8, the first pixel column 81 includes only G subpixels in which pixel data with a grayscale value of 255 is written. The second pixel column 82 includes R subpixels and B subpixels arranged alternately. When displaying a yellow image on a pixel array, pixel data with a gray level value of 255 is written into the R subpixels, and pixel data with a gray level value of 255 is written into the B subpixels.

In the case of the first pixel column 81, the charging amount of the subpixels is uniform, so no luminance difference or VSS ripple occurs. This is because the G subpixels charge the data voltage up to the target voltage in a short period of time without a transition of pixel data between the G subpixels adjacent above and below in the first pixel column 81.

On the other hand, in the case of the second pixel column 82, if charge sharing is not performed, the transition width of pixel data between upper and lower neighboring subpixels is large, so the charge amount of the R and B subpixels is insufficient, and the data voltage (Vdata) When changes occur, VSS ripple occurs due to coupling. In the case of the second pixel column 82, when the resolution of the display device increases or the driving frequency increases and the on-time of the demultiplexer array 112 decreases, if charge sharing is not performed, the amount of charge in the R and B subpixels decreases. VSS ripple becomes worse.

If charge sharing is not performed, the difference in charging characteristics of subpixels between the first and second pixel columns 81 and 82 is large, so a luminance difference may be visible in the two neighboring columns 81 and 82. The G subpixels can charge the data voltage up to the target voltage in a short time without data transition between the vertically neighboring G subpixels in the first pixel column 81. On the other hand, the transition width of the data voltage between the vertically neighboring R and B subpixels in the second pixel column 82 is large, so the target voltage of the data voltage may not be charged.

FIG. 9 is a diagram quantitatively showing the transition width when charge sharing is not performed when displaying a yellow image as in FIG. 8. In FIG. 9, R -> B is a case where R pixel data of an odd pixel line (Odd line) changes to B pixel data of an even pixel line (Even line). Figure 9 shows that the transition width of the pixel data voltage is the largest when changing from gray level 0 to gray level 255 and vice versa. This is an example where the transition width at this time is converted to 100. Hereinafter, the standard transition width refers to an example in which the transition width is 100. If there is no charge share, when changing from pixel data of an odd pixel line (Odd line) to pixel data of an even pixel line (Even line), the transition width of the charge share section is the same as the transition width of the odd pixel line (Odd line). Assuming that the power consumption at this time is 100%, if charge sharing is performed, the transition width of pixel data is reduced, so power consumption and charging characteristics of subpixels can be improved.

Figure 10 is a waveform diagram showing a charge share section. The first time (t1) set as the charge share period is the Nth pixel data voltage ((N-1)th Data) and the Nth pixel data voltage (Nth) continuously applied through the same data line as shown in FIG. 10. It is the section between Data)). The Nth pixel data voltage ((N-1)th Data) is the voltage of the pixel data to be written in the subpixel of the Nth pixel line, and the Nth pixel data voltage (Nth Data) is the voltage of the subpixel of the Nth pixel line. This is the voltage of the pixel data to be written. The first time t1 may be set within the pulse width section of the source output enable signal SOE. If charge sharing is performed when the transition width between the Nth pixel data voltage ((N-1)th Data) and the Nth pixel data voltage (Nth Data) is 100, the transition width of the pixel data can be reduced to 50. there is. The effect of reducing the transition width may vary depending on the average voltage of interconnected channels or data lines.

Figure 11 is a waveform diagram showing the charge sharing method according to the first embodiment of the present invention. This embodiment can perform charge sharing between data lines using the demultiplexer array 112 without a charge sharing circuit.

The charge sharing method according to the first embodiment of the present invention includes a data driver that outputs a data voltage through the first and second channels (CH1, CH2), 1-1 and 2-1 switch elements (M1, A first demultiplexer 21 that distributes the data voltage output through the first channel CH1 to the first and second data lines using M2), 1-2 and 2-2 switch elements M1 , M2) to distribute the data voltage output through the second channel (CH2) to the third and fourth data lines 1023 and 1024, and first and second demultiplexers ( A control unit that controls the first and second demultiplexers 21 and 22 by generating control signals (MUX1 and MUX2) for controlling the on/off of the switch elements 21 and 22 (21, 22), that is, timing Includes a controller 130. All switch elements (M1, M2) of the first and second demultiplexers (21, 22) are turned on simultaneously during the charge sharing period set to the first time (t1) to turn on the first and second data lines (1021). , 1022). At the second time t2, the 1-1 and 1-2 switch elements S1 are simultaneously turned on, so that the first channel CH1 is connected to the first data line 1021 and at the same time the second channel (CH1) is connected to the first data line 1021. CH2) is connected to the third data line (1023). Subsequently, at the third time t3, the 2-1 and 2-2 switch elements S2 are simultaneously turned on, so that the first channel CH1 is connected to the second data line 1022 and at the same time, the first channel CH1 is connected to the second data line 1022. Channel 2 (CH2) is connected to the fourth data line 1024. After the data voltage is charged in the data lines (1021 to 1024), the threshold voltage of the driving element (DT) is simultaneously sampled from the left and right neighboring subpixels, and the light emitting elements are driven with a data voltage compensated by the threshold voltage. .

Referring to FIGS. 8, 10, and 11, the timing controller 130 simultaneously generates the first and second MUX signals (MUX1 and MUX2) as gate-on voltages during the charge sharing period to generate the gate-on voltage of the demultiplexer array 112. The switch elements M1 and M2 are turned on simultaneously.

During the first time t1, the first pulses 111 and 112 of the first and second MUX signals MUX1 and MUX2 are simultaneously generated as the gate-on voltage VGL. During the first time t1, all switch elements M1 and M2 of the demultiplexer array 112 are turned on simultaneously. The first demultiplexer 21 connects the first and second data lines 1021 and 1022 for a first time t1. At this time, the voltage of the first and second data lines 1021 and 1022 changes to the average voltage of the data voltage Vdata applied to each of the first and second data lines 1021 and 1022, resulting in a transition of the data voltage. Width may be reduced. The second demultiplexer 22 connects the third and fourth data lines 1023 and 1024 for a first time t1. At this time, the voltage of the third and fourth data lines 1023 and 1024 changes to the average voltage of the data voltage Vdata applied to each of the third and fourth data lines 1023 and 1024, resulting in a transition of the data voltage. Width may be reduced.

After the first time t1, the second pulses 113 and 114 of the first and second MUX signals MUX1 and MUX2 are sequentially generated as the gate-on voltage VGL to increase the data voltage of the Nth pixel line. Time division is distributed to the data lines (1021 to 1024). During the second time t2, the second pulse 113 of the first MUX signal MUX1 is generated as the gate-on voltage VGL and the first switch element M1 is turned on. At this time, the first pixel data voltage D1(N) is charged in the capacitor 51 of the first data line 1021 through the first switch element M1. Subsequently, during the third time t3, the second pulse 114 of the second MUX signal MUX2 is generated as the gate-on voltage VGL and the second switch element M2 is turned on. At this time, the second pixel data voltage D2(N) is charged in the capacitor 52 of the second data line 1022 through the second switch element M2. The second time t2 is the same as the first step S1 in FIG. 6, and the third time t3 is the same as the second step S2 in FIG. 6.

When subpixels neighboring left and right in the N pixel line are referred to as first and second subpixels, the first pixel data voltage D1(N) is the data voltage to be supplied to the first subpixel, and the second pixel data The voltage D2(N) is a data voltage to be supplied to the second subpixel.

In the first embodiment, charge sharing is possible in each of the first and second demultiplexers 21 and 22, and charge sharing is not possible between the first and second demultiplexers 21 and 22. For this reason, in the first embodiment, charge share may be limited in some color images. For example, as shown in FIG. 8, when a yellow image is displayed on a pixel array, charge sharing is performed on each of the first and second column pixels 81 and 82, but between the column pixels 81 and 82. Since the data lines 1021 to 1024 are not connected, charge sharing does not occur between the column pixels 81 and 82.

In FIG. 8 , when the first and second pixel groups 83 and 84 include two left and right neighboring subpixels, the charge share voltage of the first pixel group 83 is (255+255) according to the first embodiment. )/2, so there is no charge share effect. Therefore, since the voltage at the first time (t1) between changing from the N-1th pixel data voltage to be applied to the first pixel group 83 to the N-th pixel data voltage is equal to the N-1th pixel data voltage, the pixel data Transitions do not decrease.

According to the first embodiment, the charge share voltage of the second pixel group 84 is (0+255)/2, so the transition width of the pixel data voltage is reduced to 50.

FIG. 12 is a diagram quantitatively showing the effect of improving the transition width of the data voltage by implementing the charge share method of the first embodiment when displaying a yellow image on a pixel array as shown in FIG. 8. In this embodiment, the transition width of the pixel data voltage in some pixels of the pixel array is reduced to 50 compared to the reference transition width of 100 during the first time t1 and then changes to the target voltage of the next data voltage. FIG. 13 shows changes in the transition width of the data voltage (V 1022 ) applied to the second data line ₁₀₂₂ and the data voltage (V 1022 ) applied to the third data line (V ₁₀₂₃ ) in the pixel array as shown in FIG. 8. give. The first embodiment can improve the charging characteristics and power consumption of subpixels because the transition width of the data voltage is reduced compared to the case where charge sharing is not performed.

Figure 14 is a diagram showing a charge share circuit connected between channels of the data driver. Figures 15a and 15b are waveform diagrams showing the charge sharing method according to the second embodiment of the present invention. Figure 15a shows Embodiment 2-1 in which the pulse of the CS signal defining the charge share section is generated simultaneously with the pulse of the first and second MUX signals (MUX1 and MUX2). Figure 15b shows Example 2-2 in which the first pulse of the CS signal is generated simultaneously with the pulse of the first MUX signal (MUX1), and the second pulse of the CS signal is generated simultaneously with the pulse of the second MUX signal (MUX2). Show it.

Referring to FIGS. 14 to 15B, the charge sharing circuit includes a plurality of charge sharing switch elements (hereinafter referred to as “CS SW”, S21 to S23) for connecting channels (CH1 to CH6) of the data driver 110. ) includes.

The CS SWs (S21 to S23) are disposed in the IC in which the data driver 110 is integrated and can be turned on/off simultaneously under the control of the timing controller 130. The timing controller 130 generates a CS signal to control the CS SWs (S21 to S23).

The first CS SW (S21) is connected between the first and second channels (CH1 and CH2). The first CS SW (S21) is turned on when the CS signal shown in FIGS. 15A and 15B is the gate-on voltage (VGL). When the first CS SW (S21) is turned on, the first and second channels (CH1, CH2) are connected to each other, so that the average voltage of the first and second channels (CH1, CH2) is equal to that of the first and second channels. are set to CH1 and CH2, and this average voltage is set as the charge share voltage of the first to fourth data lines 1021 to 1024.

The second CS SW (S22) is connected between the third and fourth channels (CH3 and CH4). The second CS SW (S22) is turned on when the CS signal shown in FIGS. 15A and 15B is the gate-on voltage (VGL). When the second CS SW (S22) is turned on, the third and fourth channels (CH3, CH4) are connected to each other, so that the average voltage of the third and fourth channels (CH3, CH4) is equal to that of the third and fourth channels. are set to CH3 and CH4, and this average voltage is set as the charge share voltage of the fifth to eighth data lines 1025 to 1028.

The second embodiment of the present invention can be divided into Example 2-1 and Example 2-2.

14 and 15A, in Example 2-1, all switch elements (M1, M2) and CS SW (S21) of the first and second demultiplexers (21, 22) at the first time (t1) It turns on at the same time. During the first time t2, the pulse 151 of the CS signal, the first pulse 152 of the first MUX signal (MUX1), and the first pulse 153 of the second MUX signal (MUX2) are simultaneously gate-on. The voltage VGL is generated so that the switch elements M1, M2, and S2 are turned on simultaneously. At this time, the first to fourth data lines 1021 to 1024 are connected to each other through the demultiplexers 21 and 22 and CS SW (S21), and the average voltage applied to the data lines 1021 to 1024 is Voltage is stored in data lines 1021 to 1024. At this time, the data lines 1021 to 1024 connected to the first pixel group 401 are connected to each other, so that the average voltage of the voltage applied to the data lines 1021 to 1024 is applied to the data lines 1021 to 1024. It is saved. At the same time, the data lines 1025 to 1028 connected to the second pixel group 402 are connected to each other, and the average voltage of the voltage applied to the data lines 1025 to 1028 is stored in the data lines 1025 to 1028. do. The first pixel group 401 includes subpixels that charge the data voltage Vdata output through the first and second channels CH1 and CH2 of the data driver 110. The second pixel group 402 includes subpixels that charge the data voltage Vdata output through the third and fourth channels CH3 and CH4 of the data driver 110. Accordingly, during the charge sharing period, the voltage of the data lines 1021 to 1028 may change to the average voltage, thereby reducing the transition width of the data voltage Vdata applied to the data lines 1021 to 1028. Since an average voltage is applied to the data lines for each pixel group during the charge share period, the charge share voltage for each pixel group can be optimized.

After the first time t1, the second pulses 154 and 155 of the first and second MUX signals MUX1 and MUX2 are sequentially generated as the gate-on voltage VGL, thereby increasing the data voltage of the N-th pixel line ( D1(N) and D2(N)) are time-divided and distributed to the data lines 1021 to 1028. During the second time t2, the second pulse 154 of the first MUX signal MUX1, which is synchronized with the first pixel data voltage D1(N), is generated as the gate-on voltage VGL to activate the first switch element. (M1) is turned on. At this time, the first pixel data voltage D1(N) is charged in the capacitor 51 of the first data line 1021 through the first switch element M1. Subsequently, during the third time t3, the second pulse 155 of the second MUX signal MUX2, which is synchronized with the second pixel data voltage D2(N), is generated as the gate-on voltage VGL, thereby generating the second pulse 155. The switch element (M2) is turned on. At this time, the second pixel data voltage D2(N) is charged in the capacitor 52 of the second data line 1022 through the second switch element M2.

Referring to FIGS. 14 and 15B, in Example 2-2, the charge sharing period is the 1-1 time (t11) when the first switch element (M1) and CS SW (S21, S22, and S23) are simultaneously turned on. and a 1-2nd time (t12) in which the second switch element (M2) and CS SW (S21, S22, S23) are simultaneously turned on.

During the 1-1 time (t11), the first pulse 161 of the CS signal and the first pulse 162 of the first MUX signal (MUX1) are simultaneously generated as the gate-on voltage (VGL) and the first switch elements (M1) and CS SWs (S21, S22, S23) are turned on simultaneously. At this time, the odd-numbered data lines (1021, 1023, 1025, and 1027) are connected to each other through switch elements (M1, S21, S22, and S23) and applied to these data lines (1021, 1023, 1025, and 1027). The average voltage is stored in the data lines 1021, 1023, 1025, and 1027. Therefore, during the 1-1 time t11, the voltage of the odd-numbered data lines 1021, 1023, 1025, and 1027 changes to the average voltage, and the data voltage applied to these data lines 1021, 1023, 1025, and 1027 The transition width of (Vdata) may be reduced.

During the 1-2 time (t12), the second pulse 1613 of the CS signal and the first pulse 164 of the second MUX signal (MUX2) are simultaneously generated as the gate-on voltage (VGL) to activate the second switch elements ( M2) and CS SWs (S21, S22, S23)) are turned on simultaneously. At this time, the even-th data lines (1022, 1024, 1026, and 1028) are connected to each other through switch elements (M2, S21, S22, and S23) and applied to these data lines (1022, 1024, 1026, and 1028). The average voltage is stored in the data lines 1022, 1024, 1026, and 1028. Therefore, during the 1-2 time t12, the voltage of the even-th data lines 1022, 1024, 1026, and 1028 changes to the average voltage, and the data voltage applied to the data lines 1022, 1024, 1026, and 1028 The transition width of (Vdata) may be reduced.

After the charge share period (t11, t12), the second pulses (165, 166) of the first and second MUX signals (MUX1, MUX2) are sequentially generated as the gate-on voltage (VGL) and the data of the Nth pixel line The voltages D1(N) and D2(N) are distributed in time division to the data lines 1021 to 1028. During the second time t2, the second pulse 165 of the first MUX signal MUX1, which is synchronized with the first pixel data voltage D1(N), is generated as the gate-on voltage VGL to activate the first switch element. (M1) is turned on. At this time, the first pixel data voltage D1(N) is charged in the capacitor 51 of the first data line 1021 through the first switch element M1. Subsequently, during the third time t3, the second pulse 166 of the second MUX signal MUX2, which is synchronized with the second pixel data voltage D2(N), is generated as the gate-on voltage VGL, thereby generating the second pulse 166. The switch element M2 is turned on. At this time, the second pixel data voltage D2(N) is charged in the capacitor 52 of the second data line 1022 through the second switch element M2.

Charge share according to the second embodiment of the present invention may operate in the same way as the third and fourth embodiments.

Figure 16 is a diagram showing a charge share circuit disposed on the substrate of the display panel. Figure 17 is a waveform diagram showing the charge sharing method according to the third embodiment of the present invention.

Referring to FIGS. 16 and 17 , the charge share circuit may be disposed on the substrate of the display panel 100 along with the pixel array. This charge share circuit includes CS SWs (S31 to S36) for connecting data lines (1021 to 1028) during the charge share period.

CS SWs (S31 to S36) can be turned on/off simultaneously under the control of the timing controller 130. The timing controller 130 generates a CS signal to control the CS SWs (S31 to S36).

Each of the CS SWs (S31 to S36) connects neighboring odd-numbered data lines and even-numbered data lines during the charge share period. The first CS SW (S31) is connected between the first and second data lines 1021 and 1022 and operates on the first and second data lines ( 1021 and 1022) are connected, and are turned off for the second and third times (t2 and T3) to separate the first and second data lines 1021 and 1022. The second CS SW (S32) is connected between the second and third data lines 1022 and 1023 and operates on the second and third data lines (S32) at the first time t1 under the control of the timing controller 130. 1022 and 1023) are connected, and are turned off for the second and third times (t2 and T3) to separate the second and third data lines (1022 and 1023). The third CS SW (S33) is connected between the third and fourth data lines 1023 and 1024 and operates on the third and fourth data lines (S33) at the first time t1 under the control of the timing controller 130. 1023 and 1024) are connected, and are turned off for the second and third times (t2 and T3) to separate the third and fourth data lines 1023 and 1024.

Looking at the charge sharing operation of the data lines (1021 to 1024) connected to the first channel (CH1), the data lines (1021 to 1023) are transmitted through the CS SWs (S31, S32, and S33) at the first time (t1). ) is connected to the charge share, the average voltage of the voltage applied to the data lines (1021 to 1024) is applied to the data lines (1021 to 1024). During the second and third times t2 and T3, the data lines 1021 to 1024 are separated from each other and different data voltages Vdata are independently applied to the data lines 1021 to 1024.

CS SWs (S31 to S36) are turned on when the CS signal is the gate-on voltage (VGL). At the first time t1, the pulse 171 of the CS signal is generated as the gate-on voltage VGL, and the CS SWs S31 to S36 are simultaneously turned on. At this time, the data lines 1021 to 1024 connected to the first pixel group 601 are connected to each other, so that the average voltage of the voltage applied to the data lines 1021 to 1024 is applied to the data lines 1021 to 1024. It is saved. At the same time, the data lines 1025 to 1028 connected to the second pixel group 602 are connected to each other, and the average voltage of the voltage applied to the data lines 1025 to 1028 is stored in the data lines 1025 to 1028. do. The first pixel group 601 includes subpixels that charge the data voltage Vdata output through the first and second channels CH1 and CH2 of the data driver 110. The second pixel group 602 includes subpixels that charge the data voltage Vdata output through the third and fourth channels CH3 and CH4 of the data driver 110. Accordingly, during the charge sharing period, the voltage of the data lines 1021 to 1028 may change to the average voltage, thereby reducing the transition width of the data voltage Vdata applied to the data lines 1021 to 1028. Since an average voltage is applied to the data lines for each pixel group during the charge share period, the charge share voltage for each pixel group can be optimized. When a yellow image is displayed on the pixel array, the charge share voltage, that is, the average voltage, may be {(255*3)+0}/4. At the first time t1, the voltages of all data lines 1021 to 1028 are set to the average voltage.

After the first time t1, the pulses 172 and 173 of the first and second MUX signals MUX1 and MUX2 are sequentially generated as the gate-on voltage VGL, thereby increasing the data voltage D1 ( N) and D2(N)) are time-divided and distributed to the data lines (1021 to 1028). During the second time t2, the pulse 171 of the first MUX signal MUX1 synchronized with the first pixel data voltage D1(N) is generated as the gate-on voltage VGL, thereby causing the first switch element M1 ) turns on. At this time, the first pixel data voltage D1(N) is charged in the capacitor 51 of the first data line 1021 through the first switch element M1. Subsequently, during the third time t3, the pulse 172 of the second MUX signal MUX2 synchronized with the second pixel data voltage D2(N) is generated as the gate-on voltage VGL, thereby causing the second switch element (M2) is turned on. At this time, the second pixel data voltage D2(N) is charged in the capacitor 52 of the second data line 1022 through the second switch element M2.

FIG. 18 is a diagram quantitatively showing the effect of improving the transition width of the data voltage by implementing the charge share method of the third embodiment when displaying a yellow image on a pixel array. In this embodiment, the transition width of the data voltage in all pixels of the pixel array is reduced to 75 compared to the standard transition width of 100 and then changed to the target voltage of the next data voltage. The third embodiment can improve the charging characteristics and power consumption of subpixels due to the charge sharing effect compared to the case where charge sharing is not performed. Power consumption is reduced to 75% when a yellow image is displayed on the pixel array.

FIG. 19 is a diagram showing another example of a charge share circuit disposed on a display panel substrate. Figure 20 is a waveform diagram showing the charge sharing method according to the fourth embodiment of the present invention.

Referring to FIGS. 19 and 20 , the charge share circuit may be disposed on the substrate of the display panel 100 along with the pixel array. This charge share circuit includes CS SWs (S41 to S44) for connecting data lines (1021 to 1028) during the charge share period.

CS SWs (S41 to S44) can be turned on/off simultaneously under the control of the timing controller 130. The timing controller 130 generates a CS signal to control the CS SWs (S41 to S4).

The first CS SW (S41) is connected between the first and third data lines 1021 and 1023 and operates on the first and third data lines ( 1021 and 1023) are connected, and are turned off for the second and third times (t2 and T3) to separate the first and third data lines (1021 and 1023). When the first CS SW 41 is turned on, the R subpixels and B subpixels are connected simultaneously through the data lines 1021 and 1023. When a yellow image is displayed on the pixel array, the charge share voltage applied to the first and third data lines 1021 and 1023 at the first time t1 may be (255+0)/2.

The second CS SW (S42) is connected between the second and fourth data lines 1022 and 1024 and operates on the second and fourth data lines ( 1022 and 1024) are connected, and are turned off for the second and third times (t2 and T3) to separate the second and fourth data lines (1022 and 1024). When the second CS SW 42 is turned on, subpixels of the same color, that is, G subpixels, are simultaneously connected through data lines 1022 and 1024. When a yellow image is displayed on the pixel array, the charge share voltage applied to the first and third data lines 1021 and 1023 at the first time t1 may be (255+255)/2.

CS SWs (S31 to S36) are turned on when the CS signal is the gate-on voltage (VGL). At the first time t1, the pulse 201 of the CS signal is generated as the gate-on voltage VGL, and the CS SWs S41 to S44 are simultaneously turned on. At this time, neighboring odd-numbered data lines 1021 and 1023 are connected to each other, and the average voltage of the voltage applied to the data lines 1021 and 1023 is stored in the data lines 1021 and 1023. Accordingly, during the charge sharing period, the voltage of the data lines 1021 and 1023 may change to the average voltage, thereby reducing the transition width of the data voltage Vdata applied to the data lines 1021 and 1023. When a yellow image is displayed on the pixel array, the charge share voltage applied to the data lines 1021 and 1023 is (255+0)/2.

During the first time t1, neighboring even-th data lines 1022 and 1024 are connected to each other, and the average voltage of the voltage applied to the data lines 1022 and 1024 is stored in the data lines 1022 and 1024. do. Accordingly, during the charge sharing period, the voltage of the data lines 1022 and 1024 may change to the average voltage, thereby reducing the transition width of the data voltage Vdata applied to the data lines 1022 and 1024. When a yellow image is displayed on the pixel array, the charge share voltage applied to the data lines 1022 and 1024 is (255+255)/2.

After the first time t1, the pulses 172 and 173 of the first and second MUX signals MUX1 and MUX2 are sequentially generated as the gate-on voltage VGL, thereby increasing the data voltage D1 ( N) and D2(N)) are time-divided and distributed to the data lines (1021 to 1028). During the second time t2, the pulse 202 of the first MUX signal MUX1 synchronized with the first pixel data voltage D1(N) is generated as the gate-on voltage VGL, thereby causing the first switch element M1 ) turns on. At this time, the first pixel data voltage D1(N) from the first channel CH1 is charged in the capacitor 51 of the first data line 1021 through the first switch element M1. Subsequently, during the third time t3, the pulse 172 of the second MUX signal MUX2 synchronized with the second pixel data voltage D2(N) is generated as the gate-on voltage VGL, thereby causing the second switch element (M2) is turned on. At this time, the second pixel data voltage D2(N) from the first channel CH1 is charged in the capacitor 52 of the second data line 1022 through the second switch element M2.

FIG. 21 is a diagram quantitatively showing the effect of improving the transition width of the data voltage by implementing the charge share method of the fourth embodiment when displaying a yellow image on a pixel array. In this embodiment, the transition width of the pixel data voltage (Vdata) applied to the odd-numbered data lines (1021, 1023, 1025, and 1027) of the pixel array is reduced to 50 compared to the standard transition width of 100 due to the charge share voltage, and then The data voltage changes to the target voltage. The fourth embodiment can improve the charging characteristics and power consumption of subpixels due to the charge sharing effect compared to the case where charge sharing is not performed. Power consumption is reduced by 50% when a yellow image is displayed on the pixel array.

Since 1 horizontal period (1H) is small in a high-resolution display device or a high-speed display device, the demultiplexer array 112 may be omitted from the display panel driving circuit to secure the charging time of the pixels. 22 and 23 are examples of charge share circuits applied to such display devices. The charge share circuit can be applied as the charge share circuit shown in FIGS. 16 and 19. FIG. 22 illustrates the charge share circuit shown in FIG. 19.

FIG. 22 is a diagram showing an example of a charge sharing circuit disposed on a substrate of a display panel without a demultiplexer. Figure 23 is a waveform diagram showing the charge sharing method according to the fifth embodiment of the present invention.

22 and 23, channels CH1 to CH12 of the data driver 110 are connected to data lines 1021 to 1028 in a 1:1 ratio. CS SWs (S51 to S54) are connected between data lines (1021 to 1028).

CS SWs (S51 to S54) are turned on when the CS signal is the gate-on voltage (VGL). At the first time t1, a pulse of the CS signal is generated as the gate-on voltage VGL, and the CS SWs S51 to S54 are simultaneously turned on. At this time, neighboring odd-numbered data lines 1021 and 1023 are connected to each other, and the average voltage of the voltage applied to the data lines 1021 and 1023 is stored in the data lines 1021 and 1023. During the first time t1, neighboring even-th data lines 1022 and 1024 are connected to each other, and the average voltage of the voltage applied to the data lines 1022 and 1024 is stored in the data lines 1022 and 1024. do. Therefore, during the charge sharing period, the voltage of the odd-numbered data lines 1021 and 1023 may change to the average voltage, thereby reducing the transition width of the data voltage Vdata applied to the data lines 1021 and 1023. Additionally, during the charge sharing period, the voltage of the even-numbered data lines 1022 and 1024 may change to the average voltage, thereby reducing the transition width of the data voltage Vdata applied to the data lines 1022 and 1024.

Subsequently, the first pixel data voltage D1(N) output through the first channel CH1 at the second time t2 is charged in the capacitor 51 of the first data line 1021. The second pixel data voltage D2(N) output through the second channel CH2 at the third time t3 is charged in the capacitor 51 of the second data line 1022.

In this embodiment, the transition width of the pixel data voltage Vdata applied to the odd-numbered data lines 1021, 1023, 1025, and 1027 of the pixel array is reduced to the charge share voltage. The fifth embodiment can improve the charging characteristics and power consumption of subpixels due to the charge sharing effect compared to the case where charge sharing is not performed. Power consumption can be reduced to a lower level than in the fourth embodiment because there is no demultiplexer.

FIG. 24 is a diagram showing another example of a charge share circuit disposed on a display panel substrate. Figure 25 is a waveform diagram showing the charge sharing method according to the sixth embodiment of the present invention. The sixth embodiment can set the optimal charge share voltage for each horizontal line of the pixel array regardless of the data pattern of the input image. In the sixth embodiment, the operation logic unit of the timing controller 130 stores pixel data of 1 pixel line (hereinafter referred to as “1 line data”) in 1 line memory, calculates the average of 1 line data, and calculates the average of 1 line data. Output as shared data. The timing controller 130 transmits charge share data to the data driver 110 or the analog power circuit. The data driver 110 or the DAC of the analog power circuit converts the charge share data from the timing controller 130 into an analog voltage and outputs the charge share voltage Vavg. Since the charge share voltage (Vavg) is determined as an analog voltage corresponding to the average gray level value of 1 line data for each pixel line of the pixel array, it can be varied for each pixel line depending on the input image and the charge share effect can be maximized. It can be set to the optimal voltage.

Referring to FIGS. 24 and 25 , the charge share circuit may be disposed on the substrate of the display panel 100 along with the pixel array. This charge share circuit includes CS SWs (S60 to S68) for connecting data lines (1021 to 1028) during the charge share period.

A third power line 63 to which a charge share voltage (Vavg) is applied may be formed on the display panel 100. The charge share voltage (Vavg) is supplied to the data lines through CS SWs (S60 to S68). CS SWs (S60 to S68) can be turned on/off simultaneously under the control of the timing controller 130. The timing controller 130 generates a CS signal to control CS SWs (S60 to S68).

Each of the CS SWs (S61 to S68) is connected between adjacent odd-numbered data lines and even-numbered data lines. Each of the CS SWs (S61 to S68) includes a gate connected to the control signal line 64 to which the CS signal is applied, a first electrode connected to an odd-numbered data line, and a second electrode connected to an even-numbered data line. Among the CS SWs (S60 to S68), the power supply CS SW (S60) disposed on the outermost side of the display panel 100 is the gate connected to the control signal line 64, and the third to which the charge share voltage (Vavg) is applied. It includes a first electrode connected to the power line 63, and a second electrode connected to the second data line 1021.

Each of the CS SWs (S60 to S68) connects neighboring odd-numbered data lines and even-numbered data lines during the charge share period. The CS SW (S60) for power supply supplies a charge share voltage (Vavg) to the first electrode of the first CS SW (SW60) during a first time (t1), and during second and third times (t2, t3). The current path between the third power line 63 and the first CS SW (S61) is blocked.

The first CS SW (S61) is connected between the first and second data lines 1021 and 1022 and operates on the first and second data lines ( 1021 and 1022) are connected, and are turned off for the second and third times (t2 and T3) to separate the first and second data lines 1021 and 1022. The second CS SW (S62) is connected between the second and third data lines 1022 and 1023 and operates on the second and third data lines ( 1022 and 1023) are connected, and are turned off for the second and third times (t2 and T3) to separate the second and third data lines (1022 and 1023).

At the first time (t1), the charge share voltage (Vavg) applied to the data lines (1021 to 1024) is increased due to the charge share in which the data lines (1021 to 1023) are connected through the CS SWs (S61 to 68). It is applied to lines 1021 to 1024. Since the charge share voltage (Vavg) is the average voltage of 1 line data, it provides the optimal charge share effect in all data lines (1021 to 1028). During the second and third times (t2. T3), the CS SWs (S61 to 68) are turned off and the data lines (1021 to 1024) are separated from each other, so that different data voltages (Vdata) are applied to the data lines (1021). ~1024) is independently authorized.

CS SWs (S60 to S68) are turned on when the CS signal is the gate-on voltage (VGL). At the first time t1, a pulse of the CS signal is generated as the gate-on voltage VGL, and the CS SWs S60 to S68 are simultaneously turned on. At this time, the data lines (1021 to 1024) are connected to each other and a charge share voltage (Vavg) set to the average voltage of the voltage of 1 line data applied to the data lines (1021 to 1028) is applied to the data lines (1021 to 1028). 1024). Therefore, during the charge sharing period, the voltage of the data lines 1021 to 1024 changes to the average voltage of 1 line data, and the transition width of the data voltage Vdata applied to the data lines 1021 to 1024 may be reduced. .

After the first time t1, pulses of the first and second MUX signals MUX1 and MUX2 are sequentially generated as the gate-on voltage VGL, and the data voltages D1(N) and D2( N)) is time-divided and distributed to the data lines (1021 to 1028). During the second time t2, a pulse of the first MUX signal MUX1 synchronized with the first pixel data voltage D1(N) is generated as the gate-on voltage VGL to turn the first switch element M1. -It comes on. At this time, the first pixel data voltage D1(N) is charged in the capacitor 51 of the first data line 1021 through the first switch element M1. Subsequently, during the third time t3, the pulse 172 of the second MUX signal MUX2 synchronized with the second pixel data voltage D2(N) is generated as the gate-on voltage VGL, thereby causing the second switch element (M2) is turned on. At this time, the second pixel data voltage D2(N) is charged in the capacitor 52 of the second data line 1022 through the second switch element M2.

FIG. 26 is a diagram quantitatively showing the effect of improving the transition width of the data voltage by implementing the charge share method of the sixth embodiment when displaying a yellow image on a pixel array. In this embodiment, after charging the charge share voltage Vavg, which is set to the average voltage of 1 line data in all pixels of the pixel array, it changes to the target voltage of the next data voltage Vdata, so the transition width of the data voltage Vdata is It decreases. The sixth embodiment can achieve the optimal charge share effect compared to the case where charge share is not implemented. Power consumption can be reduced to at least 50% compared to the case without charge sharing.

FIGS. 27A to 30B are diagrams showing in detail a driving method including a charge sharing section in neighboring subpixels that include the pixel circuit shown in FIG. 3 and share an output buffer. CS SW (S30) shown in FIGS. 17A to 30B may be any one of the switch elements (M1, M2) or CS SWs of the demultiplexer in the above-described embodiments.

Figure 27a is a circuit diagram showing the current path flowing in the charge share section t1. FIG. 27B is a waveform diagram showing the first time t1 in the driving waveform diagram of the pixel circuits 101A and 101B.

Referring to FIGS. 27A and 27B, the pulse 270 of the CS signal is generated as the gate-on voltage (VGL) in the charge share period (t1). At this time, the CS SW (30) is turned on and a current path is formed between the neighboring data lines (1021 and 1022) through the CS SW (S30), so that charge sharing is performed and the data lines (1021 and 1022) The average voltage is applied to the capacitors 51 and 52. During the charge share period (t1), the MUX signals (MUX1, MUX2), the first scan signal (SCAN1 (N)) and the second scan signal (SCAN2 (N)) are the gate-off voltage (VGH), and the EM signal ( EM(N)) is the gate-on voltage (VGL).

Figure 28a is a circuit diagram showing the current path in the first and second stages (S1(t2), S2(t3)). FIG. 27B is a waveform diagram showing the first and second stages (S1(t2) and S2(t3)) in the driving waveform diagram of the pixel circuits 101A and 101B.

Referring to FIGS. 28A and 28B, pulses 271 and 272 of the MUX signals (MUX1 and MUX2) are sequentially generated in the first and second stages (S1 (t2) and S2 (t3)) to demultiplexer (21). ) After the first switch element (M1) is turned on, the second switch element (M2) is turned on. In the first step (S1(t2)), the first pixel data voltage D1(N) is applied to the capacitor 51 of the first data line 1021 through the first switch element M1. Subsequently, in the second step (S2(t3)), the second pixel data voltage D2(N) is applied to the capacitor 52 of the second data line 1022 through the second switch element M2. Accordingly, the pixel data voltages D1(N) and D2(N) are sequentially stored in the data lines 1021 and 1022 in the first and second stages (S1(t2) and S2(t3)). In the first and second steps (S1(t2), S2(t3)), the CS signal, the first scan signal (SCAN1(N)) and the second scan signal (SCAN2(N)) are connected to the gate-off voltage (VGH). , and the EM signal (EM(N)) is the gate-on voltage (VGL).

Figure 29a is a circuit diagram showing the current path in the third step (S3). FIG. 27B is a waveform diagram showing the third step (S3) in the driving waveform diagram of the pixel circuits 101A and 101B.

Referring to FIGS. 29A and 29B, in the third step (S3), the CS signal and the MUX signals (MUX1 and MUX2) are at the gate-off voltage (VGH). In the third step (S3), the pulse 274 of the second scan signal (SCAN2(N)) is inverted to the gate-on voltage (VGL). In the third step S3, the first scan signal SCAN1(N) maintains the gate-off voltage VGH, and the EM signal EM(N) maintains the gate-on voltage VGL. The second to fifth switch elements (T2, T3, T4, T5) apply the gate-on voltage (VGL) of the second scan signal (SCAN2(N)) and the EM signal (EM(N)) in the third step (S3). ) is turned on according to the At this time, in the subpixels 101A and 101B, the voltage across the capacitor Cst and the anode of the light emitting element EL are simultaneously initialized to the reference voltage Vref.

Figure 30a is a circuit diagram showing the current path in the fourth step (S4). FIG. 30B is a waveform diagram showing the fourth step (S4) in the driving waveform diagram of the pixel circuits 101A and 101B.

Referring to FIGS. 30A and 30B, in the fourth step (S4), the EM signal (EM(N)) is inverted to the gate-off voltage (VGH) so that the light emitting device (EL) does not emit light, and the first scan signal (SCAN1) is inverted to the gate-off voltage (VGH). (N)) pulse 273 is inverted to the gate-on voltage (VGL). In the fourth step (S4), the CS signal and the MUX signals (MUX1 and MUXS) maintain the gate-off voltage, and the second scan signal (SCAN2(N)) maintains the gate-on voltage (VGL). During the fourth step (S4), the first, second, and fifth switch elements (T1, T2, T5) are operated according to the gate-on voltage (VGL) of the scan signals (SCAN1 (N), SCAN2 (N)). Turns on. At this time, the pixel data voltage is applied to one end of the capacitor Cst, and the threshold voltage Vth of the driving element DT is applied to the other end of the capacitor Cst, so that the data is compensated by the threshold voltage of the driving element DT. The voltage (Vdata) is sampled across the capacitor (Cst). After the fourth step (S4), the EM signal (EM(N)) is inverted to the gate-on voltage in the fifth step (S5) to a current determined according to the gate-source voltage (Vgs) of the driving element (DT). The light emitting element (EL) emits light.

FIGS. 31A to 35B are diagrams showing in detail a driving method including a charge sharing section in neighboring subpixels that include the pixel circuit shown in FIG. 4 and share an output buffer. 31A to 35B, the CS SW (S30) may be either the switch elements (M1, M2) or the CS SWs of the demultiplexer in the above-described embodiments.

Referring to FIGS. 31A and 31B, the pulse 285 of the EM signal EM(N) is inverted to the gate-off voltage VGH in the 0th period t0. At this time, the third and fourth switch elements T13 and T14 are turned off and current is not supplied to the light emitting element EL, so the light emitting element EL does not emit light. During the 0th period t0, the CS signal, MUX signals MUX1 and MUX2, and scan signals SCAN(N-1) and SCAN(N) maintain the gate-off voltage VGH.

Referring to FIGS. 32A and 32B, the pulse 270 of the CS signal is inverted to the gate-on voltage (VGL) in the charge share period (t1). At this time, the CS SW (30) is turned on and a current path is formed between the neighboring data lines (1021 and 1022) through the CS SW (S30), so that charge sharing is performed and the data lines (1021 and 1022) The average voltage is applied to the capacitors 51 and 52. During the charge share period t1, the MUX signals MUX1 and MUX2, the scan signals SCAN1(N) and SCAN2(N), and the EM signal EM(N) are the gate off voltage VGH.

Referring to FIGS. 33A and 33B, the pulse 281 of the first MUX signal (MUX1) is applied to the gate of the first switch element (M1) at the second time (t2), so that the first switch element (M1) turns. -It comes on. At this time, the first data voltage D1(N) is applied to the first data line 1021 through the first switch element M1 and stored in the first capacitor 51. At the second time t2, the CS signal, the second MUX signal MUX2, the scan signals SCAN(N-1), SCAN(N), and the EM signal EM(N) are connected to the gate off voltage ( VGH).

Referring to FIGS. 34A and 34B, at the third time t3, the pulse 282 of the second MUX signal (MUX2) and the pulse 284 of the scan signals (SCAN(N-1) and SCAN(N)) is inverted to the gate-on voltage VGL, so that the second switch element M2 and the switch elements T11, T12, T14, T15, and T16 of the pixel circuits 101A and 101B are simultaneously turned on. At the third time t3, the CS signal, the first MUX signal MUX1, and the EM signal EM(N) maintain the gate-off voltage VGH. At the third time t3, the first and sixth switch elements T11 and T16 are turned on so that the gate voltage of the driving elements DT rises to Vdata+Vth. At this time, the data voltage Vdata stored in the capacitor Cst of the first data line 1021 in the first subpixel 101A is applied to the gate of the driving element DT, and the data voltage Vdata is applied to the gate of the driving element DT in the first subpixel 101A. The data voltage Vdata generated through the output buffer AMP of the driver 110 is applied to the gate of the driver device DT. At the third time t3, the CS signal, the first MUX signal MUX1, and the EM signal EM(N) are the gate-off voltage VGH.

Referring to FIGS. 35A and 35B, in the fourth period t4, the scan signals SCAN(N-1) and SCAN(N) maintain the gate-off voltage VGH, and the EM signal EM(N) ) is inverted to the gate-on voltage (VGL) and the third and fourth switch elements (T13 and T14) are turned on. At the fourth time t4, a current pass between the first power line 61 to which the pixel driving voltage VDD is applied and the light emitting device EL may flow, causing the light emitting device EL to emit light.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

41, 42: Charge sharing unit 51~54: Capacitor of data line
100: Display panel 101, 101A, 101B: Subpixel
102, 1021~1024: data line 103, 31~33: gate line
110: data driver 112, 21, 22: demultiplexer
120: Gate driver 130: Timing controller
M1, M2: Switch elements of demultiplexer
S21~S23, S31~S36, S41~S44, S51~S54, S60~S68: Switch element for charge sharing
t1: First time (charge share section)
t2, t3: second and third time (charging period of data lines)

Claims (14)

delete a data driver that outputs a data voltage through first and second channels;
a first demultiplexer that distributes the data voltage output through the first channel to first and second data lines using 1-1 and 2-1 switch elements;
a second demultiplexer that distributes the data voltage output through the second channel to third and fourth data lines using 1-2 and 2-2 switch elements;
a charge sharing unit selectively connecting the first and second channels; and
A control unit that controls switch on/off timing of the first and second demultiplexers and the charge sharing unit,
All switch elements of the first and second demultiplexers and switch elements of the charge sharing unit are simultaneously turned on for a first time, so that the first channel and the second channel are connected, and the data lines are connected to the first and second channels. Connected to 2 channels,
At a second time, the 1-1 and 1-2 switch elements are simultaneously turned on so that the first channel is connected to the first data line and the second channel is connected to the third data line,
At a third time, the 2-1 and 2-2 switch elements are turned on simultaneously, so that the first channel is connected to the second data line and the second channel is connected to the fourth data line. Device. Following paragraph 2,
A display device in which all switch elements of the first and second demultiplexers and switch elements of the charge sharing unit are simultaneously turned on during the first time. Following paragraph 2,
The first time is divided into a 1-1 time and a 1-2 time,
During the 1-1 time, the 1-1 and 1-2 switch elements and the switch elements of the charge sharing unit are simultaneously turned on, so that the second channel is connected to the first channel, and the first and Third data lines are connected to the first and second channels,
After the 2-1 and 2-2 switch elements and the switch elements of the charge sharing unit are simultaneously turned on for the 1-2 time, the second channel is connected to the first channel, and the second channel is connected to the first channel. and a display device in which fourth data lines are connected to the first and second channels. a data driver that outputs a data voltage through first and second channels;
a first demultiplexer that distributes the data voltage output through the first channel to first and second data lines using 1-1 and 2-1 switch elements;
a second demultiplexer that distributes the data voltage output through the second channel to third and fourth data lines using 1-2 and 2-2 switch elements;
a charge sharing unit selectively connecting the data lines; and
A control unit that controls switch on/off timing of the first and second demultiplexers and the charge sharing unit,
The switch elements of the charge sharing unit are simultaneously turned on for a first time so that the data lines are connected through the switch elements of the charge sharing unit,
At a second time, the 1-1 and 1-2 switch elements are simultaneously turned on so that the first channel is connected to the first data line and the second channel is connected to the third data line,
At a third time, the 2-1 and 2-2 switch elements are turned on simultaneously, so that the first channel is connected to the second data line and the second channel is connected to the fourth data line. Device. According to claim 5,
Each of the switch elements of the charge sharing unit is
A display device that connects adjacent odd-numbered data lines and even-numbered data lines. According to claim 5,
Each of the switch elements of the charge sharing unit is
switch elements connecting adjacent odd-numbered data lines; and
A display device including switch elements connecting adjacent even number data lines. According to claim 5,
an operation logic unit that calculates the average value of 1 line data written in 1 pixel line of the display panel;
a voltage converter that converts the average value into a voltage and generates a charge share voltage; and
A display device further comprising a power wiring formed on the display panel to supply the charge share voltage to the charge share unit. According to claim 8,
The charge share section
A display further comprising a switch element for power supply that supplies the charge share voltage to the switch elements at the first time and blocks a current path between the charge share voltage and the switch element at the second and third times. Device. a data driver that outputs a data voltage through first and second channels;
a charge sharing unit selectively connecting a first data line connected to the first channel and a second data line connected to the second channel; and
It includes a control unit that controls switch on/off timing of the charge sharing unit,
The switch elements of the charge sharing unit are simultaneously turned on for a first time and the data lines are connected through the switch elements of the charge sharing unit and then turned off at the second and third times,
At a second time, a first data voltage from the first channel is stored in the first data line,
A display device in which a second data voltage from the second channel is stored in the second data line at a third time. delete A data driver that outputs a data voltage through first and second channels, and a data voltage output through the first channel using 1-1 and 2-1 switch elements, are connected to the first and second data lines. a first demultiplexer for distributing, a second demultiplexer for distributing the data voltage output through the second channel to third and fourth data lines using 1-2 and 2-2 switch elements, and the first In a method of driving a display device including a charge sharing unit for selectively connecting a second channel,
At a first time, all switch elements of the first and second demultiplexers and switch elements of the charge sharing unit are simultaneously turned on, so that the first channel and the second channel are connected, and the data lines are connected to the first and second channels. connected to 2 channels;
At a second time, the 1-1 and 1-2 switch elements are simultaneously turned on so that the first channel is connected to the first data line and the second channel is connected to the third data line. ; and
At a third time, the 2-1 and 2-2 switch elements are simultaneously turned on so that the first channel is connected to the second data line and the second channel is connected to the fourth data line. A method of driving a display device including. A data driver that outputs a data voltage through first and second channels, and a data voltage output through the first channel using 1-1 and 2-1 switch elements, are connected to the first and second data lines. A first demultiplexer for distributing, a second demultiplexer for distributing the data voltage output through the second channel to third and fourth data lines using 1-2 and 2-2 switch elements, and the data line In a method of driving a display device including a charge sharing unit for selectively connecting the devices,
At a first time, the switch elements of the charge sharing unit are simultaneously turned on and the data lines are connected through the switch elements of the charge sharing unit;
At a second time, the 1-1 and 1-2 switch elements are simultaneously turned on so that the first channel is connected to the first data line and the second channel is connected to the third data line. ; and
At a third time, the 2-1 and 2-2 switch elements are simultaneously turned on so that the first channel is connected to the second data line and the second channel is connected to the fourth data line. A method of driving a display device including. a data driver that outputs a data voltage through first and second channels, and a charge sharer that selectively connects a first data line connected to the first channel and a second data line connected to the second channel, and the charger. In a method of driving a display device including a control unit that controls switch on/off timing of the share unit,
Turning on the switch elements of the charge sharing unit simultaneously for a first time so that the data lines are connected through the switch elements of the charge sharing unit; and
After the switch elements of the charge sharing unit are turned off and the first data voltage from the first channel is stored in the first data line at a second time, the second data voltage from the second channel is stored at a third time. A method of driving a display device including storing data in the second data line.