GB2611619A

GB2611619A - Pixel circuit and display device including the same

Info

Publication number: GB2611619A
Application number: GB2211680.0A
Authority: GB
Inventors: Sung Yu Jae; Hoon Park Jae
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2021-01-27
Filing date: 2022-08-10
Publication date: 2023-04-12
Anticipated expiration: 2042-08-10
Also published as: GB202211680D0; GB2611619B

Abstract

The pixel circuit comprises: Driving transistor, DT, with a first electrode connected to first node, DRD, connected to first constant voltage, ELVDD, a gate electrode connected to second node, DRG, and a second electrode connected to third node, DRS; OLED with an anode connected to fourth node, n4, and a cathode connected to second constant voltage, ELVSS, lower than ELVDD; First switch transistor for supplying data voltage, Vdata, to node DRG in response to a first gate pulse, SC1; Second switch transistor, M2, for applying a third constant voltage, Vref, lower than ELVDD to node DRG in response to a second gate pulse, SC2; Third switch transistor, M3, for supplying a fourth constant voltage, Vinit, lower than Vref and higher than ELVSS, to node n4 in response to a third gate pulse, SC3; Fourth switch transistor, M4, for applying ELVDD to node DRD in response to a fourth gate pulse, EM1; Fifth switch transistor, M5, which connects node DRS to node n4 in response to a fifth gate pulse, EM2; First capacitor, C1, connected between node DRG and node DRS; and second capacitor, C2, connected between node DRS and constant voltage node, Vx.

Description

PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2021- 0117326, filed September 03, 2021 and Korean Patent Application No. 10-2021-0174576 filed December 08, 2021.

BACKGROUND

1. Field

[0002] The present disclosure relates to a pixel circuit and a display device including the same.

2. Discussion of Related Art [0003] Electroluminescence display devices may be divided into inorganic light-emitting display devices and organic light-emitting displays according to a material of an emission layer. An active matrix organic light-emitting display device includes an organic light-emitting diode (OLED) that generates light by itself and has advantages in terms of a high response rate, high luminous efficiency, high brightness, and a large viewing angle. In an organic light-emitting display device, an OLED is formed at each pixel. The organic light-emitting display device has a high response rate, high luminous efficiency, high brightness, and a large viewing angle and is capable of expressing black gradation in perfect black, thereby achieving a high contrast ratio and a high color reproduction rate.

[0004] A pixel circuit of an organic light emitting display device includes an OLED and a driving element for driving the OLED. A data voltage and a reference voltage may be alternately applied to data lines connected to the pixel circuit. In this case, since the data lines charge and discharge the data voltage and the reference voltage in a cycle of one horizontal period, power consumption of the display device increases.

[0005] In a state in which the driving element is connected to the OLED in such a pixel circuit, if the pixel circuit is driven in a sampling step and an addressing step, the luminance of the pixels may change under the influence of the resistance and the capacitance of the OLED. If there is a deviation between the resistance and the capacitance of the OLED between the pixels due to the process deviation of the OLED, the luminance non-uniformity between the pixels may appear more severe.

[0006] For example, when the data voltage is applied to the gate electrode of the driving element while the driving element is connected to the OLED, a gate-source voltage of the driving element may change under the influence of a voltage charged in a previous frame due to the internal high resistance of the OLED, so that the luminance of the pixel may also change. For example, if the luminance of the pixel is high in the previous frame, the gate-source voltage of the driving element lowers since the internal node voltage of the OLED is high in the sampling step of a current frame, and thus the luminance of the pixel lowers. Conversely, if the luminance of the pixel is low in the previous frame, the gate-source voltage of the driving element increases since the internal node voltage of the OLED is low in the sampling step of the current frame, and thus the luminance of the pixel increases.

SUMMARY

[0007] An object of the present disclosure is to solve the above-mentioned necessity and/or problems. [0008] The present disclosure provides a pixel circuit capable of improving power consumption and excluding the influence of a light emitting element when pixel data is written into pixels, and a display device including the same. An invention is set out in the independent claims.

[0009] The problems of the present disclosure are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [0010] A pixel circuit according to an embodiment of the present disclosure may include: a driving element including a first electrode connected to a first node to which a first constant voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node; a light emitting element including an anode electrode connected to a fourth node, and a cathode electrode to which a second constant voltage lower than the first constant voltage is applied; a first switch element configured to supply a data voltage to the second node in response to a first gate pulse; a second switch element configured to apply a third constant voltage lower than the first constant voltage to the second node in response to a second gate pulse; a third switch element configured to supply a fourth constant voltage lower than the third constant voltage and higher than the second constant voltage to the fourth node in response to a third gate pulse; a fourth switch element configured to apply the first constant voltage to the first node in response to a fourth gate pulse; a fifth switch element configured to electrically connect the third node to the fourth node in response to a fifth gate pulse; a first capacitor connected between the second node and the third node; and a second capacitor connected between the third node and a constant voltage node.

[0011] Any one of the first to fourth constant voltages ELVDD, ELVSS, Vref and Vinit may be applied to the constant voltage node Vx.

[0012] A voltage difference between the third constant voltage Vref and the fourth constant voltage Vinit may be higher than a threshold voltage Vth of the driving element DT.

[0013] A driving period of the pixel circuit may include an initialization step INIT, a sampling step SMPL set following the initialization step INIT, an addressing step WR set following the sampling step SMPL, and a light emission step EMIS set following the addressing step WR, wherein in the initialization step INIT, the second, third, and fifth switch elements M2, M3 and M5 and the driving element DT are turned on, and the first and fourth switch elements M1 and M4 are turned-off, in the sampling step SMPL, the second and fourth switch elements M2 and M4 are turned on, the first, third, and fifth switch elements Ml, M3 and M5 are turned off, in the addressing step WR, the first switch element M1 is turned on, and the second, third, fourth, and fifth switch elements M2, M3, M4 and M5 are turned off, and in the light emission step EMIS, the fourth and fifth switch elements M4 and M5 are turned on, and the first, second, and third switch elements Ml, M2 and M3 are turned off.

[0014] The driving element DT may be turned on in the initialization step INIT and turned off in the sampling step SMPL.

[0015] The third node DRS may be electrically disconnected from the fourth node n4 in the sampling step SMPL and the addressing step WR.

[0016] The first to fifth switch elements M1 to M5 may be turned on in response to a gate-on voltage and turned-off in response to a gate-off voltage, the first gate pulse SC1 may be generated as the gate-on voltage in the addressing step WR in synchronization with the data voltage, and may be generated as the gate-off voltage in the initialization step INIT, the sampling step SMPL, and the light emission step EMIS, the second gate pulse SC2 may be generated as the gate-on voltage in the initialization step INIT and the sampling step SMPL, and may be generated as the gate-off voltage in the addressing step WR and the light emission step EMIS, the third gate pulse SC3 may be generated as the gate-on voltage in the initialization step INIT, and may be generated as the gate-off voltage in the sampling step SMPL, the addressing step WR, and the light emission step EMIS, [0017] The fourth gate pulse EM1 may be generated as the gate-on voltage in the sampling step SMPL and the light emission step EMIS, and may be generated as the gate-off voltage in the initialization step INIT and the addressing step WR, and the fifth gate pulse EM2 may be generated as the gate-on voltage in the initialization step INIT and the light emission step EMIS, and may be generated as the gate-off voltage in the sampling step SMPL and the addressing step WR.

[0018] A driving period of the pixel circuit may include a first initialization step INIT1, a sampling step SMPL set following the first initialization step INIT1, an addressing step WR set following the sampling step SMPL, a second initialization step INIT2 set following the addressing step WR, and a light emission step EMIS set following the second initialization step INIT2, wherein in the first initialization step INIT1, the second, third, and fifth switch elements M2, M3 and M5 and the driving element DT may be turned on, and the first and fourth switch elements M1 and M4 may be turned-off, in the sampling step SMPL, the second and fourth switch elements M2 and M4 may be turned on, and the first, third, and fifth switch elements Ml, M3 and M5 may be turned off, in the addressing step WR, the first switch element M1 may be turned on, and the second, third, fourth, and fifth switch elements M2, M3, M4 and M5 are turned off, in the second initialization step INIT2, the third and fifth switch elements M3 and M5 may be turned on, and the first, second, third switch elements Ml, M2 and M3 may be turned off, and in the light emission step EMIS, the fourth and fifth switch elements M4 and M5 may be turned on, and the first, second, and third switch elements Ml, M2 and M3 may be turned off.

[0019] The first to fifth switch elements M1-M5 may be turned on in response to a gate-on voltage and turned-off in response to a gate-off voltage, the first gate pulse SC1 may be generated as the gate-on voltage in the addressing step WR in synchronization with the data voltage, and may be generated as the gate-off voltage in the first initialization step INIT1, the sampling step SMPL, the second initialization step INIT2, and the light emission step EMIS, the second gate pulse SC2 may be generated as the gate-on voltage in the first initialization step INIT1 and the sampling step SMPL, and may be generated as the gate-off voltage in the addressing step WR, the second initialization step INIT2, and the light emission step EMIS, the third gate pulse SC3 may generated as the gate-on voltage in the first initialization step INIT1 and the second initialization step INIT2, and may be generated as the gate-off voltage in the sampling step SMPL, the addressing step WR, and the light emission step EMIS, the fourth gate pulse EM1 may be generated as the gate-on voltage in the sampling step SMPL and the light emission step EMIS, and may be generated as the gate-off voltage in the first initialization step INIT1, the addressing step WR, and the second initialization step INIT2, and the fifth gate pulse EM2 may be generated as the gate-on voltage in the first initialization step INIT1, the second initialization step INIT2, and the light emission step EMIS, and may be generated as the gate-off voltage in the sampling step SMPL and the addressing step WR.

A display device according to an embodiment of the present disclosure may include a display panel in which a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, a plurality of power lines, and a plurality of pixel circuits connected to the plurality of data lines, the plurality of gate lines, and the plurality of power lines are arranged; a data driver configured to supply a data voltage of pixel data to the plurality of data lines; and a gate driver configured to supply a gate signal to the plurality of gate lines.

[0020] All transistors of the display panel including the driving element DT and the first, second, third, fourth and fifth switch elements Ml, M2, M3, M4 and M5 of the plurality of pixel circuits may include an n-channel oxide semiconductor.

[0021] In the present disclosure, since a data line through which a data voltage is applied and a power line through which a reference voltage is applied are separated, the frequency of a voltage applied to the data line is lowered, so that power consumption may be reduced.

[0022] In the present disclosure, in the sampling step and the addressing step, the driving element of the pixel circuit is electrically separated from the light emitting element. As a result, in the present disclosure, since data addressing and threshold voltage sampling of the driving element are not affected by a resistance of the light emitting element and a process deviation of the light emitting element, the influence of the light emitting element on the luminance of the pixel may be excluded. Accordingly, it is possible to prevent the change of the luminance of the pixel due to the influence of the light emitting element.

[0023] Effects of the present disclosure are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the attached drawings, in which: [0025] FIG. 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure; [0026] FIG. 2 is a cross-sectional view illustrating a cross-sectional structure of a display panel shown in FIG. 1; [0027] FIG. 3 is a circuit diagram illustrating a pixel circuit according to an embodiment of the present

disclosure;

[0028] FIG. 4 is a waveform diagram illustrating a method of driving a pixel circuit according to an embodiment of the present disclosure; [0029] FIG. 5A is a diagram illustrating a current flowing through the pixel circuit shown in FIG. 3 in an initialization step; [0030] FIG. 5B is a diagram illustrating a current flowing through the pixel circuit shown in FIG. 3 in a sampling step; [0031] FIG. 5C is a diagram illustrating a current flowing through the pixel circuit shown in FIG. 3 in an addressing step; [0032] FIG. 5D is a diagram illustrating a current flowing through the pixel circuit shown in FIG. 3 in a light emission step; [0033] FIG. 6 is a waveform diagram illustrating a method of driving a pixel circuit according to another embodiment of the present disclosure; and [0034] FIG. 7 is a diagram illustrating a current flowing through the pixel circuit shown in FIG. 3 in a second initialization step.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0035] The advantages and features of the present disclosure and methods for accomplishing the same will be more clearly understood from embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments but may be implemented in various different forms. Rather, the present embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to completely comprehend the scope of the present disclosure. The present disclosure is only defined within the scope of the accompanying claims.

[0036] The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally denote like elements throughout the present specification. Further, in describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0037] The terms such as "comprising," "including," "having," and "consist of' used herein are generally intended to allow other components to be added unless the terms are used with the term "only." Any references to singular may include plural unless expressly stated otherwise.

[0038] Components are interpreted to include an ordinary error range even if not expressly stated. [0039] When the position relation between two components is described using the terms such as "on," "above," "below," and "next," one or more components may be positioned between the two components unless the terms are used with the term "immediately" or "directly." [0040] The terms "first," "second," and the like may be used to distinguish components from each other, but the functions or structures of the components are not limited by ordinal numbers or component names in front of the components.

[0041] The same reference numerals may refer to substantially the same elements throughout the

present disclosure.

[0042] The following embodiments can be partially or entirely bonded to or combined with each other and can be linked and operated in technically various ways. The embodiments can be carried out independently of or in association with each other.

[0043] Each of the pixels may include a plurality of sub-pixels having different colors to in order to reproduce the color of the image on a screen of the display panel. Each of the sub-pixels includes a transistor used as a switch element or a driving element. Such a transistor may be implemented as a TFT (Thin Film Transistor).

[0044] A driving circuit of the display device writes a pixel data of an input image to pixels on the display panel. To this end, the driving circuit of the display device may include a data driving circuit configured to supply data signal to the data lines, a gate driving circuit configured to supply a gate signal to the gate lines, and the like.

[0045] In a display device of the present disclosure, the pixel circuit may include a plurality of transistors. Transistors may be implemented as oxide thin film transistors (oxide TFTs) including an n-channel oxide semiconductor, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, or the like. In embodiments, descriptions will be given based on an example in which the transistors of the pixel circuit are implemented as the n-channel oxide TFTs, but the present disclosure is not limited thereto.

[0046] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In the transistor, carriers start to flow from the source. The drain is an electrode through which carriers exit from the transistor. In a transistor, carriers flow from a source to a drain. In the case of an n-channel transistor, since carriers are electrons, a source voltage is a voltage lower than a drain voltage such that electrons may flow from a source to a drain. The n-channel transistor has a direction of a current flowing from the drain to the source. In the case of a p-channel transistor (p-channel metal-oxide semiconductor (PMOS), since carriers are holes, a source voltage is higher than a drain voltage such that holes may flow from a source to a drain. In the p-channel transistor, since holes flow from the source to the drain, a current flows from the source to the drain. It should be noted that a source and a drain of a transistor are not fixed. For example, a source and a drain may be changed according to an applied voltage. Therefore, the disclosure is not limited due to a source and a drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0047] A gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than a threshold voltage of a transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0048] The transistor is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage. In the case of an n-channel transistor, a gate-on voltage may be a gate high voltage VGH and VEH, and a gate-off voltage may be a gate low voltage VGL and VEL.

[0049] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, a display device will be mainly described as an organic light emitting display device, but the present disclosure is not limited thereto. [0050] Referring to FIGS. 1 and 2, a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply unit 140 for generating power required to drive the pixels and the display panel driver.

[0051] The display panel 100 may have a rectangular structure having a length in an X-axis direction, a width in a Y-axis direction, and a thickness in a Z-axis direction. The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to the pixels. The power lines supply a constant voltage required for driving the pixels 101 to the pixels 101. For example, the display panel 100 may include a VDD line through which a pixel driving voltage ELVDD is applied and a VSS line through which a low potential power voltage ELVSS is applied. In addition, the power lines may further include a REF line through which a reference voltage Vref is applied and an INIT line through which an initialization voltage Vinit is applied.

[0052] As shown in FIG. 2, the cross-sectional structure of the display panel 100 may include a circuit layer 12, a light emitting element layer 14, and an encapsulation layer 16 stacked on a substrate 10. [0053] The circuit layer 12 may include a TFT array including a pixel circuit connected to wires such as the data line, the gate line, and the power line, a demulfiplexer array 112, a gate driver 120, and the like.

The wires and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated with the insulating layer therebetween, and an active layer including a semiconductor material. All transistors formed in the circuit layer 12 may be implemented with n-channel oxide TFTs.

[0054] The light emitting element layer 14 may include light emitting elements EL driven by the pixel circuit. The light emitting elements EL may include a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element. In another embodiment, the light emitting element layer 14 may include a white light emitting element and a color filter. The light emitting elements EL of the light emitting element layer 14 may be covered with a multi-layered protective layer including an organic film and an inorganic film.

[0055] The encapsulation layer 16 covers the light emitting element layer 14 to seal the circuit layer 12 and the light emitting element layer 14. The encapsulation layer 16 may have a multi-insulating film structure in which an organic film and an inorganic film are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen becomes longer than that in a single layer, so that the penetration of moisture and oxygen affecting the light emitting element layer 14 may be effectively blocked.

[0056] A touch sensor layer, which is omitted from the drawing, may be formed on the encapsulation layer 16, and a polarizing plate or a color filter layer may be disposed thereon. The touch sensor layer may include capacitive touch sensors that sense a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include insulating layers and metal wiring patterns that form the capacitance of the touch sensors. The insulating layers may insulate intersecting portions in the metal wiring patterns and may planarize the surface of the touch sensor layer. The polarizing plate may improve visibility and contrast ratio by converting the polarization of external light reflected by the metal of the circuit layer and the touch sensor layer. The polarizing plate may be implemented as a circular polarizing plate or a polarizing plate in which a linear polarizing plate and a phase retardation film are bonded. A cover glass may be bonded to the polarizing plate. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer may absorb a part of the wavelength of light reflected from the circuit layer and the touch sensor layer to replace the polarizing plate and increase the color purity of an image reproduced in the pixel array.

[0057] The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes one line of pixels arranged along a line direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel line share the gate lines 103. Sub-pixels arranged in a column direction Y along a data line direction share the same data line 102. One horizontal period is a time period obtained by dividing one frame period by the total number of the pixel lines L1 to Ln.

[0058] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and an actual background is visible. The display panel 100 may be manufactured as a flexible display panel.

[0059] Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub- pixel to implement color. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels includes the pixel circuit. Hereinafter, a pixel may be interpreted as having the same meaning as a sub-pixel. Each pixel circuit is connected to the data lines, the gate lines, and the power lines.

[0060] The pixels may be arranged as real color pixels and pentile pixels. The pentile pixel may realize a higher resolution than a real color pixel by driving two sub-pixels having different colors as one pixel 101 by using a preset pixel rendering algorithm. The pixel rendering algorithm may compensate for insufficient color representation in each pixel with the color of light emitted from an adjacent pixel.

[0061] The power supply unit 140 generates a DC voltage (or constant voltage) necessary for driving the pixel array of the display panel 100 and the display panel driver by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like.

The power supply unit 140 may adjust the level of a DC input voltage applied from a host system (not shown) to generate DC voltages (or constant voltages) such as a gamma reference voltage VGMA, gate-on voltages VGH and VEH, gate-off voltages VGL and VEL, the pixel driving voltage ELVDD, the low potential power voltage ELVSS, the initialization voltage Vinit, and the reference voltage Vref. The gamma reference voltage VGMA is supplied to a data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are supplied to the gate driver 120. The constant voltages such as the pixel driving voltage ELVDD, the low potential power voltage ELVSS, the initialization voltage Vinit, and the reference voltage Vref are supplied to the pixels 101 through the power lines commonly connected to the pixels 101. The constant voltages applied to the pixel circuit may have different voltage levels. The power supply 140 may be configured to apply the respective voltages described herein to the respective nodes/electrodes described herein. The nodes/electrodes described herein may be configured to receive the respective voltages described as being applied thereto, e.g. to receive these from the power supply 140.

[0062] The display panel driver writes pixel data of an input image to the pixels of the display panel 100 under the control of the timing controller 130.

[0063] The display panel driver includes the data driver 110 and the gate driver 120. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

[0064] The demultiplexer array 112 sequentially supplies the data voltages outputted from the channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers DEMUX. The demultiplexer may include a plurality of switch elements disposed on the display panel 100. When the demultiplexer is disposed between the data lines 102 and the output terminals of the data driver 110, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

[0065] The display panel driver may further include a touch sensor driver for driving the touch sensors.

The touch sensor driver is omitted from FIG. 1. The data driver 110 and the touch sensor driver may be integrated into one drive integrated circuit (IC). In a mobile device or a wearable device, the timing controller 130, the power supply unit 140, the data driver 110, and the like may be integrated into one drive IC.

[0066] The display panel driver may operate in a low speed driving mode under the control of the timing controller 130. The low speed driving mode may be set to reduce power consumption of the display device when an input image does not change by a preset number of frames as a result of analyzing the input image. In the low speed driving mode, power consumption of the display panel driver and the display panel 100 may be reduced by lowering a refresh rate of pixels when a still image is inputted for a predetermined time or over. The low speed driving mode is not limited to when a still image is inputted. For example, when the display device operates in a standby mode or when a user command or an input image is not inputted to the display panel driver for a predetermined time or over, the display panel driver may operate in the low speed driving mode.

[0067] The data driver 110 receives the pixel data of the input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 converts the pixel data of the input image into a gamma compensation voltage every frame period using a digital to analog converter (DAC) to generate a data voltage Vdata. The gamma reference voltage VGMA is divided into a gamma compensation voltage for each grayscale through a voltage divider circuit. The gamma compensation voltage for each grayscale is provided to the DAC of the data driver 110. The data voltage Vdata is outputted from each of the channels of the data driver 110 through an output buffer.

[0068] The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed in a circuit layer 12 on the display panel 100 together with wires and a TFT array of the pixel array. The gate driver 120 may be disposed in a bezel BZ, which is the non-display area of the display panel 100, or may be distributedly disposed in the pixel array where the input image is reproduced. The gate driver 120 sequentially outputs the gate signal to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may shift the gate signal by using a shift register to sequentially supply the signals to the gate lines 103. The gate signal may include various gate pulses such as a scan pulse and an emission control pulse (hereinafter, referred to as an "EM pulse").

[0069] The timing controller 130 receives digital video data DATA of the input image and a timing signal synchronized with the digital video data DATA from the host system. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, and the like. Since a vertical period and a horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has a cycle of one horizontal period 1H.

[0070] The host system may be any one of a television (TV) system, a tablet computer, a laptop computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale an image signal from a video source to fit the resolution of the display panel 100 and transmit it to the timing controller 130 together with the timing signal.

[0071] In a normal driving mode, the timing controller 130 may multiply an input frame frequency by i (i being a natural number) times to control the operation timing of the display panel driver with a frame frequency of the input frame frequency x i Hz. The input frame frequency is 60 Hz in a national television standards committee (NTSC) method and 50 Hz in a phase-alternating line (PAL) method.

[0072] The timing controller 130 lowers the frequency of the frame rate at which pixel data is written to pixels in the low speed driving mode than in the normal driving mode. For example, a data refresh frame frequency at which pixel data is written to pixels in the normal driving mode may be generated at a frequency of 60 Hz or higher, e.g., a refresh rate of any one of 60 Hz, 120 Hz, and 144 Hz, and a data refresh frame DRF in the low speed driving mode may be generated at a refresh rate of a lower frequency than that in the normal driving mode.

[0073] Based on the timing signal Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demulfiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0074] The gate timing control signal generated from the timing controller 130 may be inputted to the shift register of the gate driver 120 through a level shifter (not shown). The level shifter may receive the gate timing control signal to generate a start pulse and a shift clock, and provide them to the shift register of the gate driver 120.

[0076] FIG. 3 is a circuit diagram illustrating a pixel circuit according to an embodiment of the present disclosure. FIG. 4 is a waveform diagram illustrating a method of driving a pixel circuit according to an embodiment of the present disclosure.

[0076] Referring to FIGS. 3 and 4, the pixel circuit includes a light emitting element EL, a driving element DT for supplying a current to the light emitting element EL, a plurality of switch elements M1 to M5, a first capacitor Cl, and a second capacitor C2. In this pixel circuit, the driving element DT and the switch elements M1 to M5 may be implemented with n-channel oxide TFTs.

[0077] The gate signal includes a first scan pulse (or first gate pulse) SC1, a second scan pulse (or second gate pulse) SC2, a third scan pulse (or third gate pulse) SC3, a first EM pulse (or fourth gate pulse) EMI, and a second EM pulse (or fifth gate pulse) EM2. In order to drive the pixel circuit shown in FIG. 3, the gate driver 120 may include a first shift register sequentially outputting the first scan pulse SC1 and a second shift register sequentially outputting the second scan pulse 3C2, a third shift register sequentially outputting the third scan pulse SC3, a fourth shift register sequentially outputting the first EM pulse EM1, and a fifth shift register sequentially outputting the second EM pulse EM2.

[0078] The constant voltages such as the pixel driving voltage ELVDD, the low potential power voltage ELVSS, the reference voltage Vref, and the initialization voltage Vinit are applied to the pixel circuit. The pixel driving voltage ELVDD is higher than the low potential power voltage ELVSS. The gate-on voltages VGH and VEH may be set to be higher than the pixel driving voltage ELVDD. The gate-off voltages VGL and VEL may be set to be lower than the low potential power voltage ELVSS. The initialization voltage Vinit may be set to a low potential voltage higher than the low potential power voltage ELVSS. The reference voltage Vref may be set to a voltage at which the driving element DT can be turned on. The reference voltage Vref may be set to be within a voltage range of the data voltage Vdata outputted from the data driver 110. The maximum voltage of the data voltage Vdata is lower than the pixel driving voltage ELVDD, and the minimum voltage of the data voltage Vdata is higher than the low potential power voltage ELVSS.

[0079] In order to sample a threshold voltage Vth of the driving element DT in a sampling step SMPL, the reference voltage Vref is preferably set to a voltage higher than the initialization voltage Vinit. The voltage difference between the reference voltage Vref and the initialization voltage Vinit is set to be greater than the threshold voltage Vth of the driving element DT. The initialization voltage Vinit needs to be set to a voltage lower than the threshold voltage of the light emitting element EL in order to realize the lowest luminance, i.e., the luminance of the black grayscale of the pixel.

[0080] As shown in FIG. 4, the driving period of the pixel circuit includes an initialization step INIT, the sampling step SMPL set following the initialization step INIT, an addressing step WR set following the sampling step SMPL, and a light emission step EMIS set following the addressing Step WR.

[0081] The first scan pulse SC1 is generated as the gate-on voltage VGH in the addressing step WR in synchronization with the data voltage Vdata of the pixel data. The first scan pulse SC1 is the gate-off voltage VGL in the initialization step INIT, the sampling step SMPL, and the light emission step EMIS. The second scan pulse SC2 is generated as the gate-on voltage VGH in the initialization step INIT and the sampling step SMPL. The second scan pulse 5C2 is the gate-off voltage VGL in the addressing step WR and the light emission step EMIS. The third scan pulse SC3 is generated as the gate-on voltage VGH in the initialization step INIT. The third scan pulse 503 is the gate-off voltage VGL in the sampling step SMPL, the addressing step WR, and the light emission step EMIS.

[0082] The first EM pulse EM1 is the gate-off voltage VEL in the initialization step INIT and the addressing step WR. The first EM pulse EM1 is generated as the gate-on voltage VEH in the sampling step SMPL and the light emission step EMIS.

[0083] The second EM pulse EM2 is generated as the gate-on voltage VEH in the initialization step INIT and the light emission step EMIS. The second EM pulse EM2 is the gate-off voltage VEL in the sampling step SMPL and the addressing step WR.

[0084] The switch elements M1 to M5 are turned on when the gate-on voltages VGH and VEH are applied to their gate electrodes, whereas they are turned off when the gate-off voltages VGL and VEL are applied to their gate electrodes. The driving element DT is turned on when the gate-source voltage Vgs is higher than the threshold voltage Vth, and generates a current according to the gate-source voltage Vgs to drive the light emitting element EL.

[0085] The light emitting element EL may be implemented with an OLED. The OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL), but is not limited thereto. The anode electrode of the light emitting element EL is connected to a fourth node n4, and the cathode electrode thereof is connected to a VSS node to which the low potential power voltage ELVSS is applied.

The VSS node is connected to the VSS line. The light emitting element EL includes a capacitor Cel formed between an anode electrode and a cathode electrode. The OLED used as the light emitting element EL may have a tandem structure in which a plurality of light emitting layers are stacked. The OLED having a tandem structure may improve the luminance and lifespan of the pixel.

[0086] When a voltage is applied to the anode and cathode electrodes of the light emitting element EL, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML) to form excitons. In this case, visible light may be emitted from the emission layer EML.

[0087] The driving element DT includes a gate electrode connected to a second node DRG, a first electrode connected to a first node DRD, and a second electrode connected to a third node DRS.

Accordingly, voltages applied to the electrodes of the driving element DT are the same as the voltages of the first to third nodes DRD, DRG, and DRS, respectively.

[0088] The first capacitor Cl is connected between the second node DRG and the third node DRS. The first capacitor Cl stores the gate-source voltage Vgs of the driving element DT. The second capacitor C2 is connected between the third node DRS and a constant voltage node Vx. A constant voltage, e.g., any one of the pixel driving voltage ELVDD, the low-potential power voltage ELVSS, the reference voltage Vref, and the initialization voltage Vinit is applied to the constant voltage node Vx. The constant voltage node Vx may be connected to the VDD line through which a relatively stable constant voltage, e.g., the pixel driving voltage ELVDD is applied.

[0089] The transmission rate of the data voltage Vdata in the gate-source voltage Vgs of the driving element DT is determined according to the capacitance ratio of the first capacitor Cl and the second capacitor C2. The capacitances of the first capacitor Cl and the second capacitor C2 may be appropriately selected according to the voltage range of the data voltage Vdata and the driving characteristics of the display panel.

[0090] In the pixel circuit shown in FIG. 3, the gate-source voltage Vgs of the driving element DT has a value of (1-C)*(Vdata-Vref)+Vth in the light emission step EMIS. Here, C' = C1/(C1+C2). If C2 = 0, C' becomes 1, and (1-C') becomes 0 (zero) in the above calculation formula, so the gate-source voltage Vgs becomes equal to the threshold voltage Vth. Accordingly, in order for the gate-source voltage Vgs of the driving element DT to change according to the data voltage Vdata of the pixel data, the second capacitor C2 is required. ;[0091] A first switch element M1 is turned on in response to the gate-on voltage VGH of the first scan pulse SCI to supply the data voltage Vdata to the second node DRG in the addressing step WR. The first switch element M1 includes a gate electrode connected to a first gate line through which the first scan pulse SC1 is applied, a first electrode connected to a data line DL through which the data voltage Vdata is applied, and a second electrode connected to the second node DRG. ;[0092] The second switch element M2 is tumed on in response to the gate-on voltage VGH of the second scan pulse SC2 to supply the reference voltage Vref to the second node DRG in the initialization step!NIT and the sampling step SMPL. The second switch element M2 includes a gate electrode connected to a second gate line through which the second scan pulse 5C2 is applied, a first electrode connected to the REF line through which the reference voltage Vref is applied, and a second electrode connected to the second node DRG. ;[0093] When the data voltage Vdata and the reference voltage Vref are applied to the pixel circuit through the data line DL, the number of transitions applied to the data line DL increases, that is, the frequency increases, and thus power consumption of the display device increases. In contrast, in the present disclosure, since the data line DL through which the data voltage Vdata is applied and the REF line through which the reference voltage Vref is applied are separated from each other, the frequency of the voltage applied to the data line DL is lowered, so that power consumption may be reduced. ;[0094] The third switch element M3 is turned on in response to the gate-on voltage VGH of the third scan pulse SC3 to apply the initialization voltage Vinit to the fourth node n4 in the initialization step INIT. The third switch element M3 includes a gate electrode connected to a third gate line through which the third scan pulse SC3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the INIT line through which the initialization voltage Vinit is applied. ;[0095] The fourth switch element M4 is turned off in response to the gate-off voltage VEL of the first EM pulse EM1 to cut off a current path between the VDD line through which the pixel driving voltage ELVDD is applied and the first node DRD in the initialization step INIT and the addressing step WR. The fourth switch element M4 is turned on in response to the gate-on voltage VEH of the first EM pulse EM1 to connect the VDD line to the first node DRD in the sampling step SMPL and the light emission step EMIS. ;The fourth switch element M4 includes a gate electrode connected to a fourth gate line through which the first EM pulse EM1 is applied, a first electrode connected to the VDD line, and a second electrode connected to the first node DRD. ;[0096] The fifth switch element M5 is turned off in response to the gate-off voltage VEL of the second EM pulse EM2 to cut off a current path between the third node DRS and the fourth node n4 in the sampling step SMPL and the addressing step WR. The fifth switch element M5 is turned on in response to the gate-on voltage VEH of the second EM pulse EM2 to form a current path between the driving element DT and the light emitting element EL in the initialization step INIT and the light emission step EMIS. The fifth switch element M5 includes a gate electrode connected to a fifth gate line through which the second EM pulse EM2 is applied, a first electrode connected to the third node DRS, and a second electrode connected to the fourth node n4. ;[0097] FIG. 5A is a diagram illustrating a current flowing through the pixel circuit shown in FIG. 3 in the initialization step INIT. In the initialization step INIT, the second, third, and fifth switch elements M2, M3, and M5 are turned on. In the initialization step INIT, the first and fourth switch elements M1 and M4 are turned off. In the initialization step INIT, the voltages of the main nodes DRD, DRG, and DRS are Vref+Vth, Vref, and Vinit, respectively. Here, "Vth" is the threshold voltage of the driving element DT. Accordingly, since the gate-source voltage Vgs of the driving element DT has a value of Vref-Vinit greater than the threshold voltage Vth in the initialization step INIT, the driving element DT is turned on. ;[0098] FIG. 5B is a diagram illustrating a current flowing through the pixel circuit shown in FIG. 3 in the sampling step SMPL. In the sampling step SMPL, the second and fourth switch elements M2 and M4 are turned on, while the other switch elements Ml, M3 and M5 are turned off. In the sampling step SMPL, when the voltage of the third node DRS rises to make the gate-source voltage Vgs of the driving element DT reach the threshold voltage Vth, the driving element DT is turned off. At the end of the sampling step SMPL, the voltages of the main nodes DRD, DRG, and DRS are ELVDD, Vref, and Vref-Vth, respectively. Accordingly, when the sampling step SMPL is finished, the gate-source voltage Vgs of the driving element DT becomes equal to the threshold voltage Vth. The threshold voltage Vth of the driving element DT sampled in this way is charged in the first capacitor Cl. ;[0099] FIG. 5C is a diagram illustrating a current flowing through the pixel circuit shown in FIG. 3 in the addressing step WR. In the addressing step WR, the first switch element M1 is turned on to apply the data voltage Vdata of the pixel data to the second node DRG. At this time, the other switch elements M2, M3, M4, and M5 are turned off. At the end of the addressing step WR, the voltages of the main nodes DRD, DRG, and DRS are changed to ELVDD, Vdata, and Vref-Vth+C*(Vdata-Vref), respectively. Here, C' = C1/(C1+C2). The gate-source voltage Vgs of the driving element DT is changed to a value of (1-C)"(Vdata-Vref)+Vth in the addressing step WR.

[00100] As shown in FIGS. 5B and 5C, in the sampling step SMPL and the addressing step WR, the third node DRS is electrically disconnected from the fourth node n4. As a result, since the data addressing and threshold voltage sampling of the driving element DT are not affected by the resistance of the light emitting element EL and the process deviation of the light emitting element EL, the influence of the light emitting element EL on the luminance of the pixel may be excluded.

[00101] FIG. 5D is a diagram showing a current flowing through the pixel circuit shown in FIG. 3 in the light emission step EMIS. In the light emission step EMIS, the fourth and fifth switch elements M4 and M5 are turned on, while the other switch elements Ml, M2, and M3 are turned off. In the light emission step EMIS, the voltages of the main nodes DRD, DRG, and DRS are changed to ELVDD, Vdata, and Vref-Vth+C'"(Vdata-Vref), respectively. In the light emission step EMIS, the voltage of the third node DRS is equal to an anode voltage Vel of the light emitting element EL. The gate-source voltage Vgs of the driving element DT has a value of (1-C')"(Vdata-Vref)+Vth in the light emission step EMIS.

[00102] FIG. 6 is a waveform diagram illustrating a method of driving a pixel circuit according to another embodiment of the present disclosure. FIG. 7 is a diagram illustrating a current flowing through the pixel circuit shown in FIG. 3 in a second initialization step. In this embodiment, descriptions substantially the same as those of the above-described embodiment will be omitted. As shown in FIG. 6, a driving period of the pixel circuit includes a first initialization step INIT1, a sampling step SMPL set following the first initialization step INIT1, an addressing step WR set following the sampling step SMPL, a second initialization step INIT2 set following the addressing step WR, and a light emission step EMIS set following the second initialization step INIT2.

[00103] Referring to FIGS. 3, 6, and 7, the first scan pulse SC1 is generated as the gate-on voltage VGH in the addressing step WR in synchronization with the data voltage Vdata of the pixel data. The first scan pulse SC1 is the gate-off voltage VGL in the first initialization step INIT1, the sampling step SMPL, the second initialization step INIT2, and the light emission step EMIS. The second scan pulse SC2 is generated as the gate-on voltage VGH in the first initialization step INIT1 and the sampling step SMPL. The second scan pulse SC2 is the gate-off voltage VGL in the addressing step WR, the second initialization step INIT2, and the light emission step EMIS. The third scan pulse SC3 is generated as the gate-on voltage VGH in the first initialization step INIT1 and the second initialization step INIT2. The third scan pulse SC3 is the gate-off voltage VGL in the sampling step SMPL, the addressing step WR, and the light emission step EMIS.

[00104] The first EM pulse EMI is a gate-off voltage VEL in the first initialization step INIT1, the addressing step WR, and the second initialization step INIT2. The first EM pulse EMI is generated as the gate-on voltage VEH in the sampling step SMPL and the light emission step EMIS.

[00105] The second EM pulse EM2 is generated as the gate-on voltage VEH in the first initialization step INIT1, the second initialization step INIT2, and the light emission step EMIS. The second EM pulse EM2 is the gate-off voltage VEL in the sampling step SMPL and the addressing step WR.

[00106] In the first initialization step INIT1, as shown in FIG. 5A, the second, third, and fifth switch elements M2, M3, and M5 are turned on. In the first initialization step INIT1, the first and fourth switch elements M1 and M4 are turned off. In the sampling step SMPL, as shown in FIG. 5B, the second and fourth switch elements M2 and M4 are turned on, while the other switch elements Ml, M3, and M5 are turned off. In the addressing step WR, as shown in FIG. 5C, the first switch element M1 is turned on to apply the data voltage Vdata of the pixel data to the second node DRG. At this time, the other switch elements M2, M3, M4, and M5 are turned off.

[00107] In the second initialization step INIT2, as shown in FIG. 7, the third and fifth switch elements M3 and M5 are turned on, and the other switch elements Ml, M2, and M4 are turned off. In the second initialization step INIT2, the voltage of the third node DRS is initialized to the initialization voltage Vinit. At this time, the voltage of the second node DRG is also increased by the initialization voltage Vinit, so that the gate-source voltage Vgs of the driving element DT is maintained at the voltage set in the addressing step WR.

[00108] In the light emission step EMIS, as shown in FIG. 5D, the fourth and fifth switch elements M4 and M5 are turned on, while the other switch elements Ml, M2, and M3 are turned off. In the light emission step EMIS, the light emitting element EL may be driven by a current generated according to the gate-source voltage Vgs of the driving element DT to emit light with a luminance corresponding to the grayscale value of the pixel data.

[00109] The objects to be achieved by the present disclosure, the means for achieving the objects, and effects of the present disclosure described above do not specify essential features of the claims, and thus, the scope of the claims is not limited to the disclosure of the present disclosure.

[00110] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and do not limit the present disclosure. The protective scope of the present disclosure should be construed based on the following claims, and all the technical concepts in the equivalent scope thereof should be construed as falling within the scope of the present disclosure.

The disclosure comprises the following items:

1. A pixel circuit comprising: a driving element including a first electrode connected to a first node to which a first constant voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node; a light emitting element including an anode electrode connected to a fourth node, and a cathode electrode to which a second constant voltage lower than the first constant voltage is applied; a first switch element configured to supply a data voltage to the second node in response to a first gate pulse; a second switch element configured to apply a third constant voltage lower than the first constant voltage to the second node in response to a second gate pulse; a third switch element configured to supply a fourth constant voltage lower than the third constant voltage and higher than the second constant voltage to the fourth node in response to a third gate pulse; a fourth switch element configured to apply the first constant voltage to the first node in response to a fourth gate pulse; a fifth switch element configured to electrically connect the third node to the fourth node n4 in response to a fifth gate pulse; a first capacitor connected between the second node and the third node; and a second capacitor connected between the third node and a constant voltage node.

2. The pixel circuit of item 1, wherein any one of the first to fourth constant voltages is applied to the constant voltage node.

3. The pixel circuit of item 1 or item 2, wherein a voltage difference between the third constant voltage and the fourth constant voltage is higher than a threshold voltage of the driving element.

4. The pixel circuit of any preceding item, wherein a driving period of the pixel circuit includes an initialization step, a sampling step set following the initialization step, an addressing step set following the sampling step, and a light emission step set following the addressing step, wherein in the initialization step, the second, third, and fifth switch elements, and the driving element are turned on, and the first and fourth switch elements are turned-off, in the sampling step, the second and fourth switch elements are turned on, the first, third, and fifth switch elements are turned off, in the addressing step, the first switch element is turned on, and the second, third, fourth, and fifth switch elements are turned off, and in the light emission step, the fourth and fifth switch elements are turned on, and the first, second, and third switch elements are turned off.

5. The pixel circuit of any preceding item, wherein the driving element is turned on in the initialization step and turned off in the sampling step.

6. The pixel circuit of any preceding item, wherein the third node is electrically disconnected from the fourth node n4 in the sampling step and the addressing step.

7. The pixel circuit of any preceding item, wherein the first to fifth switch elements are turned on in response to a gate-on voltage and turned-off in response to a gate-off voltage, the first gate pulse is generated as the gate-on voltage in the addressing step in synchronization with the data voltage, and is generated as the gate-off voltage in the initialization step, the sampling step, and the light emission step, the second gate pulse is generated as the gate-on voltage in the initialization step and the sampling step, and is generated as the gate-off voltage in the addressing step and the light emission step, the third gate pulse is generated as the gate-on voltage in the initialization step, and is generated as the gate-off voltage in the sampling step, the addressing step, and the light emission step, the fourth gate pulse is generated as the gate-on voltage in the sampling step and the light emission step, and is generated as the gate-off voltage in the initialization step and the addressing step, and the fifth gate pulse is generated as the gate-on voltage in the initialization step INIT and the light emission step, and is generated as the gate-off voltage in the sampling step SMPL and the addressing step.

8. The pixel circuit of any preceding item, wherein a driving period of the pixel circuit includes a first initialization step, a sampling step set following the first initialization step, an addressing step set following the sampling step, a second initialization step set following the addressing step, and a light emission step set following the second initialization step, wherein in the first initialization step, the second, third, and fifth switch elements and the driving element are turned on, and the first and fourth switch elements are turned-off, in the sampling step, the second and fourth switch elements are turned on, and the first, third, and fifth switch elements are turned off, in the addressing step, the first switch element is turned on, and the second, third, fourth, and fifth switch elements are turned off, in the second initialization step, the third and fifth switch elements are turned on, and the first, second, third switch elements are turned off, and in the light emission step, the fourth and fifth switch elements are turned on, and the first, second, and third switch elements are turned off.

9. The pixel circuit of any preceding item, wherein the first to fifth switch elements are turned on in response to a gate-on voltage and turned-off in response to a gate-off voltage, the first gate pulse is generated as the gate-on voltage in the addressing step in synchronization with the data voltage, and is generated as the gate-off voltage in the first initialization step, the sampling step, the second initialization step, and the light emission step, the second gate pulse is generated as the gate-on voltage in the first initialization step and the sampling step, and is generated as the gate-off voltage in the addressing step, the second initialization step, and the light emission step, the third gate pulse is generated as the gate-on voltage in the first initialization step and the second initialization step, and is generated as the gate-off voltage in the sampling step, the addressing step, and the light emission step, the fourth gate pulse is generated as the gate-on voltage in the sampling step and the light emission step, and is generated as the gate-off voltage in the first initialization step, the addressing step, and the second initialization step, and the fifth gate pulse is generated as the gate-on voltage in the first initialization step, the second initialization step, and the light emission step, and is generated as the gate-off voltage in the sampling step and the addressing step.

10. A display device comprising: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, a plurality of power lines, and a plurality of pixel circuits connected to the plurality of data lines, the plurality of gate lines, and the plurality of power lines are arranged; a data driver configured to supply a data voltage of pixel data to the plurality of data lines and a gate driver configured to supply a gate signal to the plurality of gate lines, wherein each of the plurality of pixel circuits includes: a driving element including a first electrode connected to a first node to which a first constant voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node; a light emitting element including an anode electrode connected to a fourth node, and a cathode electrode to which a second constant voltage lower than the first constant voltage is applied; a first switch element configured to supply the data voltage to the second node in response to a first gate pulse; a second switch element configured to apply a third constant voltage lower than the first constant voltage to the second node in response to a second gate pulse; a third switch element configured to supply a fourth constant voltage lower than the third constant voltage and higher than the second constant voltage to the fourth node n4 in response to a third gate pulse; a fourth switch element configured to apply the first constant voltage to the first node in response to a fourth gate pulse; a fifth switch element configured to electrically connect the third node to the fourth node n4 in response to a fifth gate pulse; a first capacitor connected between the second node and the third node; and a second capacitor connected between the third node and a constant voltage node.

11. The display device of item 10, wherein a driving period of the pixel circuit includes an initialization step, a sampling step set following the initialization step, an addressing step set following the sampling step, and a light emission step set following the addressing step, wherein in the initialization step, the second, third, and fifth switch elements and the driving element are turned on, and the first and fourth switch elements are turned-off, in the sampling step, the second and fourth switch elements are turned on, the first, third, and fifth switch elements are turned off, in the addressing step, the first switch element is turned on, and the second, third, fourth, and fifth switch elements are turned off, and in the light emission step, the fourth and fifth switch elements are turned on, and the first, second, and third switch elements are turned off.

12. The display device of item 10 or item 11, wherein the first, second, third, fourth and fifth switch elements are turned on in response to a gate-on voltage and turned-off in response to a gate-off voltage, the first gate pulse is generated as the gate-on voltage in the addressing step in synchronization with the data voltage, and is generated as the gate-off voltage in the initialization step, the sampling step, and the light emission step, the second gate pulse is generated as the gate-on voltage in the initialization step and the sampling step, and is generated as the gate-off voltage in the addressing step and the light emission step, the third gate pulse is generated as the gate-on voltage in the initialization step, and is generated as the gate-off voltage in the sampling step, the addressing step, and the light emission step, the fourth gate pulse is generated as the gate-on voltage in the sampling step and the light emission step, and is generated as the gate-off voltage in the initialization step and the addressing step, and the fifth gate pulse is generated as the gate-on voltage in the initialization step and the light emission step, and is generated as the gate-off voltage in the sampling step and the addressing step.

13. The display device of any of items 10-12, wherein a driving period of the pixel circuit includes a first initialization step, a sampling step set following the first initialization step, an addressing step set following the sampling step, a second initialization step set following the addressing step, and a light emission step set following the second initialization step, wherein in the first initialization step, the second, third, and fifth switch elements and the driving element are turned on, and the first and fourth switch elements are turned-off, in the sampling step, the second and fourth switch elements are turned on, and the first, third, and fifth switch elements are turned off, in the addressing step, the first switch element is turned on, and the second, third, fourth, and fifth switch elements are turned off, in the second initialization step, the third and fifth switch elements are turned on, and the first, second, third switch elements are turned off, and in the light emission step, the fourth and fifth switch elements are turned on, and the first, second, and third switch elements are turned off.

14. The display device of any of items 10-13, wherein the first, second, third, fourth and fifth switch elements are turned on in response to a gate-on voltage and turned-off in response to a gate-off voltage, the first gate pulse is generated as the gate-on voltage in the addressing step in synchronization with the data voltage, and is generated as the gate-off voltage in the first initialization step, the sampling step, the second initialization step, and the light emission step, the second gate pulse is generated as the gate-on voltage in the first initialization step and the sampling step, and is generated as the gate-off voltage in the addressing step, the second initialization step, and the light emission step, the third gate pulse is generated as the gate-on voltage in the first initialization step and the second initialization step, and is generated as the gate-off voltage in the sampling step, the addressing step, and the light emission step, the fourth gate pulse is generated as the gate-on voltage in the sampling step and the light emission step, and is generated as the gate-off voltage in the first initialization step, the addressing step, and the second initialization step, and the fifth gate pulse is generated as the gate-on voltage in the first initialization step, the second initialization step, and the light emission step, and is generated as the gate-off voltage in the sampling step and the addressing step.

15. The display device of any of items 10-14, wherein all transistors of the display panel including the driving element and the first, second, third, fourth and fifth switch elements of the plurality of pixel circuits include an n-channel oxide semiconductor.

Claims

WHAT IS CLAIMED IS: 1. A pixel circuit comprising: a driving element including: a first electrode connected to a first node configured for application of a first constant voltage thereto; a gate electrode connected to a second node; and a second electrode connected to a third node; a light emitting element including: an anode electrode connected to a fourth node; and a cathode electrode configured for application of a second constant voltage thereto, wherein the second constant voltage is lower than the first constant voltage; a first switch element configured to supply a data voltage to the second node in response to a first gate pulse; a second switch element configured to apply a third constant voltage lower than the first constant voltage to the second node in response to a second gate pulse; a third switch element configured to supply a fourth constant voltage lower than the third constant voltage and higher than the second constant voltage to the fourth node in response to a third gate pulse; a fourth switch element configured to apply the first constant voltage to the first node in response to a fourth gate pulse; a fifth switch element configured to electrically connect the third node to the fourth node in response to a fifth gate pulse; a first capacitor connected between the second node and the third node; and a second capacitor connected between the third node and a constant voltage node.
2. The pixel circuit of claim 1, configured for application of any one of the first to fourth constant voltages to the constant voltage node.
3. The pixel circuit of claim 1 or claim 2, configured such that a voltage difference between the third constant voltage and the fourth constant voltage is higher than a threshold voltage of the driving element.
4. The pixel circuit of any preceding claim, configured such that a driving period of the pixel circuit includes an initialization step, a sampling step set following the initialization step, an addressing step set following the sampling step, and a light emission step set following the addressing step, wherein: in the initialization step, the second, third, and fifth switch elements, and the driving element are turned on, and the first and fourth switch elements are turned-off; in the sampling step, the second and fourth switch elements are turned on, the first, third, and fifth switch elements are turned off; in the addressing step, the first switch element is turned on, and the second, third, fourth, and fifth switch elements are turned off; and in the light emission step, the fourth and fifth switch elements are turned on, and the first, second, and third switch elements are turned off.
5. The pixel circuit of claim 4, configured such that the driving element is turned on in the initialization step and turned off in the sampling step.
6. The pixel circuit of claim 4 or claim 5, configured such that the third node is electrically disconnected from the fourth node in the sampling step and the addressing step.
7. The pixel circuit of any of claims 4-6, configured such that: the first to fifth switch elements are turned on in response to a gate-on voltage and turned off in response to a gate-off voltage; the first gate pulse is generated as the gate-on voltage in the addressing step in synchronization with the data voltage, and is generated as the gate-off voltage in the initialization step, the sampling step, and the light emission step; the second gate pulse is generated as the gate-on voltage in the initialization step and the sampling step, and is generated as the gate-off voltage in the addressing step and the light emission step; the third gate pulse is generated as the gate-on voltage in the initialization step, and is generated as the gate-off voltage in the sampling step, the addressing step, and the light emission step; the fourth gate pulse is generated as the gate-on voltage in the sampling step and the light emission step, and is generated as the gate-off voltage in the initialization step and the addressing step; 20 and the fifth gate pulse is generated as the gate-on voltage in the initialization step and the light emission step, and is generated as the gate-off voltage in the sampling step and the addressing step.
8. The pixel circuit of claim 1, configured such that a driving period of the pixel circuit includes a first initialization step, a sampling step set following the first initialization step, an addressing step set following the sampling step, a second initialization step set following the addressing step, and a light emission step set following the second initialization step, wherein: in the first initialization step, the second, third, and fifth switch elements and the driving element are turned on, and the first and fourth switch elements are turned off; in the sampling step, the second and fourth switch elements are turned on, and the first, third, and fifth switch elements are turned off; in the addressing step, the first switch element is turned on, and the second, third, fourth, and fifth switch elements are turned off; in the second initialization step, the third and fifth switch elements are turned on, and the first, second, third switch elements are turned off; and in the light emission step, the fourth and fifth switch elements are turned on, and the first, second, and third switch elements are turned off.
9. The pixel circuit of claim 8, configured such that: the first to fifth switch elements are turned on in response to a gate-on voltage and turned-off in response to a gate-off voltage; the first gate pulse is generated as the gate-on voltage in the addressing step in synchronization with the data voltage, and is generated as the gate-off voltage in the first initialization step, the sampling step, the second initialization step, and the light emission step; the second gate pulse is generated as the gate-on voltage in the first initialization step and the sampling step, and is generated as the gate-off voltage in the addressing step, the second initialization step, and the light emission step; the third gate pulse is generated as the gate-on voltage in the first initialization step and the second initialization step, and is generated as the gate-off voltage in the sampling step, the addressing step, and the light emission step; the fourth gate pulse is generated as the gate-on voltage in the sampling step and the light emission step, and is generated as the gate-off voltage in the first initialization step, the addressing step, and the second initialization step; and the fifth gate pulse is generated as the gate-on voltage in the first initialization step, the second initialization step, and the light emission step, and is generated as the gate-off voltage in the sampling step and the addressing step.
10. A display device comprising: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, a plurality of power lines, and a plurality of pixel circuits connected to the plurality of data lines, the plurality of gate lines, and the plurality of power lines are arranged; a data driver configured to supply a data voltage of pixel data to the plurality of data lines and a gate driver configured to supply a gate signal to the plurality of gate lines, wherein each of the plurality of pixel circuits includes: a driving element including: a first electrode connected to a first node configured for application of a first constant voltage thereto; a gate electrode connected to a second node; and a second electrode connected to a third node; a light emitting element including: an anode electrode connected to a fourth node; and a cathode electrode configured for application of a second constant voltage thereto, wherein the second constant voltage is lower than the first constant voltage; a first switch element configured to supply the data voltage to the second node in response to a first gate pulse; a second switch element configured to apply a third constant voltage lower than the first constant voltage to the second node in response to a second gate pulse; a third switch element configured to supply a fourth constant voltage lower than the third constant voltage and higher than the second constant voltage to the fourth node in response to a third gate pulse; a fourth switch element configured to apply the first constant voltage to the first node in response to a fourth gate pulse; a fifth switch element configured to electrically connect the third node to the fourth node in response to a fifth gate pulse; a first capacitor connected between the second node and the third node; and a second capacitor connected between the third node and a constant voltage node.
11. The display device of claim 10, configured such that a driving period of the pixel circuit includes an initialization step, a sampling step set following the initialization step, an addressing step set following the sampling step, and a light emission step set following the addressing step, wherein: in the initialization step, the second, third, and fifth switch elements and the driving element are turned on, and the first and fourth switch elements are turned off; in the sampling step, the second and fourth switch elements are turned on, the first, third, and fifth switch elements are turned off; in the addressing step, the first switch element is turned on, and the second, third, fourth, and fifth switch elements are turned off; and in the light emission step, the fourth and fifth switch elements are turned on, and the first, second, and third switch elements are turned off.
12. The display device of claim 11, configured such that: the first, second, third, fourth and fifth switch elements are turned on in response to a gate-on voltage and turned off in response to a gate-off voltage; the first gate pulse is generated as the gate-on voltage in the addressing step in synchronization with the data voltage, and is generated as the gate-off voltage in the initialization step, the sampling step, and the light emission step; the second gate pulse is generated as the gate-on voltage in the initialization step and the sampling step, and is generated as the gate-off voltage in the addressing step and the light emission step; the third gate pulse is generated as the gate-on voltage in the initialization step, and is generated as the gate-off voltage in the sampling step, the addressing step, and the light emission step; the fourth gate pulse is generated as the gate-on voltage in the sampling step and the light emission step, and is generated as the gate-off voltage in the initialization step and the addressing step; and the fifth gate pulse is generated as the gate-on voltage in the initialization step and the light emission step, and is generated as the gate-off voltage in the sampling step and the addressing step.
13. The display device of claim 10, configured such that a driving period of the pixel circuit includes a first initialization step, a sampling step set following the first initialization step, an addressing step set following the sampling step, a second initialization step set following the addressing step, and a light emission step set following the second initialization step, wherein: in the first initialization step, the second, third, and fifth switch elements and the driving element are turned on, and the first and fourth switch elements are turned off; in the sampling step, the second and fourth switch elements are turned on, and the first, third, and fifth switch elements are turned off; in the addressing step, the first switch element is turned on, and the second, third, fourth, and fifth switch elements are turned off; in the second initialization step, the third and fifth switch elements are turned on, and the first, second, third switch elements are turned off; and in the light emission step, the fourth and fifth switch elements are turned on, and the first, second, and third switch elements are turned off.
14. The display device of claim 13, configured such that: the first, second, third, fourth and fifth switch elements are turned on in response to a gate-on voltage and turned off in response to a gate-off voltage; the first gate pulse is generated as the gate-on voltage in the addressing step in synchronization with the data voltage, and is generated as the gate-off voltage in the first initialization step, the sampling step, the second initialization step, and the light emission step; the second gate pulse is generated as the gate-on voltage in the first initialization step and the sampling step, and is generated as the gate-off voltage in the addressing step, the second initialization step, and the light emission step; the third gate pulse is generated as the gate-on voltage in the first initialization step and the second initialization step, and is generated as the gate-off voltage in the sampling step, the addressing step, and the light emission step; the fourth gate pulse is generated as the gate-on voltage in the sampling step and the light emission step, and is generated as the gate-off voltage in the first initialization step, the addressing step, and the second initialization step; and the fifth gate pulse is generated as the gate-on voltage in the first initialization step, the second initialization step, and the light emission step, and is generated as the gate-off voltage in the sampling step and the addressing step.
15. The display device of any of claims 10-14, wherein all transistors of the display panel including the driving element and the first, second, third, fourth and fifth switch elements of the plurality of pixel circuits include an n-channel oxide semiconductor.