KR20230044911A - Pixel circuit and display device including the same - Google Patents

Abstract

Disclosed are a pixel circuit and a display device including the same. The pixel circuit includes: a first driving element including a first electrode connected to a (1-1)^th node, a second electrode connected to a (1-2)^th node, and the second electrode connected to a (1-3)^th node; and a second driving element including a first electrode connected to a (2-1)^th node, a gate electrode connected to a (2-2)^th node, and a second electrode connected to a second-third node. A second electrode voltage of the first driving element is transmitted to the gate electrode of the second driving element, and a second electrode voltage of the second driving element is transmitted to the gate electrode of the first driving element. Therefore, the reliability of a transistor can be improved.

Description

Pixel circuit and display device including the same {PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a pixel circuit and a display device including the same.

Electroluminescence displays can be divided into inorganic light emitting displays and organic light emitting displays according to the material of the light emitting layer. An active matrix type organic light emitting display includes an organic light emitting diode (OLED) that emits light by itself, and has a fast response speed, high luminous efficiency, luminance, and viewing angle. There are advantages. Organic Light Emitting Diode (OLED) is formed in each pixel of the organic light emitting display device. The organic light emitting display device has a fast response speed, excellent luminous efficiency, luminance, viewing angle, etc., as well as black gradation. Since it can be expressed in complete black, the contrast ratio and color gamut are excellent.

A pixel circuit of a field emission display device includes an OLED used as a light emitting element and a driving element for driving the OLED. The pixel circuit may sense the threshold voltage of the driving element and compensate for a threshold voltage variation according to the accumulation of driving times of the pixels. Such a pixel circuit may sense a threshold voltage of a driving element using a source follower circuit or a diode connection circuit.

The pixel circuit of the source follower structure can sense the threshold voltage of the driving element smaller than 0 [V] and transfers the threshold voltage charged in the source node to the gate node through the capacitor. In the pixel circuit having the source follower structure, a sensing rate of a threshold voltage may decrease according to a capacitance ratio of capacitors.

A pixel circuit having a diode connection structure can apply a threshold voltage to a gate node without lowering a threshold voltage sensing rate, but it is difficult to sense a threshold voltage of a driving element smaller than 0 [V] unless additional measures are taken.

The present invention aims to address the aforementioned needs and/or problems. The present invention provides a pixel circuit capable of sensing a threshold voltage smaller than 0 [V] and improving reliability of a transistor and a display device including the same.

The objects of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

A pixel circuit according to an embodiment of the present invention includes a first driving element including a first electrode connected to a 1-1 node, a second electrode connected to a 1-2 node, and a second electrode connected to a 1-3 node. ; and a second driving element including a first electrode connected to the 2-1 node, a second electrode connected to the 2-2 node, and a second electrode connected to the 2-3 node.

The voltage of the second electrode of the first driving element is transferred to the gate electrode of the second driving element. The second electrode voltage of the second driving element is transmitted to the gate electrode of the first driving element.

A display device according to an exemplary embodiment of the present invention includes a display panel on which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixels are disposed; a data driver that converts pixel data into data voltages and supplies them to the data lines; and a gate driver supplying gate pulses to the gate lines.

A first pixel includes the first driving element. A second pixel adjacent to the first pixel includes a second driving element. The voltage of the second electrode of the first driving element is transferred to the gate electrode of the second driving element. The second electrode voltage of the second driving element is transmitted to the gate electrode of the first driving element.

The present invention can sense the threshold voltage of a driving element smaller than 0 [V] by sensing the threshold voltage of a driving element between adjacent pixels using the characteristic of high uniformity between adjacent pixels, and can improve the reliability of a transistor. can be improved

In the present invention, since the sensing step can be set for a time equal to or longer than two horizontal periods, a threshold voltage sensing time of the driving element can be sufficiently secured. In the present invention, in the sensing step, the threshold voltage of a driving element can be transmitted to the gate electrode of another adjacent driving element without deterioration of a sensing rate. Accordingly, the present invention can provide advantages of a pixel circuit having a source follower structure and a pixel circuit having a diode connection structure when sensing a threshold voltage of a driving element between adjacent pixels.

According to the present invention, by cross-applying data voltages to adjacent pixels and alternately driving EM switches, a threshold voltage shift deviation of driving elements between pixels can be offset and deterioration of driving elements and EM switch elements can be reduced.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a diagram showing a threshold voltage sensing method of a driving element in a pixel circuit according to an embodiment of the present invention.
2 is a diagram showing a method of writing pixel data in the pixel circuit of the present invention.
3 is a circuit diagram showing pixel circuits of adjacent pixels according to the first embodiment of the present invention.
FIG. 4 is a waveform diagram illustrating gate pulses applied to the pixel circuit shown in FIG. 3 and voltages of major nodes.
5 and 6 are diagrams illustrating initialization steps of the pixel circuit shown in FIG. 3 .
7 and 8 are diagrams illustrating a sensing step of the pixel circuit shown in FIG. 3 .
9 and 10 are diagrams illustrating a data writing step of the pixel circuit shown in FIG. 3 .
11 and 12 are diagrams illustrating light emitting steps of the pixel circuit shown in FIG. 3 .
13 is a diagram showing a threshold voltage of a driving element and a transfer rate of a data voltage according to capacities of 1-1 and 2-1 capacitors.
14 is a diagram showing simulation results of a pixel circuit according to the first embodiment of the present invention.
15 is a waveform diagram illustrating a driving method in which data voltages are cross-applied between adjacent pixels.
FIG. 16 is a circuit diagram showing a light emitting step of the pixel circuit shown in FIG. 3 in the driving method of the pixel circuit shown in FIG. 15 .
17A and 17B are circuit diagrams illustrating various embodiments of a capacitor connection structure of a pixel circuit.
18 is a circuit diagram showing a pixel circuit of adjacent pixels according to a second embodiment of the present invention.
19 is a circuit diagram showing a pixel circuit of adjacent pixels according to a third embodiment of the present invention.
20 is a circuit diagram showing a pixel circuit of adjacent pixels according to a fourth embodiment of the present invention.
21 is a circuit diagram showing a pixel circuit of adjacent pixels according to a fifth embodiment of the present invention.
FIG. 22 is a waveform diagram illustrating gate pulses applied to the pixel circuits shown in FIGS. 20 and 21 .
23 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.
24 is a cross-sectional view showing a cross-sectional structure of the display panel shown in FIG. 23;

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the embodiments will make the disclosure of the present invention complete, and those of ordinary skill in the art to which the present invention belongs It is provided to fully inform the scope of the invention, the invention is defined only by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to those shown in the drawings. Like reference numbers designate substantially like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When “has”, “includes”, “has”, “is made of”, etc. mentioned in this specification is used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it may be interpreted in the plural unless specifically stated otherwise.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when a positional relationship between two components is described as 'on ~', 'on top of ~', 'on the bottom of ~', 'next to', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

Although first, second, etc. may be used to distinguish the components, the function or structure of these components is not limited to the ordinal number or component name attached to the front of the component.

The following embodiments may be partially or wholly combined or combined with each other, and technically various interlocking and driving operations are possible. Each of the embodiments may be implemented independently of each other or together in an association relationship.

Each of the pixels is divided into a plurality of sub-pixels having different colors for color implementation, and each of the sub-pixels includes a transistor used as a switch element or a driving element. Such a transistor may be implemented as a TFT (Thin Film Transistor).

A driving circuit of the display device writes pixel data of an input image into pixels. A driving circuit of a flat panel display device includes a data driver for supplying data signals to data lines and a gate driver for supplying gate pulses to gate lines.

In the display device of the present invention, a pixel circuit may include a plurality of transistors. The transistor may be implemented as a thin film transistor (TFT) and may be an oxide TFT including an oxide semiconductor or an LTPS TFT including low temperature poly silicon (LTPS). In the present invention, the driving element of each of the pixels is implemented as an n-channel oxide TFT implemented as an oxide TFT. Switch elements other than driving elements in the pixels are not limited to oxide TFTs.

Compared to the LTPS TFT, the oxide TFT has a similar threshold voltage of the transistor between pixels, so the uniformity of the threshold voltage characteristic of the driving element is excellent over the entire screen. This is because the channel layer of the oxide TFT is manufactured based on an amorphous semiconductor, so there may be a difference in threshold voltage between driving elements when viewed as a whole, but there is almost no difference in threshold voltage between pixels in a local area. am. In the LTPS TFT, a threshold voltage difference of a driving element between adjacent pixels may increase depending on the position of a grain boundary due to the characteristics of multi-nodular silicon.

According to the present invention, a threshold voltage of a driving element is sensed by using substantially the same or similar driving element characteristics between adjacent pixels each including a driving element made of oxide TFTs.

A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within a transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit the transistor. The flow of carriers in a transistor flows from the source to the drain. In the case of an n-channel transistor, since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. The direction of current in an n-channel transistor is from drain to source. In the case of a p-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate pulse can swing between a Gate On Voltage and a Gate Off Voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

A transistor is turned on in response to a gate-on voltage, while it is turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage (VGH and VEH), and the gate-off voltage may be a gate low voltage (VGL and VEH).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described mainly with an organic light emitting display device, but the present invention is not limited thereto.

1 is a diagram illustrating a threshold voltage sensing method of a driving element in a pixel circuit according to an embodiment of the present invention. In FIG. 1 , 'PXL1' is a left sub-pixel and 'PXL2' is a right sub-pixel in adjacent sub-pixels. Hereinafter, the left sub-pixel PXL1 will be referred to as a first pixel PXL1 and the right sub-pixel PXL2 will be referred to as a second pixel PXL2 . Each of the first and second pixels includes driving elements DT1 and DT2 for driving light emitting elements. The driving elements DT1 and DT2 are implemented as n-channel oxide TFTs.

Referring to FIG. 1 , each of the driving elements DT1 and DT2 includes a gate electrode, a first electrode (or drain electrode), and a second electrode (or source electrode).

When the first driving element DT1 disposed in the first pixel PXL1 is turned on, the second electrode voltage (or source voltage) of the first driving element DT1 rises, and the source voltage DRS Delivered in 2 pixels (PXL2). When the second driving element DT2 disposed in the second pixel PXL2 is turned on, the second electrode voltage of the second driving element DT2 rises, and the source voltage DRS is applied to the first pixel PXL1. is forwarded to

Since the threshold voltages Vth of the first and second driving elements DT1 and DT2 are substantially the same, the threshold voltages of the driving elements DT1 and DT2 are accurately sensed in the first and second pixels PXL1 and PXL2. It can be. In particular, the threshold voltage Vth of the driving elements DT1 and DT2 can be sensed at a voltage higher than 0 [V], and can be sensed even when negatively shifted at a voltage lower than 0 [V]. In an example in which the gate voltage DRG of the second driving element DT2 is 10V and the drain voltage DRD of 13V is applied, the threshold voltage Vth of the driving elements DT1 and DT2 is -1 [V]. At this time, the source voltage DRS of the second driving element DT2 rises to 11V, and the source voltage DRS is transmitted to the first pixel PXL1. The threshold voltage Vth of the first driving element DT1 is sensed as a voltage difference between the gate voltage DTG of the first driving element DT1 and the source voltage DRS of the second driving element DT2. The threshold voltage Vth of the second driving element DT2 is sensed as a voltage difference between the gate voltage DTG of the first driving element DT1 and the source voltage DRS of the second driving element DT2. In FIG. 1, 'Vgs<0' represents a gate-to-source voltage of the driving elements DT1 and DT2 smaller than 0 [V].

2 is a diagram illustrating a method of writing pixel data in a pixel circuit according to an exemplary embodiment of the present invention. Threshold voltage sensing of the driving element and writing of pixel data are separated on the time axis.

Referring to FIG. 2 , the data voltage Vdata1 of pixel data to be written in the first pixel PXL1 is applied to the gate electrode of the first driving element DT1 through the capacitor C1. The switch element T01 of the first pixel circuit PXL1 is connected between the data line and the gate electrode of the first driving element DT1. The switch element T01 supplies the data voltage Vdata1 to the capacitor C1 in response to the scan pulse SCAN.

The data voltage Vdata2 of pixel data to be written in the second pixel PXL2 is applied to the gate electrode of the first driving element DT1 through the capacitor C. The switch element T02 of the first pixel circuit PXL1 is connected between the data line and the gate electrode of the second driving element DT2. The switch element T02 supplies the data voltage Vdata2 to the capacitor C2 in response to the scan pulse SCAN.

3 is a circuit diagram showing pixel circuits of adjacent pixels according to the first embodiment of the present invention. FIG. 4 is a waveform diagram illustrating gate pulses applied to the pixel circuit shown in FIG. 3 and voltages of major nodes. In FIG. 4 , 'DRG' is the gate voltage of the 1-2nd and 2-2nd nodes n12 and n22, that is, the driving elements DT1 and DT2. 'DRS' is the source voltage of the 1-3 and 2-3 nodes n13 and n23, that is, the driving elements DT1 and DT2. 'DRG_1' is the voltage of the 1-4th and 2-4th nodes n14 and n24. 'AND' is the anode voltage of the light emitting elements EL1 and EL2.

3 and 4 , the first pixel PXL1 includes a first light emitting element EL1, a first driving element DT1, 1-1 to 1-7 switch elements M11 to M17, and 1-1 and 1-2 capacitors Csup1 and Cst1. The second pixel PXL2 includes the second light emitting element EL2, the second driving element DT2, the 2-1st to 2-7th switch elements M21 to M27, and the 2-1st and 2nd- It includes 2 capacitors Csup2 and Cst2. The driving elements DT1 and DT2 and the switch elements M11 to M27 may be implemented as n-channel oxide TFTs.

The first and second pixels PXL1 and PXL2 share power lines to which constant voltages EVDD, EVSS, Vref, and Vinit are applied, and gate lines to which gate pulses SCAN1, SCAN2, EM1, EM2, and EM3 are applied. share them The first and second pixels PXL1 and PXL2 are connected to different data lines. The first pixel PXL1 may be connected to the first data line to which the first data voltage Vdata1 is applied. The second pixel PXL2 may be connected to the second data line to which the second data voltage Vdata2 is applied.

The power supply lines include a VDD line to which the pixel driving voltage EVDD is applied, a VSS line to which the pixel reference voltage EVSS is applied, an INIT line to which the initialization voltage Vinit is applied, and a REF line to which the reference voltage Vref is applied. can include The pixel driving voltage EVDD is a voltage higher than the maximum voltage of the data voltages Vdata1 and Vdata2. The reference voltage Vref is lower than the minimum voltage of the data voltages Vdata1 and Vdata2. The pixel reference voltage EVSS and the initialization voltage Vinit are voltages lower than the reference voltage Vref. The pixel reference voltage EVSS and the initialization voltage Vinit may be set to the same voltage or different voltages.

The voltages of the data voltages Vdata1 and Vdata2 may be determined according to the gray level of pixel data in a dynamic range of 5 [V] to 10 [V]. In this case, EVDD=constant voltage within the range of 13[V] to 16[V], EVSS=constant voltage within the range of 0[V] to 2[V], Vref=3.0[V], Vinit=0[V] to 2[V] ] may be set to a constant voltage within, but is not limited thereto.

The gate pulses SCAN1 , SCAN2 , EM1 , EM2 , and EM3 are generated as swinging pulses between gate-on voltages VGH and VEH and gate-off voltages VGL and VEL. The gate-on voltages VGH and VEH may be set to higher voltages than the pixel driving voltage EVDD. The gate-off voltages VGL and VEL may be set to voltages lower than the pixel reference voltage EVSS. The gate pulses SCAN1, SCAN2, EM1, EM2, and EM3 are a first scan pulse SCAN1 applied to a first gate line, a second scan pulse SCAN2 applied to a second gate line, and a third gate line applied. A first discharge control pulse (hereinafter referred to as a “pulse” pulse) (EM1), a second EM pulse (EM2) applied to the fourth gate line, and a third EM pulse (EM3) applied to the fifth gate line. includes The gate driver of the display device includes a first shift register generating the first scan pulse SCAN1, a second shift register generating the second scan pulse SCAN2, and a third shift register generating the first EM pulse. registers, a fourth shift register for generating the second EM pulse, and a fifth shift register for generating the fifth EM pulse.

As shown in FIG. 4 , the driving period of the pixel circuit may be divided into an initialization phase (Pi), a sensing phase (Ps), a data writing phase (Pw), a boosting phase (Pb), and an emission phase (Pem). A hold step (Ph) may be set between the data writing step (Pw) and the boosting step (Pb).

In the initialization step Pi, as shown in FIG. 4 , the first scan pulse SCAN1 and the second EM pulse EM2 are generated as gate-on voltages VGH and VEH. In the initialization step (Pi), the second scan pulse (SCAN2), the first EM pulse (EM1), and the third EM pulse (EM3) are the gate off voltages (VGL, VEL).

In the sensing step Ps, as shown in FIG. 4 , the first scan pulse SCAN1 and the first EM pulse EM1 are generated as gate-on voltages VGH and VEH. The second scan pulse SCAN2 , the second EM pulse EM2 , and the third EM pulse EM3 are gate off voltages VGL and VEL in the sensing step Ps.

In the data writing step Pw, as shown in FIG. 4 , the second scan pulse SCAN2 is generated with a gate-on voltage VGH that is synchronized with the data voltages Vdata1 and Vdata2 of the pixel data. Gate pulses SCAN1 , EM1 , EM2 , and EM3 other than the second scan pulse SCAN2 are generated as gate-off voltages VGL and VEL in the data writing step Pw.

In the hold phase (Ph), all gate pulses (SCAN1, SCAN2, EM1, EM2, and EM3) are gate off voltages (VGL, VEL). At this time, the main nodes n11 to n14 and n21 to n24 of the pixel circuit are floating to maintain voltage.

As shown in FIG. 4 in the boosting phase Pb and the emission phase Pem, the first and second EM pulses EM1 and EM2 are the gate-on voltage VEH, while the first and second scan pulses (SCAN1, SCAN2) and the third EM pulse (EM3) are the gate off voltage (VGL).

The light emitting elements EL1 and EL2 may be implemented as OLEDs. An OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer, EIL), but is not limited thereto. When voltage is applied to the anode and cathode electrodes of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML) to form excitons. At this time, visible light is emitted from the light emitting layer EML.

Anode electrodes of the light emitting elements EL1 and EL2 are connected to the driving elements DT1 and DT2 with the switch elements M16, M17, M26 and M27 interposed therebetween. When the switch elements M16, M17, M26, and M27 are turned on, the anode electrodes of the light emitting elements EL1 and EL2 are connected to the driving elements DT1 and DT2 to receive current from the driving elements DT1 and DT2. can be illuminated by Cathode electrodes of the light emitting elements EL1 and EL2 are connected to the VSS line to which the pixel reference voltage EVSS is applied. The light emitting elements EL1 and EL2 include a capacitor Cel1 connected between an anode electrode and a cathode electrode, as shown in FIGS. 17A and 17B .

In the first pixel PXL1 , the first driving element DT1 drives the first light emitting element EL1 by generating a current according to the gate-source voltage Vgs. The first driving element DT1 includes a first electrode connected to the 1-1 node n11, a gate electrode connected to the 1-2 node n12, and a second electrode connected to the 1-3 node n13. include

The 1-1 capacitor Csup1 is connected between the 1-2 node n12 and the 1-4 node n14 to transfer the data voltage Vdata1 of pixel data to the 1-2 node n12. . The 1-2 capacitor Cst1 is connected between the 1-2 node n12 and the 1-3 node n13 to store the gate-to-source voltage Vgs of the first driving element DT1. Capacities of the 1-1 capacitor Csup1 and the 1-2 capacitor Cst1 may be set to the same or different values.

The 1-1 switch element M11 is turned on according to the gate-on voltage VGH of the first scan pulse SCAN1 in the initialization phase Pi and the sensing phase Ps, and the 1-4 node n14 is connected to the 2-3 node n23 of the second pixel PXL2. The 1-1 switch element M11 includes a gate electrode connected to the first gate line to which the first scan pulse SCAN1 is applied, a first electrode connected to the 1-4 node n14, and a 2-3 node ( and a second electrode connected to n23).

The 1st-2nd switch element M12 is turned on according to the gate-on voltage VGH of the first scan pulse SCAN1 in the initialization phase Pi and the sensing phase Ps to generate the first reference voltage Vref. -2 Supply to node n12. The 1-2 switch element M12 includes a gate electrode connected to the first gate line to which the first scan pulse SCAN1 is applied, a first electrode connected to the REF line to which the reference voltage Vref is applied, and the 1-2 th switch element M12. and a second electrode connected to the node n12.

The first to third switch elements M13 are turned on according to the gate-on voltage VGH of the first scan pulse SCAN1 in the initialization phase Pi and the sensing phase Ps to set the initialization voltage Vinit to the first It is supplied to the anode electrode of the light emitting element EL1. The 1-3 switch element M13 includes a gate electrode connected to a first gate line to which the first scan pulse SCAN1 is applied, a first electrode connected to an INIT line to which an initialization voltage Vinit is applied, and a first light emitting element. and a second electrode connected to the anode electrode of (EL1).

The first to fourth switch elements M14 are turned on according to the gate-on voltage VGH of the second scan pulse SCAN2 synchronized with the data voltage Vdata1 of the pixel data in the data writing step Pw, and thus the data voltage (Vdata1) is supplied to the 1st-4th node n14. The first to fourth switch elements M14 include a gate electrode connected to a second gate line to which the second scan pulse SCAN2 is applied, a first electrode connected to a first data line to which a data voltage Vdata1 is applied, and a first electrode connected to a first data line to which a data voltage Vdata1 is applied. -4 includes a second electrode connected to the node n14.

The first to fifth switch elements M15 are turned on according to the gate-on voltage VEH of the first EM pulse EM1 in the sensing step Ps, the boosting step Pb, and the light emitting step Pem to turn on the pixel The driving voltage EVDD is supplied to the 1-1 node n11. The first to fifth switch elements M15 include a gate electrode connected to the third gate line to which the first EM pulse EM1 is applied, a first electrode connected to the VDD line to which the pixel driving voltage EVDD is applied, and the first to fifth switch elements M15. 1 includes a second electrode connected to node n11.

The first to sixth switch elements M16 are turned on according to the gate-on voltage VEH of the second EM pulse EM2 in the initialization phase (Pi), the boosting phase (Pb), and the light emission phase (Pem). The 1-3 node n13 is connected to the anode electrode of the first light emitting element EL1. The 1-6th switch element M16 includes a gate electrode connected to the fourth gate line to which the second EM pulse EM2 is applied, a first electrode connected to the 1-3th node n13, and a first light emitting element EL1. ) and a second electrode connected to the anode electrode.

In the first to seventh switch elements M17, a threshold voltage shift deviation of the driving elements DT1 and DT2 may occur between adjacent pixels PXL1 and PXL2, and data It may be used when the voltages Vdata1 and Vdata2 are alternately applied between the pixels PXL1 and PXL2. The 1-7th switch element M17 includes a gate electrode connected to the fifth gate line to which the third EM pulse EM3 is applied, a first electrode connected to the 2-3 node n23, and a first light emitting element EL1. ) and a second electrode connected to the anode electrode. When the data voltages Vdata1 and Vdata2 are not cross-applied between the pixels PXL1 and PXL2, the third EM pulse EM3 maintains the gate-off voltage VEL as shown in FIG. The switch element M17 is in an off state. The first to seventh switch elements M17 may be omitted as shown in FIGS. 18 to 21 .

In the second pixel PXL2 , the second driving element DT2 generates current according to the gate-source voltage Vgs to drive the second light emitting element EL2 . The second driving element DT2 includes a first electrode connected to the 2-1 node n21, a gate electrode connected to the 2-2 node n22, and a second electrode connected to the 2-3 node n23. include

The 2-1 capacitor Csup2 is connected between the 2-2 node n22 and the 2-4 node n24 to transfer the data voltage Vdata2 of pixel data to the 2-2 node n22. . The 2-2nd capacitor Cst2 is connected between the 2-2nd node n22 and the 2-3rd node n23 to store the gate-source voltage Vgs of the second driving element DT2. Capacities of the 2-1 capacitor Csup2 and the 2-2 capacitor Cst2 may be set to the same or different values.

The 2-1st switch element M21 is turned on according to the gate-on voltage VGH of the first scan pulse SCAN1 in the initialization phase Pi and the sensing phase Ps, and the 2-4th node n24 is connected to the 1-3 nodes n13 of the first pixel PXL1. The 2-1 switch element M21 includes a gate electrode connected to the first gate line to which the first scan pulse SCAN1 is applied, a first electrode connected to the 2-4 node n24, and a 1-3 node ( and a second electrode connected to n13).

The 2-2nd switch element M22 is turned on according to the gate-on voltage VGH of the first scan pulse SCAN1 in the initialization phase Pi and the sensing phase Ps to set the reference voltage Vref to the second -2 Supply to node n22. The 2-2nd switch element M22 includes a gate electrode connected to the first gate line to which the first scan pulse SCAN1 is applied, a first electrode connected to the REF line to which the reference voltage Vref is applied, and the 2-2nd switch element M22. and a second electrode connected to node n22.

The 2-3rd switch element M23 is turned on according to the gate-on voltage VGH of the first scan pulse SCAN1 in the initialization phase Pi and the sensing phase Ps to set the initialization voltage Vinit to the second It is supplied to the anode electrode of the light emitting element EL2. The 2-3 switch element M23 includes a gate electrode connected to the first gate line to which the first scan pulse SCAN1 is applied, a first electrode connected to the INIT line to which the initialization voltage Vinit is applied, and a second light emitting element. and a second electrode connected to the anode electrode of (EL2).

The second-fourth switch element M24 is turned on according to the gate-on voltage VGH of the second scan pulse SCAN2 synchronized with the data voltage Vdata2 of the pixel data in the data writing step Pw, and thus the data voltage (Vdata2) is supplied to the 2-4th node n24. The 2-4 switch element M24 includes a gate electrode connected to the second gate line to which the second scan pulse SCAN2 is applied, a first electrode connected to the second data line to which the data voltage Vdata2 is applied, and a second gate electrode connected to the second data line to which the data voltage Vdata2 is applied. -4 includes a second electrode connected to the node n24.

The second-fifth switch element M25 is turned on according to the gate-on voltage VEH of the first EM pulse EM1 in the sensing step Ps, the boosting step Pb, and the light emitting step Pem to turn on the pixel The driving voltage EVDD is supplied to the 2-1 node n21. The 2-5th switch element M25 includes a gate electrode connected to the third gate line to which the first EM pulse EM1 is applied, a first electrode connected to the VDD line to which the pixel driving voltage EVDD is applied, and the second-to-fifth switch element M25. 1 includes a second electrode connected to node n21.

The 2-6th switch element M26 is turned on according to the gate-on voltage VEH of the second EM pulse EM2 in the initialization phase (Pi), the boosting phase (Pb), and the emission phase (Pem), and 2-3 The node n23 is connected to the anode electrode of the second light emitting element EL2. The 2-6th switch element M26 includes a gate electrode connected to the fourth gate line to which the second EM pulse EM2 is applied, a first electrode connected to the 2-3 node n23, and a second light emitting element EL2. ) and a second electrode connected to the anode electrode.

In the 2-7th switch element M27, a threshold voltage shift deviation of the driving elements DT1 and DT2 may occur between adjacent pixels PXL1 and PXL2, and to offset this threshold voltage shift deviation, the data voltage Vdata1 , Vdata2) may be used when cross-applied between the pixels PXL1 and PXL2. The 2-7th switch element M27 includes a gate electrode connected to the fifth gate line to which the third EM pulse EM3 is applied, a first electrode connected to the 1-3 node n13, and a second light emitting element EL2. ) and a second electrode connected to the anode electrode. When the data voltages Vdata1 and Vdata2 are not cross-applied between the pixels PXL1 and PXL2, the third EM pulse EM3 maintains the gate-off voltage VEL as shown in FIG. The switch element M27 is off. The 2-7th switch element M27 can be omitted as shown in FIGS. 18 to 21 .

In the initialization step (Pi), as shown in FIGS. 5 and 6, the 1-1, 1-2, 1-3, 1-6, 2-1, 2-2, and 2- 3 and 2-6th switch elements M11, M12, M13, M16, M21, M22, M23, M26 and driving elements DT1 and DT2 are turned on, and other switch elements M14 and M15 , M17, M24, M25, M27) are turned off. At this time, the light emitting elements EL1 and EL2 are not turned on. In the initialization step (Pi), the main nodes (n12, n13, n14, n22, n23, n24), capacitors (Csup1, Cst1, Csup2, Cst2) and light emitting elements (EL1, EL2) of the pixel circuit are initialized. . In the initialization step Pi, the voltages of the 1-2nd and 2-2nd nodes n12 and n22 are the reference voltage Vref. In the initialization step (Pi), the anode electrodes of the first-third, first-fourth, second-third, and second-fourth nodes n13, n14, n23, and n24 and the light emitting elements EL1 and EL2 The voltage is the initialization voltage (Vinit).

In the sensing step (Ps), as shown in FIGS. 7 and 8 , the 1-1, 1-2, 1-3, 1-5, 2-1, 2-2, and 2- 3 and 2-5 switch elements M11, M12, M13, M15, M21, M22, M23, and M25 are turned on, and other switch elements M14, M16, M17, M24, M26, and M27 is turned off. The driving elements DT1 and DT2 are turned off when the gate-source voltage Vgs reaches the threshold voltage Vth in the sensing step Ps. In the sensing step (Ps), the threshold voltage (Vth) of the first drive element (DT1) is sensed at the 1-3 node (n13), and this threshold voltage (Vth) is applied to the 2-1 switch element (M21), It is transmitted to the 2-2nd node n22 through the 2-4th node n24 and the 2-1st capacitor Csup2. The threshold voltage Vth of the second drive element DT2 is sensed at the 2-3 node n23, and the threshold voltage Vth is applied to the 1-1 switch element M11 and the 1-4 node n14. ) and the 1-2nd node n12 through the 1-1st capacitor Csup1. Therefore, in the sensing step, the voltages of the 1-2nd and 2-2nd nodes n12 and n22 increase by the threshold voltage Vth of the driving elements DT1 and DT2.

Since the sensing step (Ps) can be set more than 2 horizontal periods, the threshold voltage sensing time of the driving elements DT1 and DT2 can be sufficiently secured to effectively sense the threshold voltage in a high-resolution display panel in which one horizontal period becomes smaller. there is. In addition, in the sensing step Ps, the threshold voltages Vth of the driving elements DT1 and DT2 are gate electrodes of the driving elements DT1 and DT2, that is, the 1-2 and 2-2 nodes, without deterioration of the sensing rate. It can be passed to (n11, n12). Accordingly, the pixel circuit of the present invention can sense the threshold voltages Vth of the driving elements DT1 and DT2 by using the advantages of the pixel circuit of the source follower structure and the diode connection structure.

In the data writing step Pw, as shown in FIGS. 9 and 10 , the first to fourth and second to fourth switch elements M14 and M24 are turned on, and the other switch elements M11 are turned on. ~M13, M15~M17, M21~M23, M25~M27) are turned off. At this time, the data voltage Vdata1 of the pixel data to be written in the first pixel PXL1 is applied to the 1-2 node n12 through the 1-4 switch element M14 and the 1-1 capacitor Csup1. is authorized At the same time, the data voltage Vdata2 of the pixel data to be written in the second pixel PXL2 is applied to the 2-2 node n22 through the 2-4 switch element M24 and the 2-1 capacitor Csup2. is authorized

In the data writing step (Pw), the voltage of the 1-2nd node (n12) is changed to the data voltage (Vdata1), and the threshold voltage (Vth) is changed to the 1-4th node (Vth) by capacitor coupling through the 1-1st capacitor (Csup1). It is delivered to the node n14. At the same time, the voltage of the 2-2nd node n22 changes to the data voltage Vdata2, and the threshold voltage Vth is changed to the 2-4th node n24 by capacitor coupling through the 2-1st capacitor Csup2. is forwarded to At this time, the voltages of the 1-3 and 2-3 nodes n13 and n14 may increase through the parasitic capacitance.

In the boosting step Pb, all switch elements M11 to M17 and M21 to M27 are turned off. At this time, the capacitors of the light emitting elements EL1 and EL2 are charged and the anode voltage AND is increased. In the boosting step (Pb), the 1-2nd to 1-4th nodes (n12 to n14) and the 2-2nd to 2-4th nodes (n22 to n24) are floated, and the nodes ( The voltages (DRG, DRG_1, DRS) of n12 to n14 and n22 to n24 rise.

In the light emitting step (Pem), as shown in FIGS. 11 and 12 , the first to fifth, first to sixth, second to fifth, and second to sixth switch elements M15, M16, M25, and M26 are is turned on, and the other switch elements (M11 to M14, M17, M21 to M24, and M27) are turned off. At this time, the first light emitting element EL1 may emit light by current generated according to the gate-source voltage Vgs of the first driving element DT1. At the same time, the second light emitting element EL2 may emit light by current generated according to the gate-source voltage Vgs of the second driving element DT2.

13 is a diagram showing transfer rates of the threshold voltages Vth and data voltages Vdata of the driving elements DT1 and DT2 according to capacities of the 1-1 and 2-1 capacitors Csup. As can be seen in FIG. 13, when the 1-1st and 2-1st capacitors Csup are small (Csup≒0), the threshold voltages Vth of the driving elements DT1 and DT2 are It is hardly transmitted to the 2-2 nodes n12 and n22.

When the capacities of the 1-1st and 2-1st capacitors Csup1 and Csup2 increase (Csup>>0), the driving elements DT transmitted to the 1-2nd and 2-2nd nodes n12 and n22 ) of the threshold voltage (Vth) and the transmission rate of the data voltage (Vdata) increases. When the data writing step Pw ends, the gate-to-source voltage Vgs of the driving elements DT1 and DT2 is Vgs=[(Vdata-Vinit)*Csup]+Vth. The pixel circuit of the present invention transmits the threshold voltage Vth and the data voltage Vdata of the driving elements DT1 and DT2 to the gate electrodes of the driving elements DT1 and DT2 once through capacitor coupling. The loss rate can be improved. Capacities of the 1-1st and 2-1st capacitors Csup may be set to the same or different capacities as those of the 1-2nd and 2-2nd capacitors Cst1 and Cst2.

14 is a simulation result of a pixel circuit according to the first embodiment of the present invention. As a result of this simulation, the inventors of the present application found that the threshold voltages of the driving elements DT1 and DT2 can be sensed at voltages greater than 0 [V] as well as sensed even when negatively shifted to voltages less than 0 [V]. Confirmed.

The pixel circuit of the present invention can be driven only by the driving method shown in FIGS. 4 to 13 described above. In another embodiment, the data voltages Vdata1 and Vdata2 may be alternately applied between the pixels PXL1 and PXL2 in the pixel circuit of the present invention. For example, when an input image is input to a display device in a fixed pattern for a long period of time, the threshold voltage shift amount of the driving elements DT1 and DT2 may vary between the pixels PXL1 and PXL2. In this case, the shift deviation of threshold voltages of driving elements between pixels may be offset by cross-applying the data voltage Vdata to the pixels at a predetermined unit time period. Here, the unit time may be n (n is a positive integer) frame period or n (n is a positive integer) seconds. This method can be applied to a still image in which a fixed pattern lasts for a long time in an input image or to any image regardless of whether or not the input image has a fixed pattern.

The method of crossing the data voltage across the pixels is to drive the pixel circuit in the same manner as in FIG. 4 for a first unit time (or first driving period) and then to FIG. 15 for a second unit time (or second driving period). The pixel circuit can be driven in the same way. Here, the first unit time may be interpreted as an odd-numbered unit time, and the second unit time may be interpreted as an even-numbered unit time. This driving method can cancel the shift deviation of the threshold voltage of the driving elements DT1 and DT2 between the pixels PXL1 and PXL2 and reduce deterioration of the driving elements DT1 and DT2. In addition, in this driving method, since the switch elements M16, M17, M26, and M27 to which the second and third EM pulses EM2 and EM3 are applied are alternately driven at a predetermined time period, the switch elements M16, M17, Reliability of the device can be improved by reducing deterioration of M26 and M27).

15 is a waveform diagram illustrating a driving method in which data voltages are cross-applied between adjacent pixels. FIG. 16 is a circuit diagram showing a light emitting step of the pixel circuit shown in FIG. 3 in the driving method of the pixel circuit shown in FIG. 15 . In this embodiment, detailed descriptions of components substantially the same as those of the first embodiment will be omitted.

15 and 16, the first pixel PXL1 includes a first light emitting element EL1, a first driving element DT1, 1-1 to 1-7 switch elements M11 to M17, and 1-1 and 1-2 capacitors Csup1 and Cst1. The second pixel PXL2 includes the second light emitting element EL2, the second driving element DT2, the 2-1st to 2-7th switch elements M21 to M27, and the 2-1st and 2nd- It includes 2 capacitors Csup2 and Cst2. The driving elements DT1 and DT2 and the switch elements M11 to M27 may be implemented as n-channel oxide TFTs.

As shown in FIG. 15 , the driving period of the pixel circuit may be divided into an initialization phase (Pi), a sensing phase (Ps), a data writing phase (Pw), a boosting phase (Pb), and an emission phase (Pem). A hold step (Ph) may be set between the data writing step (Pw) and the boosting step (Pb).

In the initialization step (Pi), as shown in FIG. 15, the first scan pulse (SCAN1) and the third EM pulse (EM3) are generated as gate-on voltages (VGH, VEH). In the initialization step (Pi), the second scan pulse (SCAN2), the first EM pulse (EM1), and the second EM pulse (EM2) are gate off voltages (VGL, VEL).

In the sensing step Ps, as shown in FIG. 15 , the first scan pulse SCAN1 and the first EM pulse EM1 are generated as gate-on voltages VGH and VEH. The second scan pulse SCAN2 , the second EM pulse EM2 , and the third EM pulse EM3 are gate off voltages VGL and VEL in the sensing step Ps.

In the data writing step Pw, as shown in FIG. 15 , the second scan pulse SCAN2 is generated with a gate-on voltage VGH that is synchronized with the data voltages Vdata1 and Vdata2 of the pixel data. Gate pulses SCAN1 , EM1 , EM2 , and EM3 other than the second scan pulse SCAN2 are generated as gate-off voltages VGL and VEL in the data writing step Pw.

In the hold phase (Ph), all gate pulses (SCAN1, SCAN2, EM1, EM2, and EM3) are gate off voltages (VGL, VEL). At this time, the main nodes n11 to n14 and n21 to n24 of the pixel circuit are floating to maintain voltage.

As shown in FIG. 15 in the boosting phase Pb and the emission phase Pem, the first and third EM pulses EM1 and EM3 are the gate-on voltage VEH, while the first and second scan pulses (SCAN1, SCAN2) and the second EM pulse (EM2) are the gate off voltage (VGL).

During the first unit time, as shown in FIG. 3 , the data voltage Vdata1 of the first pixel data to be written in the first pixel PXL1 is applied to the first to fourth switch elements M14 of the first pixel PXL1. At the same time, the data voltage Vdata2 of the second pixel data to be written in the second pixel PXL2 is applied to the second-fourth switch element M24 of the second pixel PXL2.

During the second unit of time, as shown in FIG. 16 , the data voltage Vdata1 of the first pixel data to be written in the first pixel PXL1 is applied to the second-fourth switch element M24 of the second pixel PXL2. At the same time, the data voltage Vdata1 of the second pixel data to be written in the second pixel PXL2 is applied to the first through fourth switch elements M14 of the first pixel PXL1.

As shown in FIGS. 3 and 4 , the 1st-4th switch element M14 transmits the second scan pulse SCAN2 synchronized with the data voltage Vdata1 of the first pixel data in the data writing step Pw of the first unit time. It is turned on according to the gate-on voltage VGH and supplies the data voltage Vdata1 to the first to fourth nodes n14. As shown in FIGS. 15 and 16 , the 1st-4th switch element M14 transmits the second scan pulse SCAN2 synchronized with the data voltage Vdata2 of the second pixel data in the data writing step Pw of the second unit time. It is turned on according to the gate-on voltage VGH and supplies the data voltage Vdata2 to the first to fourth nodes n14.

As shown in FIGS. 3 and 4 , the second-fourth switch element M24 transmits the second scan pulse SCAN2 synchronized with the data voltage Vdata2 of the second pixel data in the data writing step Pw of the first unit time. It is turned on according to the gate-on voltage VGH and supplies the data voltage Vdata2 to the second-fourth node n24. As shown in FIGS. 15 and 16 , the 2-4th switch element M24 transmits the second scan pulse SCAN2 synchronized with the data voltage Vdata1 of the first pixel data in the data writing step Pw of the second unit time. It is turned on according to the gate-on voltage VGH and supplies the data voltage Vdata1 to the second-fourth node n24.

The first to sixth and second to sixth switch elements M16 and M26 perform an initialization step (Pi), a boosting step (Pb), and a light emitting step ( Pem) is turned on according to the gate-on voltage VEH of the second EM pulse EM2. At this time, as shown in FIG. 11 , the current from the first driving element DT1 flows to the first light emitting element EL1 through the 1-7 switch elements M17, and the current from the second driving element DT2 It flows to the second light emitting element EL2 through the 2-7th switch element M27. The first to sixth and second to sixth switch elements M16 and M26 are in an off state according to the second EM pulse EM2 maintaining the gate off voltage VEL for a second unit time as shown in FIGS. 15 and 16 is maintained, so it is not driven.

The 1-7th and 2-7th switch elements M17 and M27 are turned off according to the third EM pulse EM3 maintaining the gate-off voltage VEL for a first unit time, as shown in FIGS. 3 and 4 . Since it maintains the state, it is not driven. As shown in FIGS. 15 and 16 , the 1-7th and 2-7th switch elements M17 and M27 perform an initialization phase (Pi), a boosting phase (Pb), and a light emitting phase (Pem) for a second unit time. ) is turned on according to the gate-on voltage VEH of the third EM pulse EM3. At this time, as shown in FIG. 16, the current from the first driving element DT1 flows to the second light emitting element EL2 through the 2-7th switch elements M27, and the current from the second driving element DT2 It flows to the first light emitting element EL1 through the 1-7th switch element M17.

The capacitors Csup1, Cst1, Csup2, and Cst2 are not limited to the above-described embodiments. The capacitors Csup1, Cst1, Csup2, and Cst2 may be connected to the pixel circuit as shown in FIGS. 17A and 17B.

Referring to FIG. 17A , capacitors Csup1 , Cst1 , Csup2 , and Cst2 may be connected in the same connection structure as in the above-described embodiments. That is, the 1-1 capacitor Csup1 is connected between the 1-2 node n12 and the 1-4 node n14, and the 2-1 capacitor Csup2 is connected to the 2-2 node n22. And is connected between the 2-4th node (n24). The 1-2nd capacitor Cst1 is connected between the 1-2nd node n12 and the 1-3rd node n13, and the 2-2nd capacitor Cst2 is connected to the 2-2nd node n22. It can be connected between 2-3 node n23.

Referring to FIG. 17B, the 1-1 capacitor Csup1 is connected between the 1-2 node n12 and the 1-4 node n14, and the 2-1 capacitor Csup2 is connected to the 2-2 node Csup2. It is connected between the node n22 and the second-fourth node n24. The 1-2nd capacitor (Cst1) is connected between the 1-4th node (n14) and the 1-3rd node (n13), and the 2-2nd capacitor (Cst2) is connected to the 2-4th node (n24). It can be connected between 2-3 node n23.

18 is a circuit diagram showing a pixel circuit of adjacent pixels according to a second embodiment of the present invention. 19 is a circuit diagram showing a pixel circuit of adjacent pixels according to a third embodiment of the present invention. Gate pulses SCAN1 , SCAN2 , EM1 , and EM2 and data voltages Vdata1 and Vdata2 as shown in FIG. 4 are applied to the pixel circuit of these embodiments. In these embodiments, the 1-2 and 2-2 nodes n11 and n21 are initialized with the reference voltage Vref applied to the 1-2 and 2-2 switch elements M12 and M22. .

20 is a circuit diagram showing a pixel circuit of adjacent pixels according to a fourth embodiment of the present invention. 21 is a circuit diagram showing a pixel circuit of adjacent pixels according to a fifth embodiment of the present invention. In these embodiments, each of the pixels PXL1 and PXL2 may be implemented as a pixel circuit including five transistors and two capacitors. FIG. 22 is a waveform diagram illustrating gate pulses applied to the pixel circuits shown in FIGS. 20 and 21 . In these embodiments, the 1-2nd and 2-2nd nodes n11 and n21 are connected to the data voltages Vdata1 and Vdata2 applied to the 1-2nd and 2-2nd switch elements M32 and M42. initialized

20, 21, and 22, the first pixel PXL1 includes a first light emitting element EL1, a first driving element DT1, and 1-1 to 1-4 switch elements M11. , M32, M13, M34), and the 1-1 and 1-2 capacitors Csup1 and Cst1. The second pixel PXL2 includes the second light emitting element EL2, the second driving element DT2, the 2-1st to 2-4th switch elements M21, M42, M23, and M44, and the 2-1st and 2-2 capacitors Csup2 and Cst2. The driving elements DT1 and DT2 and the switch elements M11, M32, M13, M34, M21, M42, M23, and M44 may be implemented as n-channel oxide TFTs.

The first and second pixels PXL1 and PXL2 share power lines to which constant voltages EVDD, EVSS, and Vinit are applied, and gate lines to which gate pulses SCAN1, SCAN2, and EM are applied. The first and second pixels PXL1 and PXL2 are connected to different data lines. The first pixel PXL1 may be connected to the first data line to which the first data voltage Vdata1 is applied. The second pixel PXL2 may be connected to the second data line to which the second data voltage Vdata2 is applied.

The power lines may include a VDD line to which the pixel driving voltage EVDD is applied, a VSS line to which the pixel reference voltage EVSS is applied, and an INIT line to which the initialization voltage Vinit is applied. The pixel driving voltage EVDD is a voltage higher than the maximum voltage of the data voltages Vdata1 and Vdata2. The pixel reference voltage EVSS and the initialization voltage Vinit are voltages lower than the minimum voltages of the data voltages Vdata1 and Vdata2. The pixel reference voltage EVSS and the initialization voltage Vinit may be set to the same voltage or different voltages.

The gate pulse (SCAN, EM) swings between a gate-on voltage (VGH, VEH) and a gate-off voltage (VGL, VEL). The gate-on voltages VGH and VEH may be set to higher voltages than the pixel driving voltage EVDD. The gate-off voltages VGL and VEL may be set to voltages lower than the pixel reference voltage EVSS. The gate pulses SCAN and EM include a scan pulse SCAN applied to the first gate line and an EM pulse EM applied to the second gate line. The gate driver of the display device may include a first shift register that generates the scan pulse (SCAN) and a second shift register that generates the EM pulse.

As shown in FIG. 22 , the driving period of the pixel circuit may be divided into an initialization phase (Pi), a sensing phase (Ps), a data writing phase (Pw), a boosting phase (Pb), and an emission phase (Pem). A hold step (Ph) may be set between the data writing step (Pw) and the boosting step (Pb).

In the initialization step (Pi), the scan pulse (SCAN) and the EM pulse (EM) are generated as gate-on voltages (VGH, VEH). In the sensing step Ps, the scan pulse SCAN is generated with the gate-on voltage VGH, and the EM pulse EM is inverted with the gate-off voltage VEL.

In the data writing step (Pw), the scan pulse (SCAN) is generated with a gate-on voltage (VGH) synchronized with the data voltages (Vdata1, Vdata2) of the pixel data, and the EM pulse (EM) is the gate-off voltage (VEL). .

In the hold phase (Ph), the scan pulse (SCAN) and the EM pulse (EM) are gate off voltages (VGL, VEL). In the boosting phase (Pb) and the emission phase (Pem), the EM pulse (EM) is the gate-on voltage (VEH), while the scan pulse (SCAN) is the gate-off voltage (VGL).

The light emitting elements EL1 and EL2 may be implemented as OLEDs. The anode electrode of the first light emitting element EL1 is connected to the first driving element DT1 with the first to fourth switch elements M34 and M44 interposed therebetween. The anode electrode of the second light emitting element EL2 is connected to the second driving element DT2 with the 2-4th switch element M44 interposed therebetween. When the switch elements M34 and M44 are turned on, the anode electrodes of the light emitting elements EL1 and EL2 are connected to the driving elements DT1 and DT2 to emit light by current from the driving elements DT1 and DT2. there is. Cathode electrodes of the light emitting elements EL1 and EL2 are connected to the VSS line to which the pixel reference voltage EVSS is applied. The light emitting elements EL1 and EL2 include a capacitor Cel1 connected between an anode electrode and a cathode electrode.

In the first pixel PXL1 , the first driving element DT1 drives the first light emitting element EL1 by generating a current according to the gate-source voltage Vgs. The first driving element DT1 includes a first electrode connected to the 1-1 node n11, a gate electrode connected to the 1-2 node n12, and a second electrode connected to the 1-3 node n13. include

The 1-1 capacitor Csup1 is connected between the 1-2 node n12 and the 1-4 node n14. As shown in FIG. 20, the 1-2 capacitor Cst1 is connected between the 1-2 node n12 and the 1-3 node n13, or as shown in FIG. 22, the 1-4 node It may be connected between (n14) and the 1-3 nodes (n13). The 2-1st capacitor Csup2 is connected between the 2-2nd node n22 and the 2-4th node n24. As shown in FIG. 20, the 2-2nd capacitor Cst2 is connected between the 2-2nd node n22 and the 2-3rd node n23, or as shown in FIG. 22, the 2-4th node It may be connected between (n24) and the 2-3 node (n23).

The 1-1st switch element M11 is turned on according to the gate-on voltage VGH of the scan pulse SCAN in the initialization phase Pi, the sensing phase Ps, and the data writing phase Pw, and The fourth node n14 is connected to the second-third node n23 of the second pixel PXL2. The 1-1 switch element M11 includes a gate electrode connected to the first gate line to which the scan pulse SCAN is applied, a first electrode connected to the 1-4 node n14, and a 2-3 node n23. It includes a second electrode connected to.

The 1st-2nd switch element M32 is turned on according to the gate-on voltage VGH of the scan pulse SCAN in the initialization phase Pi, the sensing phase Ps, and the data writing phase Pw, so that the first data The voltage Vdata1 is supplied to the 1-2 node n12. The first-second switch element M12 includes a gate electrode connected to a first gate line to which a scan pulse SCAN is applied, a first electrode connected to a first data line to which a first data voltage Vdata1 is applied, and a first electrode connected to a first data line to which a first data voltage Vdata1 is applied. -2 includes a second electrode connected to the node n12.

The first to third switch elements M13 are turned on according to the gate-on voltage VGH of the scan pulse SCAN in the initialization phase Pi, the sensing phase Ps, and the data writing phase Pw, so that the initialization voltage ( Vinit) is supplied to the anode electrode of the first light emitting element EL1. The 1-3 switch element M13 includes a gate electrode connected to a first gate line to which a scan pulse SCAN is applied, a first electrode connected to an INIT line to which an initialization voltage Vinit is applied, and a first light emitting element EL1. ) and a second electrode connected to the anode electrode.

The first to fourth switch elements M34 are turned on according to the gate-on voltage VEH of the EM pulse EM in the initialization phase (Pi), the boosting phase (Pb), and the emission phase (Pem), and The third node n13 is connected to the anode electrode of the first light emitting element EL1. The first-fourth switch element M34 includes a gate electrode connected to the second gate line to which the EM pulse EM is applied, a first electrode connected to the 1-3 node n13, and a first light emitting element EL1. and a second electrode connected to the anode electrode.

In the second pixel PXL2 , the second driving element DT2 generates current according to the gate-source voltage Vgs to drive the second light emitting element EL2 . The second driving element DT2 includes a first electrode connected to the 2-1 node n21, a gate electrode connected to the 2-2 node n22, and a second electrode connected to the 2-3 node n23. include

The 2-1st switch element M21 is turned on according to the gate-on voltage VGH of the scan pulse SCAN in the initialization phase Pi, the sensing phase Ps, and the data writing phase Pw. The fourth node n24 is connected to the first through third nodes n13 of the first pixel PXL1. The 2-1 switch element M21 includes a gate electrode connected to the first gate line to which the scan pulse SCAN is applied, a first electrode connected to the 2-4 node n24, and a 1-3 node n13. It includes a second electrode connected to.

The 2-2nd switch element M22 is turned on according to the gate-on voltage VGH of the scan pulse SCAN in the initialization phase Pi, the sensing phase Ps, and the data writing phase Pw, thereby providing second data. The voltage Vdata2 is supplied to the 2-2 node n22. The 2-2 switch element M22 includes a gate electrode connected to a first gate line to which a scan pulse SCAN is applied, a first electrode connected to a second data line to which a second data voltage Vdata2 is applied, and a second -2 includes a second electrode connected to the node n22.

The 2-3rd switch element M23 is turned on according to the gate-on voltage VGH of the scan pulse SCAN in the initialization phase Pi, the sensing phase Ps, and the data writing phase Pw, so that the initialization voltage ( Vinit) is supplied to the anode electrode of the second light emitting element EL2. The 2-3 switch element M23 includes a gate electrode connected to the first gate line to which the scan pulse SCAN is applied, a first electrode connected to the INIT line to which the initialization voltage Vinit is applied, and the second light emitting element EL2. ) and a second electrode connected to the anode electrode.

The second-fourth switch element M44 is turned on according to the gate-on voltage VEH of the EM pulse EM in the initialization phase (Pi), the boosting phase (Pb), and the light emission phase (Pem) to generate the second- The third node n23 is connected to the anode electrode of the second light emitting element EL2. The 2-4th switch element M44 includes a gate electrode connected to the second gate line to which the EM pulse EM is applied, a first electrode connected to the 2-3rd node n23, and the second light emitting element EL2. and a second electrode connected to the anode electrode.

23 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention. 24 is a cross-sectional view showing a cross-sectional structure of the display panel shown in FIG. 23;

Referring to FIGS. 23 and 24 , a display device according to an exemplary embodiment of the present invention includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and pixels of the display panel 100. and a power supply unit 140 generating power necessary for driving the display panel driving unit.

The display panel 100 may have a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array displaying an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to pixels. The power lines supply constant voltages (EVDD, EVSS, Vref, and Vinit) necessary for driving the pixels 101 to the pixels 101 .

As shown in FIG. 24 , the cross-sectional structure of the display panel 100 may include a circuit layer 12, a light emitting element layer 14, and an encapsulation layer 16 stacked on a substrate 10. can

The circuit layer 12 may include a TFT array including pixel circuits connected to wires such as data lines, gate lines, and power lines, a demultiplexer array 112 , a gate driver 120 , and the like. The wiring and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated with an insulating layer interposed therebetween, and an active layer including a semiconductor material. All transistors formed on the circuit layer 12 may be implemented as n-channel oxide TFTs of a coplanar structure.

The light emitting element layer 14 may include a light emitting element EL driven by a pixel circuit. The light emitting element EL may include a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element. In another embodiment, the light emitting device layer 14 may include a white light emitting device and a color filter. The light emitting elements EL of the light emitting element layer 14 may be covered by a protective layer including an organic layer and a protective layer.

The encapsulation layer 16 covers the light emitting element layer 14 so as to seal the circuit layer 12 and the light emitting element layer 14 . The encapsulation layer 16 may have a multi-insulation layer structure in which organic layers and inorganic layers are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic layer flattens the surface of the inorganic layer. When the organic layer and the inorganic layer are stacked in multiple layers, the movement path of moisture or oxygen is longer than that of a single layer, so that penetration of moisture and oxygen affecting the light emitting element layer 14 can be effectively blocked.

A touch sensor layer, which is omitted in the drawings, is formed on the encapsulation layer 16, and a polarizing plate or color filter layer may be disposed thereon. The touch sensor layer may include capacitive touch sensors that sense a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include metal wiring patterns and insulating layers forming capacitance of the touch sensors. The insulating layers may insulate portions where the metal wiring patterns intersect and planarize a surface of the touch sensor layer. The polarizer may improve visibility and contrast ratio by converting polarization of external light reflected by metal of the touch sensor layer and the circuit layer. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase retardation film are bonded together or a circular polarizing plate. A cover glass may be adhered on the polarizing plate. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer may absorb some wavelengths of light reflected from the circuit layer and the touch sensor layer to replace the role of the polarizer and increase color purity of an image reproduced in the pixel array.

The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes one line of pixels disposed along a line direction (X-axis direction) in the pixel array of the display panel 100 . Pixels arranged on one pixel line share gate lines 103 . Sub-pixels arranged in the column direction (Y) along the data line direction share the same data line 102 . One horizontal period is a time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and a real object in the background is visible. The display panel 100 may be made of a flexible display panel.

Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels may include a pixel circuit. Hereinafter, a pixel may be interpreted as having the same meaning as a sub-pixel. Each of the pixel circuits may be implemented with the circuits of the above-described embodiments.

Pixels can be arranged as real color pixels and pentile pixels. A pentile pixel can implement a higher resolution than a real color pixel by driving two sub-pixels of different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm may compensate for insufficient color expression in each pixel with the color of light emitted from an adjacent pixel.

The power supply unit 140 uses a DC-DC converter to generate DC voltage (or constant voltage) required to drive the pixel array of the display panel 100 and the display panel driver. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply unit 140 adjusts the level of a DC input voltage applied from a host system (not shown) to generate a gamma reference voltage (VGMA), gate voltages (VGH, VEH, VGL, and VEL), a pixel driving voltage (EVDD), and a pixel reference voltage. It is possible to generate constant voltages such as (EVSS), an initialization voltage (Vinit), and a reference voltage (Vref). The gamma reference voltage VGMA is supplied to the data driver 110 . Gate voltages (VGH, VEH, VGL, VEL) are supplied to the gate driver 120 . The pixel driving voltage EVDD and the pixel reference voltage EVSS are supplied to the pixels 101 through power lines commonly connected to the pixels 101 .

The display panel driver writes pixel data of an input image into pixels of the display panel 100 under the control of a timing controller 130 .

The display panel driver includes a data driver 110 and a gate driver 120 . The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102 .

The demultiplexer array 112 sequentially supplies data voltages output from channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switch elements disposed on the display panel 100 . When the demultiplexer is disposed between the output terminals of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

The display panel driver may further include a touch sensor driver for driving touch sensors. The touch sensor driver is omitted in FIG. 23 . The data driver 110 and the touch sensor driver may be integrated into one drive integrated circuit (IC). In a mobile device or a wearable device, the timing controller 130, the power supply unit 140, the data driver 110, and the like may be integrated into one drive IC.

The display panel driver may operate in a low speed driving mode under the control of the timing controller 130 . The low-speed driving mode may be set to reduce power consumption of the display device when the input image does not change by a preset number of frames by analyzing the input image. The low-speed driving mode can reduce power consumption of the display panel driver and the display panel 100 by lowering the refresh rate of pixels when a still image is input for a predetermined period of time or more. The low-speed drive mode is not limited when a still image is input. For example, when the display device operates in a standby mode or when a user command or an input image is not input to the display panel driving circuit for a predetermined period of time or more, the display panel driving circuit may operate in a low speed driving mode.

The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 generates a data voltage Vdata by converting pixel data of an input image into a gamma compensation voltage for each frame period using a digital to analog converter (DAC). The gamma reference voltage VGMA is divided into gamma compensation voltages for each gray level through a voltage divider circuit. The gamma compensation voltage for each gray level is provided to the DAC of the data driver 110 . The data voltage Vdata is output from each of the channels of the data driver 110 through an output buffer.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed on the circuit layer 12 on the display panel 100 together with the TFT array and wires of the pixel array. The gate driver 120 may be disposed on the bezel area (BZ), which is a non-display area of the display panel 100, or may be distributedly disposed within a pixel array where an input image is reproduced.

As shown in FIG. 23 , the gate driver 120 is disposed in the bezel area BZ on one side of the display panel 100 and applies a gate pulse [Gout(N) to the gate lines 103 in a single feeding method. ] can be supplied. In addition, the gate driver 120 is disposed in the bezel area BZ on both sides of the display panel 100 with the pixel array of the screen interposed therebetween, and double-feeds the gate lines 103 to generate gate pulses [Gout]. (N)] can be supplied.

The gate driver 120 sequentially outputs gate pulses to the gate lines 103 under the control of the timing controller 130 . The gate driver 120 may sequentially supply the gate pulses to the gate lines 103 by shifting the gate pulses using a shift register.

The timing controller 130 receives digital video data (DATA) of an input image and a timing signal synchronized therewith from the host system. The timing signal may include a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a clock (CLK), and a data enable signal (DE). Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical sync signal Vsync and the horizontal sync signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

The host system may be any one of a television (TV) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale an image signal from a video source according to the resolution of the display panel 100 and transmit the timing signal to the timing controller 130 together with the timing signal.

In the normal driving mode, the timing controller 130 multiplies the input frame frequency by i to control the operation timing of the display panel driver at a frame frequency of input frame frequency × i (i is a natural number) Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the Phase-Alternating Line (PAL) method.

The timing controller 130 lowers the frequency of the frame rate at which pixel data is written into pixels in the low-speed driving mode compared to the normal driving mode. For example, in the normal driving mode, the data refresh frame frequency in which pixel data is written to the pixels may occur at a frequency of 60 Hz or higher, for example, at a refresh rate of any one of 60 Hz, 120 Hz, and 144 Hz, and the data refresh in the low speed driving mode The frame DRF may be generated at a refresh rate of a lower frequency than that of the low-speed driving mode. The timing controller 130 may lower the driving frequency of the display panel driving unit by lowering the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower the refresh rate of pixels in the low-speed driving mode.

The timing controller 130 controls the data timing control signal for controlling the operation timing of the data driver 110 and the operation timing of the demultiplexer array 112 based on the timing signals Vsync, Hsync, and DE received from the host system. A gate timing control signal for controlling the operation timing of the gate driving unit 120 is generated. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110 , the demultiplexer array 112 , the touch sensor driver, and the gate driver 120 .

The gate timing control signal generated from the timing controller 130 may be input to the shift register of the gate driver 120 through a level shifter (not shown). The level shifter may receive a gate timing control signal, generate a start pulse and a shift clock, and provide the generated start pulse and shift clock to the shift register of the gate driver 120 .

Since the content of the specification described in the problem to be solved, the problem solution, and the effect above does not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display panel 110: data driving unit
120: gate driver 130: timing controller
PXL1, PXL2: Pixel Pi: Initialization phase
Ps: sensing phase Pw: data writing phase
Ph: hold phase Pb: boost phase
Pem: light emission stage EVDD: pixel driving voltage
EVSS: Pixel Reference Voltage Vinit: Initialization Voltage
Vref: reference voltage SCAN1, SCAN2: scan pulse
EM, EM1, EM2: Light emission control pulse (EM pulse) EL1, EL2: Light emitting element
DT1, DT2: drive element M11 to M17, M21 to M27: switch element
Csup1, Csup2: 1st-1st and 2nd-1st capacitors
Cst1, Cst2: 1-2nd and 2-2nd capacitors

Claims (19)

a first driving element including a first electrode connected to the 1-1 node, a second electrode connected to the 1-2 node, and a second electrode connected to the 1-3 node; and
A second driving element including a first electrode connected to the 2-1 node, a second electrode connected to the 2-2 node, and a second electrode connected to the 2-3 node;
The second electrode voltage of the first driving element is transmitted to the gate electrode of the second driving element;
A pixel circuit in which the second electrode voltage of the second driving element is transmitted to the gate electrode of the first driving element. According to claim 1,
a first light emitting element;
a second light emitting element;
a 1-1 switch element including a gate electrode to which a first scan pulse is applied, a first electrode connected to a 1-4 node, and a second electrode connected to the 2-3 node;
a first-second switch element including a gate electrode to which the first scan pulse is applied, a first electrode to which a reference voltage is applied, and a second electrode connected to the first-to-second node;
1-3 switch elements including a gate electrode to which the first scan pulse is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the anode electrode of the first light emitting element;
1-4 switch elements including a gate electrode to which a second scan pulse is applied, a first electrode connected to a first data line, and a second electrode connected to the 1-4 nodes;
1-5 switch elements including a gate electrode to which a first EM pulse is applied, a first electrode to which a pixel driving voltage is applied, and a second electrode connected to the 1-1 node;
1-6 switch elements including a gate electrode to which a second EM pulse is applied, a first electrode connected to the 1-3 node, and a second electrode connected to the anode electrode of the first light emitting element;
a 2-1 switch element including a gate electrode to which the first scan pulse is applied, a first electrode connected to a 2-4 node, and a second electrode connected to the 1-3 node;
a 2-2 switch element including a gate electrode to which the first scan pulse is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the 2-2 node;
a 2-3 switch element including a gate electrode to which the first scan pulse is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode electrode of the second light emitting element;
a 2-4 switch element including a gate electrode to which the second scan pulse is applied, a first electrode connected to a second data line, and a second electrode connected to the 2-4 node;
a 2-5 switch element including a gate electrode to which the first EM pulse is applied, a first electrode to which the pixel driving voltage is applied, and a second electrode connected to the 2-1 node; and
A pixel circuit further comprising a 2-6th switch element including a gate electrode to which the second EM pulse is applied, a first electrode connected to the 2-3 node, and a second electrode connected to the anode electrode of the second light emitting element. . According to claim 2,
1-7 switch elements including a gate electrode to which a third EM pulse is applied, a first electrode connected to the 2-3 node, and a second electrode connected to the anode electrode of the first light emitting element; and
A pixel further comprising 2-7 switch elements including a gate electrode to which the third EM pulse is applied, a first electrode connected to the 1-3 node, and a second electrode connected to the anode electrode of the second light emitting element Circuit. According to claim 2,
A pixel reference voltage is applied to cathode electrodes of the first and second light emitting devices;
The pixel driving voltage is higher than a maximum voltage of data voltages applied to the data lines;
The reference voltage is lower than the minimum voltage of the data voltage,
The pixel circuit wherein the pixel reference voltage and the initialization voltage are lower than the reference voltage. According to claim 2,
a 1-1 capacitor connected between the 1-2 node and the 1-4 node;
a 1-2 capacitor connected between the 1-2 node and the 1-3 node, or connected between the 1-4 node and the 1-3 node;
a 2-1 capacitor connected between the 2-2 node and the 2-4 node; and
and a 2-2 capacitor connected between the 2-2 node and the 2-3 node, or connected between the 2-4 node and the 2-3 node. According to claim 3,
The first driving period of the pixel circuit includes an initialization step, a sensing step, a data writing step, a boosting step, and a light emitting step;
In the initialization phase of the first driving period, the first scan pulse and the second EM pulse are generated with a gate-on voltage, and the second scan pulse, the first EM pulse, and the third EM pulse generate a gate-on voltage. is the off voltage,
In the sensing step of the first driving period, the first scan pulse and the first EM pulse are generated with the gate-on voltage, and the second scan pulse, the second EM pulse, and the third EM pulse generate the gate-on voltage. is the gate off voltage,
In the data writing step of the first driving period, the second scan pulse is generated with the gate-on voltage synchronized with the data voltage applied to the data lines, and the first scan pulse, the first EM pulse, the a second EM pulse and the third EM pulse are the gate off voltage;
In the boosting phase and the emission phase of the first driving period, the first EM pulse and the second EM pulse are the gate-on voltages, and the first scan pulse, the second scan pulse, and the third EM pulse are is the gate off voltage,
The switch elements are turned on in response to the gate-on voltage and turned off in response to the gate-off voltage;
A pixel circuit in which a first data voltage is applied to the first data line and a second data voltage is applied to the second data line during the first driving period. According to claim 6,
The second driving period of the pixel circuit includes an initialization step, a sensing step, a data writing step, a boosting step, and a light emitting step;
In the initialization phase of the second driving period, the first scan pulse and the third EM pulse are generated with a gate-on voltage, and the second scan pulse, the first EM pulse, and the second EM pulse generate a gate-on voltage. is the off voltage,
In the sensing step of the second driving period, the first scan pulse and the first EM pulse are generated with the gate-on voltage, and the second scan pulse, the second EM pulse, and the third EM pulse generate the is the gate off voltage,
In the data writing step of the second driving period, the second scan pulse is generated with the gate-on voltage synchronized with the data voltage applied to the data lines, and the first scan pulse, the first EM pulse, the a second EM pulse and the third EM pulse are the gate off voltage;
In the boosting phase and the emission phase of the second driving period, the first EM pulse and the third EM pulse are the gate-on voltages, and the first scan pulse, the second scan pulse, and the second EM pulse are is the gate off voltage,
During the second driving period, the second data voltage is applied to the first data line, and the first data voltage is applied to the second data line. According to claim 1,
a first light emitting element;
a second light emitting element;
a 1-1 switch element including a gate electrode to which a scan pulse is applied, a first electrode connected to a 1-4 node, and a second electrode connected to the 2-3 node;
a 1-2 switch element including a gate electrode to which the scan pulse is applied, a first electrode to which a first data voltage is applied, and a second electrode connected to the 1-2 node;
1-3 switch elements including a gate electrode to which the scan pulse is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the anode electrode of the first light emitting element;
1-4 switch elements including a gate electrode to which an EM pulse is applied, a first electrode connected to the 1-3 node, and a second electrode connected to the anode electrode of the first light emitting element;
a 2-1 switch element including a gate electrode to which the scan pulse is applied, a first electrode connected to a 2-4 node, and a second electrode connected to the 1-3 node;
a 2-2 switch element including a gate electrode to which the scan pulse is applied, a first electrode to which a second data voltage is applied, and a second electrode connected to the 2-2 node;
a 2-3 switch element including a gate electrode to which the scan pulse is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode electrode of the second light emitting element;
a 2-4 switch element including a gate electrode to which the EM pulse is applied, a first electrode connected to the 2-3 node, and a second electrode connected to the anode electrode of the second light emitting element;
a 1-1 capacitor connected between the 1-2 node and the 1-4 node;
a 1-2 capacitor connected between the 1-2 node and the 1-3 node, or connected between the 1-4 node and the 1-3 node;
a 2-1 capacitor connected between the 2-2 node and the 2-4 node; and
and a 2-2 capacitor connected between the 2-2 node and the 2-3 node, or connected between the 2-4 node and the 2-3 node. According to claim 8,
A pixel reference voltage is applied to cathode electrodes of the first and second light emitting devices;
The pixel driving voltage is higher than maximum voltages of the first and second data voltages;
The pixel circuit wherein the pixel reference voltage and the initialization voltage are lower than minimum voltages of the first and second data voltages. According to claim 8,
The driving period of the pixel circuit includes an initialization step, a sensing step, a data writing step, a boosting step, and an emission step,
In the initialization step, the scan pulse and the EM pulse are generated with a gate-on voltage;
In the sensing step, the scan pulse is generated with the gate-on voltage and the EM pulse is the gate-off voltage;
In the data writing step, the scan pulse is generated with the gate-on voltage synchronized with the first and second data voltages, and the EM pulse is the gate-off voltage;
In the boosting step and the light emission step, the EM pulse is generated with the gate-on voltage, and the scan pulse is the gate-off voltage;
The switch elements are turned on in response to the gate-on voltage and turned off in response to the gate-off voltage. a display panel on which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixels are disposed;
a data driver that converts pixel data into data voltages and supplies them to the data lines; and
a gate driver supplying gate pulses to the gate lines;
The first pixel is
A first driving element including a first electrode connected to the 1-1 node, a second electrode connected to the 1-2 node, and a second electrode connected to the 1-3 node;
A second pixel adjacent to the first pixel,
A second driving element including a first electrode connected to the 2-1 node, a second electrode connected to the 2-2 node, and a second electrode connected to the 2-3 node;
The second electrode voltage of the first driving element is transmitted to the gate electrode of the second driving element;
A display device in which the second electrode voltage of the second driving element is transmitted to the gate electrode of the first driving element. According to claim 11,
The gate pulse is
a first scan pulse, a second scan pulse, a first EM pulse, and a second EM pulse;
The first pixel,
a first light emitting element;
a 1-1 switch element including a gate electrode to which the first scan pulse is applied, a first electrode connected to a 1-4 node, and a second electrode connected to a 2-3 node;
a first-second switch element including a gate electrode to which the first scan pulse is applied, a first electrode to which a reference voltage is applied, and a second electrode connected to the first-to-second node;
1-3 switch elements including a gate electrode to which the first scan pulse is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the anode electrode of the first light emitting element;
1-4 switch elements including a gate electrode to which the second scan pulse is applied, a first electrode connected to a first data line, and a second electrode connected to the 1-4 nodes;
1-5 switch elements including a gate electrode to which the first EM pulse is applied, a first electrode to which a pixel driving voltage is applied, and a second electrode connected to the 1-1 node;
1-6 switch elements including a gate electrode to which the second EM pulse is applied, a first electrode connected to the 1-3 node, and a second electrode connected to the anode electrode of the first light emitting element;
a 1-1 capacitor connected between the 1-2 node and the 1-4 node; and
Further comprising a 1-2 capacitor connected between the 1-2 node and the 1-3 node or connected between the 1-4 node and the 1-3 node,
The second pixel,
a second light emitting element;
a 2-1 switch element including a gate electrode to which the first scan pulse is applied, a first electrode connected to a 2-4 node, and a second electrode connected to the 1-3 node;
a 2-2 switch element including a gate electrode to which the first scan pulse is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the 2-2 node;
a 2-3 switch element including a gate electrode to which the first scan pulse is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode electrode of the second light emitting element;
a 2-4 switch element including a gate electrode to which the second scan pulse is applied, a first electrode connected to a second data line, and a second electrode connected to the 2-4 node;
a 2-5 switch element including a gate electrode to which the first EM pulse is applied, a first electrode to which the pixel driving voltage is applied, and a second electrode connected to the 2-1 node;
2-6 switch elements including a gate electrode to which the second EM pulse is applied, a first electrode connected to the 2-3 node, and a second electrode connected to the anode electrode of the second light emitting element;
a 2-1 capacitor connected between the 2-2 node and the 2-4 node; and
and a 2-2 capacitor connected between the 2-2 node and the 2-3 node, or connected between the 2-4 node and the 2-3 node. According to claim 12,
The gate pulse,
further comprising a third EM pulse;
The first pixel,
Further comprising 1-7 switch elements including a gate electrode to which a third EM pulse is applied, a first electrode connected to the 2-3 node, and a second electrode connected to the anode electrode of the first light emitting element,
The second pixel,
Display further comprising 2-7 switch elements including a gate electrode to which the third EM pulse is applied, a first electrode connected to the 1-3 node, and a second electrode connected to the anode electrode of the second light emitting element Device. According to claim 12,
A pixel reference voltage is applied to cathode electrodes of the first and second light emitting devices;
The pixel driving voltage is higher than a maximum voltage of data voltages applied to the data lines;
The reference voltage is lower than the minimum voltage of the data voltage,
The display device of claim 1 , wherein the pixel reference voltage and the initialization voltage are lower than the reference voltage. 15. The method of claim 14,
The first driving period of the first and second pixels includes an initialization step, a sensing step, a data writing step, a boosting step, and an emission step,
In the initialization phase of the first driving period, the first scan pulse and the second EM pulse are generated with a gate-on voltage, and the second scan pulse, the first EM pulse, and the third EM pulse generate a gate-on voltage. is the off voltage,
In the sensing step of the first driving period, the first scan pulse and the first EM pulse are generated with the gate-on voltage, and the second scan pulse, the second EM pulse, and the third EM pulse generate the gate-on voltage. is the gate off voltage,
In the data writing step of the first driving period, the second scan pulse is generated with the gate-on voltage synchronized with the data voltage applied to the data lines, and the first scan pulse, the first EM pulse, the a second EM pulse and the third EM pulse are the gate off voltage;
In the boosting phase and the emission phase of the first driving period, the first EM pulse and the second EM pulse are the gate-on voltages, and the first scan pulse, the second scan pulse, and the third EM pulse are is the gate off voltage,
The switch elements are turned on in response to the gate-on voltage and turned off in response to the gate-off voltage;
A display device wherein a first data voltage is applied to the first data line and a second data voltage is applied to the second data line during the first driving period. According to claim 15,
The second driving period of the first and second pixels includes an initialization step, a sensing step, a data writing step, a boosting step, and an emission step,
In the initialization phase of the second driving period, the first scan pulse and the third EM pulse are generated with a gate-on voltage, and the second scan pulse, the first EM pulse, and the second EM pulse generate a gate-on voltage. is the off voltage,
In the sensing step of the second driving period, the first scan pulse and the first EM pulse are generated with the gate-on voltage, and the second scan pulse, the second EM pulse, and the third EM pulse generate the is the gate off voltage,
In the data writing step of the second driving period, the second scan pulse is generated with the gate-on voltage synchronized with the data voltage applied to the data lines, and the first scan pulse, the first EM pulse, the a second EM pulse and the third EM pulse are the gate off voltage;
In the boosting phase and the emission phase of the second driving period, the first EM pulse and the third EM pulse are the gate-on voltages, and the first scan pulse, the second scan pulse, and the second EM pulse are is the gate off voltage,
During the second driving period, the second data voltage is applied to the first data line, and the first data voltage is applied to the second data line. According to claim 11,
The gate pulse is
including a scan pulse and an EM pulse;
The first pixel,
a second light emitting element;
a 1-1 switch element including a gate electrode to which the scan pulse is applied, a first electrode connected to a 1-4 node, and a second electrode connected to the 2-3 node;
a 1-2 switch element including a gate electrode to which the scan pulse is applied, a first electrode to which a first data voltage is applied, and a second electrode connected to the 1-2 node;
1-3 switch elements including a gate electrode to which the scan pulse is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the anode electrode of the first light emitting element;
1-4 switch elements including a gate electrode to which the EM pulse is applied, a first electrode connected to the 1-3 node, and a second electrode connected to the anode electrode of the first light emitting element;
a 1-1 capacitor connected between the 1-2 node and the 1-4 node; and
Further comprising a 1-2 capacitor connected between the 1-2 node and the 1-3 node or connected between the 1-4 node and the 1-3 node,
The second pixel,
a second light emitting element;
a 2-1 switch element including a gate electrode to which the scan pulse is applied, a first electrode connected to a 2-4 node, and a second electrode connected to the 1-3 node;
a 2-2 switch element including a gate electrode to which the scan pulse is applied, a first electrode to which a second data voltage is applied, and a second electrode connected to the 2-2 node;
a 2-3 switch element including a gate electrode to which the scan pulse is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode electrode of the second light emitting element;
a 2-4 switch element including a gate electrode to which the EM pulse is applied, a first electrode connected to the 2-3 node, and a second electrode connected to the anode electrode of the second light emitting element;
a 2-1 capacitor connected between the 2-2 node and the 2-4 node; and
and a 2-2 capacitor connected between the 2-2 node and the 2-3 node, or connected between the 2-4 node and the 2-3 node. 18. The method of claim 17,
A pixel reference voltage is applied to cathode electrodes of the first and second light emitting devices;
The pixel driving voltage is higher than maximum voltages of the first and second data voltages;
The display device of claim 1 , wherein the pixel reference voltage and the initialization voltage are lower than minimum voltages of the first and second data voltages. 18. The method of claim 17,
The driving period of the first and second pixels includes an initialization step, a sensing step, a data writing step, a boosting step, and an emission step,
In the initialization step, the scan pulse and the EM pulse are generated with a gate-on voltage;
In the sensing step, the scan pulse is generated with the gate-on voltage and the EM pulse is the gate-off voltage;
In the data writing step, the scan pulse is generated with the gate-on voltage synchronized with the first and second data voltages, and the EM pulse is the gate-off voltage;
In the boosting step and the light emission step, the EM pulse is generated with the gate-on voltage, and the scan pulse is the gate-off voltage;
The switch elements are turned on in response to the gate-on voltage and turned off in response to the gate-off voltage.

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