KR20230009250A - Pixel circuit and display device including the same - Google Patents

Abstract

Disclosed are a pixel circuit and a display device including the same. According to the present invention, a pixel circuit includes: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node, and configured to supply an electric current to a light emitting element; a first switch element configured to be turned on according to a gate-on voltage of a scan pulse to supply a data voltage to the first node; and a second switch element configured to be turned off according to a gate-off voltage of a light emitting control pulse generated in antiphase of the scan pulse. Accordingly, it is possible to prevent deterioration of image quality due to a ripple of a low-potential power supply voltage commonly applied between pixels.

Description

Pixel circuit and display device including the same {PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a pixel circuit and a display device including the same.

Electroluminescence displays can be divided into inorganic light emitting displays and organic light emitting displays according to the material of the light emitting layer. An active matrix type organic light emitting display includes an organic light emitting diode (OLED) that emits light by itself, and has a fast response speed, high luminous efficiency, luminance, and viewing angle. There are advantages. Organic Light Emitting Diode (OLED) is formed in each pixel of the organic light emitting display device. The organic light emitting display device has a fast response speed, excellent luminous efficiency, luminance, viewing angle, etc., as well as black gradation. Since it can be expressed in complete black, the contrast ratio and color gamut are excellent.

A pixel circuit of an organic light emitting display includes a light emitting element, a driving element for driving the light emitting element, and one or more switch elements. The switch elements are turned on/off according to the gate voltage to connect or disconnect main nodes of the pixel circuit. The driving element and the switch element may be implemented as transistors.

A low potential power supply voltage is commonly applied to pixels of the organic light emitting display device. When a switch element connected to a low-potential power supply voltage through a capacitor in a pixel circuit is turned on, ripples may be generated in the low-potential power supply voltage. In this case, the current flowing through the light emitting device may vary, resulting in luminance variation of pixels. When an image of a crosstalk pattern is displayed on a screen, a ripple of a low-potential power supply voltage may cause a non-uniformity of a charge amount between pixel lines, which may cause a luminance difference between pixel lines.

The present invention aims to address the aforementioned needs and/or problems.

The present invention provides a pixel circuit capable of preventing deterioration of image quality due to ripple of a low-potential power supply voltage commonly applied between pixels and a display device including the same.

The objects of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

A pixel circuit according to an exemplary embodiment of the present invention includes a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node to generate current to a light emitting device. a drive element that supplies; a first switch element turned on according to a gate-on voltage of a scan pulse to supply a data voltage to the first node; a second switch element that is turned off according to a gate-off voltage of an emission control pulse generated in reverse phase to the scan pulse; and a capacitor connected between the second node and the third node.

A pixel circuit according to another embodiment of the present invention includes a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node to generate current to a light emitting device. a drive element that supplies; a first switch element turned on according to a gate-on voltage of a scan pulse to supply a data voltage to the first node; a second switch element turned off according to the gate-off voltage of the emission control pulse; a third switch element that is turned on according to the gate-on voltage of the sensing pulse and supplies a reference voltage to the third node; and a capacitor connected between the second node and the third node. The emission control pulse is generated as an antiphase pulse of the sensing pulse.

A pixel circuit according to another embodiment of the present invention includes a first electrode connected to a first node to which a first positive voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node to provide a light emitting device with a drive element that supplies current; a first switch element turned on according to a gate-on voltage of a first gate pulse to supply a data voltage to the first node; a second switch element turned off according to the gate-off voltage of the second gate pulse; a third switch element turned on according to a gate-on voltage of a third gate pulse to supply a second positive voltage to the third node; a fourth switch element turned on according to a gate-on voltage of a fourth gate pulse to apply a third positive voltage to the second node; and a capacitor connected between the second node and the third node.

The second gate pulse is reversed to the gate-off voltage when the third gate pulse is reversed to the gate-on voltage, and is reversed to the gate-on voltage when the first gate pulse is reversed to the gate-on voltage.

A pixel circuit according to another embodiment of the present invention includes a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node. drive element including; a light emitting element driven by the current from the driving element, including an anode electrode connected to the fourth node and a cathode electrode to which a low potential power supply voltage is applied; a first switch element that is turned on according to the gate-on voltage of the first scan pulse and supplies a data voltage to a fifth node; a second switch element connected between the third node and the fourth node and turned off according to a gate-off voltage of a second light emission control pulse; a third switch element that is turned on according to a gate-on voltage of a third scan pulse and supplies a reference voltage to the third node; a fourth switch element that is turned on according to the gate-on voltage of the second scan pulse and connects the first gate electrode and the first electrode of the driving element; a fifth switch element that is turned off according to a gate-off voltage of a first emission control pulse to block a current path between a power line to which the pixel driving voltage is applied and the first node; a sixth switch element turned on according to the gate-on voltage of the second scan pulse to supply an initialization voltage to the fifth node; a seventh switch element turned on according to the gate-on voltage of the third scan pulse to supply the initialization voltage to the fourth node; a first capacitor connected between the second node and the fifth node; and a second capacitor connected between the third node and the fifth node.

The second light emission control pulse is generated as a gate-off voltage when the second scan pulse and the third scan pulse are at the gate-on voltage, and at least one of the second scan pulse and the third scan pulse is at the gate-off voltage. The gate-on voltage is generated when the second scan pulse is at the gate-on voltage, the gate-off voltage is generated when the second scan pulse is at the gate-on voltage, and the gate-on voltage is generated when the first scan pulse is at the gate-off voltage.

The display device of the present invention includes at least one of the pixel circuits.

The present invention blocks the current path between the driving element and the light emitting element in a section where ripple can occur in the low potential power supply voltage commonly connected to the pixels, thereby improving the ripple defect of the low potential power supply voltage. .

According to the present invention, a signal for controlling a switch element for blocking the current path is generated by receiving an output signal of a shift register that outputs another gate pulse, thereby realizing a narrow bezel of a display device.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram showing a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a cross-sectional structure of the display panel shown in FIG. 1 .
3 is a diagram showing a shift register of a gate driver and an EM generator connected to an output node of the shift register according to an embodiment of the present invention.
FIG. 4 is a waveform diagram showing input/output signals of the shift register shown in FIG. 3 .
5 is a circuit diagram showing a pixel circuit according to a first embodiment of the present invention.
FIG. 6 is a waveform diagram illustrating a gate signal applied to the pixel circuit shown in FIG. 5 .
FIG. 7 is a circuit diagram showing an EM generator generating an EM pulse applied to the pixel circuit shown in FIG. 5 .
8 is a circuit diagram showing a pixel circuit according to a second embodiment of the present invention.
FIG. 9 is a waveform diagram illustrating gate signals applied to the pixel circuit shown in FIG. 8 .
FIG. 10 is a circuit diagram showing an EM generator generating an EM pulse applied to the pixel circuit shown in FIG. 8 .
11 is a circuit diagram showing a pixel circuit according to a third embodiment of the present invention.
FIG. 12 is a waveform diagram illustrating gate signals applied to the pixel circuit shown in FIG. 11 .
FIG. 13 is a circuit diagram showing an EM generator generating an EM pulse applied to the pixel circuit shown in FIG. 11 .
14 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present invention.
FIG. 15 is a waveform diagram illustrating gate signals applied to the pixel circuit shown in FIG. 14 .
FIG. 16 is a circuit diagram showing an EM generator generating an EM pulse applied to the pixel circuit shown in FIG. 14 .
17 is a circuit diagram showing a pixel circuit according to a fifth embodiment of the present invention.
FIG. 18 is a waveform diagram illustrating a gate signal applied to the pixel circuit shown in FIG. 17 .
FIG. 19 is a circuit diagram showing an EM generator generating a second EM pulse applied to the pixel circuit shown in FIG. 17 .
20 is a circuit diagram showing a pixel circuit according to a sixth embodiment of the present invention.
FIG. 21 is a waveform diagram illustrating gate signals applied to the pixel circuit shown in FIG. 20 .
22 and 23 are circuit diagrams showing an EM generator generating a second EM pulse applied to the pixel circuit shown in FIG. 20 .

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the embodiments will make the disclosure of the present invention complete, and those of ordinary skill in the art to which the present invention belongs It is provided to fully inform the scope of the invention, the invention is defined only by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to those shown in the drawings. Like reference numbers designate substantially like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When “has”, “includes”, “has”, “is made of”, etc. mentioned in this specification is used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it may be interpreted in the plural unless specifically stated otherwise.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when a positional relationship between two components is described as 'on ~', 'on top of ~', 'on the bottom of ~', 'next to', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

Although first, second, etc. may be used to distinguish the components, the function or structure of these components is not limited to the ordinal number or component name attached to the front of the component.

The following embodiments may be partially or wholly combined or combined with each other, and technically various interlocking and driving operations are possible. Each of the embodiments may be implemented independently of each other or together in an association relationship.

Each of the pixels is divided into a plurality of sub-pixels having different colors for color implementation, and each of the sub-pixels includes a transistor used as a switch element or a driving element. Such a transistor may be implemented as a TFT (Thin Film Transistor).

A driving circuit of the display device writes pixel data of an input image into pixels. A driving circuit of a flat panel display device includes a data driving circuit for supplying data signals to data lines, a gate driving circuit for supplying gate signals to gate lines, and the like.

In the display device of the present invention, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistor may be implemented as a TFT of a Metal-Oxide-Semiconductor FET (MOSFET) structure, and may be an oxide TFT including an oxide semiconductor or an LTPS TFT including low temperature poly silicon (LTPS). Hereinafter, transistors constituting the pixel circuit and the gate driving circuit will be described based on an example implemented with an n-channel oxide TFT implemented with an oxide TFT, but the present invention is not limited thereto.

A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within a transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit the transistor. The flow of carriers in a transistor flows from the source to the drain. In the case of an n-channel transistor, since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. The direction of current in an n-channel transistor is from drain to source. In the case of a p-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal can swing between a Gate On Voltage and a Gate Off Voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

A transistor is turned on in response to a gate-on voltage, while it is turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage, and the gate-off voltage may be a gate low voltage.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described mainly with an organic light emitting display device, but the present invention is not limited thereto. In addition, the present invention is not limited to the names of components or signals in the following embodiments and claims.

Referring to FIGS. 1 and 2 , a display device according to an exemplary embodiment of the present invention includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and pixels and a power supply unit 140 generating power necessary for driving the display panel driving unit.

The display panel 100 may have a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array displaying an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to pixels. The power supply lines supply the pixels 101 with a constant voltage necessary for driving the pixels 101 . For example, the display panel 100 may include a VDD line to which the pixel driving voltage ELVDD is applied and a VSS line to which the low potential power supply voltage ELVSS is applied. In addition, the power lines may further include a REF line to which the reference voltage Vref is applied and an INIT line to which the initialization voltage Vinit is applied.

As shown in FIG. 2 , the cross-sectional structure of the display panel 100 may include a circuit layer 12, a light emitting element layer 14, and an encapsulation layer 16 stacked on a substrate 10. can

The circuit layer 12 may include a TFT array including pixel circuits connected to wires such as data lines, gate lines, and power lines, a demultiplexer array 112 , a gate driver 120 , and the like. The wiring and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated with an insulating layer interposed therebetween, and an active layer including a semiconductor material. All transistors formed in the circuit layer 12 can be implemented as n-channel oxide TFTs.

The light emitting element layer 14 may include a light emitting element EL driven by a pixel circuit. The light emitting element EL may include a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element. In another embodiment, the light emitting device layer 14 may include a white light emitting device and a color filter. The light emitting elements EL of the light emitting element layer 14 may be covered by a protective layer including an organic layer and a protective layer.

The encapsulation layer 16 covers the light emitting element layer 14 so as to seal the circuit layer 12 and the light emitting element layer 14 . The encapsulation layer 16 may have a multi-insulation layer structure in which organic layers and inorganic layers are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic layer flattens the surface of the inorganic layer. When the organic layer and the inorganic layer are stacked in multiple layers, the movement path of moisture or oxygen is longer than that of a single layer, so that penetration of moisture and oxygen affecting the light emitting element layer 14 can be effectively blocked.

A touch sensor layer, which is omitted in the drawings, is formed on the encapsulation layer 16, and a polarizing plate or color filter layer may be disposed thereon. The touch sensor layer may include capacitive touch sensors that sense a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include metal wiring patterns and insulating layers forming capacitance of the touch sensors. The insulating layers may insulate portions where the metal wiring patterns intersect and planarize a surface of the touch sensor layer. The polarizer may improve visibility and contrast ratio by converting polarization of external light reflected by metal of the touch sensor layer and the circuit layer. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase retardation film are bonded together or a circular polarizing plate. A cover glass may be adhered on the polarizing plate. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer may absorb some wavelengths of light reflected from the circuit layer and the touch sensor layer to replace the role of a polarizer and increase color purity of an image reproduced in the pixel array.

The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes one line of pixels disposed along a line direction (X-axis direction) in the pixel array of the display panel 100 . Pixels arranged on one pixel line share gate lines 103 . Sub-pixels arranged in the column direction (Y) along the data line direction share the same data line 102 . One horizontal period is a time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and a real object in the background is visible. The display panel 100 may be made of a flexible display panel.

Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels includes a pixel circuit. Hereinafter, a pixel may be interpreted as having the same meaning as a sub-pixel. Each of the pixel circuits is connected to data lines, gate lines, and power lines.

Pixels can be arranged as real color pixels and pentile pixels. A pentile pixel can implement a higher resolution than a real color pixel by driving two sub-pixels of different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm may compensate for insufficient color expression in each pixel with the color of light emitted from an adjacent pixel.

The power supply unit 140 uses a DC-DC converter to generate DC voltage (or constant voltage) required to drive the pixel array of the display panel 100 and the display panel driver. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply unit 140 adjusts the level of a DC input voltage applied from a host system (not shown) to generate a gamma reference voltage (VGMA) and a gate-on voltage (VGH). DC voltages (or constant voltages) such as gate-off voltage VGL, pixel driving voltage ELVDD, low potential power supply voltage ELVSS, initialization voltage Vinit, and reference voltage Vref may be generated. The gamma reference voltage VGMA is supplied to the data driver 110 . A gate-on voltage (VGH) and a gate-off voltage (VGL) are supplied to the gate driver 120 . Constant voltages such as the pixel driving voltage ELVDD, the low potential power supply voltage ELVSS, the initialization voltage Vinit, and the reference voltage Vref are supplied to the pixels 101 through power lines commonly connected to the pixels 101. do. The constant voltages applied to the pixel circuit may have different voltage levels.

The display panel driver writes pixel data of an input image into pixels of the display panel 100 under the control of a timing controller 130 .

The display panel driver includes a data driver 110 and a gate driver 120 . The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102 .

The demultiplexer array 112 sequentially supplies data voltages output from channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switch elements disposed on the display panel 100 . When the demultiplexer is disposed between the output terminals of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

The display panel driver may further include a touch sensor driver for driving touch sensors. The touch sensor driver is omitted in FIG. 1 . The data driver 110 and the touch sensor driver may be integrated into one drive integrated circuit (IC). In a mobile device or a wearable device, the timing controller 130, the power supply unit 140, the data driver 110, and the like may be integrated into one drive IC.

The display panel driver may operate in a low speed driving mode under the control of the timing controller 130 . The low-speed driving mode may be set to reduce power consumption of the display device when the input image does not change by a preset number of frames by analyzing the input image. The low-speed driving mode can reduce power consumption of the display panel driver and the display panel 100 by lowering the refresh rate of pixels when a still image is input for a predetermined period of time or longer. The low-speed drive mode is not limited when a still image is input. For example, when the display device operates in a standby mode or when a user command or an input image is not input to the display panel driving circuit for a predetermined period of time or more, the display panel driving circuit may operate in a low speed driving mode.

The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 generates a data voltage Vdata by converting pixel data of an input image into a gamma compensation voltage for each frame period using a digital to analog converter (DAC). The gamma reference voltage VGMA is divided into gamma compensation voltages for each gray level through a voltage divider circuit. The gamma compensation voltage for each gray level is provided to the DAC of the data driver 110 . The data voltage Vdata is output from each of the channels of the data driver 110 through an output buffer.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed on the circuit layer 12 on the display panel 100 together with the TFT array and wires of the pixel array. The gate driver 120 may be disposed on the bezel area (BZ), which is a non-display area of the display panel 100, or may be distributedly disposed within a pixel array where an input image is reproduced. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130 . The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signal may include various gate pulses such as a scan pulse, a sensing pulse, an initialization pulse, and an emission control pulse (hereinafter referred to as “pulse”).

The gate driver 120 further includes a shift register that outputs a gate signal and a light emission control signal generator (hereinafter referred to as “generator”) 122 that generates an EM pulse by receiving the gate signal output from the shift register. include The EM pulse is generated as a gate-off voltage during a period in which ripples of the low-potential power supply voltage ELVSS applied to the pixels 100 may occur, and blocks the current provided to the light emitting element EL, thereby reducing the voltage of the low-potential power supply voltage. Ripple defect can be improved. A gate signal output from the shift register of the gate driver 120 may be applied to a gate line, and an EM pulse output from the EM generator 122 may be applied to another gate line.

The timing controller 130 receives digital video data (DATA) of an input image and a timing signal synchronized therewith from the host system. The timing signal may include a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a clock (CLK), and a data enable signal (DE). Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical sync signal Vsync and the horizontal sync signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

The host system may be any one of a television (TV) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale an image signal from a video source according to the resolution of the display panel 100 and transmit the timing signal to the timing controller 130 together with the timing signal.

In the normal driving mode, the timing controller 130 multiplies the input frame frequency by i to control the operation timing of the display panel driver at a frame frequency of input frame frequency × i (i is a natural number) Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the Phase-Alternating Line (PAL) method.

The timing controller 130 lowers the frequency of the frame rate at which pixel data is written into pixels in the low-speed driving mode compared to the normal driving mode. For example, in the normal driving mode, the data refresh frame frequency in which pixel data is written to the pixels may occur at a frequency of 60 Hz or higher, for example, at a refresh rate of any one of 60 Hz, 120 Hz, and 144 Hz, and the data refresh in the low speed driving mode The frame DRF may be generated at a refresh rate of a lower frequency than that of the low-speed driving mode. For example, the timing controller 130 may lower the driving frequency of the display panel driving unit by lowering the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower the refresh rate of pixels in the low-speed driving mode.

The timing controller 130 controls the data timing control signal for controlling the operation timing of the data driver 110 and the operation timing of the demultiplexer array 112 based on the timing signals Vsync, Hsync, and DE received from the host system. A gate timing control signal for controlling the operation timing of the gate driving unit 120 is generated. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110 , the demultiplexer array 112 , the touch sensor driver, and the gate driver 120 .

The gate timing control signal generated from the timing controller 130 may be input to the shift register of the gate driver 120 through a level shifter (not shown). The level shifter may receive a gate timing control signal, generate a start pulse and a shift clock, and provide them to a shift register.

3 is a diagram showing a shift register of a gate driver and an EM generator connected to an output node of the shift register according to an embodiment of the present invention. FIG. 4 is a waveform diagram showing input/output signals of the shift register shown in FIG. 3 .

Referring to FIGS. 3 and 4 , the gate driver 120 is a shift register that sequentially outputs gate signals [Gout(n−1) to Gout(n+2)] in synchronization with the shift clock CLK. ). The gate signal may include any one of a scan pulse, a sensing pulse, and an initialization pulse. The gate driver 120 may include a plurality of shift registers outputting different gate signals. As shown in FIG. 3, each of these shift registers receives a start signal VST and shift clocks CLK1 to 4, outputs a gate signal, and shifts the gate signal in synchronization with the shift clock.

The shift register includes signal transfer units [ST(n-1) to ST(n+2)] that are cascaded. Each of the signal transfer units ST(n−1) to ST(n+2) includes a VST node to which the start signal VST is input, a CLK node to which shift clocks CLK1 to 4 are input, and the like.

The start signal VST is generally input to the first signal transfer unit. In FIG. 3 , the n−1 th signal transfer unit ST(n−1) may be a first signal transfer unit receiving the start signal VST. The shift clocks CLK1 to 4 may be 4-phase clocks as shown in FIG. 4 , but, for example, the shift clocks may be k (k is a natural number) phase clock.

The signal transfer units [ST(n) to ST(n+2)] dependently connected to the n−1 th signal transfer unit [ST(n−1)] convert the carry signal CAR from the previous signal transfer unit to a start signal. It receives input as , and starts running. Each of the signal transfer units [ST(n-1) to ST(n+2)] outputs a gate signal [Gout(n-1) to Gout(n+2)] through an output node and simultaneously outputs another output node. Through this, the carry signal CAR can be output.

The buffer BUF includes a first transistor TR1 and a second transistor TR2 connected to an output node from which a gate signal is output, and the gate signal [Gout(n−1) to Gout(n+2) is generated through the output node. ] is output. The output node is connected to the gate line 103 and is connected to the input node of the EM generator 122 .

The first transistor TR1 is a pull-up transistor, and the second transistor TR2 is a pull-down transistor. The first transistor TR1 includes a gate electrode connected to the first control node Q, a first electrode connected to a first power node to which the gate driving voltage GVDD is applied, and a second electrode connected to an output node. The second transistor TR2 is connected to the first transistor TR1 with the output node interposed therebetween. The second transistor TR2 includes a gate electrode connected to the second control node QB, a first electrode connected to an output node, and a second electrode connected to a second power node to which the gate reference voltage GVSS is applied.

The EM generator 122 is connected between the output node of the shift register and the gate line to which the EM pulse is applied. The EM generator 122 may be connected to each output node of the shift register. The EM generator 122 receives the gate signals [Gout(n-1) to Gout(n+2)] output from the shift register, and generates the gate signals [Gout(n-1) to Gout(n+2)] ] can output EM pulses [EM(n-1) to EM(n+2)]. The n-1th EM generator 122 outputs the n-1th EM pulse [EM(n-1)] in response to the n-1th gate signal [Gout(n-1)]. The nth EM generator 122 outputs an nth EM pulse [EM(n−1)] in response to the nth gate signal [Gout(n)]. The n+1th EM generator 122 outputs an n+1th EM pulse [EM(n+1)] in response to the n+1th gate signal [Gout(n+1)]. A gate driving voltage VDD and a gate reference voltage VSS are input to each of the EM generators 122 . The EM pulses EM(n-1) to EM(n+2) swing between the gate drive voltage VDD and the gate reference voltage VSS.

Since the EM generator 122 does not operate as a shift register, it does not need to receive a start signal and a shift clock.

The gate driving voltages GVDD and VDD applied to the shift register of the gate driver 120 and the EM generator 122 may be set to the gate-on voltage VGH. The gate reference voltages GVSS and VSS may be set to the gate off voltage VGL.

There may be differences in electrical characteristics of driving elements between pixels due to process variation and element characteristic variation resulting from the manufacturing process of the display panel 100 , and such differences may increase as the driving time of the pixels elapses. An internal compensation circuit may be embedded in the pixel circuit or an external compensation circuit may be connected to the pixel circuit in order to compensate for a deviation in electrical characteristics of a driving element between pixels. The internal compensation circuit samples the electrical characteristics of the driving element for each sub-pixel using the internal compensation circuit implemented in each pixel circuit, and compensates for the gate-source voltage (Vgs) of the driving element by the electrical characteristic. The external compensation circuit compensates for a change in electrical characteristics of the driving element by generating a compensation value based on a result of sensing the electrical characteristics of the driving element using the external compensation circuit connected to the pixel circuit.

5 to 23 are diagrams showing various pixel circuits and their driving signals applicable to the pixels of the present invention.

5 is a circuit diagram showing a pixel circuit according to a first embodiment of the present invention. FIG. 6 is a waveform diagram illustrating a gate signal applied to the pixel circuit shown in FIG. 5 . FIG. 7 is a circuit diagram showing the EM generator 122 that generates an EM pulse (EM(n)) applied to the pixel circuit shown in FIG. 5 . The gate signal includes a scan pulse [SCAN(n)] and an EM pulse [EM(n)].

5 and 6 , the pixel circuit includes a light emitting element EL, a driving element DT supplying current to the light emitting element EL, and a driving element DT in response to a scan pulse [SCAN(n)]. Current path between the driving element DT and the light emitting element EL in response to the first switch element M01 supplying the data voltage Vdata to the gate electrode of the EM pulse [EM(n)] and a capacitor Cst connected between the second node DRG and the third node DRS. In this pixel circuit, the driving element DT and the switch elements M01 and M02 may be implemented as n-channel oxide TFTs.

A constant voltage such as a pixel driving voltage ELVDD and a low potential power supply voltage ELVSS is applied to the pixel circuit. The pixel driving voltage ELVDD is higher than the low potential power supply voltage ELVSS. The gate-on voltage VGH may be set to a higher voltage than the pixel driving voltage ELVDD. The gate-off voltage VGL may be set to a voltage lower than the low-potential power supply voltage ELVSS.

The gate driver 120 may include a shift register that sequentially outputs scan pulses SCAN(n). As shown in FIGS. 6 and 7 , the EM generator 122 may generate an EM pulse EM(n) using a small number of transistors.

The light emitting element EL may be implemented as an OLED including an anode electrode, a cathode electrode, and an organic compound layer connected between the electrodes. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer, EIL), but is not limited thereto. When voltage is applied to the anode electrode and the cathode electrode, holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) are moved to the light emitting layer (EML), and excitons are formed, whereby visible light is emitted from the light emitting layer (EML). can The anode electrode of the light emitting element EL may be connected to the second electrode of the second switch element M02, and the low potential power supply voltage ELVSS may be applied to the cathode electrode.

The driving element DT generates a current I _EL for driving the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node DRG, a first electrode connected to the first node DRD to which the pixel driving voltage ELVDD is applied, and a third electrode connected to the third node DRS. include The capacitor Cst is connected between the second node DRG and the third node DRS to store the gate-source voltage Vgs of the driving element DT.

The scan pulse [SCAN(n)] swings between a gate-on voltage (VGH) and a gate-off voltage (VGL). The scan pulse [SCAN(n)] is generated with the gate-on voltage VGH during the data addressing phase ADDR. The first switch element M01 is turned on according to the gate-on voltage VGH of the scan pulse SCAN(n) and supplies the data voltage Vdata to the second node DRG. The first switch element M01 includes a gate electrode connected to a first gate line to which a scan pulse [SCAN(n)] is applied, a first electrode connected to a data line to which a data voltage Vdata of pixel data is applied, and a second switch element M01. A second electrode connected to the node DRG is included.

The EM pulse [EM(n)] swings between a gate-on voltage (VGH) and a gate-off voltage (VGL). The EM pulse EM(n) is generated with the gate-off voltage VGL during the data addressing phase ADDR and with the gate-on voltage VGH during the emission phase EMIS. The second switch element M02 is turned off according to the gate-off voltage VGL of the EM pulse [EM(n)], and the current between the driving element DT and the light emitting element EL during the data addressing phase ADDR. block the pass The second switch element M02 is turned on according to the gate-on voltage VGH of the EM pulse [EM(n)] and passes current between the driving element DT and the light emitting element EL during the light emitting phase EMIS. form At this time, the light emitting element EL may emit light by the current I _EL from the driving element DT. The second switch element M02 includes a gate electrode connected to the second gate line to which the EM pulse [EM(n)] is applied, a first electrode connected to the third node DRS, and an anode electrode of the light emitting element EL. It includes a second electrode connected to it.

When the scan pulse SCAN(n) is inverted to the gate-on voltage VGH, a ripple may be generated in the low-potential power supply voltage ELVSS due to capacitor coupling through parasitic capacitance. The emission pulse [EM(n)] is generated as an anti-phase pulse with respect to the scan pulse [SCAN(n)] to reduce the current applied to the light emitting element EL when a ripple can occur in the low potential power supply voltage ELVSS. block it At this time, since the light emitting element EL cannot emit light, a luminance change of the light emitting element EL due to the ripple of the low potential power supply voltage ELVSS can be prevented.

The EM generator 122 may include the circuit shown in FIG. 7 .

Referring to FIG. 7 , the EM generator 122 includes a first EM switch element T01 and a second EM switch element T02. The first EM switch element T01 supplies the gate driving voltage VDD to an output node connected to the second gate line. The switch elements T01 and T02 may be implemented as n-channel oxide TFTs.

The gate driving voltage VDD is applied to the first electrode of the first EM switch element T01. The gate driving voltage VDD may be the gate on voltage VGH. The gate electrode and the second electrode of the first EM switch element T01 are connected to the output node. The second EM switch element T02 is turned on according to the gate-on voltage VGH of the scan pulse SCAN(n) and discharges the voltage of the output node up to the gate reference voltage VSS. The gate reference voltage VSS may be the gate off voltage VGL. The second EM switch element T02 includes a gate electrode to which a scan pulse [SCAN(n)] is applied, a first electrode connected to an output node, and a second electrode connected to a VSS node to which a gate reference voltage VSS is applied. do. Accordingly, the EM generator 122 may generate an EM pulse [EM(n)] in an antiphase of the scan pulse [SCAN(n)] in response to the scan pulse [SCAN(n)].

In order to drive the pixel circuit shown in FIG. 5, the gate driver 120 is an EM generator composed of one shift register outputting a scan pulse [SCAN(n)] and two switch elements T01 and T02. (122). The gate driver 120 does not require a separate shift register for outputting and shifting the EM pulse [EM(n)]. Accordingly, since the circuit area occupied by the gate driver circuit is reduced, the bezel area BZ of the display panel 100 may be narrowed.

8 to 13 are diagrams showing a pixel circuit connected to an external compensation circuit and an EM generator generating an EM pulse applied to the pixel circuit. The external compensation circuit includes a REF line (or sensing line, RL) connected to the pixel circuit, and an analog to digital converter (ADC) that converts the sensing voltage stored in the REF line RL into digital data. The sensing voltage may include electrical characteristics of the driving element DT, for example, a threshold voltage and/or mobility. An integrator may be connected to the input terminal of the ADC. The timing controller 130 to which the external compensation circuit is applied generates a compensation value for compensating for a change in electrical characteristics of the driving element DT according to the sensing data input from the ADC, and adds or multiplies the compensation value to the pixel data of the input image. A change in electrical characteristics of the driving element DT may be compensated for. ADC may be built into the data driver 110 .

8 is a circuit diagram showing a pixel circuit according to a second embodiment of the present invention. FIG. 9 is a waveform diagram illustrating gate signals applied to the pixel circuit shown in FIG. 8 . FIG. 10 is a circuit diagram showing an EM generator 122 that generates an EM pulse (EM(n)) applied to the pixel circuit shown in FIG. 8 . In this embodiment, the gate signal includes a scan pulse [SCAN(n)], a sensing pulse [SENSE(n)], and an EM pulse [EM(n)].

8 and 9 , the pixel circuit includes a light emitting element EL, a driving element DT supplying current to the light emitting element EL, and a driving element DT in response to a scan pulse [SCAN(n)]. A first switch element (M11) for supplying the data voltage (Vdata) to the gate electrode of the first switch element (M11), a first switch element (M11) for blocking the current path between the driving element (DT) and the light emitting element (EL) in response to the EM pulse [EM (n)] 2 switch element M12, a third switch element M13 connecting the third node DRS to the REF line RL in response to the sensing pulse [SENSE(n)], and the second node DRG A capacitor Cst connected between the three nodes DRS is included. In this pixel circuit, the driving element DT and the switch elements M11, M12, and M13 may be implemented as n-channel oxide TFTs.

A constant voltage such as a pixel driving voltage ELVDD and a low potential power supply voltage ELVSS is applied to the pixel circuit. The pixel driving voltage ELVDD is higher than the low potential power supply voltage ELVSS. The gate-on voltage VGH may be set to a higher voltage than the pixel driving voltage ELVDD. The gate-off voltage VGL may be set to a voltage lower than the low-potential power supply voltage ELVSS. The reference voltage Vref may be set to a low potential voltage close to the low potential voltage ELVSS.

The driving period of the pixel circuit may be divided into an initialization phase (INIT), a programming phase (PR), a sensing phase (SENSE), a sampling phase (SMPL), and an emission phase (EMIS).

The scan pulse [SCAN(n)] is synchronized with the data voltage Vdata of the pixel data and generated as the gate-on voltage VGH in the programming step PR. The scan pulse [SCAN(n)] may rise to the gate-on voltage VGH at a timing close to the end point of the initialization step INIT. The scan pulse [SCAN(n)] is the gate off voltage VGL in the sensing step SENSE, the sampling step SMPL, and the light emitting step EMIS. The sensing pulse SENSE(n) rises to the gate-on voltage VGH in the initialization phase INIT and maintains the gate-on voltage VGH during the programming phase PR and the sensing phase SENSE. The sensing pulse SENSE(n) is the gate-off voltage VGL in the sampling stage SMPL and the emission stage EMIS.

The EM pulse [EM(n)] is generated in antiphase of the sensing pulse [SENSE(n)]. Accordingly, the EM pulse EM(n) is inverted to the gate-off voltage VGL in the initialization phase INIT and maintains the gate-off voltage VGL during the programming phase PR and the sensing phase SENSE. The EM pulse [EM(n)] is the gate-on voltage (VGH) in the sampling phase (SMPL) and the emission phase (EMIS).

The reference voltage switch element SPRE and the sampling switch element SAM may be connected to the REF line RL to which the reference voltage Vref is applied. The reference voltage switch element SPRE and the sampling switch element SAM are turned on under the control of the timing controller 130 . The reference voltage switch element SPRE is turned on during the initialization phase INIT and the programming phase PR to supply the reference voltage Vref to the REF line RL. The sampling switch element SAM is turned on in the sampling phase SMPL to connect the REF line RL to the ADC.

The light emitting element EL may be implemented as an OLED including an anode electrode, a cathode electrode, and an organic compound layer connected between the electrodes. The anode electrode of the light emitting element EL may be connected to the second electrode of the second switch element M12, and the low potential power supply voltage ELVSS may be applied to the cathode electrode.

The driving element DT generates a current for driving the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node DRG, a first electrode connected to the first node DRD to which the pixel driving voltage ELVDD is applied, and a third electrode connected to the third node DRS. include The capacitor Cst is connected between the second node DRG and the third node DRS.

The first switch element M11 is turned on according to the gate-on voltage VGH of the scan pulse SCAN(n) and supplies the data voltage Vdata to the second node DRG in the programming step PR. . The first switch element M11 includes a gate electrode connected to a first gate line to which a scan pulse SCAN(n) is applied, a first electrode connected to a data line to which a data voltage Vdata is applied, and a second node DRG. ) and a second electrode connected to the

The second switch element M12 is turned off according to the gate-off voltage VGL of the EM pulse [EM(n)] to provide a driving element during the initialization phase INIT, the programming phase PR, and the sensing phase SENSE. A current path between DT and the light emitting element EL is blocked. The second switch element M12 is turned on according to the gate-on voltage VGH of the EM pulse [EM(n)] to pass current between the driving element DT and the light emitting element EL during the light emitting phase EMIS. form The second switch element M12 includes a gate electrode connected to the second gate line to which the EM pulse [EM(n)] is applied, a first electrode connected to the third node DRS, and an anode electrode of the light emitting element EL. It includes a second electrode connected to it.

The third switch element M13 is turned on according to the gate-on voltage VGH of the sensing pulse SENSE(n), REF to which the reference voltage Vref is applied during the programming phase PR and the sensing phase SENSE. The line RL is connected to the third node DRS. In the sensing step SENSE, the voltage of the third node DRS is stored in the capacitor Csen of the REF line RL, and the electrical characteristics of the driving element DT are stored in the REF line RL, and the REF line RL ) is converted into digital data through the ADC in the sampling step (SMPL). The third switch element M13 includes a gate electrode connected to the third gate line to which the sensing pulse SENSE(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the REF line RL. contains electrodes.

When the sensing pulse SENSE(n) is inverted to the gate-on voltage VGH, a ripple may be generated in the low-potential power supply voltage ELVSS due to capacitor coupling through parasitic capacitance. The light emitting pulse [EM(n)] is generated as an anti-phase pulse with respect to the sensing pulse [SCAN(n)] to reduce the current applied to the light emitting element EL when a ripple can occur in the low potential power supply voltage ELVSS. block it At this time, since the light emitting element EL cannot emit light, a luminance change of the light emitting element EL due to the ripple of the low potential power supply voltage ELVSS can be prevented.

The EM generator 122 may include the circuit shown in FIG. 10 .

Referring to FIG. 10 , the EM generator 122 includes a first EM switch element T11 and a second EM switch element T12. The switch elements T11 and T12 may be implemented as n-channel oxide TFTs.

The first EM switch element T11 supplies the gate driving voltage VDD to an output node connected to the second gate line. The gate driving voltage VDD is applied to the first electrode of the first EM switch element T11. The gate driving voltage VDD may be the gate on voltage VGH. The gate electrode and the second electrode of the first EM switch element T11 are connected to the output node. The second EM switch element T12 is turned on according to the gate-on voltage VGH of the sensing pulse SENSE(n) and discharges the voltage of the output node up to the gate reference voltage VSS. The gate reference voltage VSS may be the gate off voltage VGL. The second EM switch element T12 includes a gate electrode to which the sensing pulse SENSE(n) is applied, a first electrode connected to the output node, and a second electrode connected to the VSS node. Accordingly, the EM generator 122 may generate an EM pulse [EM(n)] with an antiphase of the sensing pulse [SENSE(n)] in response to the sensing pulse [SENSE(n)].

In order to drive the pixel circuit shown in FIG. 8 , the gate driver 120 includes a first shift register that sequentially outputs a scan pulse [SCAN(n)] and a first shift register that sequentially outputs a sensing pulse [SENSE(n)]. A second shift register may be included. As shown in FIGS. 9 and 10 , the EM generator 122 may generate an EM pulse [EM(n)] using a small number of transistors. The gate driver 120 does not require a separate shift register for outputting and shifting the EM pulse [EM(n)]. Accordingly, since the circuit area occupied by the gate driver circuit is reduced, the bezel area BZ of the display panel 100 may be narrowed.

11 is a circuit diagram showing a pixel circuit according to a third embodiment of the present invention. FIG. 12 is a waveform diagram illustrating gate signals applied to the pixel circuit shown in FIG. 11 . FIG. 13 is a circuit diagram showing the EM generator 122 that generates an EM pulse (EM(n)) applied to the pixel circuit shown in FIG. 11 . In this embodiment, the gate signal includes a scan pulse [SCAN(n)] and an EM pulse [EM(n)]. The pixel circuit according to the third embodiment of the present invention except that the second and third switch elements M21 and M23 are simultaneously turned on/off in response to the scan pulse SCAN(n) is the pixel of the second embodiment. circuit is substantially the same. In the pixel circuit according to the third embodiment of the present invention, detailed descriptions of substantially the same parts as those of the second embodiment will be omitted.

11 and 12, the pixel circuit includes a light emitting element EL, a driving element DT supplying current to the light emitting element EL, and a driving element DT in response to a scan pulse [SCAN(n)]. A first switch element (M21) for supplying the data voltage (Vdata) to the gate electrode of the first switch element (M21), a first block for blocking the current path between the driving element (DT) and the light emitting element (EL) in response to the EM pulse [EM (n)] 2 switch element M22, a third switch element M23 connecting the third node DRS to the REF line RL in response to the scan pulse [SCAN(n)], and the second node DRG A capacitor Cst connected between the three nodes DRS is included. In this pixel circuit, the driving element DT and the switch elements M21, M22, and M23 may be implemented as n-channel oxide TFTs.

The scan pulse [SCAN(n)] is generated as the gate-on voltage VGH in the programming phase PR, the sensing phase SENSE, and the sampling phase SMPL. The scan pulse SCAN(n) is the gate-off voltage VGL in the initialization phase INIT and the emission phase EMIS. The EM pulse [EM(n)] is generated in antiphase of the scan pulse [SCAN(n)]. Accordingly, the EM pulse EM(n) is generated as the gate-off voltage VGL in the programming phase PR, the sensing phase SENSE, and the sampling phase SMPL. The EM pulse [EM(n)] is the gate-on voltage VGH in the initialization phase INIT and the emission phase EMIS.

The reference voltage switch element SPRE is turned on during the initialization phase INIT and the programming phase PR to supply the reference voltage Vref to the REF line RL. The sampling switch element SAM is turned on in the sampling phase SMPL to connect the REF line RL to the ADC.

The first switch element M21 is turned on according to the gate-on voltage VGH of the scan pulse [SCAN(n)], and the data voltage ( A data line to which Vdata) is applied is connected to the second node DRG. The first switch element M21 includes a gate electrode connected to a first gate line to which a scan pulse SCAN(n) is applied, a first electrode connected to a data line to which a data voltage Vdata is applied, and a second node DRG. ) and a second electrode connected to the

The second switch element M22 is turned off according to the gate-off voltage VGL of the EM pulse [EM(n)], and the driving element ( A current path between the DT) and the light emitting element EL is blocked. The second switch element M22 is turned on according to the gate-on voltage VGH of the EM pulse [EM(n)] to pass current between the driving element DT and the light emitting element EL during the light emitting phase EMIS. form The second switch element M22 includes a gate electrode connected to the second gate line to which the EM pulse [EM(n)] is applied, a first electrode connected to the third node DRS, and an anode electrode of the light emitting element EL. It includes a second electrode connected to it.

The third switch element M23 is turned on according to the gate-on voltage VGH of the scan pulse [SCAN(n)], and the reference voltage ( The REF line RL to which Vref) is applied is connected to the third node DRS. The third switch element M23 includes a gate electrode connected to the first gate line to which the scan pulse SCAN(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the REF line RL. contains electrodes.

When the scan pulse [SCAN(n)] is inverted to the gate-on voltage VGH, a ripple may be generated in the low potential power supply voltage ELVSS. The emission pulse [EM(n)] is generated as an anti-phase pulse with respect to the scan pulse [SCAN(n)] to reduce the current applied to the light emitting element EL when a ripple can occur in the low potential power supply voltage ELVSS. block it

The EM generator 122 may include the circuit shown in FIG. 13 .

Referring to FIG. 13 , the EM generator 122 includes a first EM switch element T21 and a second EM switch element T22. The switch elements T21 and T22 may be implemented as n-channel oxide TFTs.

The first EM switch element T21 supplies the gate driving voltage VDD to an output node connected to the second gate line. A gate driving voltage VDD is applied to the first electrode of the first EM switch element T21. The gate driving voltage VDD may be the gate on voltage VGH. The gate electrode and the second electrode of the first EM switch element T21 are connected to the output node. The second EM switch element T22 is turned on according to the gate-on voltage VGH of the scan pulse SCAN(n) and discharges the voltage of the output node up to the gate reference voltage VSS. The gate reference voltage VSS may be the gate off voltage VGL. Accordingly, the EM generator 122 may generate an EM pulse [EM(n)] in an antiphase of the scan pulse [SCAN(n)] in response to the scan pulse [SCAN(n)].

In order to drive the pixel circuit shown in FIG. 11, the gate driver 120 includes a shift register that sequentially outputs a scan pulse [SCAN(n)] and an EM composed of a small number of transistors as shown in FIG. A generator 122 may be included. As shown in FIGS. 12 and 13 , the EM generator 122 may generate an EM pulse [EM(n)] using a small number of transistors. The gate driver 120 does not require a separate shift register for outputting and shifting the EM pulse [EM(n)]. Accordingly, since the circuit area occupied by the gate driving circuit is reduced, the bezel area BZ of the display panel 100 may be narrowed.

14 to 16 are diagrams illustrating a pixel circuit including an internal compensation circuit and a driving signal thereof. 14 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present invention. FIG. 15 is a waveform diagram illustrating gate signals applied to the pixel circuit shown in FIG. 14 . FIG. 16 is a circuit diagram showing the EM generator 122 generating an EM pulse (EM(n)) applied to the pixel circuit shown in FIG. 14 . In this embodiment, the gate signal includes an initialization pulse [INIT(n)], a scan pulse [SCAN(n)], a sensing pulse [SENSE(n)], and an EM pulse [EM(n)].

14 and 15, the pixel circuit includes a light emitting element EL, a driving element DT supplying current to the light emitting element EL, and a driving element DT in response to a scan pulse [SCAN(n)]. A first switch element (M31) for supplying the data voltage (Vdata) to the gate electrode of the first switch element (M31), a first switch element (M31) for blocking the current path between the driving element (DT) and the light emitting element (EL) in response to the EM pulse [EM (n)] 2 The switch element M32, the third switch element M33 for connecting the third node DRS to the REF line RL in response to the sensing pulse [SENSE(n)], and the initialization pulse [INIT(n)] A fourth switch element M34 supplying the initialization voltage Vinit to the second node DRG in response, and a capacitor Cst connected between the second node DRG and the third node DRS. In this pixel circuit, the driving element DT and the switch elements M31 to M34 may be implemented as n-channel oxide TFTs.

A constant voltage such as a pixel driving voltage ELVDD, a low potential power supply voltage ELVSS, a reference voltage Vref, and an initialization voltage Vinit is applied to the pixel circuit. The pixel driving voltage ELVDD is higher than the low potential power supply voltage ELVSS. The gate-on voltage VGH may be set to a higher voltage than the pixel driving voltage ELVDD. The gate-off voltage VGL may be set to a voltage lower than the low-potential power supply voltage ELVSS. The reference voltage Vref may be set to a low potential voltage close to the low potential voltage ELVSS. The initialization voltage Vinit may be set to a voltage at which the driving element DT can be turned on.

The driving period of the pixel circuit may be divided into an initialization phase (INIT), a sensing phase (SENSE), an addressing phase (WR), a boosting phase (BOOST), and an emission phase (EMIS). In the initialization phase INIT, the driving element DT is turned on. In the sensing step SENSE, when the voltage of the third node DRS rises and the gate-source voltage Vgs of the driving element DT becomes lower than the threshold voltage Vth, the driving element DT is turned off. . When the driving element DT is turned off in the sensing step SENSE, the threshold voltage Vth of the driving element DT is sampled by the capacitor Cst. When the data voltage Vdata is applied to the second node DRG in the addressing step WR, the gate voltage of the driving element DT is applied with the compensated data voltage Vdata by the threshold voltage Vth. After the voltages of the floating second node DRG and the third node DRS increase in the boosting step BOOST, the gate-to-source voltage Vgs compensated by the threshold voltage Vth of the driving element DT. ), a current for driving the light emitting element EL is generated from the driving element DT.

The initialization pulse [INIT(n)] is generated as the gate-on voltage VGH in the initialization phase INIT and the sensing phase SENSE. The initialization pulse [INIT(n)] is the gate off voltage VGL in the addressing phase WR, the boosting phase BOOST, and the emission phase EMIS. The scan pulse [SCAN(n)] is synchronized with the data voltage Vdata of the pixel data and generated as the gate-on voltage VGH in the addressing step WR. The scan pulse SCAN(n) is the gate-off voltage VGL in the initialization phase INIT, the sensing phase SENSE, the boosting phase BOOST, and the emission phase EMIS. The sensing pulse SENSE(n) is generated as the gate-on voltage VGH in the initialization stage INIT. The sensing pulse SENSE(n) is the gate-off voltage VGL in the sensing phase SENSE, the addressing phase WR, the boosting phase BOOST, and the emission phase EMIS.

The EM pulse [EM(n)] is inverted to the gate-off voltage (VGL) when the sensing pulse [SENSE(n)] is inverted to the gate-on voltage (VGH), and the scan pulse [SCAN(n)] is inverted to the gate-on voltage When it inverts to (VGH), it inverts to the gate-on voltage (VGH). Accordingly, the EM pulse EM(n) is generated as the gate-off voltage VGL in the initialization stage INIT and the sensing stage SENSE. The EM pulse [EM(n)] is the gate-on voltage (VGH) in the addressing phase (WR), the boosting phase (BOOST), and the emission phase (EMIS).

The light emitting element EL may be implemented as an OLED including an anode electrode, a cathode electrode, and an organic compound layer connected between the electrodes. The anode electrode of the light emitting element EL may be connected to the second electrode of the second switch element M32, and the low potential power supply voltage ELVSS may be applied to the cathode electrode.

The driving element DT generates a current for driving the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node DRG, a first electrode connected to the first node DRD to which the pixel driving voltage ELVDD is applied, and a third electrode connected to the third node DRS. include The capacitor Cst is connected between the second node DRG and the third node DRS.

The first switch element M31 is turned on according to the gate-on voltage VGH of the scan pulse SCAN(n) and supplies the data voltage Vdata to the second node DRG in the addressing step WR. . The first switch element M31 includes a gate electrode connected to a first gate line to which a scan pulse SCAN(n) is applied, a first electrode connected to a data line to which a data voltage Vdata is applied, and a second node DRG. ) and a second electrode connected to the

The second switch element M32 is turned off according to the gate-off voltage VGL of the EM pulse [EM(n)], and the driving element DT and the light emitting element ( EL) blocks the current path between them. The second switch element M32 is turned on according to the gate-on voltage VGH of the EM pulse [EM(n)] and operates as a driving element during the addressing phase WR, the boosting phase BOOST, and the emission phase EMIS. A current path is formed between the DT and the light emitting element EL. The second switch element M32 includes a gate electrode connected to the second gate line to which the EM pulse [EM(n)] is applied, a first electrode connected to the third node DRS, and an anode electrode of the light emitting element EL. It includes a second electrode connected to it.

The third switch element M33 is turned on according to the gate-on voltage VGH of the sensing pulse SENSE(n) to remove the REF line RL to which the reference voltage Vref is applied in the initialization step INIT. 3 Connect to node (DRS). The third switch element M33 includes a gate electrode connected to the third gate line to which the sensing pulse SENSE(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the REF line RL. contains electrodes.

The fourth switch element M34 is turned on according to the gate-on voltage VGH of the initialization pulse INIT(n) and supplies the initialization voltage Vinit to the second node in the initialization stage INIT and the sensing stage SENSE. (DRG). The fourth switch element M34 includes a gate electrode connected to the fourth gate line to which the initialization pulse INIT(n) is applied, a first electrode connected to the INI line to which the initialization voltage Vinit is applied, and a second node DRG. ) and a second electrode connected to the

The EM generator 122 may include the circuit shown in FIG. 16 .

Referring to FIG. 16 , the EM generator 122 includes first to sixth switch elements T31 to T36. The switch elements T31 to T36 may be implemented as n-channel oxide TFTs.

The first EM switch element T31 is turned on when the voltage of the pull-up control node 161 is charged to the gate-on voltage, and applies the gate driving voltage VDD to the output node connected to the second gate line. supply At this time, the voltage of the EM pulse [EM(n)] rises to the gate-on voltage VGH. The gate driving voltage VDD is applied to the first electrode of the first EM switch element T31. The gate driving voltage VDD may be the gate on voltage VGH. The first EM switch element T31 includes a gate electrode connected to the pull-up control node 161, a first electrode to which the gate driving voltage VDD is applied, and a second electrode connected to the output node.

The second EM switch element T32 is turned on when the pull-down control node 162 is charged to the gate-on voltage, and connects the VSS node to which the gate reference voltage VSS is applied to the output node to output Discharge the node. The gate reference voltage VSS may be the gate off voltage VGL. When the second EM switch element T32 is turned on, the voltage of the EM pulse [EM(n)] is lowered to the gate-off voltage VGL. The second EM switch element T32 includes a gate electrode connected to the pull-down control node 162, a first electrode connected to the output node, and a second electrode connected to the VSS node.

The third EM switch element T33 is turned on according to the gate-on voltage VGH of the scan pulse SCAN(n) to charge the pull-up control node 161 . The fourth EM switch element T34 is turned on according to the gate-on voltage VGH of the sensing pulse SENSE(n) to discharge the pull-up control node 161 . When the third EM switch element T33 is turned on and the fourth EM switch element T34 is turned off, the first EM switch element T31 is turned on. When the third EM switch element T33 is turned off and the fourth EM switch element T34 is turned on, the pull-up control node 161 is discharged and the first EM switch element T31 is turned off. . When both the third and fourth EM switch elements T33 and T34 are turned off, the pull-up control node 161 floats and maintains the previous state.

The third EM switch element T33 includes a gate electrode to which a scan pulse [SCAN(n)] is applied, a first electrode to which a gate driving voltage VDD is applied, and a second electrode connected to the pull-up control node 161. do. The fourth EM switch element T34 includes a gate electrode to which the sensing pulse SENSE(n) is applied, a first electrode connected to the pull-up control node 161, and a second electrode connected to the VSS node.

The fifth EM switch element T35 is turned on according to the gate-on voltage VGH of the sensing pulse SENSE(n) to charge the pull-down control node 162 . The sixth EM switch element T36 is turned on according to the gate-on voltage VGH of the scan pulse SCAN(n) to discharge the pull-down control node 162. When the fifth EM switch element T35 is turned on and the sixth EM switch element T36 is turned off, the second EM switch element T32 is turned on. When the fifth EM switch element T35 is turned off and the sixth EM switch element T36 is turned on, the pull-down control node 162 is discharged and the second EM switch element T32 is turned off. . When both the fifth and sixth EM switch elements T35 and T36 are turned off, the pull-down control node 162 floats and maintains the previous state.

The fifth EM switch element T35 includes a gate electrode to which the sensing pulse SENSE(n) is applied, a first electrode to which the gate driving voltage VDD is applied, and a second electrode connected to the pull-down control node 162. do. The sixth EM switch element T36 includes a gate electrode to which the scan pulse SCAN(n) is applied, a first electrode connected to the pull-down control node 162, and a second electrode connected to the VSS node.

To drive the pixel circuit shown in FIG. 14 , the gate driver 120 sequentially outputs an initialization pulse [INIT(n)] and a first shift register that sequentially outputs a scan pulse [SCAN(n)]. 2 shift registers, and a third shift register sequentially outputting sensing pulses SENSE(n). As shown in FIGS. 15 and 16 , the EM generator 122 may generate an EM pulse [EM(n)] using a small number of transistors T31 to T36. The gate driver 120 does not require a separate shift register for outputting and shifting the EM pulse [EM(n)]. Accordingly, since the circuit area occupied by the gate driving circuit is reduced, the bezel area BZ of the display panel 100 may be narrowed.

17 is a circuit diagram showing a pixel circuit according to a fifth embodiment of the present invention. FIG. 18 is a waveform diagram illustrating a gate signal applied to the pixel circuit shown in FIG. 17 . FIG. 19 is a circuit diagram showing the EM generator 122 generating the second EM pulse EM2(n) applied to the pixel circuit shown in FIG. 17 . In this embodiment, the gate signal is a first scan pulse [SCAN1 (n)], a second scan pulse [SCAN2 (n)], a third scan pulse [SCAN3 (n)], a first EM pulse [EM1 (n)] ], and a second EM pulse [EM2(n)].

17 and 18 , the pixel circuit includes a light emitting element EL, a driving element DT supplying current to the light emitting element EL, and a driving element (in response to a first scan pulse SCAN1(n)). Current path between the driving element DT and the light emitting element EL in response to the first switch element M41 supplying the data voltage Vdata to the gate electrode of the DT and the first EM pulse [EM1(n)] a second switch element M42 for blocking the third scan pulse [SCAN3(n)], a third switch element M43 for connecting the third node DRS to the initialization line INI in response to the third scan pulse [SCAN3(n)], and a second scan The fourth switch element M44 supplies the reference voltage Vref to the second node DRG in response to the pulse [SCAN2(n)], and the pixel driving voltage in response to the first EM pulse [EM1(n)] ELVDD to the first node DRD, a fifth switch element M45, a first capacitor Cst connected between the second node DRG and the fourth node n4, and the fourth node and the VDD node It includes a second capacitor (Cd) connected therebetween. The VDD node is connected to the VDD line to which the pixel driving voltage ELVDD is applied.

In this pixel circuit, the driving element DT and the switch elements M31 to M34 may be implemented as n-channel oxide TFTs.

A constant voltage such as a pixel driving voltage ELVDD, a low potential power supply voltage ELVSS, a reference voltage Vref, and an initialization voltage Vinit is applied to the pixel circuit. The pixel driving voltage ELVDD is higher than the low potential power supply voltage ELVSS. The gate-on voltage VGH may be set to a higher voltage than the pixel driving voltage ELVDD. The gate-off voltage VGL may be set to a voltage lower than the low-potential power supply voltage ELVSS. The initialization voltage Vinit may be set to a low potential voltage close to the low potential voltage ELVSS. The reference voltage Vref may be set to a voltage at which the driving element DT can be turned on.

The driving period of this pixel circuit can be divided into an initialization phase (INIT), a sampling phase (SMPL), an addressing phase (WR), and an emission phase (EMIS).

The first scan pulse [SCAN(n)] is synchronized with the data voltage Vdata of the pixel data and generated as the gate-on voltage VGH in the addressing step WR. The first scan pulse SCAN1(n) is the gate off voltage VGL in the initialization phase INIT, the sampling phase SMPL, and the emission phase EMIS. The second scan pulse SCAN2(n) is generated as a gate-on voltage VGH during the initialization stage INIT and the sampling stage SMPL. The second scan pulse SCAN2(n) is the gate off voltage VGL in the addressing phase WR and the emission phase EMIS. The third scan pulse SCAN3(n) is generated as the gate-on voltage VGH in the initialization stage INIT. The third scan pulse SCAN3(n) is the gate off voltage VGL in the sampling step SMPL, the addressing step WR, and the light emitting step EMIS.

The first EM pulse EM1(n) is generated at the gate-off voltage VGL in the initialization phase INIT and the addressing phase WR. The first EM pulse EM1(n) is the gate-on voltage VGH for the sampling stage SMPL and the emission stage EMIS.

The second EM pulse [EM2(n)] is inverted to the gate-off voltage VGL when the third scan pulse [SCAN3(n)] is inverted to the gate-on voltage VGH, and the first scan pulse [SCAN1(n) )] is inverted to the gate-on voltage (VGH) when it is inverted to the gate-on voltage (VGH). Accordingly, the second EM pulse EM2(n) is generated at the gate-off voltage VGL in the initialization phase INIT and the sampling phase SMPL. The second EM pulse EM2(n) is the gate-on voltage VGH in the addressing phase WR and the emission phase EMIS.

The light emitting element EL may be implemented as an OLED including an anode electrode, a cathode electrode, and an organic compound layer connected between the electrodes. The anode electrode of the light emitting element EL may be connected to the fourth node n4 , and the low potential power supply voltage ELVSS may be applied to the cathode electrode.

The driving element DT generates a current for driving the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node DRG, a first electrode connected to the first node DRD, and a third electrode connected to the third node DRS.

The first capacitor Cst is connected between the second node DRG and the third node DRS. The second capacitor Cd is connected between the fourth node n4 and the VDD node.

The first switch element M41 is turned on according to the gate-on voltage VGH of the first scan pulse SCAN1(n) and applies the data voltage Vdata to the second node DRG in the addressing step WR. supply The first switch element M41 includes a gate electrode connected to a first gate line to which a first scan pulse SCAN1(n) is applied, a first electrode connected to a data line to which a data voltage Vdata is applied, and a second node. and a second electrode connected to (DRG).

The second switch element M42 is turned off according to the gate-off voltage VGL of the second EM pulse EM2(n), and emits light with the driving element DT during the initialization stage INIT and the sampling stage SMPL. A current path between the elements EL is blocked. The second switch element M42 is turned on according to the gate-on voltage VGH of the second EM pulse EM2(n), and emits light from the driving element DT during the addressing phase WR and the light emission phase EMIS. A current path is formed between the elements EL. The second switch element M42 includes a gate electrode connected to the second gate line to which the second EM pulse EM2(n) is applied, a first electrode connected to the third node DRS, and a fourth node n4. and a second electrode connected to the anode electrode of the light emitting element EL by way of a second electrode.

The third switch element M43 is turned on according to the gate-on voltage VGH of the third scan pulse SCAN3(n), and the INIT line INI to which the initialization voltage Vinit is applied in the initialization step INIT is connected to the third node DRS. The third switch element M43 includes a gate electrode connected to the third gate line to which the third scan pulse SCAN3(n) is applied, a first electrode connected to the third node DRS, and an INIT line INI. It includes a second electrode.

The fourth switch element M44 is turned on according to the gate-on voltage VGH of the second scan pulse SCAN2(n) to provide the reference voltage Vref in the initialization stage INIT and the sampling stage SMPL. 2 Supply to node (DRG). The fourth switch element M44 has a gate electrode connected to the fourth gate line to which the second scan pulse SCAN2(n) is applied, a first electrode to which the reference voltage Vref is applied, and a second node DRG. It includes a second electrode connected to it.

The fifth switch element M45 is turned off according to the gate-off voltage VGL of the first EM pulse EM1(n), so that the pixel driving voltage ELVDD is reduced in the initialization stage INIT and the addressing stage WR. A current path between the applied VDD line and the first node DRD is blocked. The fifth switch element M45 is turned on according to the gate-on voltage VGH of the first EM pulse EM1(n), and outputs the VDD line to the first node ( DRD). The fifth switch element M45 includes a gate electrode connected to the fifth gate line to which the first EM pulse EM1(n) is applied, a first electrode connected to the VDD line, and a second electrode connected to the first node DRD. includes

The EM generator 122 may include the circuit shown in FIG. 19 .

Referring to FIG. 19 , the EM generator 122 includes first to sixth switch elements T41 to T46. The switch elements T41 to T46 may be implemented as n-channel oxide TFTs. The EM generator 122 receives the first and third scan pulses SCAN1(n) and SCAN3(n) and outputs a second EM pulse EM2.

The first EM switch element T41 includes a gate electrode connected to the pull-up control node 191, a first electrode to which the gate driving voltage VDD is applied, and a second electrode connected to the output node. The second EM switch element T42 includes a gate electrode connected to the pull-down control node 192, a first electrode connected to an output node, and a second electrode connected to a VSS node to which a gate reference voltage VSS is applied.

The third EM switch element T43 is turned on according to the gate-on voltage VGH of the first scan pulse SCAN1(n) to charge the pull-up control node 191. The fourth EM switch element T44 is turned on according to the gate-on voltage VGH of the third scan pulse SCAN1(n) to discharge the pull-up control node 191. The third EM switch element T43 includes a gate electrode to which the first scan pulse SCAN1(n) is applied, a first electrode to which the gate driving voltage VDD is applied, and a second electrode connected to the pull-up control node 191. includes The fourth EM switch element T44 includes a gate electrode to which the third scan pulse SCAN1(n) is applied, a first electrode connected to the pull-up control node 191, and a second electrode connected to the VSS node.

The fifth EM switch element T45 is turned on according to the gate-on voltage VGH of the third scan pulse SCAN3(n) to charge the pull-down control node 192. The sixth EM switch element T46 is turned on according to the gate-on voltage VGH of the first scan pulse SCAN1(n) to discharge the pull-down control node 192. The fifth EM switch element T45 includes a gate electrode to which the third scan pulse SCAN3(n) is applied, a first electrode to which the gate driving voltage VDD is applied, and a second electrode connected to the pull-down control node 192. includes The sixth EM switch element T46 includes a gate electrode to which the first scan pulse SCAN1(n) is applied, a first electrode connected to the pull-down control node 192, and a second electrode connected to the VSS node.

To drive the pixel circuit shown in FIG. 17, the gate driver 120 sequentially outputs a first shift register that sequentially outputs a first scan pulse SCAN1(n) and a second scan pulse SCAN2(n). A second shift register that outputs to , a third shift register that sequentially outputs the third scan pulse [SCAN3(n)], and a fourth shift register that sequentially outputs the first EM pulse [EM1(n)]. can do. As shown in FIGS. 18 and 19 , the EM generator 122 may generate the second EM pulse EM2(n) using a small number of transistors T41 to T46. The gate driver 120 does not require a separate shift register for outputting and shifting the second EM pulse [EM2(n)]. Accordingly, since the circuit area occupied by the gate driving circuit is reduced, the bezel area BZ of the display panel 100 may be narrowed.

20 is a circuit diagram showing a pixel circuit according to a sixth embodiment of the present invention. FIG. 21 is a waveform diagram illustrating gate signals applied to the pixel circuit shown in FIG. 20 . 22 and 23 are circuit diagrams showing the EM generator 122 generating the second EM pulse EM2(n) applied to the pixel circuit shown in FIG. 20 . The gate signal is a first scan pulse [SC1 (n)], a second scan pulse [SC2 (n)], a third scan pulse [SC3 (n)], a first EM pulse [EM1 (n)], and a second scan pulse [SC3 (n)]. EM pulses [EM2-1(n), EM2-2(n)].

The sixth embodiment of the present invention applies a predetermined voltage to the second gate electrode of the driving element DT in a diode connection type internal compensation circuit to shift the threshold voltage of the driving element to a senseable voltage range. can As a result, the present invention can shift the threshold voltage (Vth) of the driving element (DT) shifted to a voltage of 0 [V] or less to a voltage that can be sensed.

20 and 21, the pixel circuit includes a light emitting element EL, a driving element DT, first and second capacitors C1 and C2, and first to seventh switch elements M51 to M57. includes The driving element DT and the switch elements M51 to M57 may be implemented as n-channel oxide TFTs.

In this pixel circuit, constant voltages such as the pixel driving voltage (ELVDD), the low potential power supply voltage (ELVSS), the reference voltage (Vref), and the initialization voltage (Vinit), the data voltage (Vdata) of the pixel data, and the scan pulse [SC1(n ), SC2(n), SC3(n)], and EM pulses [EM1(n), EM2-1(n), EM2-2(n)] are supplied. The voltages of scan pulses [SC1(n), SC2(n), SC3(n)] and EM pulses [EM1(n), EM2-1(n), EM2-2(n)] are gate-on voltages (VGH) and the gate-off voltage (VGL).

The constant voltage commonly applied to the pixels may be set as ELVDD > Vref > Vinit > ELVSS, but is not limited thereto. The reference voltage Vref may be set to a voltage higher than the initialization voltage Vinit so that a negative back-bias is applied to the driving element DT in the sampling step SMPL. The gate-on voltage VGH may be set to a higher voltage than the pixel driving voltage VDD. The gate-off voltage VGL may be set to a voltage lower than the low-potential power supply voltage VSS.

The driving period of the pixel circuit includes an initialization step (INIT) in which the pixel circuit is initialized, a sampling step (SMPL) in which the threshold voltage (Vth) of the driving element (DT) is sampled, and a data voltage (Vdata) is charged and pixel data is written. It may be divided into an addressing step (WR) and a light emitting step (EMIS) in which the light emitting element EL emits light.

The first scan pulse SC1(n) may be generated with a gate-on voltage VGH synchronized with the data voltage Vdata in the addressing step WR. The first scan pulse [SC1(n)] may be the gate off voltage VGL in the initialization phase INIT, the sampling phase SMPL, and the emission phase EMIS.

The second scan pulse SC2(n) rises to the gate-on voltage VGH before the third scan pulse SC3(n), and the falling edge of the third scan pulse SC3(n) It may fall to the gate off voltage (VGL) prior to the falling edge. The second scan pulse SC2(n) may be generated as the gate-on voltage VGH during the initialization stage INIT and the sampling stage SMPL. The second scan pulse SC2(n) may be the gate off voltage VGL in the addressing phase WR and the emission phase EMIS.

The third scan pulse SC3(n) may be generated as the gate-on voltage VGH in the sampling step SMPL and the addressing step WR. In the addressing step WR, the gate-on voltage period of the third scan pulse SC3(n) may overlap the gate-on voltage period of the first scan pulse SC1(n). The third scan pulse [SC3(n)] rises to the gate-on voltage VGH after the rising edge of the second scan pulse [SC2(n)], and then the second scan pulse [SC2(n) After the falling edge of ], the gate-off voltage (VGL) may be polled. The third scan pulse SC3(n) may be the gate off voltage VGL in the initialization stage INIT and the emission stage EMIS.

The first EM pulse EM1(n) may be generated at the gate-on voltage VGH during the initialization stage INIT and the light emission stage EMIS. The first EM pulse EM1(n) may be the gate off voltage VGL in the sampling phase INIT and the addressing phase WR.

The second EM pulse [EM2-1(n), EM2-2(n)] is either the 2-1st EM pulse [EM2-1(n)] or the 2-2nd EM pulse [EM2-2(n)]. Either one can happen.

While the 2-1st EM pulse [EM2-1(n)] is generated at the gate-off voltage VGL in the initialization phase INIT, the sampling phase SMPL, and the addressing phase WR, the light emitting phase EMIS may be the gate-on voltage (VGH) at

The 2-2nd EM pulse [EM2-2(n)] is generated as a gate-off voltage (VGL) in the initialization stage (INIT) and sampling stage (SMPL), whereas in the addressing stage (WR) and light emission stage (EMIS) It may be a gate-on voltage (VGH).

The anode electrode of the light emitting element EL may be connected to the fourth node n4 , and the low potential power supply voltage VSS may be applied to the cathode electrode of the light emitting element EL.

The first capacitor C1 may be connected between the second node n2 and the fifth node n5. The first capacitor C1 stores the threshold voltage Vth of the driving element DT in the sampling step SMPL. In the addressing step WR, the data voltage Vdata is transferred to the first gate electrode of the driving element DT through the first capacitor C1.

The second capacitor C2 is connected between the third node DRS and the fifth node n5. The second capacitor C2 stores the second electrode voltage, that is, the source voltage, of the driving element DT at the beginning of the light emitting step EMIS, and the gate-to-source voltage of the driving element DT in the light emitting step EMIS. (Vgs).

The driving device DT may be a MOSFET having a double gate structure. The driving element DT includes a first gate electrode connected to the second node DRG, a second gate electrode connected to the fourth node n4, a first electrode connected to the first node DRD, and a third node DRS. ) and a second electrode connected to the The first gate electrode and the second gate electrode of the driving element DT may overlap with a semiconductor pattern forming a semiconductor channel therebetween.

The first switch element M51 includes a first electrode connected to the data line to which the data voltage Vdata is applied, a second electrode connected to the fifth node n5, and a first scan pulse SC1(n) to which the first scan pulse SC1(n) is applied. It includes a gate electrode. The first switch element M51 is turned on in the addressing step WR in response to the gate-on voltage VGH of the first scan pulse SC1(n) and generates a data voltage Vdata at the fifth node n5. supply The current path between the data line and the fifth node n5 is blocked during the initialization phase INIT, the sampling phase SMPL, and the emission phase EMIS in which the first switch element M51 is turned off.

The second switch element M52 includes a first electrode connected to the third node DRS, a second electrode connected to the fourth node n4, and a second EM pulse [EM2-1(n), EM2-2(n)]. )] is applied. The second switch element M52 responds to the gate-on voltage VGH of the second EM pulses EM2-1(n) and EM2-2(n) to perform the light emitting step EMIS or the addressing step WR and It is turned on in the light emitting step EMIS to form a current path between the driving element DT and the light emitting element EL. When the second switch element M52 is in an off state, a current path between the driving element DT and the light emitting element EL is blocked so that the light emitting element EL does not emit light.

The third switch element M53 includes a first electrode connected to the third node DRS, a second electrode to which the reference voltage Vref is applied, and a gate electrode to which the third scan pulse SC3(n) is applied. do. The third switch element M53 is turned on in the sampling step SMPL and the addressing step WR in response to the gate-on voltage VGH of the third scan pulse SC3(n) to set the reference voltage Vref. supplied to the third node DRS. The current path between the REF line to which the reference voltage Vref is applied and the third node DRS is blocked during the initialization stage INIT and the light emitting stage EMIS in which the third switch element M53 is turned off.

The fourth switch element M54 includes a first electrode connected to the first node DRD, a second electrode connected to the second node DRG, and a gate electrode to which the second scan pulse SC2(n) is applied. do. The fourth switch element M54 is turned on during the initialization stage INIT and the sampling stage SMPL in response to the gate-on voltage VGH of the second scan pulse SC2(n) to generate the first node DRD. and the second node DRG are connected. When the fourth switch element M54 is turned on, the first gate electrode and the first electrode of the driving element DT are connected to operate as a diode.

The fifth switch element M55 includes a first electrode to which the pixel driving voltage ELVDD is applied, a second electrode connected to the first node DRD, and a gate electrode to which the first EM pulse EM1(n) is applied. include The fifth switch element M55 is turned on during the initialization stage INIT and the light emission stage EMIS in response to the gate-on voltage VGH of the first EM pulse EM1(n) to generate a pixel driving voltage ELVDD is supplied to the first node DRD. A current path between the VDD line to which the pixel driving voltage ELVDD is applied and the first node DRD is blocked in the sampling stage SMPL and the addressing stage WR, in which the fifth switch element M55 is turned off.

The sixth switch element M56 includes a first electrode to which the initialization voltage Vinit is applied, a second electrode connected to the fifth node n5, and a gate electrode to which the second scan pulse SC2(n) is applied. do. The sixth switch element M56 is turned on during the initialization stage INIT and the sampling stage SMPL in response to the gate-on voltage VGH of the second scan pulse SC2(n), thereby forming a fifth node n5. supply the initialization voltage (Vinit) to In the addressing step WR and the light emitting step EMIS in which the sixth switch element M56 is turned off, a current path between the INIT line to which the initialization voltage Vinit is applied and the fifth node n5 is blocked.

The seventh switch element M57 includes a first electrode to which the initialization voltage Vinit is applied, a second electrode connected to the fourth node n4, and a gate electrode to which the third scan pulse SC3(n) is applied. do. The seventh switch element M57 is turned on in the sampling stage SMPL and the addressing stage WR in response to the gate-on voltage VGH of the third scan pulse SC3(n) to generate the initialization voltage Vinit. supplied to the fourth node n4. When the seventh switch element M57 is turned on, the reference voltage Vref is applied to the third node DRS through the third switch element M53. The current path between the INIT line to which the initialization voltage Vinit is applied and the fourth node n4 is blocked during the initialization stage INIT and the light emitting stage EMIS in which the seventh switch element M57 is turned off.

In the sixth embodiment of the present invention, the threshold voltage Vth of the driving element DT is sampled by applying the reference voltage Vref to the third node DRS in the sampling step SMPL, and in the addressing step WR. The sampling step SMPL and the addressing step WR may be separated by applying the data voltage Vdata to the fifth node n5. As a result, the sixth embodiment can secure the time of the sampling step (SMPL) long enough, for example, two horizontal periods or more.

The EM generator 122 may include the circuit shown in FIG. 22 or 23 .

Referring to FIG. 22 , the EM generator 122 includes first to third EM switch elements T51, T52, and T53. The EM generator 122 receives the second and third scan pulses SC2(n) and SC3(n) and outputs the 2-1 EM pulse EM2-1(n). The EM switch elements T51, T52, and T53 may be implemented as n-channel oxide TFTs.

The 2-1st EM pulse [EM2-1(n)] is generated as a gate-off voltage (VGL) when the second and third scan pulses [SC2(n), SC3(n)] are gate-on voltages (VGH). and is generated as a gate-on voltage when at least one of the second and third scan pulses SC2(n) and SC3(n) is a gate-off voltage.

The gate driving voltage VDD is applied to the first electrode of the first EM switch element T51. The gate electrode and the second electrode of the first EM switch element T51 are connected to the output node. The second EM switch element T52 is turned on according to the gate-on voltage VGH of the second scan pulse SC2(n) and discharges the voltage of the output node up to the gate reference voltage VSS. The second EM switch element T52 includes a gate electrode to which the second scan pulse SC2(n) is applied, a first electrode connected to the output node, and a second electrode connected to the VSS node. The third EM switch element T53 is turned on according to the gate-on voltage VGH of the third scan pulse SC3(n) and discharges the voltage of the output node up to the gate reference voltage VSS. The third EM switch element T53 includes a gate electrode to which the third scan pulse SC3(n) is applied, a first electrode connected to the output node, and a second electrode connected to the VSS node.

Referring to FIG. 23 , the EM generator 122 includes first to sixth EM switch elements T61 to T66. The EM generator 122 receives the first and second scan pulses SC1(n) and SC2(n) and outputs the 2-2 EM pulses EM2-2(n). The EM switch elements T61 to T66 may be implemented as n-channel oxide TFTs.

The 2-2nd EM pulse [EM2-2(n)] is generated as a gate-off voltage (VGL) when the second scan pulse [SC2(n)] is the gate-on voltage (VGH), and the first scan pulse [SC1 (n)] is generated as a gate-on voltage when the gate-off voltage.

The first EM switch element T61 is turned on when the pull-up control node 231 is charged and applies the gate-on voltage VGH to the output node where the 2-2 EM pulse [EM2-2(n)] is output. supply The second EM switch element T62 is turned on when the pull-down control node 232 is charged to discharge the output node. The third EM switch element T63 is turned on according to the gate-on voltage VGH of the first scan pulse SC1(n) to charge the pull-up control node 231 . The fourth EM switch element T64 is turned on according to the gate-on voltage VGH of the second scan pulse SC2(n) to discharge the pull-up control node 231. The fifth EM switch element T65 is turned on according to the gate-on voltage VGH of the second scan pulse SC2(n) to charge the pull-down control node 232. The sixth EM switch element T65 is turned on according to the gate-on voltage VGH of the first scan pulse SC1(n) to discharge the pull-down control node 232.

The first EM switch element T61 includes a gate electrode connected to the pull-up control node 231, a first electrode to which the gate driving voltage VDD is applied, and a second electrode connected to the output node. The second EM switch element T62 includes a gate electrode connected to the pull-down control node 232, a first electrode connected to an output node, and a second electrode connected to a VSS node to which a gate reference voltage VSS is applied.

The third EM switch element T63 is turned on according to the gate-on voltage VGH of the first scan pulse SC(n) to charge the pull-up control node 231 . The fourth EM switch element T64 is turned on according to the gate-on voltage VGH of the second scan pulse SC2(n) to discharge the pull-up control node 231. The third EM switch element T63 includes a gate electrode to which the first scan pulse SC1(n) is applied, a first electrode to which the gate driving voltage VDD is applied, and a second electrode connected to the pull-up control node 231. includes The fourth EM switch element T64 includes a gate electrode to which the second scan pulse SC2(n) is applied, a first electrode connected to the pull-up control node 231, and a second electrode connected to the VSS node.

The fifth EM switch element T65 is turned on according to the gate-on voltage VGH of the second scan pulse SC2(n) to charge the pull-down control node 232. The sixth EM switch element T66 is turned on according to the gate-on voltage VGH of the first scan pulse SC1(n) to discharge the pull-down control node 232. The fifth EM switch element T65 includes a gate electrode to which the second scan pulse SC2(n) is applied, a first electrode to which the gate driving voltage VDD is applied, and a second electrode connected to the pull-down control node 232. includes The sixth EM switch element T66 includes a gate electrode to which the first scan pulse SC1(n) is applied, a first electrode connected to the pull-down control node 232, and a second electrode connected to the VSS node.

In order to drive the pixel circuit shown in FIG. 20 , the gate driver 120 sequentially outputs a first shift register that sequentially outputs a first scan pulse SC1(n) and a second scan pulse SC2(n). A second shift register that outputs to , a third shift register that sequentially outputs the third scan pulse [SC3(n)], and a fourth shift register that sequentially outputs the first EM pulse [EM1(n)]. can do. As shown in FIGS. 21 to 23 , the EM generator 122 generates second EM pulses [EM2-1(n), EM2-2( n)] may occur. The gate driver 120 does not require a separate shift register for outputting and shifting the second EM pulses EM2-1(n) and EM2-2(n). Accordingly, since the circuit area occupied by the gate driving circuit is reduced, the bezel area BZ of the display panel 100 may be narrowed.

Since the content of the specification described in the problem to be solved, the problem solution, and the effect above does not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display panel 110: data driving unit
120: gate driver 122: emission control signal generator
130: timing controller 140: power supply
EL: light emitting element of pixel circuit DT: driving element of pixel circuit
M01~M02: switch element of pixel circuit Cst, C1, C2: capacitor of pixel circuit
T01~T66: EM switch element SCAN, SCAN1, SCAN2, SC1~SC3: scan pulse
EM, EM1, EM2, EM2-1, EM2-2: EM pulse

Claims (17)

a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node to supply current to a light emitting element;
a first switch element turned on according to a gate-on voltage of a scan pulse to supply a data voltage to the first node;
a second switch element that is turned off according to a gate-off voltage of an emission control pulse generated in reverse phase to the scan pulse; and
A pixel circuit including a capacitor coupled between the second node and the third node. According to claim 1,
The first switch element,
a gate electrode connected to a first gate line to which the scan pulse is applied, a first electrode connected to a data line to which the data voltage is applied, and a second electrode connected to the first node;
The second switch element,
A pixel circuit including a gate electrode connected to a second gate line to which the emission control pulse is applied, a first electrode connected to the third node, and a second electrode connected to an anode electrode of the light emitting element. According to claim 1,
and a third switch element turned on according to the gate-on voltage of the scan pulse to supply a reference voltage to the third node. According to claim 3,
The first switch element,
a gate electrode connected to a first gate line to which the scan pulse is applied, a first electrode connected to a data line to which the data voltage is applied, and a second electrode connected to the first node;
The second switch element,
A gate electrode connected to a second gate line to which the emission control pulse is applied, a first electrode connected to the third node, and a second electrode connected to an anode electrode of the light emitting element;
The third switch element is
A pixel circuit including a gate electrode connected to the first gate line, a first electrode connected to the third node, and a second electrode connected to a power line to which the reference voltage is applied. a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node to supply current to a light emitting element;
a first switch element turned on according to a gate-on voltage of a scan pulse to supply a data voltage to the first node;
a second switch element turned off according to the gate-off voltage of the emission control pulse;
a third switch element that is turned on according to the gate-on voltage of the sensing pulse and supplies a reference voltage to the third node; and
A capacitor connected between the second node and the third node;
A pixel circuit in which the emission control pulse is generated as an antiphase pulse of the sensing pulse. According to claim 5,
The first switch element,
a gate electrode connected to a first gate line to which the scan pulse is applied, a first electrode connected to a data line to which the data voltage is applied, and a second electrode connected to the first node;
The second switch element,
A gate electrode connected to a second gate line to which the emission control pulse is applied, a first electrode connected to the third node, and a second electrode connected to an anode electrode of the light emitting element;
The third switch element,
A pixel circuit including a gate electrode connected to a third gate line to which the sensing pulse is applied, a first electrode connected to the third node, and a second electrode connected to a power line to which the reference voltage is applied. a driving element including a first electrode connected to a first node to which a first constant voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node to supply current to a light emitting element;
a first switch element turned on according to a gate-on voltage of a first gate pulse to supply a data voltage to the first node;
a second switch element turned off according to the gate-off voltage of the second gate pulse;
a third switch element turned on according to a gate-on voltage of a third gate pulse to supply a second positive voltage to the third node;
a fourth switch element turned on according to a gate-on voltage of a fourth gate pulse to apply a third positive voltage to the second node; and
A capacitor connected between the second node and the third node;
The second gate pulse,
wherein the third gate pulse is reversed to the gate-off voltage when the third gate pulse is reversed to the gate-on voltage, and is reversed to the gate-on voltage when the first gate pulse is reversed to the gate-on voltage. a driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node;
a light emitting element driven by the current from the driving element, including an anode electrode connected to the fourth node and a cathode electrode to which a low potential power supply voltage is applied;
a first switch element that is turned on according to the gate-on voltage of the first scan pulse and supplies a data voltage to a fifth node;
a second switch element connected between the third node and the fourth node and turned off according to a gate-off voltage of a second light emission control pulse;
a third switch element that is turned on according to a gate-on voltage of a third scan pulse and supplies a reference voltage to the third node;
a fourth switch element that is turned on according to the gate-on voltage of the second scan pulse and connects the first gate electrode and the first electrode of the driving element;
a fifth switch element that is turned off according to a gate-off voltage of a first emission control pulse to block a current path between a power line to which the pixel driving voltage is applied and the first node;
a sixth switch element turned on according to the gate-on voltage of the second scan pulse to supply an initialization voltage to the fifth node;
a seventh switch element turned on according to the gate-on voltage of the third scan pulse to supply the initialization voltage to the fourth node;
a first capacitor connected between the second node and the fifth node; and
A second capacitor connected between the third node and the fifth node;
The second emission control pulse
A gate-off voltage is generated when the second scan pulse and the third scan pulse are at the gate-on voltage, and a gate-on voltage is generated when at least one of the second scan pulse and the third scan pulse is at the gate-off voltage. or
The pixel circuit of claim 1 , wherein the gate-off voltage is generated when the second scan pulse is at the gate-on voltage, and the gate-on voltage is generated when the first scan pulse is at the gate-off voltage. A display in which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power lines are disposed. panel;
a data driver supplying data voltages of pixel data to the data lines; and
a gate driver supplying scan pulses and emission control pulses to the gate lines;
Each of the pixel circuits,
a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node to supply current to a light emitting element;
a first switch element turned on according to the gate-on voltage of the scan pulse to supply a data voltage to the first node;
a second switch element turned off according to the gate-off voltage of the emission control pulse; and
A capacitor connected between the second node and the third node;
The display device in which the emission control pulse is generated in an antiphase of the scan pulse. According to claim 9,
The gate driver,
a first EM switch element including a first electrode to which the gate-on voltage is applied, a gate electrode connected to an output node to which the emission control pulse is output, and a second electrode; and
A display device comprising a second EM switch element including a gate electrode to which the scan pulse is applied, a first electrode connected to the output node, and a second electrode to which the gate-off voltage is applied. A display in which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power lines are disposed. panel;
a data driver supplying data voltages of pixel data to the data lines; and
A gate driver supplying scan pulses, sensing pulses, and emission control pulses to the gate lines;
Each of the pixel circuits,
a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node to supply current to a light emitting element;
a first switch element turned on according to a gate-on voltage of a scan pulse to supply a data voltage to the first node;
a second switch element turned off according to the gate-off voltage of the emission control pulse;
a third switch element that is turned on according to the gate-on voltage of the sensing pulse and supplies a reference voltage to the third node; and
A capacitor connected between the second node and the third node;
The display device of claim 1 , wherein the emission control pulse is generated as an antiphase pulse of the sensing pulse. According to claim 11,
The gate driver,
a first EM switch element including a first electrode to which the gate-on voltage is applied, a gate electrode connected to an output node to which the emission control pulse is output, and a second electrode; and
A display device comprising a second EM switch element including a gate electrode to which the sensing pulse is applied, a first electrode connected to the output node, and a second electrode to which the gate-off voltage is applied. A display in which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power lines are disposed. panel;
a data driver supplying data voltages of pixel data to the data lines; and
a gate driver supplying a first gate pulse, a second gate pulse, a third gate pulse, and a fourth gate pulse to the gate lines;
Each of the pixel circuits,
a driving element including a first electrode connected to a first node to which a first constant voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node to supply current to a light emitting element;
a first switch element turned on according to a gate-on voltage of a first gate pulse to supply a data voltage to the first node;
a second switch element turned off according to the gate-off voltage of the second gate pulse;
a third switch element turned on according to a gate-on voltage of a third gate pulse to supply a second positive voltage to the third node;
a fourth switch element turned on according to a gate-on voltage of a fourth gate pulse to apply a third positive voltage to the second node; and
A capacitor connected between the second node and the third node;
The second gate pulse,
The display device of claim 1 , wherein when the third gate pulse is reversed to the gate-on voltage, the gate-off voltage is reversed, and when the first gate pulse is reversed to the gate-on voltage, the gate-on voltage is reversed. According to claim 13,
The gate driver,
a first EM switch element that is turned on when a pull-up control node is charged and supplies the gate-on voltage to an output node from which the second gate pulse is output;
a second EM switch element that turns on when a pull-down control node is charged and discharges the output node;
a third EM switch element turned on according to the gate-on voltage of the first gate pulse to charge the pull-up control node;
a fourth EM switch element turned on according to the gate-on voltage of the third gate pulse to discharge the pull-up control node;
a fifth EM switch element turned on according to the gate-on voltage of the third gate pulse to charge the pull-down control node; and
and a sixth EM switch element turned on according to the gate-on voltage of the first gate pulse to discharge the pull-down control node. A display in which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power lines are disposed. panel;
a data driver supplying data voltages of pixel data to the data lines; and
a gate driver supplying a first scan pulse, a second scan pulse, a third scan pulse, a first light emission control pulse, and a second light emission control pulse to the gate lines;
Each of the pixel circuits,
a driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node;
a light emitting element driven by the current from the driving element, including an anode electrode connected to the fourth node and a cathode electrode to which a low potential power supply voltage is applied;
a first switch element that is turned on according to the gate-on voltage of the first scan pulse and supplies a data voltage to a fifth node;
a second switch element connected between the third node and the fourth node and turned off according to a gate-off voltage of a second light emission control pulse;
a third switch element that is turned on according to a gate-on voltage of a third scan pulse and supplies a reference voltage to the third node;
a fourth switch element that is turned on according to the gate-on voltage of the second scan pulse and connects the first gate electrode and the first electrode of the driving element;
a fifth switch element that is turned off according to a gate-off voltage of a first emission control pulse to block a current path between a power line to which the pixel driving voltage is applied and the first node;
a sixth switch element turned on according to the gate-on voltage of the second scan pulse to supply an initialization voltage to the fifth node;
a seventh switch element turned on according to the gate-on voltage of the third scan pulse to supply the initialization voltage to the fourth node;
a first capacitor connected between the second node and the fifth node; and
A second capacitor connected between the third node and the fifth node;
The second emission control pulse,
A gate-off voltage is generated when the second scan pulse and the third scan pulse are at the gate-on voltage, and a gate-on voltage is generated when at least one of the second scan pulse and the third scan pulse is at the gate-off voltage. or
The display device of claim 1 , wherein the gate-off voltage is generated when the second scan pulse is the gate-on voltage, and the gate-on voltage is generated when the first scan pulse is the gate-off voltage. According to claim 15,
The gate driver,
a first EM switch element including a first electrode to which the gate-on voltage is applied, a gate electrode connected to an output node to which the second emission control pulse is output, and a second electrode;
a second EM switch element for discharging the output node in response to the second scan pulse; and
and a third EM switch element for discharging the output node in response to the third scan pulse. According to claim 15,
The gate driver,
a first EM switch element that is turned on when a voltage of a pull-up control node is charged and supplies the gate-on voltage to an output node from which the second gate pulse is output;
a second EM switch element that turns on when a pull-down control node is charged and discharges the output node;
a third EM switch element turned on according to the gate-on voltage of the first scan pulse to charge the pull-up control node;
a fourth EM switch element turned on according to the gate-on voltage of the second scan pulse to discharge the pull-up control node;
a fifth EM switch element turned on according to the gate-on voltage of the second scan pulse to charge the pull-down control node; and
and a sixth EM switch element turned on according to the gate-on voltage of the first scan pulse to discharge the pull-down control node.

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