KR102625440B1 - Display panel and electroluminescence display using the same - Google Patents

Abstract

The present invention relates to a display panel and an electroluminescent display device using the same. This display panel is connected to the first data line and receives the voltage stored in the capacitor of the first data line during the first frame period, and then receives the first data voltage output from the data driver during the second frame period. pixel circuit; and a second data line connected to the second data line to directly receive the second data voltage output from the data driver during the first frame period and then receive the voltage stored in the capacitor of the second data line during the second frame period. and a second pixel circuit.

Description

Display panel and electroluminescent display device using the same {DISPLAY PANEL AND ELECTROLUMINESCENCE DISPLAY USING THE SAME}

The present invention relates to a display panel in which a demultiplexer (DEMUX) is disposed between a data driver and data lines, and an electroluminescence display device using the same.

Flat panel displays include liquid crystal displays (LCD), electroluminescence displays, field emission displays (FED), and plasma display panels (PDP).

Electroluminescent displays are divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness, and viewing angle. There is an advantage.

OLED, an organic light emitting display device, includes an organic compound layer formed between an anode and a cathode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL) may be included. When voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emitting layer (EML) to form excitons, and as a result, the emitting layer (EML) emits visible light. is released.

Each pixel of a flat panel display device is divided into a number of sub-pixels of different colors to implement color, and each of the sub-pixels includes a transistor used as a switch element or driving element. These transistors can be implemented as TFTs (Thin Film Transistors).

The driving circuit of the flat panel display device includes a data driving circuit that supplies a data signal to the data lines, a gate driving circuit that supplies a gate signal (or scan signal) to the gate lines (or scan lines), and the like. The gate driving circuit can be formed directly on the same substrate as the TFT (thin film transistor) array of pixels that make up the screen. Hereinafter, the gate driving circuit formed directly on the substrate of the display panel will be referred to as a “GIP circuit.” The GIP circuit can sequentially supply gate signals to gate lines by shifting the output using a shift register.

The organic light emitting display device includes pixel circuits arranged in each subpixel. Each of the pixel circuits includes multiple transistors. Gate signals with different waveforms may be applied to these transistors. A GIP circuit is needed equal to the number of gate signals applied to the pixel circuit. Each GIP circuit includes a shift register, and wires through which start pulses, shift clocks, etc. to control the shift register are transmitted are required.

The GIP circuit is placed in the bezel area on the display panel substrate. The bezel area is a non-display area outside the screen where an image is displayed, that is, the pixel array (active area). As the GIP circuit becomes larger, the bezel area on the display panel becomes larger, making it impossible to implement a narrow bezel.

In order to improve the image quality and lifespan of organic light emitting display devices, compensation circuits are applied to pixel circuits to compensate for differences in driving characteristics of pixels.

In the trend of high-resolution and high-speed driving of organic light emitting display devices, existing compensation methods cannot sufficiently compensate for differences in pixel driving characteristics. For example, as the resolution increases and the driving frequency increases, one horizontal period for writing data to pixels of one line in the display panel decreases. 1 horizontal period is the time to write data to pixels arranged in 1 horizontal line on the screen. The driving circuit of the organic light emitting display device samples the threshold voltage of the driving element within one horizontal period, compensates the data voltage with the threshold voltage, and writes data to the pixels. 1 As the horizontal period becomes smaller, the threshold voltage sampling period of the driving element decreases. If the time required to sample the threshold voltage of the driving element is insufficient, the threshold voltage of the driving voltage may be sensed inaccurately, resulting in differences in driving characteristics between pixels. Differences in driving characteristics between pixels may result in differences in luminance, causing spots to appear on the screen, even if data of the same gray level is written to all pixels.

The present invention uses a demultiplexer to reduce the number of channels in a data driving circuit and secure sufficient time to compensate for differences in driving characteristics of pixels, as well as a display panel that can minimize luminance differences between pixels and an electric field using the same. A light emitting display device is provided.

The display panel of the present invention includes a first data line that charges a first data voltage during a first frame period; a second data line charging a second data voltage in a second frame period; A first pixel connected to the first data line and receiving the voltage stored in the capacitor of the first data line during the first frame period, and then receiving the first data voltage output from the data driver during the second frame period. Circuit; and connected to the second data line to directly receive the second data voltage output from the data driver during the first frame period and then supply the voltage stored in the capacitor of the second data line during the second frame period. and a receiving second pixel circuit.

The electroluminescent display device of the present invention outputs a first data voltage through an output terminal in a first frame period, then outputs a second data voltage, and then outputs the second data voltage through the output terminal in a second frame period. a data driver that outputs the first data voltage after outputting it; After supplying the first data voltage to the first data line during the first frame period, supplying the second data voltage to the second data line, and then supplying the second data voltage to the second data line during the second frame period. a demultiplexer for supplying the first data voltage to the first data line; It is connected to the first data line and receives the voltage stored in the capacitor of the first data line during the first frame period, and then the output terminal of the data driver and the data line are connected through the demultiplexer during the second frame period. a first pixel circuit that receives the first data voltage output from the data driver when connected; and connected to the second data line to directly receive the second data voltage output from the data driver through the demultiplexer and the second data line for the predetermined time in the first frame period, and then and a second pixel circuit that receives the voltage stored in the capacitor of the second data line during the period.

The present invention charges the voltage of the first data signal to the first data line, stores the voltage, and then supplies the voltage of the second data signal to the second pixel and simultaneously supplies the voltage stored in the first data line to the first pixel. By sampling the threshold voltage of the driving element, the data voltage can be compensated in real time by the threshold voltage of the driving element. The present invention can secure sufficient time to sample the threshold voltage of pixels.

The present invention prevents the phenomenon in which the luminance difference between pixels is perceived by transferring the data voltage stored in the data line to the pixel circuit and by swapping at a predetermined time period by transferring the data voltage from the data driver directly to the pixel circuit. You can.

1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention.
2 and 3 are circuit diagrams showing examples of pixel circuits applicable to the present invention.
Figure 4 is a flowchart showing an example of a data line driving method using a demultiplexer.
Figure 5 is a flowchart showing a pixel driving method according to an embodiment of the present invention.
Figure 6 is a circuit diagram showing in detail pixel circuits and signal wires according to the first embodiment of the present invention.
FIG. 7 is a waveform diagram showing a method of driving the pixel circuit shown in FIG. 6.
FIG. 8 is a diagram showing signal wires connected to pixels of the Nth to N+1th lines of the display panel.
FIG. 9 is a waveform diagram showing signals applied to pixels of the Nth and N+1th lines shown in FIG. 8.
FIGS. 10A to 17B are diagrams showing step-by-step the driving method of the pixel circuit shown in FIGS. 6 and 7.
Figure 18 is a circuit diagram showing in detail pixel circuits and signal wires according to the second embodiment of the present invention.
FIG. 19 is a waveform diagram showing a method of driving the pixel circuit shown in FIG. 18.
FIG. 20 is a diagram showing signal wires connected to pixels of the Nth to N+1th lines of the display panel.
FIGS. 21A to 28B are diagrams showing step-by-step the driving method of the pixel circuit shown in FIGS. 18 and 19.
Figure 29 is a circuit diagram showing in detail pixel circuits and signal wires according to the third embodiment of the present invention.
FIG. 30 is a waveform diagram showing a method of driving the pixel circuit shown in FIG. 29.
FIGS. 31A to 40B are diagrams showing step-by-step the driving method of the pixel circuit shown in FIGS. 29 and 30.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. Only the embodiments are intended to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “comprises,” “includes,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two components is described as 'on top', 'on top', 'on the bottom', 'next to ~', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the electroluminescent display device of the present invention, the pixel circuit and the GIP circuit may include one or more of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal output from the GIP circuit swings between the gate on voltage and gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate on voltage, while the transistor is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage (Gate High Voltage, VGH), and the gate-off voltage may be the gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be the gate low voltage (VGL) and the gate-off voltage may be the gate high voltage (VGH).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings. In the following embodiments, the description will focus on an organic light emitting display device including an organic light emitting material. The technical idea of the present invention is not limited to organic light emitting display devices, but can be applied to inorganic light emitting display devices including inorganic light emitting materials.

The present invention uses a demultiplexer (DEMUX) to time-divide the data voltage output through one channel of the data driver to N (N is an even number of 2 or more) data lines. As a result of data distribution by the demultiplexer, data voltages to be applied to pixels arranged in two or more lines on the screen of the display panel are stored in capacitors connected to the data lines, and the data voltages are sampled in the data lines. The data voltage stored in the capacitors of the data lines is held until the next data is applied. Next, the present invention uses a pixel circuit to simultaneously compensate for the data voltage by the difference in the electrical characteristics of the driving elements in the pixels arranged on the two or more lines and simultaneously drive the light emitting elements (EL) of the pixels with the compensated data voltage. do.

In the present invention, N data lines are sequentially charged with a data voltage to be supplied to pixels arranged in two or more lines on a screen, and then the electrical characteristics of the pixels are simultaneously compensated. Therefore, the present invention can sufficiently secure the time required for compensation of pixels arranged in two or more lines on the screen by more than twice that of the prior art, and can secure more spare time that can be used for additional compensation or other purposes. .

Referring to FIG. 1, an electroluminescent display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit for writing data into pixels 101 of the display panel 100.

The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 that intersect the data lines 103, and pixels arranged in a matrix form.

Each pixel may be divided into red subpixel, green subpixel, and blue subpixel to implement color. Each of the pixels may further include a white subpixel. Each of the subpixels 101 includes a pixel circuit. Hereinafter, pixel may be interpreted as having the same meaning as subpixel.

The pixel circuit includes a light emitting element, a driving element, one or more switch elements, and a capacitor, such as the examples in Figures 2 and 3. The driving element and switch element can be implemented as a TFT (Thin Film Transistor). It should be noted that the pixel circuit is not limited to Figures 2 and 3. For example, Figures 2 and 3 may illustrate a pixel circuit implemented based on a p-channel TFT, but the pixel circuit may also be implemented as a pixel circuit based on a known n-channel TFT. The pixel circuit is connected to the data line 102 and the gate line 103.

As shown in FIGS. 2 and 3, the display panel 100 includes a first power line 41 for supplying a pixel driving voltage (VDD) to the subpixels 101, and a reference voltage for initializing the pixel circuit ( It may further include a second power line 42 for supplying Vref) to the subpixels 101 and a VSS electrode for supplying a low-potential power supply voltage (VSS) to the pixels. The power lines and VSS electrode are connected to a power circuit not shown.

Touch sensors may be disposed on the display panel 100. Touch input can be sensed using separate touch sensors or sensed through pixels. Touch sensors can be implemented as on-cell type or add-on type touch sensors placed on the screen of the display panel or embedded in the pixel array. You can.

The display panel driving circuit includes a data driver 110 and a gate driver 120. The display panel driving circuit further includes a demultiplexer 112 disposed between the data driver 110 and the data lines 102.

The display panel driving circuit writes data of the input image to the pixels of the display panel 100 under the control of a timing controller (TCON) 130. The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensors. The touch sensor driver is omitted in FIG. 1. In a mobile device, the display panel driving circuit, timing controller 130, and power circuit may be integrated into one integrated circuit.

The display panel driving circuit may operate in a low-speed driving mode. The low-speed driving mode can be set to analyze the input image and reduce power consumption of the display device when the input image does not change by a preset number of frames. In other words, the low-speed driving mode can reduce power consumption by controlling the data writing cycle of pixels to be long by lowering the refresh rate of pixels when a still image is input for more than a certain period of time. The low-speed drive mode is not limited to when a still image is input. For example, when the display device operates in standby mode or when a user command or input image is not input to the display panel driving circuit for more than a predetermined period of time, the display panel driving circuit may operate in a low-speed driving mode.

The data driver 110 converts the pixel data (digital data) of the input image received from the timing controller 130 every frame period into a gamma compensation voltage to generate the voltage of the data signal (hereinafter referred to as “data voltage”). do. The data driver 110 outputs a data voltage through an output buffer in each channel.

The demultiplexer 112 is disposed between the data driver 110 and the data lines 102 using a plurality of switch elements and distributes the data voltage output from the data driver 110 to the data lines 102. In FIG. 6, “AMP” represents the output buffer of the data driver 110. “S1” and “S2” represent switch elements of the demultiplexer 112. The output buffer AMP connected to one channel in the data driver 110 may be connected to neighboring data lines 21A and 21B through the demultiplexer 112, as shown in FIG. 6. The demultiplexer 112 may be formed directly on the substrate of the display panel 100 or may be integrated into one IC package together with the data driver 110.

The gate driver 120 may be implemented as a GIP circuit formed directly on the bezel area (Bezel, BZ) of the display panel 100 along with the TFT array of the pixel array. The gate driver 120 outputs a gate signal to the gate lines 103 under the control of the timing controller 130. The gate driver 120 can sequentially supply the signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signal includes scan signals (SCAN1, SCAN2) for selecting the pixels of the line where data will be written, and an emission control signal (hereinafter referred to as “EM signal”) that defines the emission time of the pixels charged with the data voltage. do.

The gate driver 120 may include a first gate driver 121 and a second gate driver 122. The first gate driver 121 outputs scan signals (SCAN1, SCAN2) and sequentially shifts the scan signals (SCAN1, SCAN2) according to the shift clock. The second gate driver 122 outputs the EM signal EM and sequentially shifts the EM signal EM according to the shift clock. In the case of a model without a bezel, switch elements constituting the first and second gate drivers 121 and 122 may be distributed in a pixel array.

The timing controller 130 receives digital video data (DATA) of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and a data enable signal (DE in FIG. 7). The host system may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, and a mobile device system.

The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel drivers 110, 112, and 120 with a frame frequency of input frame frequency × × i (i is a positive integer greater than 0) Hz. can do. The input frame frequency is 60Hz in the NTSC (National Television Standards Committee) method and 50Hz in the PAL (Phase-Alternating Line) method. The timing controller 130 may lower the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower the refresh rate of pixels in a low-speed driving mode.

The timing controller 130 provides a data timing control signal for controlling the operation timing of the data driver 110 and the operation timing of the demultiplexer 112 based on timing signals (Vsync, Hsync, DE) received from the host system. A switch control signal for controlling the operation timing of the gate driver 120 is generated. The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120. The level shifter converts the low level voltage of the gate timing control signal to the gate low voltage (VGL) and the high level voltage of the gate timing control signal to the gate high voltage (VGH). .

The timing controller 130 may change the transmission order of pixel data, the switch on/off order of the demultiplexer 112, and the output order of the gate driver 120 on a frame period basis in order to reduce the luminance difference between pixels.

2 and 3 are circuit diagrams showing examples of pixel circuits applicable to the present invention. The pixel circuits shown in FIGS. 2 and 3 are examples of an internal compensation circuit that senses the threshold voltage (Vth) of the driving element and compensates the data voltage (Vdata) by the threshold voltage (Vth). The internal compensation circuit is built into each pixel circuit and samples the threshold voltage of the driving element, which changes according to the electrical characteristics of the driving element in each pixel circuit, and compensates the data voltage in real time by the threshold voltage of the driving element. Meanwhile, it should be noted that the present invention is not limited to the pixel circuit shown in FIGS. 2 and 3. For example, the pixel circuit of the present invention can be applied as an internal compensation circuit that senses the mobility (μ) of the driving element and compensates the data voltage (Vdata) by the mobility.

Referring to FIG. 2, an example of a pixel circuit includes a light emitting element (EL), a plurality of thin film transistors (TFTs) (T1 to T5, DT), a capacitor (Cst), etc. The TFTs (T1 to T5, DT) may be implemented as p-channel TFTs (PMOS), but are not limited to this.

The switch TFTs (T1 to T5) are turned on/off according to the gate signal from the gate lines (31 to 33) to initialize the pixel circuit, then connect the source and drain of the driving TFT (DT), and then apply the data voltage. It is supplied to the capacitor (Cst). And the switch TFTs (T1 to T5) switch the current pass between the driving TFT (DT) and the light emitting device (DT). When the gate and drain of the driving TFT (DT) are connected, the driving TFT (DT) operates in the form of a diode, and the voltage between the source and gate of the driving TFT (DT) rises to the threshold voltage of the driving TFT (DT), and the capacitor (Cst) ) is sampled.

The light emitting element (EL) can be implemented as OLED. OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the fourth and fifth switch TFTs (T4 and T5) through the fourth node (n4). The cathode of the OLED is connected to the VSS electrode to which a low-potential power supply voltage (VSS) is applied. The driving TFT (DT) drives the OLED by supplying current to the OLED. OLED emits light with a current amount controlled by the driving TFT (DT) according to the data voltage (Vdata). The current path of the OLED is switched by the fourth switch TFT (T4).

The capacitor Cst is connected between the first node n1 and the second node n2. The first node n1 is connected to the second electrode of the first switch TFT (T1), the first electrode of the third switch TFT (T3), and the first electrode of the capacitor (Cst). The second node (n2) is connected to the second electrode of the capacitor (Cst), the gate of the driving element (DT), and the first electrode of the second switch TFT (T2). The compensated data voltage (Vdata) is charged to the capacitor (Cst) by the threshold voltage (Vth) of the sampled driving TFT (DT). Therefore, since the data voltage (Vdata) in each subpixel is compensated by the threshold voltage (Vth) of the driving TFT (DT), the characteristic deviation of the driving TFT in the subpixels is compensated and the driving TFT can be driven with uniform driving characteristics. .

The first switch TFT (T1) is a switch element that supplies the data voltage (Vdata) to the first node (n1) in response to the first scan signal (SCAN1). The first switch TFT (T1) includes a gate connected to the first gate line 31, a first electrode connected to the data line 21, and a second electrode connected to the first node (n1). The first scan signal SCAN1 may be simultaneously applied to pixels arranged on two lines of the pixel array through the first gate line 31. The first scan signal SCAN1 samples the threshold voltage of the driving TFT (DT) in the pixels arranged on the two lines and defines a compensation period for charging the pixels with the data voltage. The first scan signal SCAN1 may be generated as a pulse of the gate-on voltage VGL. The pulse width of the first scan signal SCAN1 may be set to 1 horizontal period (1H in FIG. 7) or less as shown in FIG. 10. Within the pulse width of the first scan signal (SCAN1), the threshold voltage of the driving TFT (DT) formed in the pixels arranged on the two lines is sampled simultaneously, and the data voltage is simultaneously charged to the pixels to write data. It can be.

The second switch TFT (T2) connects the gate of the driving TFT (DT) and the second electrode in response to the second scan signal (SCAN2), thereby causing the driving TFT (DT) to operate as a diode. The second switch TFT (T2) includes a gate connected to the second gate line 32, a first electrode connected to the second node (n2), and a second electrode connected to the third node (n3). The second scan signal SCAN2 may be simultaneously applied to pixels arranged on two lines of the pixel array through the second gate line 32. The pulse of the second scan signal SCAN2 is generated as the gate-on voltage VGL during the initialization period and compensation period of the pixels arranged on the two lines. The pulse width of the second scan signal SCAN2 may be set to 1 horizontal period (1H) or less.

The third switch TFT (T3) supplies a predetermined reference voltage (Vref) to the first node (n1) in response to the EM signal (EM) to initialize the first node (n1) to the reference voltage (Vref). The third switch TFT (T3) includes a gate connected to the third gate line 33, a first electrode connected to the first node n1, and a second electrode connected to the second power line 42. The EM signal (EM) defines the turn-on/off time of the light emitting element (EL). The EM signal EM may be simultaneously applied to pixels arranged on two lines of the pixel array through the third gate line 33. The pulse of the EM signal (EM) may be generated as a gate-off voltage to block light emission of the light emitting element (EL). The gate-off voltage (VGH) section of the EM signal (EM), that is, the pulse width section, defines the turn-off time of the light-emitting device (EL) by blocking the current path of the light-emitting device (EL). When the EM signal (EM) is the gate-on voltage (VGL), the current path of the light-emitting device (EL) is connected and the light-emitting device (EL) is turned on so that the light-emitting device (EL) may emit light.

The fourth switch TFT (T4) switches the current path of the light emitting element (EL) in response to the EM signal (EM). The gate of the fourth switch TFT (T4) is connected to the third gate line (33). The first electrode of the fourth switch TFT (T4) is connected to the third node (n3), and the second electrode of the fourth switch TFT (T4) is connected to the fourth node (n4).

The fifth switch TFT (T5) initializes the voltage of the fourth node (n4) connected to the anode of the light emitting element (EL) to the reference voltage (Vref) in response to the second scan signal (SCAN2). The fifth switch TFT (T5) includes a gate connected to the second gate line 32, a first electrode connected to the second power line 42, and a second electrode connected to the fourth node n4. The second scan signal SCAN2 may be simultaneously applied to pixels arranged on two lines of the pixel array through the second gate line 32. The reference voltage Vref is supplied to the pixels through the second power line 42.

The driving TFT (DT) is a driving element that regulates the current flowing through the light emitting element (EL) according to the gate-source voltage (Vgs). The driving TFT (DT) includes a gate connected to the second node (n2), a first electrode connected to the first power line 41, and a second electrode connected to the third node (n3). The pixel driving voltage (VDD) is supplied to the pixels through the first power line 41.

Referring to FIG. 3, another example of a pixel circuit includes a light emitting element (EL), a plurality of TFTs (T11 to T16, DT), a capacitor (Cst), etc. The TFTs (T11 to T16, DT) may be implemented as p-channel TFTs (PMOS), but are not limited to this.

The capacitor Cst is connected between the first node n1 and the second node n2. The pixel driving voltage (VDD) is supplied to the pixel circuit through the first power line 41.

The capacitor Cst is connected between the first node n1 and the second node n2. The first node n1 is connected to a power line to which the pixel driving voltage VDD is applied, the first electrode of the third switch TFT T13, and the first electrode of the capacitor Cst. The second node n2 is connected to the second electrode of the capacitor Cst, the gate of the driving element DT, and the first electrode of the fifth switch TFT T15.

The first switch TFT (T11) connects the gate of the driving TFT (DT) and the second electrode in response to the Nth (N is a positive integer) scan signal (SCAN(N)). The first switch TFT (T11) includes a gate connected to the first gate line 31, a first electrode connected to the gate of the driving TFT (DT), and a second electrode connected to the second electrode of the driving TFT (DT). . The Nth scan signal SCAN(N) is applied to the pixel circuit through the first gate line 31.

The second switch TFT (T12) applies the data voltage (Vdata) to the first electrode of the driving TFT (DT) in response to the Nth scan signal (SCAN(N)). The second switch TFT (T12) includes a gate connected to the first gate line 31, a first electrode connected to the first electrode of the driving TFT (DT), and a second electrode connected to the data line 21.

The third switch TFT (T13) applies the pixel driving voltage (VDD) to the first electrode of the driving TFT (DT) in response to the EM signal (EM1). The third switch TFT (T13) includes a gate connected to the third gate line 33, a first electrode connected to the first power line 41, and a second electrode connected to the first electrode of the driving TFT (DT). . The EM signal EM1 is applied to the pixel circuit through the first gate line 33.

The fourth switch TFT (T14) connects the second electrode of the driving TFT (DT) to the anode of the light emitting element (EL) in response to the EM signal (EM1). The gate of the fourth switch TFT (T14) is connected to the third gate line (33). The first electrode of the fourth switch TFT (T14) is connected to the second electrode of the driving TFT (DT) and the second electrode of the first switch TFT (T11), and the second electrode of the fourth switch TFT (T14) emits light. It is connected to the anode of the element (EL).

The fifth switch TFT (T15) connects the second node (n2) to the second power line 42 in response to the N-1 scan signal (SCAN(N-1)). The reference voltage Vini is applied to the pixel circuit through the second power line 42. The fifth switch TFT (T15) includes a gate connected to the second gate line 32, a first electrode connected to the second node n2, and a second electrode connected to the second power line 42.

The sixth switch TFT (T16) connects the second power line 42 to the anode of the light emitting element (EL) in response to the Nth scan signal (SCAN(N)). The sixth switch TFT (T16) includes a gate connected to the first gate line 31, a first electrode connected to the second power line 42, and a second electrode connected to the anode of the light emitting element EL.

The driving TFT (DT) controls the current flowing through the light emitting element (EL) according to the gate-source voltage (Vgs). The driving TFT (DT) includes a gate connected to the second node (n2), a first electrode connected to the first electrode of the second switch TFT (T12) and the second electrode of the third switch TFT (T13), and a first switch TFT. It includes a second electrode connected to the second electrode of (T11) and the first electrode of the fourth TFT (T14).

VDD, VSS, and Vini may be direct current voltages of VDD = 7V~8V, VSS = 0V, and Vini = 1V, but are not limited thereto. Vdata may be a voltage between 0V and 5V output from the data driver 110, but is not limited to this.

FIG. 4 is a flowchart showing an example of a data line driving method using the demultiplexer 112. FIG. 4 is a flowchart showing a driving method of sequentially charging the data voltage to the data lines 102, simultaneously supplying the data voltage to the pixels, and sampling the threshold voltage of the driving element.

Referring to FIG. 4, the demultiplexer 112 sequentially applies the data voltage from the data driver 110 to the data lines. A capacitor or parasitic capacitance is connected to the data lines. Accordingly, the data voltage applied through the demultiplexer 112 is charged to the data lines (ST401).

Subsequently, after the pixels are initialized, the data voltage charged in the data lines is simultaneously applied to the capacitors of these pixels and the threshold voltage of the driving element DT is sensed (ST402). At this time, the data voltage compensated by the threshold voltage of the driving element DT is charged in the capacitor Cst. However, this method may cause data loss as the data voltage is attenuated in the process of applying the data voltage charged to the data line to the capacitor (Cst), and after charging the data voltage to multiple data lines, the threshold voltage of the driving element is reduced. Because sampling is performed, the threshold voltage sampling time of the driving element may be insufficient. The resolution of display devices is increasing and the driving frequency of display devices is increasing. Accordingly, since one horizontal period (1H) of the display device becomes shorter, it becomes more difficult to secure the sampling time of the driving element.

The present invention solves the problem of data loss applied to the capacitor (Cst) of the pixel and the problem of securing sampling time by using the driving method as shown in FIG. 5.

Figure 5 is a flowchart showing a pixel driving method according to an embodiment of the present invention.

Referring to FIG. 5, the first data voltage is applied to the first data line through the demultiplexer 112 to charge the first data line (ST501). Subsequently, the second data voltage is directly applied to the capacitor (Cst) of the second pixel through the demultiplexer 112 and the second data line, and at the same time, the first data voltage charged in the first data line is applied to the capacitor (Cst) of the first pixel. ) is approved (ST502). At this time, since the second data voltage is applied directly to the second pixel on the second data line, the voltage does not change, while the first data voltage is charged for a predetermined time on the first data line and then is charged to the capacitor ( It may be reduced in the process of being transmitted to Cst). Therefore, even if the first data voltage and the second data voltage are the same voltage with the same gray level, a luminance difference can be perceived between the first and second pixels.

In the next frame period (ST503), the second data voltage is first applied to the second data line through the demultiplexer 112, and the second data line is charged with the second data voltage (ST504). Subsequently, the first data voltage is directly applied to the capacitor (Cst) of the first pixel through the demultiplexer 112 and the first data line, and at the same time, the second data voltage charged in the second data line is applied to the capacitor (Cst) of the second pixel. ) is applied (ST505). At this time, the first data voltage does not change because it is applied directly to the first pixel on the first data line, while the second data voltage is charged for a predetermined time on the second data line and then is charged to the capacitor (Cst) of the second pixel. ) may be reduced in the process of transmission.

The present invention changes the charging order of data voltages charged in data lines on a frame period basis. The user does not perceive the luminance difference between the pixels because the luminance of the pixels with the luminance difference changes every frame period. Therefore, the present invention can prevent the perception of a luminance difference due to asymmetric loss between data written to neighboring pixels.

In each of the embodiments of the present invention, when the data voltage stored in the capacitors (CA, CB) of the data lines (21A, 21B) is Vdata, Vdata stored in the capacitors (CA, CB) of the data lines (21A, 21B) After the voltage is transferred to the capacitor Cst of the pixel circuits 101A and 101B, the voltage of the capacitor Cst is am. Here, Cline is CA or CB. A large Cline can be helpful in terms of data transfer efficiency. When implementing Cline with the parasitic capacitance of the data lines (21A, 21B), if the parasitic capacitance of the data lines (21A, 21B) is small, data transfer efficiency decreases. In this case, data transfer efficiency can be increased by adding a separate capacitor to the data lines 21A and 21B to increase the capacitance of the data lines 21A and 21B.

In each of the embodiments of the present invention, the data driver 110 outputs the first data voltage D1 through the output terminal in the first frame period FR1 and then outputs the second data voltage D2, After outputting the second data voltage D2 through the output terminal in the second frame period FR2, the first data voltage is output. The first and second data voltages D1 and D2 are sequentially output from the data driver 110 through the same output terminal and time-divided to the first and second data lines 21A and 21B by the demultiplexer 112. do. The demultiplexer 112 supplies the first data voltage D1 to the first data line 21A in the first frame period FR1 and then supplies the second data voltage D2 to the second data line 21B. . Subsequently, the demultiplexer 112 supplies the second data voltage D2 to the second data line D2 in the second frame period FR2 and then supplies the first data voltage D1 to the first data line D1. supply.

The first pixel circuit 101A is connected to the first data line 21A and receives the voltage stored in the capacitor CA of the first data line 21A for a predetermined time in the first frame period FR1, and then receives the voltage stored in the capacitor CA of the first data line 21A. The first data voltage output from the data driver 112 during the two-frame period (FR2) is directly received without delay. After the first data voltage D1 output from the data driver 110 in the first frame period FR1 is applied to the first data line 21A, the output terminal of the data driver 110 is connected to the first data voltage D1 by the demultiplexer 112. With the first data line 21A separated, the first data voltage is stored in the capacitor CA of the first data line 21A. The first pixel circuit 101A is connected to the output terminal of the data driver 110 and the first data line 21A in the second frame period FR2 through the demultiplexer 112 and the first data line 21A. The first data voltage output from the data driver 110 is directly supplied.

The second pixel circuit 101B is connected to the second data line 21B and directly receives the second data voltage D2 output from the data driver 110 in the first frame period FR1 without delay. The voltage stored in the capacitor CB of the second data line 21B is supplied during the second frame period FR2. The second pixel circuit 101B is connected to the output terminal of the data driver 110 and the second data line 21B in the first frame period FR1 through the demultiplexer 112 and the second data line 21B. The second data voltage D2 output from the data driver 110 is directly supplied. After the second data voltage D2 output from the data driver 110 in the second frame period FR2 is applied to the second data line 21B, the output terminal of the data driver 110 is connected to the second data voltage D2 by the demultiplexer 112. In a state where the and second data lines 21B are separated, the second data voltage D2 is stored in the capacitor CB of the second data line 21B.

In the first frame period FR1, the first data voltage D1 stored in the capacitor CA of the first data line 21A is applied to the first pixel circuit 101A. In the second frame period FR2, the second data voltage D2 stored in the capacitor CB of the second data line 21B is applied to the capacitor CB of the second pixel circuit 101B.

Figure 6 is a circuit diagram showing in detail the pixel circuits 101A and 101B and signal wires according to the first embodiment of the present invention. The pixel circuits 101A and 101B shown in FIG. 6 are pixels of the Nth (N is a positive integer) line of the display panel 100. Since the first and second pixel circuits 101A and 101B shown in FIG. 6 are examples of being implemented with the pixel circuit shown in FIG. 2, a detailed description of the configuration of the pixel circuits 101A and 101B will be omitted. FIG. 7 is a waveform diagram showing a method of driving the pixel circuit shown in FIG. 6. In FIGS. 6 and 7, “Vdata” is the data voltage output from the data driver 110. D1(N) and D2(N) represent the data voltage (Vdata) of pixel data to be written in pixels of the Nth line. D1(N) is the first data voltage applied to the first pixel circuit 101A through the first data line 21A, and D2(N) is the second pixel circuit 101B through the second data line 21B. ) is the second data voltage applied to. D1(N+1) and D2(N+1) represent the data voltage (Vdata) of pixel data to be written in pixels of the N+1-th line.

One cycle of the data enable signal (DE) and the horizontal synchronization signal is one horizontal period (1H). FIG. 8 is a diagram showing signal wires connected to pixels 101 of the Nth to N+1th lines (L(N) to L(N+3)) of the display panel 100. FIG. 9 is a waveform diagram showing signals applied to pixels 101 of the Nth and N+1th lines shown in FIG. 8.

Referring to FIGS. 6 and 7 , the demultiplexer 112 includes first and second switch elements S1 and S2. Each of the switch elements S1 and S2 may be implemented with a p-channel transistor that is the same as the transistors of the pixel circuits 101A and 101B. The first switch element S1 is connected between the output terminal of the data driver 110 and the first data line 21A and is turned on according to the gate-on voltage VGL of the first switch signal DMUX1 to operate the data driver 110. The output terminal of (110) is connected to the first data line (21A). The gate of the first switch element (S1) is connected to the first DMUX line to which the first switch signal (DMUX1) is applied. The first electrode of the first switch element S1 is connected to the output terminal of the data driver 110, and the second electrode of the first switch element S1 is connected to the first data line 21A. The second switch element S2 is connected between the output terminal of the data driver 110 and the second data line 21B and is turned on according to the gate-on voltage VGL of the second switch signal DMUX2 to operate the data driver 110. The output terminal of (110) is connected to the second data line (21B). The gate of the second switch element (S2) is connected to the second DMUX line to which the second switch signal (DMUX2) is applied. The first electrode of the second switch element S2 is connected to the output terminal of the data driver 110, and the second electrode of the second switch element S2 is connected to the second data line 21B.

Pixel circuits 101A and 101B are driven with an internal compensation method. To this end, the driving period of the pixel circuits 101A and 10B is such that the data voltage to be written to any one of the first and second pixel circuits 101A and 101B is the data line every frame period FR1 and FR1. In the first section (t1) in which the first and second pixel circuits (101A and 101B) are initialized, the data in the capacitors of the first and second pixel circuits (101A and 101B) are charged. A third section (t3) for supplying voltage and sampling the threshold voltage of the driving device, and a third section (t3) in which a current path is connected to the light emitting device (EL) of the first and second pixel circuits 101A and 101B to cause the pixels to emit light. It is divided into 4 sections (t4). As shown in FIG. 7, the third section t3 may be set to be longer than the first section t1 and may be set to be longer than the combined time of the first and second sections t1 and t2. .

The first frame period (FR1) may be an odd-numbered frame period, and the second frame period (FR2) may be an even-numbered frame period, but is not limited thereto. For example, when the display panel 100 is driven at high speed, the first frame period FR1 is set to the 4N+1 and 4N+2 frame periods, and the second frame period FR2 is set to the 4N+3 and 4N+ frames. Can be set to 4 frame period.

During the first frame period FR1, after the pulse 71 of the first switch signal DMUX1 is generated in the first section t1, the pulse 72 of the second switch pulse DMUX2 is generated in the third section ( It occurs at t3). The second section t2 is set between the pulse 71 of the first switch signal DMUX1 and the pulse 72 of the second switch signal DMUX2. The pulse 71 of the first switch signal DMUX1 is synchronized with the first data voltage D1(N), and the pulse 72 of the second switch signal DMUX2 is synchronized with the second data voltage D2(N). is motivated by The pulses 71 and 72 of the switch signals (DMUX1 and DMUX2) are generated as the gate-on voltage (VGL), and the switch elements (S1 and S2) of the demultiplexer 112 turn in response to the pulses (71 and 72). -It turns on.

The pulse 72 of the second switch signal DMUX2 is set to be longer than the pulse 71 of the first switch signal DMUX1 during the first frame period FR1. The width of the pulse 71 of the first switch signal DMUX1 may be set as short as the time during which the data voltage can be transmitted to the first data line 21A, that is, t1. In comparison, the width of the pulse 72 of the second switch signal DMUX2 must be such that the data voltage can be transmitted to the capacitor Cst of the pixel circuits 101A and 101B and the threshold voltage of the driving element DT can be sampled. It must be set longer than the pulse 71 of the first switch signal (DMUX1). If the third section t3 is small, the threshold voltage Vth of the driving element DT is not properly compensated, and spots may appear in the displayed image.

In every frame period FR1, FR2, the pulse 73 of the first scan signal SCAN1(N) is generated after the pulse 74 of the second scan signal SCAN2(N). Pulses 73 and 74 of the scan signals (SCAN1(N) and SCAN2(N)) are generated with the gate-on voltage (VGL) to switch TFTs (T1, T2, and T5) of the pixel circuits (101A and 101B). is turned on in response to pulses 73 and 74 of the scan signal. The pulse 73 of the first scan signal (SCAN1(N)) is generated as the gate-on voltage (VGL) during the third period (t3), and the first scan signal (SCAN1) is generated during the remaining time except for the third period (t3). (N)) maintains the gate-off voltage (VGH). The pulse 74 of the second scan signal SCAN2(N) is generated as the gate-on voltage VGL during the second and third sections t2 and t3, and The voltage of the second scan signal SCAN2(N) maintains the gate-off voltage VGH during the remaining time.

In every frame period FR1 and FR2, the pulse 75 of the EM signal EM(N) is generated simultaneously with the pulse 73 of the first scan signal SCAN1(N). The pulse 75 of the EM signal (EM(N)) is generated at the gate-off voltage (VGH) during the third and 3-1 sections (t3, t3-1), and the third and 3-1 sections (t3) , t3-1), the voltage of the EM signal (EM(N)) is maintained at the gate-on voltage (VGL) for the remaining time. When the EM signal EM(N) is the gate-on voltage VGL, the switch TFTs T3 and T4 may be turned on. The current path of the light emitting element (EL) is switched according to the voltage level of the EM signal (EM(N)). The light emitting device EL may emit light during the fourth period t4.

Even if the pixel data to be written in the first pixel circuit 101A and the pixel data to be written in the second pixel circuit 101B have the same gray level, due to loss of the first data voltage charged first in the first data line 21A, , the luminance of the first pixel circuit 101A may be lower than that of the second pixel circuit 101B. Accordingly, the present invention changes the charging order of data voltages to be applied to pixels in the second frame period FR2 so that the user does not perceive this luminance difference.

During the second frame period FR2, after the pulse 72 of the second switch signal DMUX2 is generated in the first section t1, the pulse 71 of the first switch pulse DMUX1 is generated in the third section ( It occurs at t3). The second section t2 is set between the pulse 72 of the second switch signal DMUX2 and the pulse 71 of the first switch signal DMUX1. The pulse 72 of the second switch signal DMUX2 is synchronized with the second data voltage D2(N), and the pulse 71 of the first switch signal DMUX1 is synchronized with the first data voltage D1(N). is motivated by Pulses 71 and 72 of the switch signals DMUX1 and DMUX2 are generated as the gate-on voltage VGL. The pulse 71 of the first switch signal DMUX1 generated in the second frame period FR2 is set to be longer than the pulse 72 of the second switch signal DMUX2.

FIGS. 10A to 17B are diagrams showing a step-by-step method of driving the pixel circuits 101A and 101B shown in FIGS. 6 and 7.

10A to 13B show a method of driving neighboring pixel circuits 101A and 101B during the first frame period FR1.

The pixel driving method of the first frame period FR1 includes a first period t1 in which the first data voltage D1(N) is charged in the first data line 21A, and the first and second pixel circuits 101A. , 101B) is initialized, the data voltages D1(N) and D2(N) are simultaneously supplied and driven to the capacitors Cst of the first and second pixel circuits 101A and 101B. It is divided into a third period t3 in which the threshold voltage Vth of the elements DT is sampled, and a fourth period t4 in which the first and second pixel circuits 101A and 101B emit light. A 3-1 section (t3-1), which is a hold section, may be set between the third section (t3) and the fourth section (t4), but this section (t3-1) can be omitted.

FIG. 10A is a circuit diagram showing a current path flowing in the first section t1 in the pixel circuits 101A and 101B. FIG. 10B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the first section t1.

Referring to FIGS. 10A and 10B, the pulse 71 of the first switch signal (DMUX1) is applied to the gate of the first switch element (S1) in the first section (t1) and the first switch element (S1) turns. -It comes on. At this time, the first data voltage (D1(N)) is applied to the first data line (21A) through the first switch element (S1) and stored in the first capacitor (CA) connected to the first data line (21A). do. During the first period t1, the voltages of the second switch signal DMUX2, the first scan signal SCAN1(N), and the second scan signal SCAN2(N) are the gate-off voltage VGH, and the EM signal The voltage at (EM(N)) is the gate-on voltage (VGL).

FIG. 11A is a circuit diagram showing a current path flowing in the second section t2 in the pixel circuits 101A and 101B. FIG. 11B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the second section t2.

Referring to FIGS. 11A and 11B , the first switch signal DMUX1 is inverted to the gate-off voltage VGH in the second period t2. In the second period t2, the second scan signal SCAN2(N) is inverted to the gate-on voltage VGL. During the second period t2, the second switch signal DMUX2 and the first scan signal SCAN1(N) maintain the gate-off voltage VGH, and the EM signal EM(N) maintains the gate-on voltage ( VGL) is maintained. The second to fifth switch TFTs (T2, T3, T4, T5) are connected to the gate-on voltage (VGL) of the second scan signal (SCAN2(N)) and the EM signal (EM(N)) in the second period (t2). ) is turned on according to the At this time, in the pixel circuits 101A and 101B, the first node n1, the second node n2, and the anode of the light emitting element EL are simultaneously initialized to the reference voltage Vref.

FIG. 12A is a circuit diagram showing a current path flowing in the third section t3 in the pixel circuits 101A and 101B. FIG. 12B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the third section t3.

Referring to FIGS. 12A and 12B, in the third period t3, the second switch signal DMUX2 and the first scan signal SCAN1(N) are inverted to the gate-on voltage VGL, and the second switch element S2 ) and the first switch TFT (T1) of the pixel circuits 101A and 101B are turned on simultaneously. The EM signal EM(N) is inverted to the gate-off voltage VGH so that the light emitting element EL does not emit light in the third period t3. During the third period t3, the first switch signal DMUX1 maintains the gate-off voltage VGH, and the second scan signal SCAN2(N) maintains the gate-on voltage VGL. During the third period t3, the first, second, and fifth switch TFTs T1, T2, and T5 are operated according to the gate-on voltage VGL of the scan signals SCAN1(N) and SCAN2(N). Turns on. At this time, the second data voltage D2(N) is transmitted to the first node of the second pixel circuit 101B through the second data line 21B and the first switch TFT (T1) of the second pixel circuit 101B. It is applied to (n1). At the same time, the first data voltage D1(N) stored in the first capacitor CA of the first data line 21A is transmitted to the first pixel through the first switch TFT T1 of the first pixel circuit 101A. It is applied to the first node (n1) of the circuit 101A. During the third period t3, the driving TFT DT is turned on in the pixel circuits 101A and 101B. In each of the pixel circuits 101A and 101B, a data voltage obtained by compensating the threshold voltage (Vth) of the driving element (DT) is stored in the capacitor (Cst) in the third period (t3).

The first data voltage D1(N) applied to the capacitor Cst of the first pixel circuit 101A in the third period t3 may be reduced due to the capacitors CA and Cst. On the other hand, since the second data voltage D2(N) is applied directly to the capacitor Cst of the second pixel circuit 101B, there is no loss.

The voltage applied to both ends of the capacitor Cst of the pixel circuits 101A and 101B during the third period t3 is shown in Table 1 below. In Table 1, “Vdata” is the data voltage.

During the 3-1 period t3-1, main nodes of the pixel circuits 101A and 101B are floating. In the 3-1st period (t3-1), the scan signals (SCAN1(N), SCAN2(N)) are inverted to the gate-off voltage (VGH), and the EM signal (EM(N)) is inverted to the gate-off voltage (VGH). ) is maintained. At this time, the pixel circuits 101A and 101B of the N-th line maintain the third section state. During the 3-1 section (t3-1), pulses 71 and 72 of the first and second switch control signals (DMUX1 and DMUX2) and scan signals (SCAN1 (N+1) and SCAN2 (N+1) ) is applied to the pixel circuits of the N+1 line (L(N+1)) and pixel data is written.

delete

Meanwhile, during the 3-1 period t3-1, the capacitor Cst and the driving element DT of the pixel circuits 101A and 101B may float and the voltage of the capacitor may change. In order to prevent this phenomenon, the present invention changes the scan signals (SCAN1(N), SCAN2(N)) to the gate-off voltage (VGL) and simultaneously changes the EM signal (EM'(N)) to the gate-on voltage (VGL). ) can be inverted.

FIG. 13A is a circuit diagram showing a current path flowing in the fourth section t4 in the pixel circuits 101A and 101B. FIG. 13B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the fourth section (t4).

Referring to FIGS. 13A and 13B, in the fourth period t4, the scan signals SCAN1(N) and SCAN2(N) maintain the gate-off voltage VGH, and the EM signal EM(N) maintains the gate-off voltage VGH. The gate-on voltage VGL is inverted and the third and fourth switch TFTs T3 and T4 are turned on. During the fourth period t4, a current pass between the power line to which the pixel driving voltage VDD is applied and the light emitting device EL may flow, causing the light emitting device EL to emit light. At this time, the current (I _OLED ) flowing through the light emitting device may vary in the first and second pixel circuits 101A and 101B due to a difference in the data voltage applied to the storage (Cst) in the third period (t3). . Table 2 below shows the current I _OLED flowing through the light emitting device EL of the pixel circuits 101A and 101B in the fourth period t4. In Table 2, μ is the mobility of electrons in MOSFET (Metal-Oxide-Semiconductor FET). Cox is the capacitance of the gate oxide film. W is the channel width of the MOSFET, and L is the channel length.

I _OLED of the first pixel circuit 101A I _OLED of the second pixel circuit 101B

As shown in Table 2, if a current difference in the light emitting element (EL) occurs between pixels and this luminance difference is fixed for a time longer than a human perception time, the user can perceive the luminance difference between pixels. The present invention inverts the luminance difference between pixels in a time unit at which a person cannot perceive the luminance difference between neighboring pixels.

14A to 17B show a method of driving neighboring pixel circuits 101A and 101B during the second frame period FR2.

The pixel driving method of the second frame period FR2 includes a first period t1 in which the second data voltage D2(N) is charged in the second data line 21B, and the first and second pixel circuits 101A. , 101B) is initialized, the data voltages D1(N) and D2(N) are simultaneously supplied and driven to the capacitors Cst of the first and second pixel circuits 101A and 101B. It is divided into a third period t3 in which the threshold voltage Vth of the elements DT is sampled, and a fourth period t4 in which the first and second pixel circuits 101A and 101B emit light. A 3-1 section (t3-1), which is a hold section, may be set between the third section (t3) and the fourth section (t4), but this section (t3-1) can be omitted.

Referring to FIGS. 14A and 14B, the pulse 72 of the second switch signal DMUX2 is applied to the gate of the second switch element S2 in the first period t1, so that the second switch element S2 turns. -It comes on. At this time, the second data voltage (D2(N)) is applied to the second data line (21B) through the second switch element (S2) and stored in the second capacitor (CB) connected to the second data line (21B). do. During the first period t1, the voltages of the first switch signal DMUX1, the first scan signal SCAN1(N), and the second scan signal SCAN2(N) are the gate-off voltage VGH, and the EM signal The voltage at (EM(N)) is the gate-on voltage (VGL).

FIG. 15A is a circuit diagram showing a current path flowing in the second section t2 in the pixel circuits 101A and 101B. FIG. 15B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the second section (t2).

Referring to FIGS. 15A and 15B, the second switch signal DMUX2 is inverted to the gate-off voltage VGH in the second period t2. In the second period t2, the second scan signal SCAN2(N) is inverted to the gate-on voltage VGL. During the second period t2, the first switch signal DMUX1 and the first scan signal SCAN1(N) maintain the gate-off voltage VGH, and the EM signal EM(N) maintains the gate-on voltage ( VGL) is maintained. The second to fifth switch TFTs (T2, T3, T4, T5) are connected to the gate-on voltage (VGL) of the second scan signal (SCAN2(N)) and the EM signal (EM(N)) in the second period (t2). ) is turned on according to the At this time, in the pixel circuits 101A and 101B, the first node n1, the second node n2, and the anode of the light emitting element EL are simultaneously initialized to the reference voltage Vref.

FIG. 16A is a circuit diagram showing a current path flowing in the third section t3 in the pixel circuits 101A and 101B. FIG. 16B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the third section t3.

16A and 16B, in the third period t3, the first switch signal DMUX1 and the first scan signal SCAN1(N) are inverted to the gate-on voltage VGL, and the first switch element S1 ) and the first switch TFT (T1) of the pixel circuits 101A and 101B are turned on simultaneously. The EM signal EM(N) is inverted to the gate-off voltage VGH so that the light emitting element EL does not emit light in the third period t3. During the third period t3, the second switch signal DMUX2 maintains the gate-off voltage VGH, and the second scan signal SCAN2(N) maintains the gate-on voltage VGL. During the third period t3, the first, second, and fifth switch TFTs T1, T2, and T5 are operated according to the gate-on voltage VGL of the scan signals SCAN1(N) and SCAN2(N). Turns on. At this time, the first data voltage D1(N) is transmitted to the first node of the first pixel circuit 101A through the first data line 21A and the first switch TFT (T1) of the first pixel circuit 101A. It is applied to (n1). At the same time, the second data voltage D2(N) stored in the second capacitor CB of the second data line 21B is transmitted to the second pixel through the first switch TFT T1 of the second pixel circuit 101B. It is applied to the first node (n1) of the circuit 101B. During the third period t3, the driving TFT DT is turned on in the pixel circuits 101A and 101B. In each of the pixel circuits 101A and 101B, a data voltage obtained by compensating the threshold voltage (Vth) of the driving element (DT) is stored in the capacitor (Cst) in the third period (t3).

The second data voltage D2(N) applied to the capacitor Cst of the second pixel circuit 101B in the third period t3 may be reduced due to the capacitors CB and Cst. On the other hand, since the first data voltage D1(N) is applied directly to the capacitor Cst of the first pixel circuit 101A, there is no loss.

The voltage applied to both ends of the capacitor Cst of the pixel circuits 101A and 101B during the third period t3 is shown in Table 3 below.

During the 3-1 period t3-1, main nodes of the pixel circuits 101A and 101B are floating. In the 3-1st period (t3-1), the scan signals (SCAN1(N), SCAN2(N)) are inverted to the gate-off voltage (VGH), and the EM signal (EM(N)) is inverted to the gate-off voltage (VGH). ) is maintained. At this time, the pixel circuits 101A and 101B of the N-th line maintain the third section state. During the 3-1 section (t3-1), pulses 71 and 72 of the first and second switch control signals (DMUX1 and DMUX2) and scan signals (SCAN1 (N+1) and SCAN2 (N+1) ) is applied to the pixel circuits of the N+1 line (L(N+1)) and pixel data is written.

delete

FIG. 17A is a circuit diagram showing a current path flowing in the fourth section t4 in the pixel circuits 101A and 101B. FIG. 17B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the fourth section (t4).

Referring to FIGS. 17A and 17B, in the fourth period t4, the scan signals SCAN1(N) and SCAN2(N) maintain the gate-off voltage VGH, and the EM signal EM(N) maintains the gate-off voltage VGH. The gate-on voltage VGL is inverted and the third and fourth switch TFTs T3 and T4 are turned on. During the fourth period t4, a current pass between the power line to which the pixel driving voltage VDD is applied and the light emitting device EL may flow, causing the light emitting device EL to emit light. At this time, the current (I _OLED ) flowing through the light emitting device may vary in the first and second pixel circuits 101A and 101B due to a difference in the data voltage applied to the storage (Cst) in the third period (t3). . Table 4 below shows the current I _OLED flowing through the light emitting device EL of the pixel circuits 101A and 101B in the fourth period t4.

IOLED of first pixel circuit 101A IOLED of second pixel circuit 101B

Figure 18 is a circuit diagram showing in detail the pixel circuits 101A and 101B and signal wires according to the second embodiment of the present invention. FIG. 19 is a waveform diagram showing a driving method of the pixel circuits 101A and 101B shown in FIG. 18. The waveform shown in FIG. 19 is substantially the same as that in FIG. 7. FIG. 20 is a diagram showing signal wires connected to pixels of the Nth to N+1th lines (L(N) to L(N+3)) of the display panel 100. In the description of the second embodiment of the present invention, detailed description of structures and functions that are substantially the same as those of the first embodiment described above will be omitted.

The second embodiment of the present invention simultaneously writes data voltages to the upper and lower neighboring pixel circuits 101A and 101B. In the second embodiment of the present invention, after charging the first data voltage in the first data line connected to the first pixel circuit 101A, the second data voltage is applied to the capacitor Cst of the second pixel circuit 101B. At the same time, the first data voltage charged in the first data line is applied to the capacitor Cst of the first pixel circuit 101A. Therefore, in the second embodiment of the present invention, as the gate lines 31, 32, and 33 are shared in the first and second pixel circuits 101A and 101B that are adjacent above and below, as shown in FIG. 20, the gate lines 31, 32, and 33 are shared. By minimizing the circuit area of the driver 120, a narrow bezel of the display device can be implemented.

18 and 19, during the first frame period FR1, after the pulse 71 of the first switch signal DMUX1 is generated in the first section t1, the pulse 71 of the second switch pulse DMUX2 A pulse 72 is generated in the third section t3. The second section t2 is set between the pulse 71 of the first switch signal DMUX1 and the pulse 72 of the second switch signal DMUX2. The pulse 71 of the first switch signal DMUX1 is synchronized with the first data voltage D1(N), and the pulse 72 of the second switch signal DMUX2 is synchronized with the second data voltage D2(N). is motivated by

During the second frame period FR2, after the pulse 72 of the second switch signal DMUX2 is generated in the first section t1, the pulse 71 of the first switch pulse DMUX1 is generated in the third section ( It occurs at t3). The second section t2 is set between the pulse 72 of the second switch signal DMUX2 and the pulse 71 of the first switch signal DMUX1. The pulse 72 of the second switch signal DMUX2 is synchronized with the second data voltage D2(N), and the pulse 71 of the first switch signal DMUX1 is synchronized with the first data voltage D1(N). is motivated by

In every frame period FR1, FR2, the pulse 73 of the first scan signal SCAN1(N) is generated after the pulse 74 of the second scan signal SCAN2(N). Pulses 73 and 74 of the scan signals (SCAN1(N) and SCAN2(N)) are generated with the gate-on voltage (VGL) to switch TFTs (T1, T2, and T5) of the pixel circuits (101A and 101B). is turned on in response to pulses 73 and 74 of the scan signal. The pulse 73 of the first scan signal (SCAN1(N)) is generated as the gate-on voltage (VGL) during the third period (t3), and the first scan signal (SCAN1) is generated during the remaining time except for the third period (t3). (N)) maintains the gate-off voltage (VGH). The pulse 74 of the second scan signal SCAN2(N) is generated as the gate-on voltage VGL during the second and third sections t2 and t3, and The voltage of the second scan signal SCAN2(N) maintains the gate-off voltage VGH during the remaining time.

In every frame period FR1 and FR2, the pulse 75 of the EM signal EM(N) is generated simultaneously with the pulse 73 of the first scan signal SCAN1(N). The pulse 75 of the EM signal (EM(N)) is generated at the gate-off voltage (VGH) during the third and 3-1 sections (t3, t3-1), and the third and 3-1 sections (t3) , t3-1), the voltage of the EM signal (EM(N)) is maintained at the gate-on voltage (VGL) for the remaining time. When the EM signal EM(N) is the gate-on voltage VGL, the switch TFTs T3 and T4 may be turned on. The current path of the light emitting element (EL) is switched according to the voltage level of the EM signal (EM(N)). The light emitting device EL may emit light during the fourth period t4.

FIGS. 21A to 28B are diagrams showing a step-by-step method of driving the pixel circuits 101A and 101B shown in FIGS. 18 and 19.

21A to 24B show a method of driving neighboring pixel circuits 101A and 101B during the first frame period FR1.

FIG. 21A is a circuit diagram showing a current path flowing in the first section t1 in the pixel circuits 101A and 101B. FIG. 21B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the first section t1.

Referring to FIGS. 21A and 21B, the pulse 71 of the first switch signal (DMUX1) is applied to the gate of the first switch element (S1) in the first period (t1), so that the first switch element (S1) turns. -It comes on. At this time, the first data voltage (D1(N)) is applied to the first data line (21A) through the first switch element (S1) and stored in the first capacitor (CA) connected to the first data line (21A). do. During the first period t1, the voltages of the second switch signal DMUX2, the first scan signal SCAN1(N), and the second scan signal SCAN2(N) are the gate-off voltage VGH, and the EM signal The voltage at (EM(N)) is the gate-on voltage (VGL).

FIG. 22A is a circuit diagram showing a current path flowing in the second section t2 in the pixel circuits 101A and 101B. Figure 22b is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the second section (t2).

Referring to FIGS. 22A and 22B, the first switch signal DMUX1 is inverted to the gate-off voltage VGH in the second period t2. In the second period t2, the second scan signal SCAN2(N) is inverted to the gate-on voltage VGL. During the second period t2, the second switch signal DMUX2 and the first scan signal SCAN1(N) maintain the gate-off voltage VGH, and the EM signal EM(N) maintains the gate-on voltage ( VGL) is maintained. The second to fifth switch TFTs (T2, T3, T4, T5) are connected to the gate-on voltage (VGL) of the second scan signal (SCAN2(N)) and the EM signal (EM(N)) in the second period (t2). ) is turned on according to the At this time, in the pixel circuits 101A and 101B, the first node n1, the second node n2, and the anode of the light emitting element EL are simultaneously initialized to the reference voltage Vref.

FIG. 23A is a circuit diagram showing a current path flowing in the third section t3 in the pixel circuits 101A and 101B. FIG. 23B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the third section t3.

23A and 23B, in the third period t3, the second switch signal DMUX2 and the first scan signal SCAN1(N) are inverted to the gate-on voltage VGL, and the second switch element S2 ) and the first switch TFT (T1) of the pixel circuits 101A and 101B are turned on simultaneously. The EM signal EM(N) is inverted to the gate-off voltage VGH so that the light emitting element EL does not emit light in the third period t3. During the third period t3, the first switch signal DMUX1 maintains the gate-off voltage VGH, and the second scan signal SCAN2(N) maintains the gate-on voltage VGL. During the third period t3, the first, second, and fifth switch TFTs T1, T2, and T5 are operated according to the gate-on voltage VGL of the scan signals SCAN1(N) and SCAN2(N). Turns on. At this time, the second data voltage D2(N) is transmitted to the first node of the second pixel circuit 101B through the second data line 21B and the first switch TFT (T1) of the second pixel circuit 101B. It is applied to (n1). At the same time, the first data voltage D1(N) stored in the first capacitor CA of the first data line 21A is transmitted to the first pixel through the first switch TFT T1 of the first pixel circuit 101A. It is applied to the first node (n1) of the circuit 101A. During the third period t3, the driving TFT DT is turned on in the pixel circuits 101A and 101B. In each of the pixel circuits 101A and 101B, a data voltage obtained by compensating the threshold voltage (Vth) of the driving element (DT) is stored in the capacitor (Cst) in the third period (t3).

The voltage applied to both ends of the capacitor Cst of the pixel circuits 101A and 101B during the third period t3 is shown in Table 1.

During the 3-1 period t3-1, main nodes of the pixel circuits 101A and 101B are floating. In the 3-1st period (t3-1), the scan signals (SCAN1(N), SCAN2(N)) are inverted to the gate-off voltage (VGH), and the EM signal (EM(N)) is inverted to the gate-off voltage (VGH). ) is maintained. At this time, the pixel circuits 101A and 101B of the N-th line maintain the third section state.

FIG. 24A is a circuit diagram showing a current path flowing in the fourth section t4 in the pixel circuits 101A and 101B. FIG. 24B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the fourth section (t4).

24A and 24B, in the fourth period t4, the scan signals SCAN1(N) and SCAN2(N) maintain the gate-off voltage VGH, and the EM signal EM(N) maintains the gate-off voltage VGH. The gate-on voltage VGL is inverted and the third and fourth switch TFTs T3 and T4 are turned on. During the fourth period t4, a current pass between the power line to which the pixel driving voltage VDD is applied and the light emitting device EL may flow, causing the light emitting device EL to emit light. At this time, the current (I _OLED ) flowing through the light emitting device (EL) of the first and second pixel circuits 101A and 101B is shown in Table 2.

As shown in Table 2, if a current difference in the light emitting element (EL) occurs between pixels and this luminance difference is fixed for a time longer than a human perception time, the user can perceive the luminance difference between pixels. The present invention inverts the luminance difference between pixels in a time unit at which a person cannot perceive the luminance difference between neighboring pixels.

25A to 28B show a method of driving neighboring pixel circuits 101A and 101B during the second frame period FR2.

Referring to FIGS. 25A and 25B, the pulse 72 of the second switch signal DMUX2 is applied to the gate of the second switch element S2 in the first period t1, so that the second switch element S2 turns. -It comes on. At this time, the second data voltage (D2(N)) is applied to the second data line (21B) through the second switch element (S2) and stored in the second capacitor (CB) connected to the second data line (21B). do. During the first period t1, the voltages of the first switch signal DMUX1, the first scan signal SCAN1(N), and the second scan signal SCAN2(N) are the gate-off voltage VGH, and the EM signal The voltage at (EM(N)) is the gate-on voltage (VGL).

FIG. 26A is a circuit diagram showing a current path flowing in the second section t2 in the pixel circuits 101A and 101B. Figure 26b is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the second section (t2).

Referring to FIGS. 26A and 26B, the second switch signal DMUX2 is inverted to the gate-off voltage VGH in the second period t2. In the second period t2, the second scan signal SCAN2(N) is inverted to the gate-on voltage VGL. During the second period t2, the first switch signal DMUX1 and the first scan signal SCAN1(N) maintain the gate-off voltage VGH, and the EM signal EM(N) maintains the gate-on voltage ( VGL) is maintained. The second to fifth switch TFTs (T2, T3, T4, T5) are connected to the gate-on voltage (VGL) of the second scan signal (SCAN2(N)) and the EM signal (EM(N)) in the second period (t2). ) is turned on according to the At this time, in the pixel circuits 101A and 101B, the first node n1, the second node n2, and the anode of the light emitting element EL are simultaneously initialized to the reference voltage Vref.

FIG. 27A is a circuit diagram showing a current path flowing in the third section t3 in the pixel circuits 101A and 101B. FIG. 27B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the third section t3.

27A and 27B, in the third period t3, the first switch signal DMUX1 and the first scan signal SCAN1(N) are inverted to the gate-on voltage VGL, and the first switch element S1 ) and the first switch TFT (T1) of the pixel circuits 101A and 101B are turned on simultaneously. In the third period t3, the EM signal EM(N) is inverted to the gate-off voltage VGH. During the third period t3, the second switch signal DMUX2 maintains the gate-off voltage VGH, and the second scan signal SCAN2(N) maintains the gate-on voltage VGL. During the third period t3, the first, second, and fifth switch TFTs T1, T2, and T5 are operated according to the gate-on voltage VGL of the scan signals SCAN1(N) and SCAN2(N). Turns on. At this time, the first data voltage D1(N) is transmitted to the first node of the first pixel circuit 101A through the first data line 21A and the first switch TFT (T1) of the first pixel circuit 101A. It is applied to (n1). At the same time, the second data voltage D2(N) stored in the second capacitor CB of the second data line 21B is transmitted to the second pixel through the first switch TFT T1 of the second pixel circuit 101B. It is applied to the first node (n1) of the circuit 101B. During the third period t3, the driving TFT DT is turned on in the pixel circuits 101A and 101B. In each of the pixel circuits 101A and 101B, a data voltage obtained by compensating the threshold voltage (Vth) of the driving element (DT) is stored in the capacitor (Cst) in the third period (t3).

The second data voltage D2(N) applied to the capacitor Cst of the second pixel circuit 101B in the third period t3 may be reduced due to the capacitors CB and Cst. On the other hand, since the first data voltage D1(N) is applied directly to the capacitor Cst of the first pixel circuit 101A, there is no loss.

The voltage applied to both ends of the capacitor Cst of the pixel circuits 101A and 101B during the third period t3 is shown in Table 3.

During the 3-1 period t3-1, main nodes of the pixel circuits 101A and 101B are floating. In the 3-1st period (t3-1), the scan signals (SCAN1(N), SCAN2(N)) are inverted to the gate-off voltage (VGH), and the EM signal (EM(N)) is inverted to the gate-off voltage (VGH). ) is maintained. At this time, the pixel circuits 101A and 101B of the N-th line maintain the third section state.

FIG. 28A is a circuit diagram showing a current path flowing in the fourth section t4 in the pixel circuits 101A and 101B. FIG. 28B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the fourth section (t4).

Referring to FIGS. 28A and 28B, in the fourth period t4, the scan signals SCAN1(N) and SCAN2(N) maintain the gate-off voltage VGH, and the EM signal EM(N) maintains the gate-off voltage VGH. The gate-on voltage VGL is inverted and the third and fourth switch TFTs T3 and T4 are turned on. During the fourth period t4, a current pass between the power line to which the pixel driving voltage VDD is applied and the light emitting device EL may flow, causing the light emitting device EL to emit light. At this time, the current (I _OLED ) flowing through the light emitting device is connected to the first and second pixel circuits 101A and 101B due to the difference in the data voltage applied to the storage (Cst) in the third section (t3) as shown in Table 4. may vary from

Figure 29 is a circuit diagram showing in detail pixel circuits and signal wires according to the third embodiment of the present invention. Detailed descriptions of components that are substantially the same as those of the embodiments described above in FIG. 29 will be omitted. FIG. 30 is a waveform diagram showing a method of driving the pixel circuit shown in FIG. 29.

29 and 30, the demultiplexer 112 includes first and second switch elements S1 and S2. Each of the switch elements S1 and S2 may be implemented with a p-channel transistor that is the same as the transistors of the pixel circuits 101A and 101B. The first switch element S1 is turned on according to the gate-on voltage VGL of the first switch signal DMUX1 and connects the output terminal of the data driver 110 to the first data line 21A. The second switch element S2 is turned on according to the gate-on voltage VGL of the second switch signal DMUX2 and connects the output terminal of the data driver 110 to the second data line 21B.

During the first frame period FR1, after the pulse 71 of the first switch signal DMUX1 is generated in the third section t3, the pulse 72 of the second switch pulse DMUX2 is generated in the fourth section ( It occurs at t4). The pulse 71 of the first switch signal DMUX1 is synchronized with the first data voltage D1(N), and the pulse 72 of the second switch signal DMUX2 is synchronized with the second data voltage D2(N). is motivated by

The pulse 72 of the second switch signal DMUX2 is set to be longer than the pulse 71 of the first switch signal DMUX1 during the first frame period FR1. The width of the pulse 71 of the first switch signal DMUX1 may be set as short as the time during which the data voltage can be transmitted to the first data line 21A, that is, t1. In comparison, the width of the pulse 72 of the second switch signal DMUX2 must be such that the data voltage can be transmitted to the capacitor Cst of the pixel circuits 101A and 101B and the threshold voltage of the driving element DT can be sampled. It must be set longer than the pulse 71 of the first switch signal (DMUX1).

In every frame period (FR1, FR2), the pulse 73 of the N-1th scan signal (SCAN(N-1)) is followed by the pulse 74 of the Nth scan signal (SCAN(N)). The pulse 73 of the N-1 scan signal (SCAN(N-1)) is synchronized with the data voltage applied to the pixel circuits of the N-1th line (not shown). The pulse 73 is synchronized with the second data voltage D2(N) to be applied to the second pixel circuit 101B disposed on the N-th line L(N) in the first frame period FR1. . The pulse 73 of the Nth scan signal (SCAN(N)) is a first data voltage to be applied to the first pixel circuit 101A disposed on the Nth line (L(N)) in the second frame period (FR2). It is synchronized to (D1(N))). Pulses 73 and 74 of the scan signals (SCAN1(N) and SCAN2(N)) are generated with the gate-on voltage (VGL) to switch TFTs (T1, T2, T5, T6) is turned on in response to pulses 73 and 74 of the scan signal. The pulse 73 of the N-1 scan signal (SCAN(N-1)) is generated as the gate-on voltage (VGL) during the second period (t2), and the N-th pulse is generated during the remaining time except for the second period (t2). The voltage of the -1 scan signal (SCAN(N-1)) maintains the gate-off voltage (VGH). The pulse 74 of the Nth scan signal (SCAN(N)) is generated as the gate-on voltage (VGL) during the fourth period (t4), and the Nth scan signal (SCAN(N)) is generated during the remaining time except for the fourth period (t4). (N)) maintains the gate-off voltage (VGH). The third section t3 is set between the pulse 73 of the N-1th scan signal SCAN(N-1) and the pulse 74 of the Nth scan signal SCAN(N).

In every frame period (FR1, FR2), the pulse 75 of the EM signal (EM(N)) is approximately one horizontal period (1H) longer than the pulse 73 of the N-1th scan signal (SCAN1(N-1)). ) is previously generated as the gate-off voltage (VGH). The pulse 75 of the EM signal (EM(N)) is generated as a gate-off voltage (VGH) during the first to fourth-1 sections (t1 to t4-1), and the first to fourth-1 sections (t1) The voltage of the EM signal (EM(N)) is maintained at the gate-on voltage (VGL) during the remaining time (t5) except for ~ t4-1). When the EM signal EM(N) is the gate-on voltage VGL, the switch TFTs T3 and T4 may be turned on. The current path of the light emitting element (EL) is switched according to the voltage level of the EM signal (EM(N)). The light emitting element EL may be connected to a current path and emit light during the fifth period t5.

During the second frame period FR2, after the pulse 72 of the second switch signal DMUX2 is generated in the third section t3, the pulse 71 of the first switch pulse DMUX1 is generated in the fourth section ( It occurs at t4). The pulse 72 of the second switch signal DMUX2 is synchronized with the second data voltage D2(N), and the pulse 71 of the first switch signal DMUX1 is synchronized with the first data voltage D1(N). is motivated by Pulses 71 and 72 of the switch signals DMUX1 and DMUX2 are generated as the gate-on voltage VGL. The pulse 71 of the first switch signal DMUX1 generated in the second frame period FR2 is set to be longer than the pulse 72 of the second switch signal DMUX2.

FIGS. 31A to 40B are diagrams showing step-by-step the driving method of the pixel circuit shown in FIGS. 29 and 30.

31A to 35B show a method of driving neighboring pixel circuits 101A and 101B during the first frame period FR1.

The pixel driving method in the first frame period FR1 includes a first period t1 in which the current path of the light emitting element EL is blocked, a second period t2 in which the pixel circuits 101A and 101B are initialized, and a first period t2 in which the pixel circuits 101A and 101B are initialized. In the third period t3 in which the data voltage D1(N) is charged in the first data line 21A, the data voltage D1(N) is applied to the capacitor Cst of the first and second pixel circuits 101A and 101B. A fourth section (t4) that simultaneously supplies N) and D2 (N)) and samples the threshold voltage (Vth) of the driving elements (DT), and a fifth section (t4) in which the pixel circuits 101A and 101B emit light. It is divided into t5). A 4-1 section (t4-1), which is a hold section, may be set between the fourth section (t4) and the fifth section (t5), but this section (t4-1) can be omitted.

FIGS. 31A and 31B are diagrams showing a current path flowing in the first section t1 in the pixel circuits 101A and 101B.

Referring to FIGS. 31A and 31B, a pulse 75 of the EM signal EM(N) is generated at the gate-off voltage VGH in the first period t1. At this time, the third and fourth switch TFTs T13 and T14 are turned off and current is not supplied to the light emitting device EL, so the light emitting device EL does not emit light. During the first period t1, the switch control signals DMUX1 and DMUX2 and the scan signals SCAN(N-1) and SCAN(N) maintain the gate-off voltage VGH.

FIG. 32A is a circuit diagram showing a current path flowing in the second section t2 in the pixel circuits 101A and 101B. FIG. 32B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the second section t2.

Referring to FIGS. 32A and 32B, the pulse 73 of the N-1th scan signal (SCAN(N-1)) is generated at the gate-on voltage (VGL) in the second period (t2). At this time, the fifth switch TFT (T15) is turned on and the gate voltage of the capacitor (Cst) and the driving TFT (DT) are initialized to the reference voltage (Vini).

FIG. 33A is a circuit diagram showing a current path flowing in the third section t3 in the pixel circuits 101A and 101B. FIG. 33B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the third section t3.

Referring to FIGS. 33A and 33B, the pulse 71 of the first switch signal DMUX1 is applied to the gate of the first switch element S1, so that the first switch element S1 is turned on. At this time, the first data voltage D1(N) is applied to the first data line 21A through the first switch element S1 and stored in the first capacitor CA. In the third period t3, the voltage of the first capacitor CA changes from the reference voltage Vini to the data voltage Vdata. The voltage of the second capacitor CB is maintained in the initialized state (0V). During the third period t3, the voltages of the second switch signal DMUX2, the scan signals SCAN(N-1), SCAN(N), and the EM signal EM(N) are the gate-off voltage VGH. )am.

FIG. 34A is a circuit diagram showing a current path flowing in the fourth section t4 in the pixel circuits 101A and 101B. Figure 34b is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the fourth section (t4). The fourth section t4 is set longer than the third section t3 to ensure a stable threshold voltage sampling time of the driving element DT.

Referring to FIGS. 34A and 34B, the second switch signal (DMUX2) and the Nth scan signal (SCAN(N)) are inverted to the gate-on voltage (VGL) in the fourth period (t4), and the second switch element (S2) ) and the switch TFTs (T11, T12) of the pixel circuits (101A, 101B) are turned on simultaneously. In the fourth period t4, the first switch signal DMUX1, the N-1 scan signal SCAN(N-1), and the EM signal EM(N) maintain the gate-off voltage VGH. During the fourth period t4, the second data voltage D2(N) is applied to the second data line 21B, the second switch TFT T12 of the second pixel circuit 101B, the driving TFT (DT), and the second data voltage D2(N). 1 is applied to the second node (n2) of the second pixel circuit (101B) through the switch TFT (T11). At the same time, the first data voltage (D1(N)) stored in the first capacitor (CA) is applied to the second switch TFT (T12), the driving TFT (DT), and the first switch TFT ( It is applied to the second node (n2) of the first pixel circuit (101A) through T11). During the fourth period t4, the driving TFT DT is turned on in the pixel circuits 101A and 101B. In each of the pixel circuits 101A and 101B, the data voltage Vdata obtained by compensating the threshold voltage Vth of the driving element DT is stored in the capacitor Cst in the fourth period t4.

The first data voltage D1(N) applied to the capacitor Cst of the first pixel circuit 101A in the fourth period t4 may be reduced due to the capacitors CA and Cst. On the other hand, since the second data voltage D2(N) is applied directly to the capacitor Cst of the second pixel circuit 101B, there is no loss. The voltage of the first pixel circuit 101A in the fourth period t4 is And the voltage of the second pixel circuit 101B is am.

During the 4-1st period t4-1, main nodes of the pixel circuits 101A and 101B are floating. In the 4-1st section (t4-1), the Nth scan signal (SCAN(N)) is inverted to the gate-off voltage (VGH), and the EM signal (EM(N)) maintains the gate-off voltage (VGH). . At this time, the pixel circuits 101A and 101B of the N-th line maintain the fourth section state.

FIG. 35A is a circuit diagram showing a current path flowing in the fifth section t5 in the pixel circuits 101A and 101B. FIG. 35B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the fifth section t5.

Referring to FIGS. 35A and 35B, in the fifth period t5, the scan signals (SCAN(N-1), SCAN(N)) maintain the gate-off voltage (VGH), and the EM signal (EM(N) ) is inverted to the gate-on voltage (VGL) and the third and fourth switch TFTs (T13 and T14) are turned on. During the fifth period t5, a current pass between the power line to which the pixel driving voltage VDD is applied and the light emitting device EL may flow, causing the light emitting device EL to emit light. At this time, the current I _OLED flowing through the light emitting device EL is in the first and second pixel circuits 101A and 101B due to the difference in the data voltage applied to the storage Cst in the third period t3. It may vary.

Table 5 below shows the current I _OLED flowing through the light emitting device EL of the pixel circuits 101A and 101B in the fifth period t5.

I _OLED of the first pixel circuit 101A I _OLED of the second pixel circuit 101B

As shown in Table 5, if a current difference in the light emitting element (EL) occurs between pixels and this luminance difference is fixed for a time longer than a human perception time, the user can perceive the luminance difference between pixels. The present invention inverts the luminance difference between pixels in a time unit at which a person cannot perceive the luminance difference between neighboring pixels.

36A to 38B show a method of driving neighboring pixel circuits 101A and 101B during the second frame period FR2.

The pixel driving method of the second frame period FR2 includes a first period t1 in which the current path of the light emitting element EL is blocked, a second period t2 in which the pixel circuits 101A and 101B are initialized, and a second period t2 in which the pixel circuits 101A and 101B are initialized. In the third period t3 in which the data voltage D2(N) is charged in the second data line 21B, the data voltage D1( A fourth section (t4) that simultaneously supplies N) and D2 (N)) and samples the threshold voltage (Vth) of the driving elements (DT), and a fifth section (t4) in which the pixel circuits 101A and 101B emit light. It is divided into t5). A 4-1 section (t4-1), which is a hold section, may be set between the fourth section (t4) and the fifth section (t5), but this section (t4-1) can be omitted.

FIGS. 36A and 36B are diagrams showing a current path flowing in the first section t1 in the pixel circuits 101A and 101B.

Referring to FIGS. 36A and 36B, a pulse 75 of the EM signal EM(N) is generated at the gate-off voltage VGH in the first period t1. At this time, the third and fourth switch TFTs T13 and T14 are turned off and current is not supplied to the light emitting device EL, so the light emitting device EL does not emit light. During the first period t1, the switch control signals DMUX1 and DMUX2 and the scan signals SCAN(N-1) and SCAN(N) maintain the gate-off voltage VGH.

FIG. 37A is a circuit diagram showing a current path flowing in the second section t2 in the pixel circuits 101A and 101B. FIG. 37B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the second section t2.

Referring to FIGS. 37A and 37B, the pulse 73 of the N-1th scan signal (SCAN(N-1)) is generated at the gate-on voltage (VGL) in the second period (t2). At this time, the fifth switch TFT (T15) is turned on and the gate voltage of the capacitor (Cst) and the driving TFT (DT) are initialized to the reference voltage (Vini).

FIG. 38A is a circuit diagram showing a current path flowing in the third section t3 in the pixel circuits 101A and 101B. FIG. 38B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the third section t3.

Referring to FIGS. 38A and 38B, the pulse 72 of the second switch signal DMUX2 is applied to the gate of the second switch element S2, so that the second switch element S2 is turned on. At this time, the second data voltage D2(N) is applied to the second data line 21B through the second switch element S2 and stored in the second capacitor CB. In the third period t3, the voltage of the second capacitor CB changes from the reference voltage Vini to the data voltage Vdata. The voltage of the first capacitor (CA) is maintained in the initialized state (0V). During the third period t3, the voltage of the first switch signal DMUX1, the scan signals SCAN(N-1), SCAN(N), and the EM signal EM(N) is the gate-off voltage VGH. )am.

FIG. 39A is a circuit diagram showing a current path flowing in the fourth section t4 in the pixel circuits 101A and 101B. FIG. 39B is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the fourth section (t4).

Referring to FIGS. 39A and 39B, in the fourth period t4, the first switch signal (DMUX1) and the Nth scan signal (SCAN(N)) are inverted to the gate-on voltage (VGL) and the first switch element (S1) ) and the switch TFTs (T11, T12) of the pixel circuits (101A, 101B) are turned on simultaneously. In the fourth period t4, the second switch signal DMUX2, the N-1 scan signal SCAN(N-1), and the EM signal EM(N) maintain the gate-off voltage VGH. During the fourth period t4, the first data voltage D1(N) is applied to the first data line 21A, the second switch TFT T12 of the first pixel circuit 101A, the driving TFT (DT), and the first data line 21A. 1 is applied to the second node (n2) of the first pixel circuit (101A) through the switch TFT (T11). At the same time, the second data voltage (D2(N)) stored in the second capacitor (CB) is applied to the second switch TFT (T12), the driving TFT (DT), and the first switch TFT ( It is applied to the second node (n2) of the second pixel circuit (101B) through T11). During the fourth period t4, the driving TFT DT is turned on in the pixel circuits 101A and 101B. In each of the pixel circuits 101A and 101B, the data voltage Vdata obtained by compensating the threshold voltage Vth of the driving element DT is stored in the capacitor Cst in the fourth period t4.

The second data voltage D2(N) applied to the capacitor Cst of the second pixel circuit 101B in the fourth period t4 may be reduced due to the capacitors CA and Cst. On the other hand, since the first data voltage D1(N) is applied directly to the capacitor Cst of the first pixel circuit 101B, there is no loss. The voltage of the first pixel circuit 101A in the fourth period t4 is And the voltage of the second pixel circuit 101B is am.

During the 4-1st period t4-1, main nodes of the pixel circuits 101A and 101B are floating. In the 4-1st section (t4-1), the Nth scan signal (SCAN(N)) is inverted to the gate-off voltage (VGH), and the EM signal (EM(N)) maintains the gate-off voltage (VGH). . At this time, the pixel circuits 101A and 101B of the N-th line maintain the fourth section state.

FIG. 40A is a circuit diagram showing a current path flowing in the fifth section t5 in the pixel circuits 101A and 101B. Figure 40b is a waveform diagram showing the operation of the pixel circuits 101A and 101B in the fifth section (t5).

Referring to FIGS. 40A and 40B, in the fifth period t5, the scan signals (SCAN(N-1), SCAN(N)) maintain the gate-off voltage (VGH), and the EM signal (EM(N) ) is inverted to the gate-on voltage (VGL) and the third and fourth switch TFTs (T13 and T14) are turned on. During the fifth period t5, a current pass between the power line to which the pixel driving voltage VDD is applied and the light emitting device EL may flow, causing the light emitting device EL to emit light. At this time, the current I _OLED flowing through the light emitting device EL is in the first and second pixel circuits 101A and 101B due to the difference in the data voltage applied to the storage Cst in the third period t3. It may vary.

Table 6 below shows the current I _OLED flowing through the light emitting device EL of the pixel circuits 101A and 101B in the fifth period t5.

I _OLED of the first pixel circuit 101A I _OLED of the second pixel circuit 101B

In all embodiments, the pixel driving method of the present invention includes a method of transferring the data voltage stored in the data line to the capacitor of the pixel circuit, and a method of directly transferring the data voltage from the data driver to the capacitor of the pixel circuit for a predetermined period of time. For example, swap every frame. Therefore, according to the present invention, the user does not perceive the difference in luminance between pixels.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

21, 21A, 21B, 102: data lines 31~33, 103: gate lines
41, 42: power line 100: display panel
101, 101A, 101B: Pixel (pixel circuit) 110: Data driver
112: demultiplexer 120: gate driver
130: Timing controller

Claims (13)

A demultiplexer that outputs a first data voltage input from the data driver in response to a first pulse and outputs a second data voltage input from the data driver in response to a second pulse;
a first data line including a capacitor that charges the first data voltage input from the demultiplexer;
a second data line including a capacitor for charging the second data voltage input from the demultiplexer;
It is connected to the first data line and receives the voltage stored in the capacitor of the first data line during the first frame period, and then supplies the first data voltage through the demultiplexer and the first data line during the second frame period. a receiving first pixel circuit; and
It is connected to the second data line and directly receives the second data voltage through the demultiplexer and the second data line during the first frame period, and is then stored in the capacitor of the second data line during the second frame period. comprising a second pixel circuit supplied with a voltage;
A display panel wherein the widths of the first pulse and the second pulse are different from each other in each frame period. According to claim 1,
The first data voltage stored in the capacitor of the first data line is applied to the first pixel circuit during the first frame period,
A display panel in which the second data voltage stored in the capacitor of the second data line is applied to the capacitor of the second pixel circuit during the second frame period. According to claim 2,
Each of the first and second pixel circuits is
A light emitting device having an anode and a cathode;
a driving element that supplies current to the light emitting element to drive the light emitting element;
A display panel including a capacitor charged with a data voltage compensated by the threshold voltage of the driving element. According to claim 3,
After the first data voltage is charged in the capacitor of the first data line during the first section of the first frame period and the first and second pixel circuits are initialized during the second section of the first frame period, During the third section of the first frame period, the voltage stored in the capacitor of the first data line is applied to the capacitor of the first pixel circuit, and the second voltage output from the data driver is simultaneously applied to the capacitor of the second pixel circuit. After the data voltage is directly applied, a current pass is connected to the light emitting elements of the first and second pixel circuits during the fourth section of the first frame period,
After the second data voltage is charged in the capacitor of the second data line during the first section of the second frame period and the first and second pixel circuits are initialized during the second section of the second frame period, During the third section of the second frame period, the voltage stored in the capacitor of the second data line is applied to the capacitor of the second pixel circuit, and the first voltage output from the data driver is simultaneously applied to the capacitor of the first pixel circuit. After the data voltage is directly applied, a current pass is connected to the light emitting elements of the first and second pixel circuits during the fourth section of the second frame period,
During the third section of the first and second frame periods, the threshold voltage of the driving element of the first pixel circuit is sampled to the capacitor of the first pixel circuit, and the threshold voltage of the driving element of the second pixel circuit is sampled to the capacitor of the first pixel circuit. A display panel that is sampled by the capacitor of the second pixel circuit. According to claim 4,
Each of the pixel circuits is
A first switch element including a gate connected to a first gate line to which a first scan signal is applied, a first electrode connected to a data line, and a second electrode connected to the first electrode of the capacitor;
A second electrode including a gate connected to a second gate line to which a second scan signal is applied, a first electrode connected to the second electrode of the capacitor and the gate of the driving element, and a second electrode connected to the second electrode of the driving element. switch element;
a third switch element including a gate connected to a third gate line to which an emission control signal is applied, a first electrode connected to a first electrode of the capacitor, and a second electrode to which a predetermined reference voltage is applied;
a fourth switch element including a gate connected to the third gate line, a first electrode connected to the second electrode of the driving element, and a second electrode connected to the anode of the light emitting element; and
A fifth switch element including a gate connected to the second gate line, a first electrode to which the reference voltage is applied, and a second electrode connected to the anode of the light emitting element,
The switch elements are turned on according to the gate-on voltage and turned off according to the gate-off voltage,
The emission control signal, the first scan signal, and the second scan signal are the gate-off voltage during the first period,
The second scan signal is generated with the gate-on voltage during the second and third periods, and the first scan signal is generated with the gate-on voltage during the third period,
The display panel wherein the emission control signal is generated with the gate-off voltage during the second and third sections and is inverted to the gate-on voltage during the fourth section. The method of claim 4 or 5,
A display panel wherein the third section is longer than the second section. According to claim 6,
A display panel wherein the voltage of the emission control signal is the gate-off voltage when the voltage of the first and second scan signals is inverted to the gate-off voltage between the third period and the fourth period. According to claim 6,
A display panel in which the voltage of the first and second scan signals is inverted to the gate-off voltage between the third section and the fourth section and simultaneously the voltage of the emission control signal is inverted to the gate-on voltage. According to claim 3,
A current path of the light emitting device is blocked in each of the first and second pixel circuits during a first section of the first frame period, and the first and second pixel circuits are blocked during a second section of the first frame period. initialized, the first data voltage is charged to the capacitor of the first data line during the third section of the first frame period, and the first data voltage is charged to the capacitor of the first pixel circuit during the fourth section of the first frame period. At the same time as applying the voltage stored in the capacitor of the first data line, the second data voltage output from the data driver is directly applied to the capacitor of the second pixel circuit, and then the second data voltage is directly applied to the capacitor of the second pixel circuit during the fifth section of the first frame period. A current path is connected to the light emitting elements of the first and second pixel circuits,
A current path of the light emitting device is blocked in each of the first and second pixel circuits during a first section of the second frame period, and the first and second pixel circuits are blocked during a second section of the second frame period. initialized, the second data voltage is charged to the capacitor of the second data line during the third section of the second frame period, and the second data voltage is charged to the capacitor of the second pixel circuit during the fourth section of the second frame period. 2 At the same time as applying the voltage stored in the capacitor of the data line, the first data voltage output from the data driver is directly applied to the capacitor of the first pixel circuit, and then the first data voltage is applied directly to the capacitor of the first pixel circuit during the fifth section of the second frame period. A current path is connected to the light emitting elements of the first and second pixel circuits,
During the fourth section of the first and second frame periods, the threshold voltage of the driving element of the first pixel circuit is sampled to the capacitor of the first pixel circuit, and the threshold voltage of the driving element of the second pixel circuit is sampled to the capacitor of the first pixel circuit. A display panel that is sampled by the capacitor of the second pixel circuit. According to clause 9,
Each of the pixel circuits is
A first electrode including a gate connected to a first gate line to which a first scan signal is applied, a first electrode connected to the gate of the driving element and a second electrode of the capacitor, and a second electrode connected to the second electrode of the driving element. switch element;
a second switch element including a gate connected to the first gate line, a first electrode connected to a first electrode of the driving element, and a second electrode connected to a data line;
A third gate including a gate connected to a third gate line to which an emission control signal is applied, a first electrode to which a predetermined pixel driving voltage is applied and connected to the first electrode of a capacitor, and a second electrode connected to the first electrode of the driving element. switch element;
a fourth switch element including a gate connected to the third gate line, a first electrode connected to a second electrode of the driving element and a second electrode of the first switch element, and a second electrode connected to the anode of the light emitting element;
a fifth switch element including a gate connected to a second gate line to which a second scan signal is applied, a first electrode connected to a second electrode of the capacitor, and a second electrode to which a predetermined reference voltage is applied; and
A sixth switch element including a gate connected to the first gate line, a first electrode to which the reference voltage is applied, and a second electrode connected to the anode of the light emitting element,
The switch elements are turned on according to the gate-on voltage and turned off according to the gate-off voltage,
The light emission control signal is generated at the gate-off voltage during the first to fourth sections and then inverted to the gate-on voltage during the fifth section,
A display panel in which the first scan signal is generated with the gate-on voltage during the third period after the second scan signal is generated with the gate-on voltage during the second period. According to claim 10,
A display panel in which the fourth section is longer than the third section. After outputting the first data voltage through the output terminal in the first frame period, the second data voltage is output, and then after outputting the second data voltage through the output terminal in the second frame period, the first data voltage is a data driver that outputs;
After supplying the first data voltage to the first data line during the first frame period, supplying the second data voltage to the second data line, and then supplying the second data voltage to the second data line during the second frame period. a demultiplexer for supplying the first data voltage to the first data line;
It is connected to the first data line and receives the voltage stored in the capacitor of the first data line during the first frame period, and then the output terminal of the data driver and the data line are connected through the demultiplexer during the second frame period. a first pixel circuit that receives the first data voltage output from the data driver when connected; and
It is connected to the second data line and directly receives the second data voltage output from the data driver through the demultiplexer and the second data line for a predetermined time in the first frame period, and then It includes a second pixel circuit that receives the voltage stored in the capacitor of the second data line,
The demultiplexer,
a first MUX switch element that outputs the first data voltage input from the data driver in response to a first pulse; and
It includes a second MUX switch element that outputs the second data voltage input from the data driver in response to the second pulse,
An electroluminescence display device in which the widths of the first pulse and the second pulse are different from each other in each frame period.
delete

Images