KR20210144401A - Display device and driving method thereof - Google Patents

Abstract

A display device and a driving method thereof are disclosed. The display device includes: a plurality of shared scan lines connected between first and second sub-pixel arrays and shared between the first and second sub-pixels; and a plurality of divided scan lines separated at a boundary between the first and second sub-pixel arrays. Accordingly, it is possible to prevent a phenomenon in which luminance difference is recognized at the boundary between the sub-pixel arrays.

Description

Display device and its driving method

The present invention relates to a display device capable of differently controlling a driving frequency of a screen for each region without degrading image quality, and a driving method thereof.

The electroluminescent display is roughly classified into an inorganic light emitting display and an organic light emitting display according to the material of the light emitting layer. An active matrix type organic light emitting diode display includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has a fast response speed and high luminous efficiency, luminance, and viewing angle. There are advantages. In the organic light emitting display device, a light emitting diode element (referred to as "Organic Light Emitting Diode," OLED) is formed in each pixel. The organic light emitting display device has a fast response speed and excellent luminous efficiency, luminance, viewing angle, etc. Since the grayscale can be expressed as complete black, the contrast ratio and color reproduction ratio are excellent.

Pixels of the organic light emitting diode display include an OLED, a driving device that drives the OLED by controlling a current flowing through the OLED according to a gate-source voltage (Vgs), and a storage capacitor that maintains the gate voltage of the driving device.

The driving device may be implemented as a transistor. In order to make the image quality of the entire screen of the organic light emitting diode display uniform, the driving element must have uniform electrical characteristics among all pixels. However, there may be differences in electrical characteristics of driving devices between pixels due to process variations and device characteristic variations caused in the manufacturing process of the display panel, and the differences may increase as the driving time of the pixels elapses. An internal compensation technique or an external compensation technique may be applied to the organic light emitting diode display in order to compensate for variations in electrical characteristics of the driving element between pixels.

The internal compensation technology senses the threshold voltage of the driving device for each sub-pixel using an internal compensation circuit built into each pixel, and compensates the gate-source voltage (Vgs) of the driving device by the threshold voltage in real time.

The external compensation technology senses in real time the current or voltage of the driving device that changes according to the electrical characteristics of the driving device by using an external compensation circuit. The external compensation technology can compensate for the electrical characteristic deviation of the driving element in each pixel in real time by modulating the pixel data of the input image by the electric characteristic deviation of the driving element sensed for each pixel.

The user may play two or more content images on one screen or play images of different applications on the screen by executing two or more applications. In such a multi-tasking environment, the screen of the display device is driven at a single frame frequency.

In a multitasking environment, if the screen is divided and the driving frequencies of the pixels are differently driven for each region, data of the pixels may be undesirably lost or erased. Accordingly, in the prior art, it is difficult to differently control driving frequencies of pixels to which an internal compensation circuit is applied in a multi-tasking environment.

SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned needs and/or problems.

The present invention provides a display device capable of differently controlling driving frequencies of pixels for each divided region within a screen, and a driving method thereof.

The present invention provides a display device capable of reducing power consumption without degrading image quality in a multi-tasking environment, and a method of driving the same.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an embodiment of the present invention includes: a first sub-pixel array including a first group of data lines, a first group of scan lines, and a plurality of pixel circuits; and a second sub-pixel array AA2 including a second group of data lines, a second group of scan lines, and a plurality of pixel circuits.

the first group of scan lines and the second group of scan lines include a plurality of shared scan lines connected between the first and second sub-pixel arrays and shared between the first and second sub-pixels; and a plurality of divided scan lines separated at a boundary between the first and second sub-pixel arrays.

A display device according to another embodiment of the present invention includes: a first sub-pixel array driven at a first frame frequency; and a second sub-pixel array driven at a second frame frequency equal to or different from the first frame frequency.

The first and second sub-pixel arrays include a plurality of shared scan lines connected between the first and second sub-pixel arrays.

The first sub-pixel array includes a first group of divided scan lines coupled to pixels in the first sub-pixel array. The second sub-pixel array includes a second group of divided scan lines coupled to pixels in the second sub-pixel array.

In the method of driving the display device, a first image is displayed on the first sub-pixel array by driving the first sub-pixel array at a first frame frequency, and a second frame frequency equal to or different from the first frame frequency is used. A second image is displayed on the second sub-pixel array by driving the 2 sub-pixel array.

The present invention prevents data loss or erasure of pixels driven at a low frame frequency in a frame skip period by connecting a data writing scan line between sub-pixel arrays and separating an initialization scan line at a boundary between the sub-pixel arrays. It is possible to prevent a phenomenon in which a difference in luminance is recognized at the boundary between the sub-pixel arrays.

The present invention can implement frequency division driving for each area without degradation of image quality in a screen division multitasking environment.

Furthermore, according to the present invention, power consumption can be reduced by stopping the driving of the data driver without driving the sub-pixel array driven at a low frequency during the frame skip period.

Effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram illustrating a display device according to an embodiment of the present invention.
2 and 3 are diagrams illustrating an example of the arrangement of pentile pixels.
3 is a diagram illustrating an example of real pixel arrangement.
4 is a diagram schematically showing a pixel circuit of the present invention.
5A to 7B are diagrams illustrating the operation of the pixel circuit shown in FIG. 4 in stages.
8 is a flowchart illustrating a method of driving a display device according to an exemplary embodiment of the present invention.
9 is a diagram illustrating an example in which the first and second sub-pixel arrays are driven at the same frame frequency.
10 is a diagram illustrating an example in which the first and second sub-pixel arrays are driven at different frame frequencies.
11 is a diagram illustrating an example in which scan lines are shared between first and second sub-pixel arrays without being separated.
12 is a circuit diagram illustrating a phenomenon in which data of a pixel circuit driven at a low frame frequency is erased in the shared scan line structure as shown in FIG. 11 .
13 is a diagram illustrating an example in which all scan lines are separated between first and second sub-pixel arrays.
14A and 14B are waveform diagrams illustrating gate timing control signals for controlling the first gate driver and the second gate driver in the scan line structure separated as shown in FIG. 13 .
15 is a waveform diagram illustrating a scan signal applied to neighboring pixel circuits at a boundary between first and second sub-pixel arrays and a gate voltage of a driving device.
16 is a diagram illustrating an example in which an initialization scan line is separated from among scan lines between first and second sub-pixel arrays.
17A and 17B are waveform diagrams illustrating gate timing control signals for controlling the first gate driver and the second gate driver in the scan line structure separated as shown in FIG. 16 .
18 is a circuit diagram illustrating an effect of preventing erasing of a data voltage in a pixel circuit of a sub-pixel array driven at a low frame frequency in the separated scan line structure as shown in FIG. 16 .
19A to 19F are diagrams illustrating the flow of signals applied to scan lines in sections ① to ⑥ of FIG. 18 .
20 is a view showing a simulation result for verifying the power consumption improvement effect of the present invention.

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numbers regardless of reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "part" for the components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have a meaning or role distinct from each other by themselves. In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in the present specification, and the technical spirit disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

Terms including an ordinal number, such as first, second, etc., may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

When a component is referred to as being “connected” or “connected” to another component, it is understood that the other component may be directly connected or connected to the other component, but other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that no other element is present in the middle.

The singular expression includes the plural expression unless the context clearly dictates otherwise.

In the present application, terms such as "comprises" or "have" are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It should be understood that this does not preclude the existence or addition of numbers, steps, operations, components, parts, or combinations thereof.

The features of the various embodiments may be partially or wholly combined or combined with each other, and technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

The display device of the present invention may be implemented as an organic light emitting display device. The organic light emitting diode display does not require a backlight unit and may be implemented on a plastic substrate, a thin glass substrate, or a metal substrate, which are flexible materials. Accordingly, the flexible display is easily implemented as an organic light emitting display device.

In the flexible display, the size and shape of the screen may be changed by winding, folding, or bending the display panel. The flexible display may be implemented as a rollable display, a foldable display, a bendable display, a foldable display, a slideable display, and the like. Such a flexible display device can be applied to not only mobile devices such as smartphones and tablet PCs, but also TVs, automobile displays, and wearable devices, and the field of application thereof is expanding.

In the display device of the present invention, the pixel circuit and the gate driver may include a plurality of transistors. The transistors may be implemented as an oxide TFT (Thin Film Transistor) including an oxide semiconductor, an LTPS TFT including a Low Temperature Poly Silicon (LTPS), or the like. Each of the transistors may be implemented as a transistor having a p-channel metal-oxide-semiconductor field effect transistor (MOSFET) or an n-channel MOSFET structure. In the embodiment, the description will be focused on an example in which the transistors of the pixel circuit are implemented as p-channel transistors, but the present invention is not limited thereto.

A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from source to drain. In the case of the n-channel transistor, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-channel transistor, the direction of current flows from drain to source. In the case of a p-channel transistor (PMOS), since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may be changed according to an applied voltage. Accordingly, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal swings between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, while turned-off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage (hereinafter referred to as "VGH"), and the gate-off voltage may be a gate low voltage (hereinafter referred to as "VGL"). have. Hereinafter, the gate high voltage of the scan signal is referred to as VGH, and the gate high voltage of the emission control signal (hereinafter, referred to as “EM signal”) is referred to as VEL. The gate low voltage of the scan signal is referred to as VGL, and the gate low voltage of the EM signal is referred to as VEL. In the case of a p-channel transistor, VGL or VEL, and the gate-off voltage may be VGH or VEH.

In an embodiment, the switch elements of the pixel circuits and the gate drivers are turned on according to the gate-on voltage and turned off according to the gate-off voltage.

Each of the pixels of the present invention is a capacitor by sensing the threshold voltage of the driving device in a sensing step defined by a light emitting device, a driving device controlling a current flowing through the light emitting device according to a gate-source voltage, and a pulse of a scan signal. It may include an internal compensation circuit that supplies the . The internal compensation circuit may include a capacitor connected to the gate of the driving element, and switch elements connected to the capacitor and the driving element.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 3 , the display device of the present invention includes a display panel 100 and a display panel driver.

The display panel driver writes the pixel data of the input image into pixels of the screen to display the image on the screen. The display panel driver includes the first and second gate drivers 121 and 122 for supplying gate signals to the gate lines GL1 to GL2 of the display panel 100 , and pixel data to the voltage of the data signal (hereinafter, “data voltage”). The first and second data drivers 111 and 112 that are converted into " A timing controller 130 is included.

The screen of the display panel 100 is a pixel in which data lines DL1 to DL6, gate lines GL1 and GL2 crossing the data lines DL1 to DL6, and pixels P are arranged in a matrix form. Display the input image including the array. The pixels P are arranged in a pixel array in a matrix form defined by the data lines DL1 to DL6 and the gate lines GL1 and GL2.

The screen of the display panel 100 may be dividedly driven into the first and second sub-pixel arrays AA1 and AA2 . The first and second sub-pixel arrays AA1 and AA2 may divide and display pixel data of images having different frame frequencies.

Touch sensors may be disposed on the display panel 100 . The touch sensors may be implemented as in-cell type touch sensors arranged on the screen of a display panel or embedded in a pixel array as an on-cell type or an add-on type. can

Each of the pixels P includes sub-pixels having different colors for color implementation. The sub-pixels include red (hereinafter referred to as “R sub-pixel”), green (hereinafter referred to as “G sub-pixel”), and blue (hereinafter referred to as “B sub-pixel”). Although not shown, a white sub-pixel may be further included. Hereinafter, a pixel may be interpreted as a sub-pixel.

Each of the sub-pixels may include an internal compensation circuit that compensates the gate voltage of the driving device by sensing an electrical characteristic of the driving device, for example, a threshold voltage.

The pixels P may be arranged in a pixel array in various forms, such as real color pixels and pentile pixels. The pentile pixel uses a preset pentile pixel rendering algorithm to drive two sub-pixels having different colors as one pixel (P) as shown in FIG. 2 to achieve a higher resolution than a real color pixel. can be implemented The pentile pixel rendering algorithm compensates for insufficient color representation in each of the pixels P with the color of light emitted from an adjacent pixel.

In the case of a real color pixel, each of the pixels P includes R, G, and B sub-pixels as shown in FIG. 3 .

When the resolution of the pixel array is n*m, the pixel array includes n pixel columns and m pixel lines intersecting the pixel columns. The pixel column includes pixels arranged along the Y-axis direction. The pixel line includes pixels arranged along the X-axis direction. 2 and 3, #1 and #2 indicate the number of pixel lines. One horizontal period (1H) is a time obtained by dividing one frame period by the number of m pixel lines. The gate drivers 121 and 122 may sequentially output the gate signal from the first sub-pixel line to the m-th pixel line to progressively scan the pixels line by line. The internal compensation circuit of pixels includes an initialization step for initializing main nodes of the pixel circuit within one horizontal period; It can operate as a sensing step.

The pixel array of the display panel 100 may be formed on a glass substrate, a metal substrate, or a plastic substrate. In the case of a plastic OLED panel, a pixel array may be formed on a plastic substrate and implemented as a flexible panel. In the pixel array of the plastic OLED panel, an organic layer may be formed on a back plate. A touch sensor array may be disposed over the pixel array. The back plate may be a polyethylene terephthalate (PET) substrate. The back plate blocks the moisture permeation towards the organic film so that the pixel array is not exposed to humidity. The organic layer may be a thin polyimide (PI) film. A multi-layered buffer layer may be formed of an insulating material (not shown) on the organic layer. Wires for supplying power or signals applied to the pixel array and the touch sensor array may be formed on the organic layer.

The gate drivers 121 and 122 may be disposed on the substrate of the display panel 100 together with the pixel array. A gate in panel (GIP) process directly forms circuit components of the gate drivers 121 and 122 together with circuit components of a pixel array on a substrate of the display panel 100 .

The gate drivers 121 and 122 may be disposed on each of the left and right bezels of the display panel 100 to supply gate signals to the gate lines GL1 and GL2 in a single feeding method. In the double feeding method, gate signals may be simultaneously applied to both ends of one gate line. For example, the first gate driver 121 applies an N-th (N is a natural number) gate signal to one side of the N-th gate line, and the second gate driver 122 communicates with the first gate driver 121 . In synchronization, the gate signal is applied to the other side of the N-th gate line.

Each of the gate drivers 121 and 122 transmits gate signals GATE1 and GATE2 to the gate lines GL1 and GL2 in response to a gate timing control signal input from the timing controller 130 using a shift register. are supplied sequentially. The gate timing control signal may include a start pulse, a shift clock, and the like. The start pulse may be generated once at the beginning of one frame period for every frame period. The start pulse may be generated with a period of one frame period like the vertical synchronization signal. The shift register may sequentially supply the gate signals GATE1 and GATE2 to the gate lines GL1 and GL2 by shifting the start pulse to a rising edge of the shift clock. The gate signals GATE1 and GATE2 may include a scan signal and an EM signal. The gate lines GL1 and GL2 may be divided into a scan line to which a scan signal is applied and an EM line to which an EM signal is applied. The scan signal and the EM signal swing between a gate-on voltage (VGL/VEL) and a gate-off voltage (VGH/VEH).

The data drivers 111 and 112 convert the pixel data received from the timing controller 130 into a gamma compensation voltage using a digital-to-analog converter (hereinafter referred to as “DAC”) to output buffers (outputs). buffer) to output data voltages (DATA1 to DATA6). The data voltages output from the data drivers 111 and 112 are supplied to the data lines DL1 to DL6 of the pixel arrays AA1 and AA2.

The display device of the present invention may reduce power consumption by individually controlling driving frequencies of the first and second sub-pixel arrays AA1 and AA2 in a multi-tasking environment. To this end, the screen of the display panel 100 may be divided and driven into two or more screens. For example, the screen may be divided into a first sub-pixel array AA1 and a second sub-pixel array AA2 . The first sub-pixel array AA1 includes a first group of data lines, a first group of scan lines, and a plurality of pixels. The second sub-pixel array AA2 includes a second group of data lines, a second group of scan lines, and a plurality of pixels. The first group of scan lines and the second group of scan lines are connected between the first and second sub-pixel arrays AA1 and AA2 and at least one shared scan line shared between the first and second sub-pixels and at least one divided scan line separated at a boundary between the first and second sub-pixel arrays AA1 and AA2 and independently driven for each sub-pixel array. The sub-pixels of the first and second sub-pixel arrays AA1 and AA1 may be implemented with a pixel circuit having the same structure, but may be connected to divided scan lines separated from each other to be independently controlled in the initialization step. The EM lines may be connected between the first and second sub-pixel arrays to be shared in the first and second sub-pixel arrays.

In the multi-tasking environment, the first sub-pixel array AA1 may display the first content or the image of the first application. The second sub-pixel array AA2 may display an image of the second content or the second application. In a multi-tasking environment, frame frequencies of the first and second sub-pixel arrays AA1 and AA2 may be differently controlled. A frame frequency of a pixel array in which a moving image or a moving image is displayed may be higher than that of a pixel array in which a still image or an image having relatively little movement is displayed.

Each of the pixel lines #1 and #2 is shared across the first and second sub-pixel arrays AA1 and AA2 and shared in the pixel line of the first and second sub-pixel arrays AA1 and AA2. It is connected to a scan line and a divided scan line separated between the first and second sub-pixel arrays AA1 and AA2. The EM lines may be shared in the pixel line of the first and second sub-pixel arrays AA1 and AA2 across the first and second sub-pixel arrays AA1 and AA2.

The first data driver 111 supplies a data voltage of pixel data to data lines connected to the pixels P of the first sub-pixel array AA1 . The second data driver 112 supplies a data voltage of pixel data to data lines connected to the pixels P of the second sub-pixel array AA2 . Each of the first and second data drivers 111 and 112 may be implemented as one or more drive ICs.

The first gate driver 121 includes shared scan lines connected to the pixels P of the first and second sub-pixel arrays AA1 and AA2 and the pixels P of the first sub-pixel array AA1 . A scan signal is supplied to the first group of divided scan lines connected to , and an EM signal is supplied to the EM lines connected to the pixels P of the first and second sub-pixel arrays AA1 and AA2. The second gate driver 122 supplies a scan signal to the shared scan lines and a second group of divided scan lines connected to the pixels P of the second sub-pixel array AA2, and the EM lines EM signal is supplied to

The timing controller 130 transmits the pixel data of the input image received from the host system 200 to the data drivers 111 and 112 . The timing controller 130 generates a gate timing control signal for controlling the gate drivers 121 and 122 and a source timing control signal for controlling the data drivers 111 and 112 to control the data drivers 111 and 112 . ) and the operation timings of the gate drivers 121 and 122 may be controlled. A level shifter omitted from the drawing converts a low level voltage of the gate timing control signal received from the timing controller 130 into gate low voltages VGL and VEL, and A high level voltage is converted into gate high voltages VGH and VEH. The level shifter supplies a start signal swinging between the gate high voltages VGH and VEH and the gate low voltages VGL and VEL and a gate timing control signal such as a clock to the gate drivers 121 and 122 .

The power supply unit omitted from the drawing uses a DC-DC converter to the pixels P of the display panel 100 , the display panel drivers 111 , 112 , 121 , 122 , and the timing controller 130 . It generates the DC power required to drive the The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, a buck-boost converter, and the like.

The power supply unit may adjust the DC input voltage from the host system 200 to generate DC power such as a gamma reference voltage, VGL/VEL, VGH/VEH, ELVDD, ELVSS, and an initialization voltage Vini. The gamma reference voltage is divided into a gamma compensation voltage by a voltage divider circuit and supplied to the data drivers 111 and 112 . The gate voltages VGH/VEH and VGL/VEL are supplied to the level shifter and the gate drivers 121 and 122 . Pixel power, such as the pixel driving voltage ELVDD, the low potential power voltage ELVSS, and the initialization voltage Vini, is commonly supplied to the pixels P. The gate voltage may be set to VGH = 8V, VGL = -7V, and the pixel power may be set to a voltage of ELVDD = 4.6V, ELVSS = -2 to -3V, and Vini = -3 to -4V, but is not limited thereto. The data voltage Vdata may be set to Vdata = 3 to 6V, but is not limited thereto.

The initialization voltage Vini initializes the main nodes of the pixel circuit in the initialization phase of the pixels P. The initialization voltage Vini is set to a DC voltage lower than ELVDD and lower than the threshold voltage of the light emitting device to suppress light emission of the light emitting device in the initialization step and the sensing step of the pixel circuit.

The host system 200 may be any one of a television (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile system, a wearable system, and a vehicle system.

In the mobile system, the host system 200 may be implemented as an application processor (AP). The host system 200 may transmit pixel data to the timing controller 130 through a Mobile Industry Processor Interface (MIPI). In the mobile system, the timing controller 130 and the data drivers 111 and 112 may be integrated into one drive IC.

The pixel circuit may be implemented as the pixel circuit shown in FIG. 4, but is not limited thereto. The pixel circuit shown in FIG. 4 represents a pixel circuit of an arbitrary sub-pixel belonging to the N-th pixel line. The pixel circuit includes an internal compensation circuit that senses the threshold voltage Vth of the driving device DT and compensates the gate voltage of the driving device DT by the threshold voltage Vth.

As shown in FIG. 4 , the display panel includes an ELVDD line 61 for supplying ELVDD to the pixels P, an ELVSS line 62 for supplying ELVSS to the pixels P, and a pixel circuit to initialize. A Vini wiring 63 for supplying Vini to the pixels P may be included. Power lines 61 , 62 , 63 are connected to output channels of the power supply unit.

Referring to FIG. 4 , the pixel circuit includes a light emitting element EL, a plurality of transistors T11 to T16 and DT, a capacitor Cst, and the like. The transistors T11 to T16 and DT may be implemented as p-channel transistors. The transistors T11 to T16 and DT include switch elements T11 to T16 and a driving element DT. The switch elements T11 to T16 include a first switch unit 10 for initializing the gate voltages of the capacitor Cst and the driving element DT in the initialization step Ti, and the driving element (Ts) in the sensing step Ts. The second switch unit 20 senses the threshold voltage Vth of the DT) and charges the capacitor Cst with the data voltage compensated for by the threshold voltage Vth, and the ELVDD and the light emitting device EL in the light emitting step Tem. ) includes a third switch unit 30 for connecting the current path between the. The first switch unit 10 may include at least fifth and sixth switch elements T15 and T16. The second switch unit 20 may include at least first and second switch elements T11 and T12. The third switch unit 30 may include at least third and fourth switch elements T13 and T14.

The gate signal applied to the pixel circuit includes an N-1 th scan signal SCAN(N-1), an N-th scan signal SCAN(N), and an EM signal EM(N). Here, "N" is a natural number of 2 or more. The N-1 th scan signal SCAN(N-1) may be synchronized with the data voltage Vdata of the N-1 th pixel line. The Nth scan signal SCAN(N) may be synchronized with the data voltage Vdata of the Nth pixel line. The pulse of the N-th scan signal [SCAN(N)] is generated with the same pulse width as the N-1th scan signal SCAN(N-1), and the pulse of the N-1th scan signal [SCAN(N-1)] is It can be generated later than the pulse.

The capacitor Cst is connected between the first node n11 and the second node n12. ELVDD is supplied to the pixel circuit through the ELVDD wiring 61 . The first node n11 is connected to the ELVDD wiring 61 , the first electrode of the third switch element T13 , and the first electrode of the capacitor Cst. The second node n12 is connected to the second electrode of the capacitor Cst, the gate of the driving element DT, the first electrode of the first switch element T11, and the first electrode of the fifth switch element T15. do.

The first switch element T11 is turned on according to the gate-on voltage VGL of the N-th scan signal SCAN(N) to connect the gate and the second electrode of the driving element DT. The first switch element T11 includes a gate connected to the N-th scan line 125 , a first electrode connected to the second node n12 , and a second electrode connected to the third node n13 . The N-th scan signal SCAN(N) is supplied to the pixels P through the N-th scan line 125 . The third node n13 is connected to the second electrode of the driving element DT, the second electrode of the first switch element T11 , and the first electrode of the fourth switch element T14 .

The second switch element T12 is turned on according to the gate-on voltage VGL of the N-th scan signal SCAN(N) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switch element T12 includes a gate connected to the Nth scan line 125 , a first electrode connected to the fifth node n15 , and a second electrode connected to the data line 113 . The fifth node n15 is connected to the first electrode of the driving element DT, the first electrode of the second switch element T12 , and the second electrode of the third switch element T13 .

The third switch element T13 supplies the pixel driving voltage ELVDD to the first electrode of the driving element DT in response to the EM signal EM(N). The third switch element T13 includes a gate connected to the N-th EM line 126 , a first electrode connected to the ELVDD line 61 , and a second electrode connected to the fifth node n15 . The EM signal EM(N) is supplied to the pixels P through the N-th EM line 126 .

The fourth switch element T14 is turned on according to the gate-on voltage VGL of the EM signal EM(N) to connect the second electrode of the driving element DT to the anode of the light emitting element EL. The gate of the fourth switch element T14 is connected to the N-th EM line 126 . The first electrode of the fourth switch element T14 is connected to the third node n13 , and the second electrode of the fourth switch element T14 is connected to the fourth node n14 . The fourth node n14 is connected to the anode of the light emitting element EL, the second electrode of the fourth switch element T14, and the second electrode of the sixth switch element T16.

The fifth switch element T15 is turned on according to the gate-on voltage VGL of the N-1th scan signal SCAN(N-1), and connects the second node n12 to the Vini wiring 63 to During the initialization step Ti, the gates of the capacitor Cst and the driving device DT are initialized. The fifth switch element T15 includes a gate connected to the N-1 th scan line 124 , a first electrode connected to the second node n12 , and a second electrode connected to the Vini line 63 .

The N-1 th scan signal SCAN(N-1) is supplied to the pixels P through the N-1 th scan line 124 . Vini is supplied to the pixels P through the Vini wiring 63 .

The sixth switch element T16 is turned on according to the gate-on voltage VGL of the N-1th scan signal [SCAN(N-1)] to connect the Vini wiring 63 to the light emitting element ( EL) to the anode. During the initialization step Ti, the anode voltage of the light emitting device EL is discharged to the initialization voltage Vini through the sixth switch device T16. At this time, the light emitting element EL does not emit light because the voltage between the anode and the cathode is smaller than its threshold voltage. The sixth switch element T16 includes a gate connected to the N-1 th scan line 124 , a first electrode connected to the Vini line 63 , and a second electrode connected to the fourth node n14 .

The driving device DT controls the current flowing through the light emitting device EL according to the gate-source voltage Vgs to drive the light emitting device EL. The driving element DT includes a gate connected to the second node n12 , a first electrode connected to the fifth node n15 , and a second electrode connected to the third node n13 .

The light emitting element EL is connected between the fourth node n14 and the ELVSS wiring 62 . The light emitting element EL may be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL), but is not limited thereto. When a voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the light emitting layer (EML) to form excitons, and as a result, visible light from the light emitting layer (EML) this is emitted

Gates of the fifth and sixth switch elements T15 and T16 may be connected to divided scan lines separated at a boundary between the first and second sub-pixel arrays AA1 and AA2 . Gates of the first and second switch elements T11 and T12 may be connected to a shared scan line. The shared scan line may cross the first and second sub-pixel arrays AA1 and AA2 on the same pixel line and may be commonly connected to pixels of the first and second sub-pixel arrays AA1 and AA2.

5A to 7B are diagrams illustrating the operation of the pixel circuit shown in FIG. 4 in stages. 5A is a diagram illustrating a current path flowing through a pixel circuit in an initialization step Ti. 6A is a diagram illustrating a current path flowing through a pixel circuit in a sensing step (Ts). 7A is a diagram illustrating a current path flowing through a pixel circuit during a light emitting step Tem. Transistors indicated by "X" in FIGS. 5A, 6A, and 7A are transistors in an off state. 5B, 6B, and 7B are waveform diagrams showing the gate signals SCAN and EM and the data voltage DATA applied to the pixel circuit.

5A and 5B , in the initialization step Ti, the voltage of the N-1 th scan signal [SCAN(N-1)] is the gate-on voltage VGL, and the N-th scan signal [SCAN(N)] and the EM signal EM(N) are the gate-off voltage VGH. Accordingly, the fifth and sixth switch elements T15 and T16 are turned on in the initialization step Ti, so that the voltages of the second and fourth nodes n12 and n14 are discharged to the initialization voltage Vini. As a result, in the initialization step Ti, the capacitor Cst, the gate voltage of the driving device DT, and the anode voltage of the light emitting device EL are initialized to the initialization voltage Vini.

6A and 6B , in the sensing step Ts, the voltage of the N-th scan signal SCAN(N) is inverted to the gate-on voltage VGL, and the N-1th scan signal SCAN(N-1) )] is inverted to the gate-off voltage VGH. Accordingly, the first and second switch elements T11 and T12 and the driving element DT are turned on in the sensing step Ts. At this time, the data voltage Vdata is applied to the fifth node n15 and the voltage of the second node n12 is changed to DATA+Vth. DATA is the data voltage (Vdata). In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and charged in the capacitor Cst connected to the second node n12.

7A and 7B , the voltage of the EM signal EM(N) is inverted to the gate-on voltage VGL in the light emission step Tem. The third and fourth switch elements T13 and T14 are turned on in the light emission step Tem. During the light emitting step Tem, a current may flow through the driving device DT to the light emitting device EL so that the light emitting device EL may emit light.

The current flowing through the light emitting element EL is adjusted according to the gate-source voltage Vgs of the driving element DT. The gate-source voltage Vgs of the driving device DT is Vgs = DATA+Vth-ELVDD during the light emission step Tem.

8 is a flowchart illustrating a method of driving a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 8 , the timing controller 130 detects a frame frequency of image data input from the host system 200 ( S1 ). The image data may include first image data to be displayed on the first sub-pixel array AA1 and second image data to be displayed on the second sub-pixel array AA1 . The first and second image data may have the same frame frequency or different frame frequencies. In general, as in the example of FIG. 9 , when the first and second image data belong to an image of the same content or the same application, the first and second image data may be input with the same frame frequency.

Even if the contents of the first and second image data are different or the images are of different applications, the frame may be changed with the same frame frequency. Conversely, even if the contents of the first and second image data are the same, the frame frequency may be changed by the timing controller 130 according to the movement of the first image data and the second image data. For example, the timing controller 130 may reduce the frame frequency of the image data with less motion among the first and second image data to improve power consumption without degrading the image quality.

If the frame frequencies of the first and second images are the same, the timing controller 130 controls the driving frequencies of the pixels of the first and second sub-pixel arrays AA1 and AA2 to the same frame frequency ( S2 ). In this case, the first and second data drivers 111 and 112 may be normally driven every frame period to output a data voltage of pixel data. When the frame frequencies of the first and second images are the same, the first and second gate drivers 121 and 122 are synchronized with the data drivers 111 and 112 to show the scan signal and EM in FIGS. 5A to 7B for every frame period. output a signal.

When the frame frequencies of the first and second images are the same, after the pixels P of the first sub-pixel array AA1 are initialized in every frame period, pixel data is written into the pixels P. In addition, after the pixels of the second sub-pixel array AA2 are initialized in every frame period, pixel data is written to the pixels ( S3 ).

When the frame frequencies of the first and second images are different from each other, the timing controller 130 sets the driving frequency of the first sub-pixel array AA1 and the driving frequency of the pixels of the second sub-pixel arrays AA2 to be different frames from each other. It can be controlled by frequency (S4). In this case, in the case of an image having a low frame frequency among the first and second image data, there is a frame skip period in which new pixel data is not written in the pixels. The frame scan period may include one or more non-driven frame periods.

The frame frequency of the first image data may be 60 Hz and the frame frequency of the second image data may be 30 Hz. While the first sub-pixel array AA1 is driven in a frame period of 60 Hz, every frame period of the first sub-pixel array AA1 is a driving frame period in which pixel data is written to the pixels after the pixels are initialized. After the pixels of the first sub-pixel array AA1 are initialized in every frame period with a frame frequency of 60 Hz, the data voltage of new pixel data is charged in every frame period. While the first sub-pixel array AA1 is driven with a frame frequency of 60 Hz, the second sub-pixel array AA2 is driven with a frame frequency of 30 Hz. For this reason, the frame period of the second sub-pixel array AA2 may be divided into a driving frame and a non-driving frame. After the pixels of the second sub-pixel array AA1 are initialized in the driving frame period at a frame frequency of 30 Hz, the data voltage of new pixel data is charged.

Accordingly, after the pixels of the first sub-pixel array AA1 are initialized during the driving frame period of the first sub-pixel array AA1, pixel data is written to the pixels. After the pixels of the second sub-pixel array AA2 are initialized during the driving frame period of the second sub-pixel array AA2, pixel data is written to the pixels (S5).

Among the first and second sub-pixel arrays AA1 and AA2, at least one non-driving pixel among pixels of the sub-pixel array displaying an image having a low frame frequency is not initialized during the non-driving frame period and has a previously charged data voltage maintain (S6).

When the frame frequency of the second sub-pixel array is low, all pixels of the second sub-pixel array may be non-driven pixels in the non-driven frame period. In this case, the second data driver 112 may not output the data voltage in the non-driving frame period under the control of the timing controller 130 and thus may not generate power consumption.

Some of the pixels of the second sub-pixel array AA2 may be non-driving pixels in the non-driving frame period. In this case, the second data driver 112 may not output the data voltage from some channels connected to the non-driving pixels under the control of the timing controller 130 .

9 is a diagram illustrating an example in which the first and second sub-pixel arrays are driven at the same frame frequency. 10 is a diagram illustrating an example in which the first and second sub-pixel arrays are driven at different frame frequencies.

Referring to FIG. 9 , when an image having a combined resolution of the first and second sub-pixel arrays AA1 and AA2 is displayed on the first and second sub-pixel arrays AA1 and AA2, the first and second sub-pixel arrays AA1 and AA2 Frame frequencies of the pixel arrays AA1 and AA2 may be the same. In the example of FIG. 9 , pixels of the first and second sub-pixel arrays AA1 and AA2 are normally driven in every frame period F1 to F4 . In this case, the driving frame period of the first and second sub-pixel arrays AA1 and AA2 is the same. When the first and second sub-pixel arrays AA1 and AA2 are driven at a frame frequency of 60 Hz, as shown in the waveform diagram of FIG. 9 , all frame periods F1 to F4 are the first and second sub-pixel arrays AA1 and AA2 . AA2) of the driving frame period. When the first and second sub-pixel arrays AA1 and AA2 are driven at a frame frequency of 30 Hz, odd-numbered frame periods F1 and F3 are driving frames of the first and second sub-pixel arrays AA1 and AA2 period, and even-th frame periods F2 and F4 may be non-driving frame periods of the first and second sub-pixel arrays AA1 and AA2.

Referring to FIG. 10 , the first image data may be displayed in the first sub-pixel array AA1 with a frame frequency of 60 Hz with the resolution of the first sub-pixel array AA1 . The second image data may be displayed in the second sub-pixel array AA2 with the resolution of the second sub-pixel array AA2 at a frame frequency of 30 Hz. The first image data may be an image of content or an application with a lot of movement. As the moving speed of the moving object in the first image data increases, the frame frequency may increase. The second image data may be an image of an idle screen or an image of content or application with little movement.

A frame period of the sub-pixel array in which an image having a lower frame frequency among the first image data and the second image data is displayed has a frame skip period and is divided into a driving frame period and a non-driving frame period. The non-driven frame period corresponds to the frame skip period. In the example of FIG. 10 , the pixels of the second sub-pixel array AA2 are normally driven and initialized in the odd-numbered frame periods F1 and F3 during which the pixels of the first sub-pixel array AA1 are normally driven, and then the data voltage is charged. do. On the other hand, the pixels of the second sub-pixel array AA2 are not initialized because the first sub-pixel array AA1 is not driven during the even-th frame periods F2 and F4 in which the pixels are normally driven, and the previous data voltage is maintained. do.

In the example of FIG. 10 , when the first sub-pixel array AA1 is driven with a frame frequency of 60 Hz and the second sub-pixel array AA2 is driven with a frame frequency of 30 Hz, as shown in the waveform diagram of FIG. 10 , the second sub-pixel The driving frame period of the arrays AA2 is odd-numbered frame periods F1 and F3 , and the non-driving frame period of the second sub-pixel array AA2 is even-th frame period F2 and F4 . In the non-driving frame period, the second data driver 112 connected to the data lines of the second sub-pixel array AA2 is a non-driving data driver. Since the non-driven data driver does not output a data voltage, power consumption is not generated. At least one output channel of the non-driven data driver is electrically separated from the data lines, and thus floats and is in a high impedance state. When the frame frequency of the second sub-pixel array is lower than the frame frequency of the second sub-pixel array, at least one output of the second data driver 112 during a frame period in which the first data driver 111 outputs the data voltage The channel can remain in a floating, non-driven state.

11 is a diagram illustrating an example in which a scan line is shared between the first and second sub-pixel arrays AA1 and AA2 without being separated. 12 is a circuit diagram illustrating a phenomenon in which data of a pixel circuit driven at a low frame frequency is erased in the shared scan line structure as shown in FIG. 11 .

11 and 12 , the scan lines 124 and 125 may be shared between the first and second sub-pixel arrays AA1 and AA2 without being separated. The first and second gate drivers 121 and 122 are synchronized to sequentially supply the scan signals SCAN1 to SCAN3 to the scan lines 124 and 125 . The first and second gate drivers 121 and 122 simultaneously supply the first scan signal SCAN1 to the first scan line 124 and then apply the second scan signal SCAN2 to the second scan line 125 . supplied at the same time Subsequently, the first and second gate drivers 121 and 122 simultaneously supply the third scan signal SCAN3 to the third scan line.

The first sub-pixel array AA1 may include a first pixel circuit SP1 . The second sub-pixel array AA2 may include a second pixel circuit SP2 . The first and second pixel circuits SP1 and SP2 may be disposed on the same pixel line. The first and second pixel circuits SP1 and SP2 are connected to the first and second scan lines 124 and 125 to share the scan lines 124 and 125 . The first scan line 124 is a scan line that supplies the scan signal SCAN1 for initialization to the first and second pixel circuits SP1 and SP2 . The second scan line 125 is a scan line that supplies the data writing scan signal SCAN2 synchronized with the data voltage to the first and second pixel circuits SP1 and SP2 .

In the shared scan line structure as shown in FIG. 11 , when the frame frequencies of the first sub-pixel array AA1 and the second sub-pixel array AA2 are different from each other, data is undesirably erased from pixels of the pixel array driven with a low frame frequency. can lead to the phenomenon of For example, when the frame frequency of the second sub-pixel array AA2 is lower than that of the first sub-pixel array AA1 , the second pixel is initialized during the driving frame period of the first pixel circuit SP1 . The circuit SP2 may be a non-driving frame period. In this case, when the first pixel circuit SP1 is initialized, the second pixel circuit SP2 is not initialized and must maintain the previous data voltage, but as shown in FIG. 12 , the initialization scan signal SCAN1 is and since the second pixel circuits SP1 and SP2 are simultaneously applied, the previous data voltage DATA+Vth charged in the capacitor of the second pixel circuit SP2 is discharged to the initialization voltage Vini, and data is erased. ) can be

Accordingly, in the shared scan line structure shown in FIG. 11 , the frame frequencies of the first and second sub-pixel arrays AA1 and AA2 cannot be differently controlled without erasing data.

13 is a diagram illustrating an example in which all scan lines are separated between first and second sub-pixel arrays. 14A and 14B are waveform diagrams illustrating gate timing control signals for controlling the first gate driver and the second gate driver in the scan line structure separated as shown in FIG. 13 . 15 is a waveform diagram illustrating a scan signal applied to neighboring pixel circuits at a boundary between first and second sub-pixel arrays and a gate voltage of a driving device.

Referring to FIG. 13 , scan lines 124A, 124B, 125A, and 125B may be separated on a boundary line between the first and second sub-pixel arrays AA1 and AA2 . Pixel circuits of the first sub-pixel array AA1 are connected to the first group of divided scan lines 124A and 125A. Pixel circuits of the second sub-pixel array AA2 are connected to the second group of divided scan lines 124B and 125B.

As shown in FIG. 14A , the first gate driver 121 shifts the start pulse VST for each rising edge of the shift clocks CLK1 and CLK2 to transmit the scan signal (VST) to the scan lines 124A and 125A of the first group. SCAN1~SCAN3) are supplied sequentially. As shown in FIG. 14B , the second gate driver 122 applies the start pulse VST to the second group of scan lines 124B and 125B for each rising edge of the shift clocks CLK1 and CLK2 to the scan signals SCAN1 to SCAN3) is supplied sequentially.

The voltage of the shift clock input to the second gate driver 122 during the frame skip period of the second sub-pixel array AA2, that is, the non-driving frame periods F2 and F4, may be maintained as the gate-off voltage VGH. . When the voltage of the shift clock is maintained at the gate-off voltage VGH, the second gate driver 122 cannot shift the scan signal. the switch elements T11 connected to the scan lines 124B and 125B in the second pixel circuit SP2 by maintaining the gate-off voltage VGH by the voltage of the scan lines 124B and 125B of the second sub-pixel array; T12, T15, and 16) may maintain an off state. Accordingly, during the frame skip period of the second sub-pixel array AA2 , power consumption of the second sub-pixel array AA2 and the second data driver 112 is reduced, and the power consumption of the second gate driver 122 is also can be reduced.

The RC load of the first sub-pixel array AA1 and the second sub-pixel array AA2 may be slightly different even if the lengths of the separated scan lines 124A, 124B, 125A, and 125B are different. Accordingly, as shown in FIGS. 13 and 15 , a luminance difference may be seen between pixels at points A and B neighboring on the boundary line between the first sub-pixel array AA1 and the second sub-pixel array AA2 . A delay time difference of the scan signal SCAN1 may occur between pixels at points A and B. The delay time difference of the scan signal SCAN1 causes a difference ΔV in the gate voltage DRG between the driving elements DT at points A and B, so that the luminance difference is seen in the pixels at points A and B.

In the display device of the present invention, when the sub-pixel arrays AA1 and AA2 are driven at different frame frequencies within one screen, in order to prevent unwanted data erasure of the pixel circuit and non-uniformity of luminance, as shown in FIG. Among the scan lines, scan lines for initialization are separated at a boundary between the sub-pixel arrays AA1 and AA2. The scan lines for writing data are not separated and are shared by the first and second sub-pixel arrays AA1 and AA2.

In the sensing step Ts, a small electrical deviation between adjacent pixels is sensitive enough to allow a luminance deviation to be recognized. In contrast, the initialization step Ti is a step of lowering the gate voltage of the driving device DT to turn on the driving device DT to sense the threshold voltage of the driving device DT. If a time for sensing the threshold voltage of the driving element DT is secured, even a small electrical deviation between adjacent pixels has little effect on the luminance of the pixels. Accordingly, in the present invention, as shown in FIG. 16 , in the sensing step, a scan line for writing data is connected to a common line between the sub-pixel arrays AA1 and AA2, and a scan line for initialization is connected to the sub-pixel arrays AA1. , AA2), it is possible to drive the sub-pixel arrays AA1 and AA2 at different frame frequencies without degrading image quality. When the pixel array is driven at a low frame frequency, if the data drivers 111 and 112 are not driven in the non-driving frame period that is the frame skip period, little power is consumed in the data drivers 111 and 112, and the non-driven pixels Since current is not generated in the display panel, power consumption may be reduced even in the display panel. When the shift clock is not generated in the frame skip period as shown in FIG. 13 , the scan signal pulses are not output from the gate drivers 121 and 122 , and thus power consumption of the gate drivers 121 and 122 may be reduced.

The display device of the present invention normally drives a scan line for writing data in a frame skip period and supplies a gate-off voltage (VGH) to the scan line for initialization. As a result, the present invention blocks the discharge path so that the previous data voltage charged in the capacitor Cst is not discharged in the non-driving pixels, thereby preventing data from being erased in the non-driving pixels.

16 is a diagram illustrating an example in which an initialization scan line is separated from among scan lines between first and second sub-pixel arrays. 17A and 17B are waveform diagrams illustrating gate timing control signals for controlling the first gate driver and the second gate driver in the scan line structure separated as shown in FIG. 16 . 18 is a circuit diagram illustrating an effect of preventing erasing of a data voltage in a pixel circuit of a sub-pixel array driven at a low frame frequency in the separated scan line structure as shown in FIG. 16 .

Referring to FIG. 16 , the display device of the present invention includes a display panel 100 in which pixels connected to scan lines 161 to 163 and 171A to 173B and data lines are disposed. Data lines are omitted in FIG. 16 .

The scan lines 161 to 163 and 171A to 173B include the first group of scan lines 161 to 163 , 171A, 172A and 173A connected to the pixels of the first sub-pixel array AA1 and the second sub-pixel The second group of scan lines 161 to 163 , 171B, 172B, and 173B connected to the pixels of the array AA2 are included.

The scan lines 161 to 163, 171A, 172A, and 173A of the first group include the shared scan lines 161 to 163 to which the scan signals SCAN1 to SCAN3 are sequentially supplied, and the divided scan lines 171A and 172A. , 173A). The second group of scan lines 161 to 163, 171B, 172B, and 173B includes the shared scan lines 161 to 163 to which the scan signals SCAN1 to SCAN3 are sequentially supplied, and the divided scan lines 171B and 172B. , 173B).

The shared scan lines 161 to 163 are not separated between the first and second sub-pixel arrays AA1 and AA2. The shared scan lines 161 to 163 supply scan signals SCAN1 to SCAN3 for writing data to the pixels. The shared scan lines 161 to 163 are connected to the same pixel line of the first and second sub-pixel arrays AA1 and AA2 and are shared by pixels of the pixel line. The shared scan lines 161 , 162 , and 163 are switch elements for writing data in the pixel circuits SP1 and SP2 , for example, gates of the first and second switch elements T11 and T12 in FIG. 6A . connected to the , and supply scan signals SCAN1 to SCAN3 to the gates of the switch elements T11 and T12.

The divided scan lines 171A to 173B are separated on a boundary line between the first and second sub-pixel arrays AA1 and AA2 . The divided scan lines 171A to 173B supply scan signals SCAN1 to SCAN3 for initializing pixels. The pixel circuits SP1 and SP2 of each of the pixels are initialized in response to the N-1th scan signal SCAN(N-1) as shown in FIGS. 5A and 5B in the initialization step Ti, and the sensing step At (Ts), the data voltage of the pixel data is charged in response to the N-th scan signal SCNA(N) as shown in FIGS. 6A and 6B .

The first group of divided scan lines 171A, 172A, and 173A are connected to the pixels of the first sub-pixel array AA1 . The first group of divided scan lines 171A, 172A, and 173A are switch elements for initialization in the first pixel circuit SP1 , for example, the fifth and sixth switch elements T15 and 16 in FIG. 5A . It is connected to the gates to supply the scan signals SCAN1 to SCAN3 or the gate-off voltage VGH to the gates of the switch elements T15 and 16 .

The second group of divided scan lines 171B, 172B, and 173B are connected to pixels of the second sub-pixel array AA2. The second group of divided scan lines 171B, 172B, and 173B are switch elements for initialization in the second pixel circuit SP2, for example, the fifth and sixth switch elements T15 and 16 in FIG. 5A . It is connected to the gates to supply the scan signals SCAN1 to SCAN3 or the gate-off voltage VGH to the gates of the switch elements T15 and 16 .

The gate drivers 121 and 122 may initialize main nodes of the pixel circuits SP1 and SP2 by sequentially supplying scan signals to the divided scan lines 171A to 173B during the driving frame period.

The gate drivers 121 and 122 may prevent data erasure of pixels by supplying a gate-off voltage VGH to the divided scan lines 171A to 173B during a frame skip period, that is, a non-driving frame period. The gate-off voltage VGH may be sequentially or simultaneously applied to the divided scan lines 171A to 173B. The initialization switch elements T15 and T16 of the pixel circuits SP1 and SP2 maintain an off state by the gate-off voltage VGH applied to the gate during the non-driving frame period. When the initialization switch elements T15 and T16 are in an off state, since the previous data voltage charged in the capacitor Cst is not discharged, unwanted erasure of data may be prevented.

The gate drivers 121 and 122 may further include switch circuits for selectively supplying the gate-off voltage VGH and the scan signals SCAN1 to SCAN3 to the divided scan lines 171A to 173B. The switch circuits are connected between the shift register and the scan lines sequentially outputting the scan signal. The switch circuits may be disposed on the display panel 100 .

The switch circuit of the first gate driver 121 includes the 1-1 switch element ML1 connected between the neighboring shared scan lines 161 , 162 , and 163 and the divided scan lines 171A, 172A, and 173A, and the gate is off. and a second-first switch element ML2 for supplying the voltage VGH to the divided scan lines 171A, 172A, and 173A. The gate-off voltage VGH is generated from the VGH channel of the power supply.

The 1-1 switch element ML1 transmits the scan signals SCAN1 to SCAN3 to the first sub-pixel array AA1 during the driving frame period of the first sub-pixel array AA1 in response to the 1-1 control signal C1L. ) to the divided scan lines 171A, 172A, and 173A. The 1-1 switch element ML1 is connected to the gate to which the 1-1 control signal C1L is input, the first electrode connected to the shared scan lines 161 to 163 , and the divided scan lines 171A, 172A, and 173A. and a second electrode connected thereto. The first pixel circuit SP1 is initialized in response to the scan signals SCAN1 to SCAN3 input through the divided scan lines 171A, 172A, and 173A.

The 1-2-th switch element ML2 applies the gate-off voltage VGH to the first sub-pixel array AA1 during the non-driving frame period of the first sub-pixel array AA1 in response to the 1-2-th control signal C2L. ) to the divided scan lines 171A, 172A, and 173A. The 1-2-th switch element ML2 is connected to a gate to which the 1-2-th control signal C2L is input, a first electrode to which the gate-off voltage VGH is applied, and the divided scan lines 171A, 172A, and 173A. and a second electrode. The first pixel circuit SP1 is not initialized because the initialization switch elements T15 and T16 are turned off when the gate-off voltage VGH is applied to the divided scan lines 171A, 172A, and 173A. to keep

The switch circuit of the second gate driver 122 includes the 2-1 th switch element MR1 connected between the neighboring shared scan lines 161 , 162 , and 163 and the divided scan lines 171B, 172B, and 173B, and the gate is off. and a 2-2 second switch element MR2 for supplying the voltage VGH to the divided scan lines 171B, 172B, and 173B.

The 2-1 th switch element MR1 transmits the scan signals SCAN1 to SCAN3 to the second sub-pixel array AA2 during the driving frame period of the second sub-pixel array AA2 in response to the 2-1 th control signal C1R. ) to the divided scan lines 171B, 172B, and 173B. The 2-2nd switch element MR1 is connected to the gate to which the 2-1th control signal C1R is input, the first electrode connected to the shared scan lines 161 to 163 , and the divided scan lines 171B, 172B, and 173B. and a second electrode connected thereto. The second pixel circuit SP2 is initialized in response to the scan signals SCAN1 to SCAN3 input through the divided scan lines 171B, 172B, and 173B.

The second-second switch element MR2 applies the gate-off voltage VGH to the second sub-pixel array AA2 during the non-driving frame period of the second sub-pixel array AA2 in response to the second-second control signal C2R. ) to the divided scan lines 171B, 172B, and 173B. The 2-2nd switch element MR2 is connected to the gate to which the 2-2nd control signal C2R is input, the first electrode to which the gate-off voltage VGH is applied, and the divided scan lines 171B, 172B, and 173B. and a second electrode. The second pixel circuit SP2 is not initialized because the initialization switch elements T15 and T16 are turned off when the gate-off voltage VGH is applied to the divided scan lines 171B, 172B, and 173B. to keep

The timing controller 130 generates a gate timing control signal including the start pulse VST, the shift clocks CLK1 and CLK2, and the switch control signals C1L to C2R to control the operation timing of the gate drivers 121 and 122 . do.

17A and 17B are waveform diagrams illustrating gate timing control signals for controlling the first gate driver and the second gate driver in the scan line structure separated as shown in FIG. 16 . In FIGS. 17A and 17B , “DATA” is a data voltage output from the data drivers 111 and 112 .

Referring to FIG. 17A , the first sub-pixel array AA1 may be driven at a frame frequency of 60 Hz. The first data driver 111 is driven at a frame frequency of 60 Hz to output a data voltage every frame period. When the pixels of the first sub-pixel array AA1 are driven at a frame frequency of 60 Hz, the data voltage is charged after being initialized in every frame period. To this end, the 1-1 th control signal C1L maintains the gate-on voltage VGL and the 1-2 th control signal C2L maintains the gate-off voltage VGH.

While the first sub-pixel array AA1 is driven in a frame period of 60 Hz, the 1-1 switch element ML1 is turned on in response to the gate-on voltage VGL of the 1-1 control signal C1L. to connect the shared scan lines 161 to 163 to the divided scan lines 172A to 172B. When the first-first switch element ML1 is turned on, the scan signals SCAN1 to SCAN3 are applied to the gates of the initialization switch elements T15 and T16 of the first pixel circuit SP1 . While the first sub-pixel array AA1 is driven in a frame period of 60 Hz, the 1-2 th switch element ML2 maintains an off state by the gate-off voltage VGH of the 1-2 th control signal C2L. do. Accordingly, the first pixel circuit SP1 may be initialized every frame period.

Referring to FIG. 17B , the second sub-pixel array AA2 may be driven at a frame frequency of 30 Hz due to the non-driving frame periods F2 and F4 . As the non-driving frame periods F2 and F4 increase, the driving frequency of the second sub-pixel array AA2 decreases. Since the second data driver 112 does not output the data voltage during the non-driving frame periods F2 and F4, it may be driven at a frame frequency of 30 Hz. When the pixels of the second sub-pixel array AA2 are driven at a frame frequency of 30 Hz, the data voltage is charged after being initialized in the driving frame periods F1 and F3, and the pixels are not initialized in the non-driving frame periods F2 and F4. Keep the previous data voltage. To this end, the 2-1 th control signal C1R is generated as a gate-on voltage VGL in the driving frame periods F1 and F3 and is generated as a gate-off voltage VGH in the non-driving frame periods F2 and F4. do. The 2-2nd control signal C2R is generated out of phase with the 2-1th control signal C1R. That is, the second-second control signal C2R is generated as the gate-off voltage VGH in the driving frame periods F1 and F3 and is generated as the gate-on voltage VGL in the non-driving frame periods F2 and F4. .

The 2-1 th switch element MR1 is turned on in response to the gate-on voltage VGL of the 2-1 th control signal C1R during the driving frame periods F1 and F3 to be turned on to the shared scan lines 161 to 163 . is connected to the divided scan lines 172A to 172B. When the 2-1 th switch element MR1 is turned on, the scan signals SCAN1 to SCAN3 are applied to the gates of the initialization switch elements T15 and T16 of the second pixel circuit SP2 . While the second sub-pixel array AA2 is driven in a frame period of 30 Hz, the second-second switch element MR2 has a gate-off voltage of the second-second control signal C2R in the driving frame periods F1 and F3. The off state is maintained by (VGH). Accordingly, the second pixel circuit SP2 may be initialized in the driving frame periods F1 and F3 .

While the second sub-pixel array AA2 is driven in a frame period of 30 Hz, the 2-1 th switch element MR1 turns off the gate of the 2-1 th control signal C1R in the non-driving frame periods F2 and F4 The off state is maintained by the voltage (VGH). The second-second switch element MR2 is turned on in response to the gate-on voltage VGL of the second-second control signal C2R in the non-driving frame periods F2 and F4 to increase the gate-off voltage VGH. It is connected to the divided scan lines 172A to 172B. When the second-second switch element MR2 is turned on, the gate-off voltage VGH is applied to the gates of the initialization switch elements T15 and T16 of the second pixel circuit SP2. T15 and T16) are turned off. Accordingly, the second pixel circuit SP2 may maintain the previous data voltage without being initialized in the non-driving frame periods F2 and F4 .

Initialization step of non-driving frame periods F2 and F4 that are frame skip periods when the first sub-pixel array AA1 is driven with a frame frequency of 60 Hz and the second sub-pixel array AA2 is driven with a frame frequency of 30 Hz In FIG. 18 , the first and second pixel circuits SP1 and SP2 operate as shown in FIG. 18 .

Referring to FIG. 18 , in the first pixel circuit SP1 , main nodes are initialized in response to the gate-on voltage VGL of the scan signal SCAN1 in the initialization phase of the non-driving frame periods F2 and F4 so that the capacitor Cst ) is discharged to Vini. At this time, the second pixel circuit SP2 is not initialized because the gate high voltage VGH is applied to the gates of the initialization switch elements T15 and T16 . Accordingly, when the first pixel circuit SP1 is initialized, the second pixel circuit SP1 is not initialized and maintains the previous data voltage charged in the capacitor Cst.

19A to 19F are diagrams illustrating the flow of signals applied to scan lines in sections ① to ⑥ shown in FIG. 18 .

19A to 19C show scan signals applied to scan lines in sections ①, ②, and ③. The gate drivers 121 and 122 transmit the scan signal SCAN1 to all the scan lines 161 to 163 and 171A to 173B of the first and second sub-pixel arrays AA1 and AA2 in sections ①, ②, and ③. ~SCAN3) is applied sequentially.

19D to 19F show scan signals and gate-off voltages applied to scan lines in sections ④, ⑤, and ⑥. The first gate driver 121 sequentially applies the scan signals SCAN1 to SCAN3 to all the scan lines of the first sub-pixel array AA1 in sections ④, ⑤, and ⑥. In contrast, the second gate driver 122 sequentially applies the scan signals SCAN1 to SCAN3 to the shared scan lines 161 to 163 for writing data in sections ④, ⑤, and ⑥, and scans for initialization. A gate-off voltage VGH is applied to the lines 171B, 172B, and 173B. In this case, the gate-off voltage VGH may be simultaneously applied to the scan lines 171B, 172B, and 173B. In this case, since the number of control signal wirings of the switch elements ML1 to MR2 is minimized, an increase in the size of the bezel is not large.

When a sub-pixel array having a low frame frequency exists in one screen, little power is consumed in the frame skip period in the data driver for driving the data lines of the sub-pixel array and the non-driving pixels. In order to verify the effect of improving power consumption, the inventor of the present application conducted a simulation and confirmed the result of reducing power consumption as shown in FIG. 20 . The sample panel used in this simulation is a plastic OLED panel with 1080*2160 resolution. When the On Pixel Ratio (OPR) of this sample panel was 100% and 40%, the power consumption was reduced as shown in FIG. 20 as a result of driving the pixels while varying the frame frequency to 60 Hz, 45 Hz, 30 Hz, and 1 Hz. When all the pixels in the screen are emitted with the brightness of the white gradation, the on-pixel ratio (OPR) is 100&. When 40% of the pixels emit light with the brightness of the white gradation and 60% of the pixels have the black gradation, the on-pixel ratio (OPR) is 100&. When no current flows through the light emitting elements of the pixels, no light is emitted, and the gray level at this time is a black gray level. At a frame frequency of 60 Hz, as the frame skip period increases, the frame frequency of pixels decreases.

In FIG. 20 , “D-IC” is a drive IC in which data drivers 111 and 112 are integrated. The drive IC includes a digital circuit unit such as a shift register and a latch, and an analog circuit unit including a DAC and an output buffer. As the frame frequency decreases, the current of the drive IC (D-IC) decreases in the frame skip period, so that the power consumption (mW) is further reduced.

The power consumption reduction rate (%) calculated as a result of the simulation is shown in the table below. The power consumption and total power consumption reduction rate of the drive IC (D-IC) is a reduction rate compared to 60Hz. The total power consumption is the sum of the power consumption of the drive IC (D-IC) and the display panel (PANEL).

A display device according to various embodiments of the present invention may be described as follows.

First embodiment: A display device includes: a first sub-pixel array AA1 including a first group of data lines, a first group of scan lines, and a plurality of pixel circuits; and a second sub-pixel array AA2 including a second group of data lines, a second group of scan lines, and a plurality of pixel circuits.

The first group of scan lines and the second group of scan lines are a plurality of shared scan lines 161 connected between the first and second sub-pixel arrays and shared between the first and second sub-pixels. ~163); and a plurality of divided scan lines 171A to 173B separated at a boundary between the first and second sub-pixel arrays.

Second embodiment: a first pixel circuit SP1 of the first sub-pixel array and a second pixel circuit SP1 of the second sub-pixel array form the first sub-pixel array and the second sub-pixel array It is placed on the crossing pixel line (#1, #2). The first and second pixel circuits are commonly connected to the shared scan line. The first pixel circuit is connected to the divided scan line of the first sub-pixel array, and the second pixel circuit is connected to the divided scan line of the second sub-pixel array.

Third embodiment: A scan signal for writing data of the pixel circuits is applied to the shared scan line, and a scan signal for initialization of the pixel circuits is applied to the divided scan line.

Fourth embodiment: An N-1 (N is a natural number greater than or equal to 2) scan signal is applied to the divided scan line, and an N-th scan signal is applied to the shared scan line.

Fifth embodiment: The frame frequency of the second sub-pixel array is equal to or different from the frame frequency of the first sub-pixel array.

Sixth embodiment: when the motion of the image displayed on the second sub-pixel array is less than that of the image displayed on the first sub-pixel array, the frame frequency of the second sub-pixel array is the frame frequency of the second sub-pixel array lower than

Seventh embodiment: When the frame frequency of the second sub-pixel array is lower than the frame frequency of the first sub-pixel array, the first pixel circuit is initialized and the second pixel circuit maintains the previous data voltage.

Eighth embodiment: Each of the first and second pixel circuits includes: a light emitting element (EL); a driving device DT for supplying a current to the light emitting device according to a gate-source voltage; a capacitor (Cst) connected to the gate of the driving device; a first switch unit 10 for discharging the capacitor and the gate of the driving element to an initialization voltage; and a second switch unit 20 for charging the capacitor with the data voltage compensated for by the threshold voltage of the driving element.

Ninth Embodiment: The first switch unit of the first pixel circuit is controlled by a scan signal or a gate-off voltage applied to a divided scan line of the first sub-pixel array.

The first switch unit of the first pixel circuit is controlled by a scan signal or a gate-off voltage applied to the divided scan lines of the second sub-pixel array. The second switch unit of each of the first and second pixel circuits is controlled by a scan signal applied to the shared scan line. The switch elements of the first switch unit are turned on according to the gate-on voltage of the scan signal, and are turned off according to the gate-off voltage.

Tenth embodiment: An N-1 (N is a natural number equal to or greater than 2) scan signal or the gate-off voltage is applied to the divided scan lines. An Nth scan signal is applied to the shared scan line.

11th embodiment: When the frame frequency of the second sub-pixel array is lower than the frame frequency of the first sub-pixel array, the N-1th scan signal is applied to the divided scan lines of the first sub-pixel array and simultaneously , the gate-off voltage is applied to the divided scan lines of the second sub-pixel array.

Twelfth embodiment: The capacitor Cst is connected between a first node n11 to which a pixel driving voltage is applied and a second node n12 connected to a gate of the driving device. The driving element DT includes a first electrode connected to a fifth node n15 and a second electrode connected to a third node n13 . The light emitting device includes an anode connected to the fourth node n14 and a cathode to which a low potential voltage is applied.

The first switch unit may include: a fifth switch element T15 including a gate connected to the divided scan line, a first electrode connected to the second node, and a second electrode to which an initialization voltage is applied; and a sixth switch element T16 including a gate connected to the divided scan line, a first electrode to which the initialization voltage is applied, and a second electrode connected to the fourth node.

The second switch unit includes: a first switch element T11 including a gate connected to the shared scan line, a first electrode connected to the second node, and a second electrode connected to the third node; and a second switch element T12 including a gate connected to the shared scan line, a second electrode connected to the fifth node, and a second electrode connected to a data line to which a data voltage is applied.

Thirteenth embodiment: Each of the first and second pixel circuits further includes a third switch unit configured to switch a current path between the pixel driving voltage and the light emitting device in response to a light emission control signal.

The third switch unit includes a third switch element (T13) including a gate connected to the EM line to which the emission control signal is applied, a first electrode connected to the first node, and a second electrode connected to the fifth node; and a fourth switch element T14 including a gate connected to the EM line, a first electrode connected to the third node, and a second electrode connected to the fourth node.

14th embodiment: The display device includes: a first gate driver sequentially supplying a scan signal to the shared scan lines and supplying the scan signal or a gate-off voltage to the divided scan lines of a first sub-pixel array; a second gate driver sequentially supplying a scan signal to the shared scan lines and supplying the scan signal or a gate-off voltage to the divided scan lines of a second sub-pixel array; a first data driver supplying a data voltage to the first group of data lines; a second data driver supplying a data voltage to the data lines of the second group; and a timing controller for controlling operation timings of the gate drivers and the data drivers.

The pixel circuits and the switch elements of the gate drivers are turned on according to the gate-on voltage and turned off according to the gate-off voltage.

Fifteenth embodiment: when the frame frequency of the second sub-pixel array is lower than the frame frequency of the first sub-pixel array, at least during a frame period in which the first data driver outputs the data voltage One output channel is floating and undriven.

Sixteenth embodiment: the first gate driver connects the divided scan line of the first sub-pixel array to the shared scan line in response to the gate-on voltage of the first-first control signal (ML1) ); and a 2-1 th switch element ML2 configured to supply the gate-off voltage to the divided scan lines of the first sub-pixel array in response to the gate-on voltage of the 1-2 th control signal.

The first gate driver includes: a 2-1 switch element MR1 connecting the divided scan line of the second sub-pixel array to the shared scan line in response to a gate-on voltage of the 2-1 control signal; and a 2-2 second switch element ML2 configured to supply the gate-off voltage to the divided scan lines of the second sub-pixel array in response to the gate-on voltage of the 2-2 control signal.

17th embodiment: When the frame frequency of the second sub-pixel array is lower than the frame frequency of the first sub-pixel array, during the frame skip period of the second sub-pixel array, the 1-1 control signal is applied to the gate The on voltage is generated to turn on the 1-1 switch element, and the 1-2 control signal is generated as the gate-off voltage to turn off the 1-2 switch element.

The 2-1 th control signal is generated as the gate-off voltage to turn off the 2-1 th switch element. The second-second control signal is generated as the gate-on voltage to turn on the second-second switch element.

Eighteenth embodiment: A display device includes: a first sub-pixel array driven at a first frame frequency; and a second sub-pixel array driven at a second frame frequency equal to or different from the first frame frequency.

The first and second sub-pixel arrays include a plurality of shared scan lines connected between the first and second sub-pixel arrays.

The first sub-pixel array includes a first group of divided scan lines coupled to pixels in the first sub-pixel array.

The second sub-pixel array includes a second group of divided scan lines coupled to pixels in the second sub-pixel array.

19th embodiment: A scan signal swinging between a gate-on voltage and a gate-off voltage is applied to the shared scan lines, the scan signal is applied to the divided scan lines during a driving frame period, and a non-driving frame period The gate-off voltage is applied to the divided scan lines.

The method of driving the display device may include: displaying a first image on the first sub-pixel array by driving the first sub-pixel array at a first frame frequency; and driving a second sub-pixel array with a second frame frequency equal to or different from the first frame frequency to display a second image on the second sub-pixel array.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: first switch unit 20: second switch unit
30: third switch unit 100: display panel
130: timing controller 111, 112: data driver
121, 122: gate driver 200: host system
161~163: Shared scan line 171A~173B: Split scan line
AA1: first sub-pixel array AA2: second sub-pixel array
SP1: pixel circuit of the first sub-pixel array
SP2: pixel circuit of the first sub-pixel array

Claims (20)

a first sub-pixel array including a first group of data lines and a first group of scan lines, and a plurality of pixel circuits; and
a second sub-pixel array comprising a second group of data lines and a second group of scan lines, and a plurality of pixel circuits;
The first group of scan lines and the second group of scan lines are
a plurality of shared scan lines connected between the first and second sub-pixel arrays and shared between the first and second sub-pixels; and
and a plurality of divided scan lines separated at a boundary between the first and second sub-pixel arrays. The method of claim 1,
a first pixel circuit of the first sub-pixel array and a second pixel circuit of the second sub-pixel array are disposed on a pixel line crossing the first sub-pixel array and the second sub-pixel array;
the first and second pixel circuits are commonly connected to the shared scan line;
The first pixel circuit is connected to the divided scan line of the first sub-pixel array, and the second pixel circuit is connected to the divided scan line of the second sub-pixel array. The method of claim 1,
a scan signal for writing data of the pixel circuits is applied to the shared scan line;
A display device in which a scan signal for initialization of the pixel circuits is applied to the divided scan line. The method of claim 1,
An N-1th scan signal (N is a natural number greater than or equal to 2) is applied to the divided scan line,
A display device to which an Nth scan signal is applied to the shared scan line. The method of claim 1,
A frame frequency of the second sub-pixel array is the same as or different from a frame frequency of the first sub-pixel array. 6. The method of claim 5,
a frame frequency of the second sub-pixel array is lower than a frame frequency of the second sub-pixel array when the movement of the image displayed on the second sub-pixel array is less than that of the image displayed on the first sub-pixel array. 7. The method of claim 6,
a first pixel circuit of the first sub-pixel array and a second pixel circuit of the second sub-pixel array are disposed on a pixel line crossing the first sub-pixel array and the second sub-pixel array;
When the frame frequency of the second sub-pixel array is lower than the frame frequency of the first sub-pixel array,
A display device in which the second pixel circuit maintains a previous data voltage while the first pixel circuit is initialized. The method of claim 1,
a first pixel circuit of the first sub-pixel array and a second pixel circuit of the second sub-pixel array are disposed on a pixel line crossing the first sub-pixel array and the second sub-pixel array;
Each of the first and second pixel circuits,
light emitting element;
a driving device for supplying a current to the light emitting device according to a gate-source voltage;
a capacitor connected to the gate of the driving element;
a first switch unit for discharging the capacitor and the gate of the driving element to an initialization voltage; and
and a second switch unit configured to charge the capacitor with a data voltage compensated for by a threshold voltage of the driving element. 9. The method of claim 8,
The first switch unit of the first pixel circuit is controlled by a scan signal or a gate-off voltage applied to a divided scan line of the first sub-pixel array;
The first switch unit of the first pixel circuit is controlled by a scan signal or a gate-off voltage applied to a divided scan line of the second sub-pixel array;
The second switch unit of each of the first and second pixel circuits is controlled by a scan signal applied to the shared scan line,
The switch elements of the first switch unit are turned on according to a gate-on voltage of the scan signal, and are turned off according to the gate-off voltage. 10. The method of claim 9,
An N-1th (N is a natural number equal to or greater than 2) scan signal or the gate-off voltage is applied to the divided scan lines;
A display device to which an Nth scan signal is applied to the shared scan line. 11. The method of claim 10,
When the frame frequency of the second sub-pixel array is lower than the frame frequency of the first sub-pixel array,
A display device in which the N-1th scan signal is applied to the divided scan lines of the first sub-pixel array and the gate-off voltage is applied to the divided scan lines of the second sub-pixel array. 11. The method of claim 10,
the capacitor is connected between a first node to which a pixel driving voltage is applied and a second node connected to a gate of the driving element;
The driving element includes a first electrode connected to a fifth node and a second electrode connected to a third node,
The light emitting device includes an anode connected to the fourth node, and a cathode to which a low potential voltage is applied,
The first switch unit,
a fifth switch element including a gate connected to the divided scan line, a first electrode connected to the second node, and a second electrode to which an initialization voltage is applied; and
a sixth switch element including a gate connected to the divided scan line, a first electrode to which the initialization voltage is applied, and a second electrode connected to the fourth node,
The second switch unit,
a first switch element including a gate connected to the shared scan line, a first electrode connected to the second node, and a second electrode connected to the third node; and
and a second switch element including a gate connected to the shared scan line, a second electrode connected to the fifth node, and a second electrode connected to a data line to which a data voltage is applied. 13. The method of claim 12,
Each of the first and second pixel circuits,
Further comprising a third switch unit for switching a current path between the pixel driving voltage and the light emitting device in response to a light emission control signal,
The third switch unit,
a third switch element including a gate connected to the EM line to which the emission control signal is applied, a first electrode connected to the first node, and a second electrode connected to the fifth node; and
and a fourth switch element including a gate connected to the EM line, a first electrode connected to the third node, and a second electrode connected to the fourth node. The method of claim 1,
a first gate driver sequentially supplying a scan signal to the shared scan lines and supplying the scan signal or a gate-off voltage to the divided scan lines of a first sub-pixel array;
a second gate driver sequentially supplying a scan signal to the shared scan lines and supplying the scan signal or a gate-off voltage to the divided scan lines of a second sub-pixel array;
a first data driver supplying a data voltage to the first group of data lines;
a second data driver supplying a data voltage to the data lines of the second group; and
Further comprising a timing controller for controlling the operation timing of the gate drivers and the data drivers,
The pixel circuits and the switch elements of the gate drivers are turned on according to a gate-on voltage and turned off according to the gate-off voltage. 15. The method of claim 14,
When the frame frequency of the second sub-pixel array is lower than the frame frequency of the first sub-pixel array,
In a frame period in which the first data driver outputs the data voltage, at least one output channel of the second data driver is separated from the corresponding data line of the second group and floats. 15. The method of claim 14,
The first gate driver,
a 1-1 switch element connecting the divided scan line of the first sub-pixel array to the shared scan line in response to a gate-on voltage of the 1-1 control signal; and
a 2-1 switch device configured to supply the gate-off voltage to the divided scan lines of the first sub-pixel array in response to the gate-on voltage of the 1-2-th control signal;
The first gate driver,
a 2-1 switch element connecting the divided scan line of the second sub-pixel array to the shared scan line in response to the gate-on voltage of the 2-1 control signal; and
and a 2-2 switch element configured to supply the gate-off voltage to the divided scan lines of the second sub-pixel array in response to the gate-on voltage of the 2-2 control signal. 15. The method of claim 14,
When the frame frequency of the second sub-pixel array is lower than the frame frequency of the first sub-pixel array,
During the frame skip period of the second sub-pixel array,
The 1-1 control signal is generated as the gate-on voltage to turn on the 1-1 switch element,
The 1-2 control signal is generated as the gate-off voltage to turn off the 1-2 switch element,
The 2-1 control signal is generated as the gate-off voltage to turn off the 2-1 switch element,
The second-second control signal is generated as the gate-on voltage to turn on the second-second switch element. a first sub-pixel array driven at a first frame frequency; and
a second sub-pixel array driven at a second frame frequency equal to or different from the first frame frequency;
The first and second sub-pixel arrays are
a plurality of shared scan lines connected between the first and second sub-pixel arrays;
the first sub-pixel array
a first group of divided scan lines coupled to pixels in the first sub-pixel array;
the second sub-pixel array
and a second group of divided scan lines connected to pixels in the second sub-pixel array. 19. The method of claim 18,
A scan signal swinging between a gate-on voltage and a gate-off voltage is applied to the shared scan lines;
A display device in which the scan signal is applied to the divided scan lines during a driving frame period and the gate-off voltage is applied to the divided scan lines during a non-driving frame period. a plurality of shared scan lines coupled between first and second sub-pixel arrays, a first group of divided scan lines coupled to pixels in the first sub-pixel array, coupled to pixels in the second sub-pixel array A method of driving a display device including a second group of divided scan lines, the method comprising:
displaying a first image on the first sub-pixel array by driving the first sub-pixel array with a first frame frequency; and
and displaying a second image on the second sub-pixel array by driving a second sub-pixel array with a second frame frequency equal to or different from the first frame frequency.

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