KR102414594B1 - Light Emitting Display Device and Driving Method thereof - Google Patents

Abstract

The present specification provides an electroluminescent display device including a display panel, a sub-pixel, and a voltage transfer unit. The display panel has a display area that displays an image and a non-display area that does not display an image. The sub-pixel is located in the display area. The voltage transfer unit is located in the non-display area and transmits the reference voltage to the sub-pixels in response to a signal applied from the outside or a signal generated on the display panel.

Description

Electroluminescent display device and driving method thereof

The present specification relates to an electroluminescent display device and a driving method thereof.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of various types of display devices such as an electroluminescent display device, a liquid crystal display device, and a quantum dot display device is increasing.

The display device includes a display panel including a plurality of sub-pixels, a driving unit for driving the display panel, and a power supply unit for supplying power to the display panel. The driver includes a scan driver that supplies a scan signal (or a gate signal) to the display panel and a data driver that supplies a data voltage to the display panel.

In the electroluminescent display device, when a scan signal and a data voltage are supplied to the sub-pixels, the light emitting diodes of the selected sub-pixels emit light, so that an image can be displayed. The light emitting diode is implemented based on an organic material or is implemented based on an inorganic material.

The electroluminescent display device has various advantages such as being in the spotlight as a next-generation display device because it displays an image based on the light generated from the light emitting diode included in the sub-pixel. However, since the electroluminescent display device has a time-varying characteristic (or time-dependent change) in which the threshold voltage of an element included in the sub-pixel changes, it is necessary to compensate for this.

As a result, various compensation schemes capable of compensating for the time-varying characteristics of the electroluminescent display device have been proposed. However, some of the compensation schemes generally suggested require improvement because voltage drop is not taken into account, resulting in image quality issues such as vertical luminance non-uniformity or cross-talk on the display panel.

Accordingly, the inventors of the present specification have recognized the above-mentioned problems, devised a display panel for minimizing the voltage drop on the voltage applying wiring, and invented a display device to which the same is applied.

The present specification for solving the problems of the above-mentioned background technology is to prevent or improve the phenomenon of causing image quality issues such as vertical luminance non-uniformity or cross-talk on a display panel by compensating for time-varying characteristics in consideration of voltage drop. will be.

The tasks of the present specification are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

As a means of solving the above problems, the present specification provides an electroluminescent display device including a display panel, a sub-pixel, and a voltage transmitting unit. The display panel has a display area that displays an image and a non-display area that does not display an image. The sub-pixel is located in the display area. The voltage transfer unit is located in the non-display area and transmits the reference voltage to the sub-pixels in response to a signal applied from the outside or a signal generated on the display panel.

In another aspect, the present specification provides a display panel having a display area for displaying an image and a non-display area for non-displaying an image, a sub-pixel located in the display area, and voltage transfer for transferring a reference voltage to the sub-pixel located in the non-display area It provides a method of driving an electroluminescent display device including a unit. A driving method of an electroluminescent display device includes an initialization step for initializing a sub-pixel, and a sampling step for compensating for a threshold voltage of a driving transistor of the sub-pixel. During the sampling step, the voltage transfer unit operates in response to a signal applied from the outside of the display panel or a signal generated on the display panel.

The present specification provides compensation for time-varying characteristics (or changes over time) in consideration of the voltage drop of the first power supply voltage, thereby preventing or improving a phenomenon that causes image quality issues such as vertical luminance non-uniformity or cross-talk on the display panel. there is an effect

In addition, according to the present specification, by arranging a circuit for transmitting the reference voltage to the sub-pixel in the non-display area, the number of contacts of electrodes or wires in the sub-pixel can be reduced, and it is advantageous for high integration to realize a large screen and high resolution of the display panel. In this case, there is an effect of preventing a decrease in the aperture ratio.

Since the contents of the specification described in the problems, problem solving means, and effects to be solved above do not specify essential features of the claims, the scope of the claims is not limited by the matters described in the contents of the specification.

1 is a schematic block diagram of an organic light emitting display device;
Fig. 2 is a schematic block diagram of the sub-pixel shown in Fig. 1;
FIG. 3 is an exemplary arrangement view of the scan driver shown in FIG. 1 ;
4 is a block diagram of a sub-pixel circuit for explaining an organic light emitting display device according to an experimental example;
FIG. 5 is a waveform diagram for explaining some driving characteristics of the sub-pixel circuit shown in FIG. 4;
6 is a configuration diagram of a display panel schematically illustrating an organic light emitting display device according to a first exemplary embodiment of the present specification;
FIG. 7 is a waveform diagram for explaining some driving characteristics of the sub-pixel circuit shown in FIG. 6;
8 is a diagram illustrating in more detail the configuration of an Nth voltage transmitting unit according to the first embodiment of the present specification.
9 to 16 are diagrams for explaining a driving method according to the configuration of FIG. 8 in more detail;
17 is a configuration diagram of a display panel schematically illustrating an organic light emitting display device according to a second exemplary embodiment of the present specification;
FIG. 18 is a waveform diagram for explaining some driving characteristics of the sub-pixel circuit shown in FIG. 17;
19 is a configuration diagram of a display panel for schematically explaining an organic light emitting display device according to a third exemplary embodiment of the present specification;
FIG. 20 is a waveform diagram for explaining some driving characteristics of the sub-pixel circuit shown in FIG. 19;

Hereinafter, specific details for carrying out the present specification will be described with reference to the accompanying drawings.

The electroluminescent display device described below may be implemented as a TV, an image player, a personal computer (PC), a home theater, a smart phone, a virtual reality device (VR), and the like. An electroluminescent display device to be described below will be described as an organic light emitting display device implemented based on an organic light emitting diode (light emitting device) as an example. However, the electroluminescent display device to be described below may be implemented based on an inorganic light emitting diode.

In addition, the organic light emitting display device to be described below is implemented based on at least one of a P-type transistor and an N-type transistor. In the case of the P-type transistor and the N-type transistor, the positions of the source electrode and the drain electrode may be different depending on the type except for the gate electrode, and so as not to limit the position of the source electrode and the drain electrode, they are referred to as a first electrode and a second electrode.

FIG. 1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is a schematic block diagram of a sub-pixel illustrated in FIG. 1 , and FIG. 3 is an exemplary arrangement diagram of the scan driver illustrated in FIG. 1 .

1 , the organic light emitting display device includes an image processing unit 110 , a timing control unit 120 , a data driving unit 140 , a scan driving unit 130 , a display panel 150 , and a power supply unit 180 . Included.

The image processing unit 110 outputs driving signals for driving various devices along with image data supplied from the outside. The driving signal output from the image processing unit 110 may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, but these signals are omitted for convenience of description.

The timing controller 120 receives a driving signal and the like along with image data from the image processing unit 110 . The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 130 and a data timing control signal DDC for controlling the operation timing of the data driver 140 based on the driving signal. to output

The data driver 140 outputs a data voltage in response to the data timing control signal DDC supplied from the timing controller 120 . The data driver 140 samples and latches the digital data signal DATA supplied from the timing controller 120 to convert it into an analog data voltage based on the gamma reference voltage. The data driver 140 outputs a data voltage through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an integrated circuit (IC).

The scan driver 130 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120 . The scan driver 130 outputs a scan signal through the scan lines GL1 to GLm. The scan driver 130 may be formed in the form of an integrated circuit (IC).

The power supply unit 180 outputs a high potential voltage, a low potential voltage, and the like. The high potential voltage and low potential voltage output from the power supply unit 180 are supplied to the display panel 150 . The high potential voltage is supplied to the display panel 150 through the first power line EVDD, and the low potential voltage is supplied to the display panel 150 through the second power line EVSS. The voltage output from the power supply unit 180 is also used by the data driver 140 or the scan driver 130 .

The display panel 150 displays an image corresponding to the data voltage and scan signal supplied from the data driver 140 and the scan driver 130 , and power supplied from the power supply unit 180 . The display panel 150 includes sub-pixels SP that operate to display an image.

The sub-pixels SP include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or include a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The sub-pixels SP may have one or more different emission areas according to emission characteristics.

As shown in FIG. 2 , one sub-pixel SP is connected to a scan line GL1 , a data line DL1 , a first power line EVDD, and a second power line EVSS. The number of transistors and capacitors as well as a driving method of the sub-pixel SP are determined according to the configuration of the pixel circuit.

As shown in FIG. 3 , the display panel 150 has a display area AA for displaying an image based on the sub-pixels SP, and a non-display area for displaying an image in which signal lines or driving circuits are located. (NA).

The scan driver 130 is formed in the non-display area NA of the display panel 150 in a gate-in-panel method. The scan driver 130 may be disposed on the left and right sides of the display panel 150 , or may be disposed on either side of the display panel 150 . The scan driver 130 includes a plurality of stages. For example, the first stage of the scan driver 130 outputs a first scan signal for driving the first scan line of the display panel 150 .

On the other hand, the organic light emitting display device has various advantages such as being in the spotlight as a next-generation display device because it displays an image based on the light generated from the organic light emitting diode included in the sub-pixel. However, the organic light emitting display device has a time-varying characteristic (or time-dependent change) in which a threshold voltage of an element (eg, a driving transistor, etc.) included in a sub-pixel changes, and it is necessary to compensate for this.

As a result, various compensation methods capable of compensating for the time-varying characteristics of the organic light emitting display device have been proposed. However, some of the compensation schemes do not consider the voltage drop, which causes image quality issues such as vertical luminance non-uniformity or cross-talk on the display panel, and thus needs to be improved.

Hereinafter, the problems of the experimental examples that cause image quality issues such as vertical luminance non-uniformity or cross-talk on a display panel among organic light emitting display devices will be considered, and embodiments of the present specification for improving the problems will be described. However, hereinafter, for convenience of explanation, all transistors included in the sub-pixel are described as P-type as an example, but the embodiment of the present specification is also applicable to N-type transistors.

<Experimental example>

FIG. 4 is a configuration diagram of a sub-pixel circuit for explaining an organic light emitting display device according to an experimental example, and FIG. 5 is a waveform diagram for explaining some driving characteristics of the sub-pixel circuit shown in FIG. 4 .

4 and 5, the N-th sub-pixel according to the experimental example includes first to sixth transistors T1 to T6, a driving transistor DT, a capacitor Cst, and an organic light emitting diode (OLED). include

The first to sixth transistors T1 to T6 and the driving transistor DT are configured as P-type transistors. The third transistor T3 and the fourth transistor T4 are disposed in the form of a dual transistor (a structure in which two transistors are connected in series and a gate electrode is connected to each other to form a pair).

The N-th sub-pixel according to the experimental example includes a first initialization period (INI), a sampling and a second initialization period ( SAM), compensation based on the internal circuit is made. The operating characteristics during these periods are briefly described as follows.

During the first initialization period INI, the fourth transistor T4 has an N-1 th scan signal Scan[n-1] of a logic low applied through an N-1 th scan line SCAN[n-1]. is turned on in response to In this case, an initialization voltage lower than the first power voltage applied through the first power line EVDD is applied to the initialization line VINI. By this operation, the gate node DTG of the driving transistor DT is initialized based on the initialization voltage.

During the sampling and second initialization period SAM, the first transistor T1 , the third transistor T3 , and the sixth transistor T6 have the Nth logic low applied through the Nth scan line SCAN[n]. It is turned on in response to the scan signal Scan[n]. The N-th scan line SCAN[n] is a scan line that transmits an N-th scan signal for driving the N-th sub-pixels located in the N-th scan line SCAN[n]. And the N-1th scan line SCAN[n-1] transmits an N-1th scan signal for driving the N-1th sub-pixels positioned at the front end of the Nth scan line SCAN[n]. scan line.

The data voltage applied through the first data line DL1 by the turn-on operation of the first transistor T1 is applied to the first electrode of the driving transistor DT. By the turn-on operation of the third transistor T3 , the driving transistor DT is in a diode-connected state. By the turn-on operation of the third transistor T3 , the threshold voltage of the driving transistor DT is sampled. And the data voltage applied to the first electrode of the driving transistor DT is charged in the gate node DTG through the third transistor T3. By the turn-on operation of the sixth transistor T6 , the organic light emitting diode OLED is initialized based on the initialization voltage.

The compensation concept of the sub-pixel according to the experimental example is expressed as a current equation as follows.

Ioled = K(Vsg - Vth)² = K{(VDD-(Vdata-|Vth|) - |Vth| }² = K(VDD-Vdata)²

In the above equation, Ioled is the current flowing through the organic light emitting diode (OLED), K is a constant, Vsg is the voltage between the source electrode and the gate electrode of the driving transistor DT, Vth is the threshold voltage of the driving transistor DT, and VDD is The first power voltage Vdata applied through the first power line EVDD means the data voltage applied through the first data line DL1.

However, in the sub-pixel according to the experimental example, the condition of the first power voltage applied through the first power line EVDD is not taken into account, so a defect issue resulting from the IR drop (IR-Drop) of the first power voltage appeared to exist. Since the voltage drop of the first power voltage causes image quality issues such as vertical luminance non-uniformity or cross-talk on the display panel, this is improved as in the following embodiment.

<First embodiment>

6 is a configuration diagram of a display panel for schematically explaining an organic light emitting display device according to a first embodiment of the present specification, and FIG. 7 is a waveform for explaining some driving characteristics of the sub-pixel circuit shown in FIG. 6 . It is also

As shown in FIGS. 6 and 7 , in the organic light emitting display device according to the first embodiment, the voltage drop applied from the outside is applied to offset the voltage drop of the first power voltage applied to the N-th sub-pixel SP. and an Nth voltage transfer unit VRD that performs an operation for transferring a voltage to the sub-pixel. Here, the outside means the outside of the display area AA.

The Nth voltage transfer unit VRD is disposed in the non-display area NA. For example, the Nth voltage transfer unit VRD may be disposed between the scan driver 130 disposed in the non-display area NA of the display panel and the sub-pixel SP disposed in the display area AA.

The scan driver 130 includes an N-th stage STG[G] for driving the N-th sub-pixel SP disposed on the N-th scan line SCAN[n]. The N-th stage STG[G] outputs an N-th emission control signal Em[n] and an N-th scan signal Scan[n] for driving the N-th sub-pixel SP. The N-th voltage transfer unit VRD is disposed to correspond to all scan lines as well as the N-th scan line SCAN[n]. That is, the N-th voltage transfer unit VRD is configured in plurality. In addition, by arranging the N-th voltage transfer unit VRD in the non-display area NA, it is lower than disposing the N-th voltage transfer unit VRD in each of the plurality of sub-pixels SP in the display area AA. Since the pixels SP can be highly integrated, a high-resolution display panel can be realized.

The N-th voltage transfer unit VRD serves to transfer the reference voltage applied through the reference voltage line VREF to the voltage transfer node VDN of the N-th sub-pixel SP for a specific period. The reference voltage may have a voltage level between the first power line EVDD and the second power line EVSS or a level corresponding to the first power voltage applied through the first power line EVDD.

The Nth voltage transfer unit VRD includes at least one switching transistor VT. At least one switching transistor VT is turned on or off in response to a control signal applied from the outside or a scan signal output from the scan driver 130 . The externally applied control signal may mean, for example, a control signal output from a timing controller or a power supply, but is not limited thereto.

In the first embodiment, as an example, the N-th voltage transfer unit VRD is separately disposed from the scan driver 130 . However, the Nth voltage transfer unit VRD may be included in the scan driver 130 .

And as in the first embodiment, when the N-th voltage transfer unit VRD is disposed in the non-display area NA, it is more process than when the circuit operating for applying the reference voltage is disposed inside the N-th sub-pixel SP. may have advantages. The advantages of the process are explained as follows. First, voltage transmission is possible without disposing a circuit necessary for voltage transmission inside the sub-pixel, and the number of contacts of electrodes or wires in the sub-pixel can be reduced due to the external arrangement of the voltage transmission circuit. Second, since it is possible to escape from the space constraint of the sub-pixel, it is advantageous for high integration, and it is possible to prevent a decrease in the aperture ratio when realizing a large screen and high resolution of a display panel.

The N-th sub-pixel SP according to the first embodiment includes first to seventh transistors T1 to T7 , a driving transistor DT, a capacitor Cst, and an organic light emitting diode OLED. The N-th sub-pixel SP according to the first embodiment is illustrated and described as an example implemented based on a total of eight transistors, but the embodiment of the present specification is not limited thereto. Hereinafter, the configuration and connection relationship of the N-th sub-pixel SP according to the first embodiment will be described.

The first transistor T1 has a gate electrode connected to an N-th scan line SCAN[n], a first electrode connected to a first data line DL1, and a first electrode and a driving transistor of the second transistor T2. The second electrode is connected to the first electrode of (DT). The first transistor T1 is turned on in response to the N-th scan signal Scan[n] of the logic low applied through the N-th scan line SCAN[n]. When the first transistor T1 is turned on, the data voltage applied through the first data line DL1 is charged in the second electrode (or between the first transistor and the second transistor) of the first transistor T1 .

The second transistor T2 has a gate electrode connected to an Nth emission control signal line EM[n], a first electrode connected to a second electrode of the first transistor T2, and a first power line EVDD and The second electrode is connected to the first electrode of the seventh transistor T7. The second transistor T2 is turned on in response to the Nth emission control signal Em[n] of the logic low applied through the Nth emission control signal line EM[n]. When the second transistor T2 is turned on, the data voltage charged in the second electrode of the first transistor T1 is transferred to one end of the capacitor Cst through the seventh transistor T7.

The third transistor T3 has a gate electrode connected to the Nth scan line SCAN[n], a first electrode connected to a second electrode of the driving transistor DT, and a second electrode connected to the gate electrode of the driving transistor DT. The electrode is connected. The third transistor T3 is turned on in response to the N-th scan signal Scan[n] of the logic low applied through the N-th scan line SCAN[n]. When the third transistor T3 is turned on, the driving transistor DT is in a diode connection state.

The fourth transistor T4 has a gate electrode connected to an N-1th scan line SCAN[n-1], a first electrode connected to an initialization line VINI, the other end of the capacitor Cst, and a third transistor ( The second electrode is connected to the second electrode of T3 and the gate electrode of the driving transistor DT. The fourth transistor T4 is turned on in response to the N-1th scan signal Scan[n-1] of the logic low applied through the N-1th scan line SCAN[n-1]. When the fourth transistor T4 is turned on, the gate node DTG of the driving transistor DT is initialized based on the initialization voltage.

The fifth transistor T5 has a gate electrode connected to the Nth emission control signal line EM[n], a first electrode connected to the second electrode of the driving transistor DT, and an anode electrode of the organic light emitting diode OLED. The second electrode is connected to The fifth transistor T5 is turned on in response to the Nth emission control signal Em[n] of the logic low applied through the Nth emission control signal line EM[n]. When the fifth transistor T5 is turned on, the organic light emitting diode OLED emits light in response to the driving current generated through the driving transistor DT.

The sixth transistor T6 has a gate electrode connected to an N-th scan line SCAN[n], a first electrode connected to an initialization line VINI, a second electrode of the driving transistor DT, and an organic light emitting diode OLED ), the second electrode is connected to the anode electrode. The sixth transistor T6 is turned on in response to the N-th scan signal Scan[n] of the logic low applied through the N-th scan line SCAN[n]. When the sixth transistor T6 is turned on, the organic light emitting diode OLED is initialized based on the initialization voltage.

The seventh transistor T7 has a gate electrode connected to the N-th emission control signal line EM[n] and a first electrode connected to the second electrode of the first power line EVDD and the second transistor T2, A second electrode is connected to one end of the capacitor Cst. The seventh transistor T7 is turned on in response to the Nth emission control signal Em[n] of the logic low applied through the Nth emission control signal line EM[n]. When the seventh transistor T7 is turned on, the data voltage charged in the second electrode of the first transistor T1 passes through the second transistor T2 and then is transferred to one end of the capacitor Cst.

The capacitor Cst has one end connected to the second electrode of the seventh transistor T7 and the other end connected to the second electrode of the fourth transistor T4. A node provided at one end of the second electrode of the seventh transistor T7 and the capacitor Cst is defined as a voltage transfer node VDN to which the reference voltage is transmitted. The organic light emitting diode OLED has an anode electrode connected to the second electrode of the fifth transistor T5 and a cathode electrode connected to the second power line EVSS.

The N-th sub-pixel SP according to the first embodiment operates in the order of a first initialization period INI, a sampling and second initialization period SAM, a sustain period HLD, and an emission period EMI. The first initialization period INI is a period for initializing the gate node DTG of the driving transistor DT. The sampling and second initialization period SAM is a period in which the organic light emitting diode OLED is initialized while sampling the threshold voltage of the driving transistor DT. The sustain period HLD is a period in which the data voltage applied through the first data line DL1 is maintained at a specific node. The emission period EMI is a period in which the organic light emitting diode OLED emits light based on a driving current generated based on the data voltage.

The N-th sub-pixel SP according to the first embodiment includes a first initialization period INI, sampling and As the second initialization period (SAM) is provided, compensation based on the internal circuit is made. The operating characteristics during these periods are briefly described as follows. However, it is assumed that the N-1th scan signal Scan[n-1] and the Nth scan signal Scan[n] are applied at logic low for one horizontal time period 1H. In addition, it is assumed that the first initialization period INI and the sampling and second initialization period SAM are performed for one horizontal time period (1H), respectively.

During the first initialization period INI, the fourth transistor T4 has an N-1 th scan signal Scan[n-1] of a logic low applied through an N-1 th scan line SCAN[n-1]. is turned on in response to In this case, an initialization voltage lower than the first power voltage applied through the first power line EVDD is applied to the initialization line VINI. By this operation, the gate node DTG of the driving transistor DT is initialized based on the initialization voltage.

During the sampling and second initialization period SAM, the first transistor T1 , the third transistor T3 , and the sixth transistor T6 have the Nth logic low applied through the Nth scan line SCAN[n]. It is turned on in response to the scan signal Scan[n]. The data voltage applied through the first data line DL1 by the turn-on operation of the first transistor T1 is applied to the first electrode of the driving transistor DT. By the turn-on operation of the third transistor T3 , the driving transistor DT is in a diode-connected state. By the turn-on operation of the third transistor T3 , the threshold voltage of the driving transistor DT is sampled. And the data voltage applied to the first electrode of the driving transistor DT is charged in the gate node DTG through the third transistor T3. By the turn-on operation of the sixth transistor T6 , the organic light emitting diode OLED is initialized based on the initialization voltage.

The N-th sub-pixel SP according to the first embodiment has an N-th voltage transfer unit VRD such that a voltage drop of the first power voltage is considered during the first initialization period INI and the sampling and second initialization period SAM. Since the reference voltage is applied from

Ioled = K(Vsg - Vth)² = K{(VDD-(Vdata-|Vth|+VDD-Vref) - |Vth| }² = K(Vref-Vdata)²

In the above equation, Ioled is the current flowing through the organic light emitting diode (OLED), K is a constant, Vsg is the voltage between the source electrode and the gate electrode of the driving transistor DT, Vth is the threshold voltage of the driving transistor DT, and VDD is The first power voltage applied through the first power line EVDD, Vref is the reference voltage applied through the reference line VREF, and Vdata is the data voltage applied through the first data line DL1.

As can be seen from the above equation, K is determined by the difference between the reference voltage and the data voltage. That is, according to the equation, the N-th sub-pixel SP according to the first embodiment has the first power line ( It can be seen that the voltage drop of the first power voltage applied through EVDD) can be compensated.

Hereinafter, when the Nth voltage transfer unit VRD is configured of two switching transistors as an example, the description related to the first embodiment will be further detailed as follows.

8 is a diagram illustrating in more detail the configuration of an Nth voltage transmitting unit according to the first embodiment of the present specification, and FIGS. 9 to 16 are diagrams for explaining in more detail a driving method according to the configuration of FIG. 8 .

As shown in FIG. 8 , the Nth voltage transfer unit VT includes a first switching transistor VTa and a second switching transistor VTb. The first switching transistor VTa is turned on or off in response to the N-1th scan signal applied through the N-1th scan line SCAN[n-1]. The second switching transistor VTb is turned on or off in response to the N-th scan signal applied through the N-th scan line SCAN[n].

The first switching transistor VTa has a gate electrode connected to an N-1th scan line SCAN[n-1], a first electrode connected to a reference voltage line VREF, and a second electrode of the seventh transistor T7 A second electrode is connected to the voltage transfer node VDN, which is one end of the electrode and the capacitor Cst. The second switching transistor VTb has a gate electrode connected to the N-th scan line SCAN[n], a first electrode connected to a reference voltage line VREF, and a second electrode and a capacitor ( Cst), the second electrode is connected to the voltage transfer node VDN. That is, in the case of the first switching transistor VTa and the second switching transistor VTb, the gate electrodes are connected to different scan lines, but the first electrode is connected to the first electrodes and the second electrode is connected to the second electrodes in common. .

Hereinafter, a driving method according to the first embodiment will be described in connection with the Nth voltage transfer unit VT and the Nth subpixel SP. In the following description, a diagonally hatched transistor means a turned-off state, and a non-slashed transistor is a turned-on state.

As shown in FIGS. 9 and 10 , during the first initialization period INI, the first switching transistor VTa has an Nth logic low applied through an N−1th scan line SCAN[n−1]. It is turned on in response to the -1 scan signal Scan[n-1]. At this time, the reference voltage transferred through the reference line VREF is applied to the N-th sub-pixel SP through the turned-on first switching transistor VTa. By this operation, the reference voltage is charged to one end of the capacitor Cst.

In addition, during the first initialization period INI, the fourth transistor T4 receives the N-1th scan signal Scan[n-1] of the logic low applied through the N-1th scan line SCAN[n-1]. ]) is turned on. In this case, an initialization voltage lower than the first power voltage applied through the first power line EVDD is applied to the initialization line VINI. By this operation, the gate node DTG of the driving transistor DT is initialized (or discharged with a residual voltage) based on the initialization voltage.

11 and 12 , during the sampling and second initialization period SAM, the second switching transistor VTb receives an N-th scan signal of logic low applied through an N-th scan line SCAN[n]. It is turned on in response to (Scan[n]). At this time, the reference voltage transferred through the reference line VREF is applied to the N-th sub-pixel SP through the turned-on second switching transistor VTb. By this operation, the reference voltage is continuously charged to one end of the capacitor Cst.

In addition, during the sampling and second initialization period (SAM), the first transistor T1, the third transistor T3, and the sixth transistor T6 are of the logic low applied through the N-th scan line SCAN[n]. It is turned on in response to the N-th scan signal Scan[n]. The data voltage applied through the first data line DL1 by the turn-on operation of the first transistor T1 is applied to the first electrode of the driving transistor DT. By the turn-on operation of the third transistor T3 , the driving transistor DT is in a diode-connected state. By the turn-on operation of the third transistor T3 , the threshold voltage of the driving transistor DT is sampled. And the data voltage applied to the first electrode of the driving transistor DT is charged in the gate node DTG through the third transistor T3. By the turn-on operation of the sixth transistor T6 , the organic light emitting diode OLED is initialized based on the initialization voltage.

13 and 14 , during the sustain period HLD, the first switching transistor VTa has a logic high N-1 applied through the N-1 th scan line SCAN[n-1]. It is turned off in response to the scan signal Scan[n-1]. The second switching transistor VTb is turned off in response to the logic-high N-th scan signal Scan[n] applied through the N-th scan line SCAN[n].

In addition, during the sustain period HLD, the first to seventh transistors T1 to T7 provide a logic-high N-1 th scan signal Scan[n-1] and a logic high N-th scan signal Scan[n]. ) and the Nth light emission control signal Em[n] of logic high is turned off. By this operation, the capacitor Cst charges and maintains the data voltage based on the voltage difference between both ends.

15 and 16 , during the light emission period EMI, the first switching transistor VTa and the second switching transistor VTb maintain the same turned-off state as before.

In addition, during the emission period EMI, the second transistor T2 , the fifth transistor T5 , and the seventh transistor T7 are turned on in response to the Nth emission control signal Em[n] of logic low. By the turn-on operation of the second transistor T2 , the fifth transistor T5 , and the seventh transistor T7 , the driving transistor DT is turned on while generating a driving current based on the data voltage for which the threshold voltage is compensated. The organic light emitting diode OLED emits light based on a driving current transmitted from the driving transistor DT.

The voltage of the voltage transfer node, the gate node, the source node, the drain node, and the threshold voltage Vth of the driving transistor during the first initialization period INI to the light emission period EMI, and the driving current Ioled flowing through the organic light emitting diode ) is shown in a table as follows. In Table 1 below, the first power voltage is denoted as VDD and the reference voltage is denoted as Vref.

First initialization period (INI) Sampling and Second Initialization Period (SAM) retention period (HLD) Luminescence Period (EMI) voltage transfer node Vref Vref Vref VDD gate node of the driving transistor Vini Vdata-|Vth| same as before Vdata-|Vth|+
(VDD-Vref) source node of the driving transistor - Vdata same as before VDD Drain node of the driving transistor - Vdata-|Vth| same as before - drive current Ioled = K(Vsg - Vth)² = K{ VDD-(Vdata-|Vth|+VDD-Vref)-Vth)}²
= K(Vref-Vdata)²

As can be seen from the above description, since the first embodiment can prevent or solve a defect issue caused by a voltage drop of the first power voltage, image quality issues such as vertical luminance non-uniformity or cross-talk on the display panel There is an effect that can prevent or improve the phenomenon caused. In addition, in the first embodiment, by disposing a circuit for transmitting the reference voltage to the sub-pixel in the non-display area, it is possible to reduce the number of contacts of electrodes or wires in the sub-pixel, as well as advantageous to high integration, so that the display panel has a large screen and When implementing a high resolution, there is an effect of preventing a decrease in the aperture ratio.

<Second embodiment>

17 is a configuration diagram of a display panel for schematically explaining an organic light emitting display device according to a second exemplary embodiment of the present specification, and FIG. 18 is a waveform for explaining some driving characteristics of the sub-pixel circuit shown in FIG. 17 . It is also Since the second embodiment according to the present specification is a modification of the first embodiment, the description overlapping with the first embodiment may be omitted or briefly described.

17 and 18 , in the organic light emitting display device according to the second embodiment, the voltage drop applied from the outside is applied to offset the voltage drop of the first power voltage applied to the N-th sub-pixel SP. and an Nth voltage transfer unit VRD that performs an operation for transferring a voltage to the sub-pixel. Here, the outside means the outside of the display area AA.

The Nth voltage transfer unit VRD is disposed in the non-display area NA. The N-th voltage transfer unit VRD serves to transfer the reference voltage applied through the reference voltage line VREF to the N-th sub-pixel SP for a specific period. The Nth voltage transfer unit VRD includes one switching transistor VT.

The switching transistor VT has a gate electrode connected to an N-th scan line SCAN[n], a first electrode connected to a reference voltage line VREF, and a second electrode and a capacitor Cst of the seventh transistor T7. A second electrode is connected to one end of the The switching transistor VT is turned on or off in response to the N-th scan signal Scan[n] applied through the N-th scan line SCAN[n].

As in the second embodiment, if the signal is configured so that a logic low period of at least one horizontal time (1H) overlaps between the previous scan signal and the current scan signal, the first initialization period (INI) and the sampling and second initialization period (SAM) ) can be sufficiently obtained. Therefore, if the N-1th scan line SCAN[n-1] and the logic low section of the Nth scan line SCAN[n] are configured to overlap, the Nth voltage transfer unit ( VRD) can be configured.

In the second embodiment, since the previous scan signal and the current scan signal overlap and are applied, the N-th voltage transfer unit VRD does not change from the turn-off to the turn-on state for a specific period, and the turn-on state can be maintained for at least 2 horizontal times. Therefore, it is possible to prevent the voltage supply from being cut off or the node from electrically floating when the reference voltage is transferred. In addition, in the second embodiment, since the N-th voltage transfer unit VRD is configured with one switching transistor VT, the circuit can be simplified enough to further reduce the non-display area (or bezel area) of the display panel. .

Unlike the 1 horizontal time can signal, the 2 horizontal time scan signal can provide a compensation time only in the overlapping driving between pulses. Therefore, the reason why the reference voltage is applied to the sub-pixels in the initialization period INI is inevitable due to overlapping driving between scan signals. It is possible to prevent the phenomenon of electrically floating (floating).

The N-th sub-pixel SP according to the second exemplary embodiment includes first to seventh transistors T1 to T7 , a driving transistor DT, a capacitor Cst, and an organic light emitting diode OLED. Unlike the first embodiment, in the N-th sub-pixel SP according to the second embodiment, the driving transistor DT and the organic light emitting diode OLED are simultaneously operated by the N-1 th scan signal Scan[n-1]. is initialized Hereinafter, the configuration and connection relationship of the N-th sub-pixel SP according to the second embodiment will be described.

The first transistor T1 has a gate electrode connected to an N-th scan line SCAN[n], a first electrode connected to a first data line DL1, and a first electrode and a driving transistor of the second transistor T2. The second electrode is connected to the first electrode of (DT). The first transistor T1 is turned on in response to the N-th scan signal Scan[n] of the logic low applied through the N-th scan line SCAN[n]. When the first transistor T1 is turned on, the data voltage applied through the first data line DL1 is charged to the second electrode of the first transistor T1 .

The second transistor T2 has a gate electrode connected to an Nth emission control signal line EM[n], a first electrode connected to a second electrode of the first transistor T2, and a first power line EVDD and The second electrode is connected to the first electrode of the seventh transistor T7. The second transistor T2 is turned on in response to the Nth emission control signal Em[n] of the logic low applied through the Nth emission control signal line EM[n]. When the second transistor T2 is turned on, the data voltage charged in the second electrode of the first transistor T1 is transferred to one end of the capacitor Cst through the seventh transistor T7.

The third transistor T3 has a gate electrode connected to the Nth scan line SCAN[n], a first electrode connected to a second electrode of the driving transistor DT, and a second electrode connected to the gate electrode of the driving transistor DT. The electrode is connected. The third transistor T3 is turned on in response to the N-th scan signal Scan[n] of the logic low applied through the N-th scan line SCAN[n]. When the third transistor T3 is turned on, the driving transistor DT is in a diode connection state.

The fourth transistor T4 has a gate electrode connected to an N-1th scan line SCAN[n-1], a first electrode connected to an initialization line VINI, the other end of the capacitor Cst, and a third transistor ( The second electrode is connected to the second electrode of T3 and the gate electrode of the driving transistor DT. The fourth transistor T4 is turned on in response to the N-1th scan signal Scan[n-1] of the logic low applied through the N-1th scan line SCAN[n-1]. When the fourth transistor T4 is turned on, the gate node DTG of the driving transistor DT is initialized based on the initialization voltage.

The fifth transistor T5 has a gate electrode connected to the Nth emission control signal line EM[n], a first electrode connected to the second electrode of the driving transistor DT, and an anode electrode of the organic light emitting diode OLED. The second electrode is connected to The fifth transistor T5 is turned on in response to the Nth emission control signal Em[n] of the logic low applied through the Nth emission control signal line EM[n]. When the fifth transistor T5 is turned on, the organic light emitting diode OLED emits light in response to the driving current generated through the driving transistor DT.

The sixth transistor T6 has a gate electrode connected to an N-1 th scan line SCAN[n-1], a first electrode connected to an initialization line VINI, and a second electrode and organic element of the driving transistor DT. A second electrode is connected to the anode electrode of the light emitting diode (OLED). The sixth transistor T6 is turned on in response to the N-1th scan signal Scan[n-1] of the logic low applied through the N-1th scan line SCAN[n-1]. When the sixth transistor T6 is turned on, the organic light emitting diode OLED is initialized based on the initialization voltage.

The seventh transistor T7 has a gate electrode connected to the N-th emission control signal line EM[n] and a first electrode connected to the second electrode of the first power line EVDD and the second transistor T2, A second electrode is connected to one end of the capacitor Cst. The seventh transistor T7 is turned on in response to the Nth emission control signal Em[n] of the logic low applied through the Nth emission control signal line EM[n]. When the seventh transistor T7 is turned on, the data voltage charged in the second electrode of the first transistor T1 passes through the second transistor T2 and then is transferred to one end of the capacitor Cst.

The capacitor Cst has one end connected to the second electrode of the seventh transistor T7 and the other end connected to the second electrode of the fourth transistor T4. The organic light emitting diode OLED has an anode electrode connected to the second electrode of the fifth transistor T5 and a cathode electrode connected to the second power line EVSS.

The N-th sub-pixel SP according to the second exemplary embodiment operates in the order of the initialization period INI, the sampling period SAM, the sustain period HLD, and the light emission period EMI. The initialization period INI is a period in which the gate node DTG of the driving transistor DT and the organic light emitting diode OLED are simultaneously initialized. The sampling period SAM is a period for sampling the threshold voltage of the driving transistor DT. The sustain period HLD is a period in which the data voltage applied through the first data line DL1 is maintained at a specific node. The emission period EMI is a period in which the organic light emitting diode OLED emits light based on a driving current generated based on the data voltage.

The N-th sub-pixel SP according to the second exemplary embodiment includes a period in which the N-th emission control signal Em[n] is not applied (a period in which a logic high is maintained), an initialization period INI, and a sampling period SAM ), compensation based on the internal circuit is made. The operating characteristics during these periods are briefly described as follows. The N-1th scan signal Scan[n-1] and the Nth scan signal Scan[n] are applied as logic low for 2 horizontal times (2H), and the two signals overlap for 1 horizontal time (1H) Take as an example

During the initialization period INI, the fourth transistor T4 and the sixth transistor T6 receive the N-1th scan signal Scan[ n-1]) and are simultaneously turned on. In this case, an initialization voltage lower than the first power voltage applied through the first power line EVDD is applied to the initialization line VINI. By this operation, the gate node DTG of the driving transistor DT and the organic light emitting diode OLED are initialized based on the initialization voltage.

During the sampling period SAM, the first transistor T1 and the third transistor T3 correspond to the N-th scan signal Scan[n] of the logic low applied through the N-th scan line SCAN[n]. is turned on The data voltage applied through the first data line DL1 by the turn-on operation of the first transistor T1 is transferred to the N-th sub-pixel SP. The driving transistor DT is in a diode connection state by the turn-on operation of the third transistor T3 . By the turn-on operation of the third transistor T3 , the threshold voltage of the driving transistor DT is sampled.

The N-th sub-pixel SP according to the second embodiment also receives the reference voltage from the N-th voltage transfer unit VRD such that the voltage drop of the first power voltage is taken into account during the initialization period INI and the sampling period SAM. do. Accordingly, the N-th sub-pixel SP according to the second exemplary embodiment may also compensate for the voltage drop of the first power voltage applied through the first power line EVDD by the reference voltage.

Therefore, since the second embodiment has the Nth voltage transfer unit VRD that can apply the reference voltage during the initialization period INI and the sampling period SAM, the same effect as the first embodiment can be achieved. In addition, the second embodiment can prevent the voltage supply from being cut off or the node from electrically floating when the reference voltage is transmitted. In addition, in the second embodiment, since the N-th voltage transfer unit VRD is configured with one switching transistor VT, the circuit can be simplified enough to further reduce the non-display area (or bezel area) of the display panel. .

<Third embodiment>

19 is a configuration diagram of a display panel for schematically explaining an organic light emitting display device according to a third embodiment of the present specification, and FIG. 20 is a waveform for explaining some driving characteristics of the sub-pixel circuit shown in FIG. 19 . It is also Since the third embodiment according to the present specification is a modification of the first and second embodiments, the description overlapping with the first and second embodiments may be omitted or briefly described.

19 and 20 , in the organic light emitting display device according to the third embodiment, the voltage drop applied from the outside is applied to offset the voltage drop of the first power voltage applied to the N-th sub-pixel SP. and an Nth voltage transfer unit VRD that performs an operation for transferring a voltage to the sub-pixel. Here, the outside means the outside of the display area AA.

The Nth voltage transfer unit VRD is disposed in the non-display area NA. The N-th voltage transfer unit VRD serves to transfer the reference voltage applied through the reference voltage line VREF to the N-th sub-pixel SP for a specific period. The Nth voltage transfer unit VRD includes one switching transistor VT.

The switching transistor VT has a gate electrode connected to an N-1 th scan line SCAN[n-1], a first electrode connected to a reference voltage line VREF, a second electrode of a seventh transistor T7, and The second electrode is connected to the voltage transfer node VDN, which is one end of the capacitor Cst. The switching transistor VT is turned on or off in response to the N-1 th scan signal Scan[n-1] applied through the N-1 th scan line SCAN[n-1].

As in the third embodiment, if the signal is configured so that a logic low period of at least one horizontal time (1H) overlaps between the previous scan signal and the current scan signal, the first initialization period (INI) and the sampling and second initialization period (SAM) ) to have enough time to have Therefore, if the N-1th scan line SCAN[n-1] and the logic low section of the Nth scan line SCAN[n] are configured to overlap, the Nth voltage transfer unit ( VRD) can be configured.

The N-th sub-pixel SP includes first to third transistors T1 to T3, fifth to seventh transistors T5 to T7, a driving transistor DT, a capacitor Cst, and an organic light emitting diode OLED. include The N-th sub-pixel SP according to the third embodiment has a structure in which the fourth transistor T4 is deleted compared to the second embodiment.

Unlike the first embodiment, in the N-th sub-pixel SP according to the third embodiment, the diode connection of the driving transistor DT and the initialization of the organic light emitting diode OLED are simultaneously performed. Specifically, the driving transistor DT enters a diode connection state by the N-1 th scan signal Scan[n-1], and the organic light emitting diode OLED is initialized. In addition, the fifth transistor T5 is turned on by the N+1th emission control signal Em[n+1] to transmit the driving current generated through the driving transistor DT to the organic light emitting diode OLED. . Hereinafter, the configuration and connection relationship of the N-th sub-pixel SP according to the third embodiment will be described.

The first transistor T1 has a gate electrode connected to an N-th scan line SCAN[n], a first electrode connected to a first data line DL1, and a first electrode and a driving transistor of the second transistor T2. The second electrode is connected to the first electrode of (DT). The first transistor T1 is turned on in response to the N-th scan signal Scan[n] of the logic low applied through the N-th scan line SCAN[n]. When the first transistor T1 is turned on, the data voltage applied through the first data line DL1 is charged to the second electrode of the first transistor T1 .

The second transistor T2 has a gate electrode connected to an Nth emission control signal line EM[n], a first electrode connected to a second electrode of the first transistor T2, and a first power line EVDD and The second electrode is connected to the first electrode of the seventh transistor T7. The second transistor T2 is turned on in response to the Nth emission control signal Em[n] of the logic low applied through the Nth emission control signal line EM[n]. When the second transistor T2 is turned on, the data voltage charged in the second electrode of the first transistor T1 is transferred to one end of the capacitor Cst through the seventh transistor T7.

The third transistor T3 has a gate electrode connected to the N-1th scan line SCAN[n-1], a first electrode connected to the second electrode of the driving transistor DT, and a gate of the driving transistor DT. A second electrode is connected to the electrode. The third transistor T3 is turned on in response to the N-1th scan signal Scan[n-1] of the logic low applied through the N-1th scan line SCAN[n-1]. When the third transistor T3 is turned on, the driving transistor DT is in a diode connection state.

The fifth transistor T5 has a gate electrode connected to an N+1th emission control signal line EM[n+1], a first electrode connected to a second electrode of the driving transistor DT, and an organic light emitting diode OLED ), the second electrode is connected to the anode electrode. The fifth transistor T5 is turned on in response to the N+1th emission control signal Em[n+1] of the logic low applied through the N+1th emission control signal line EM[n+1]. . When the fifth transistor T5 is turned on, the organic light emitting diode OLED emits light in response to the driving current generated through the driving transistor DT.

The sixth transistor T6 has a gate electrode connected to an N-1 th scan line SCAN[n-1], a first electrode connected to an initialization line VINI, and a second electrode and organic element of the driving transistor DT. A second electrode is connected to the anode electrode of the light emitting diode (OLED). The sixth transistor T6 is turned on in response to the N-1th scan signal Scan[n-1] of the logic low applied through the N-1th scan line SCAN[n-1]. When the sixth transistor T6 is turned on, the organic light emitting diode OLED is initialized based on the initialization voltage.

The seventh transistor T7 has a gate electrode connected to the N-th emission control signal line EM[n] and a first electrode connected to the second electrode of the first power line EVDD and the second transistor T2, A second electrode is connected to one end of the capacitor Cst. The seventh transistor T7 is turned on in response to the Nth emission control signal Em[n] of the logic low applied through the Nth emission control signal line EM[n]. When the seventh transistor T7 is turned on, the data voltage charged in the second electrode of the first transistor T1 passes through the second transistor T2 and then is transferred to one end of the capacitor Cst.

The capacitor Cst has one end connected to the second electrode of the seventh transistor T7 and the other end connected to the second electrode of the fourth transistor T4. A node provided at one end of the second electrode of the seventh transistor T7 and the capacitor Cst is defined as a voltage transfer node VDN to which the reference voltage is transmitted. The organic light emitting diode OLED has an anode electrode connected to the second electrode of the fifth transistor T5 and a cathode electrode connected to the second power line EVSS.

The N-th sub-pixel SP according to the third exemplary embodiment operates in the order of the initialization & sampling period INI & SAM, the sustain period HLD, and the light emission period EMI. The initialization & sampling period INI & SAM is a period of sampling the threshold voltage of the driving transistor DT while initializing the organic light emitting diode OLED. The sustain period HLD is a period in which the data voltage applied through the first data line DL1 is maintained at a specific node. The emission period EMI is a period in which the organic light emitting diode OLED emits light based on a driving current generated based on the data voltage. The emission period EMI is made by the N+1th emission control signal Em[n+1] instead of the Nth emission control signal Em[n].

When the N-th sub-pixel SP is driven in such a manner that the previous scan signal and the current scan signal overlap as in the third embodiment, the period during which the emission control signal is applied is longer than 3 horizontal times, for example, 4 After extending to the horizontal time, the driving method can be changed to emit light based on the light emission control signal of the rear stage. That is, the method of emitting light of the Nth sub-pixel SP, which is the current stage, based on the N+1th emission control signal Em[n+1], which is the emission control signal of the subsequent stage, is used to form the emission period EMI. This means that you are free to choose the signal. This method has an advantage in that it is possible to avoid space restrictions when designing or changing the layout of sub-pixels (because the degree of freedom for arrangement of signal lines is high).

The N-th sub-pixel SP according to the third exemplary embodiment performs an initialization & sampling period (INI & SAM) during a period in which the N-th emission control signal Em[n] is not applied (a period in which a logic high is maintained). Compensation based on the internal circuit is made as it has. The operating characteristics during this period are briefly described as follows. However, the N-1th scan signal Scan[n-1] and the Nth scan signal Scan[n] are applied at logic low for 2 horizontal time (2H), and both signals for 1 horizontal time (1H) Take, for example, the overlapping of .

During the initialization & sampling period (INI & SAM), the third transistor T3 and the sixth transistor T6 perform the N-1th scan of the logic low applied through the N-1th scan line SCAN[n-1]. It is simultaneously turned on in response to the signal Scan[n-1]. By the turn-on operation of the third transistor T3 and the sixth transistor T6 , the threshold voltage of the driving transistor DT is sampled and the organic light emitting diode OLED is initialized based on the initialization voltage.

The N-th sub-pixel SP according to the third embodiment also receives the reference voltage from the N-th voltage transfer unit VRD so that the voltage drop of the first power voltage is taken into account during the initialization & sampling period INI & SAM. Accordingly, the N-th sub-pixel SP according to the third embodiment is also the voltage of the first power voltage applied through the first power line EVDD by the reference voltage applied during the initialization & sampling period INI & SAM. The drop can be compensated.

Therefore, since the third embodiment has the Nth voltage transfer unit VRD that can apply the reference voltage during the initialization & sampling period INI & SAM, the same effect as the first embodiment can be expressed. In addition, the third embodiment can prevent the voltage supply from being cut off or the node from electrically floating when the reference voltage is transmitted. In addition, in the third embodiment, since the N-th voltage transfer unit VRD is configured with one switching transistor VT, the circuit can be simplified enough to further reduce the non-display area (or bezel area) of the display panel. . In addition, since the third embodiment has a high degree of freedom for the arrangement of signal lines, it is possible to overcome the space constraint when designing or changing the layout of the sub-pixels.

As described above, the present specification provides a method to prevent or improve a phenomenon that causes image quality issues such as vertical luminance non-uniformity or cross-talk on the display panel by compensating for time-varying characteristics (or change over time) in consideration of the voltage drop of the first power supply voltage. can have an effect. In addition, according to the present specification, by arranging a circuit for transmitting the reference voltage to the sub-pixel in the non-display area, the number of contacts of electrodes or wires in the sub-pixel can be reduced, and it is advantageous for high integration to realize a large screen and high resolution of the display panel. In this case, there is an effect of preventing a decrease in the aperture ratio.

An electroluminescent display device and a driving method thereof according to an embodiment of the present specification may be described as follows.

In the electroluminescent display device according to an embodiment of the present specification, the electroluminescent display device includes a display panel having a display area for displaying an image and a non-display area for not displaying an image, sub-pixels positioned in the display area, and a ratio and a voltage transfer unit located in the display area and transmitting a reference voltage to the sub-pixels in response to a signal applied from the outside of the display panel or a signal generated on the display panel.

The display panel may include a scan line to which a plurality of sub-pixels are connected, and a voltage transfer unit may be disposed for each scan line of the non-display area.

The voltage transfer unit may operate to output the reference voltage during a sampling period for sampling the threshold voltage of the driving transistor of the sub-pixel.

The voltage transfer unit is turned on or turned in response to the N-1th scan signal for driving the N-1th subpixels of the N-1th scan line or the Nth scan signal for driving the Nth subpixels of the Nth scan line It may include at least one switching transistor that is turned off.

The voltage transfer unit transmits the first switching transistor turned on or off in response to the N-1th scan signal for driving the N-1th subpixels of the N-1th scan line and the Nth subpixels of the Nth scan line. It may include a second switching transistor that is turned on or turned off in response to the N-th scan signal for driving.

In the first switching transistor, a gate electrode is connected to an N-1th scan line, a first electrode is connected to a reference voltage line that transmits a reference voltage, a second electrode is connected to one end of a capacitor included in the sub-pixel, and the second The switching transistor may have a gate electrode connected to the N-th scan line, a first electrode connected to a reference voltage line, and a second electrode connected to one end of a capacitor included in the sub-pixel, and the other end of the capacitor is driving included in the sub-pixel A transistor may be connected to the gate electrode.

The voltage transfer unit may include a switching transistor having a gate electrode connected to the N-th scan line, a first electrode connected to a reference voltage line transmitting a reference voltage, and a second electrode connected to one end of a capacitor included in the sub-pixel, The other end of the capacitor may be connected to a gate electrode of a driving transistor included in the sub-pixel.

The voltage transfer unit may include a switching transistor having a gate electrode connected to the N-1th scan line, a first electrode connected to a reference voltage line transmitting a reference voltage, and a second electrode connected to one end of a capacitor included in the sub-pixel. and the other end of the capacitor may be connected to a gate electrode of a driving transistor included in the sub-pixel.

The sub-pixel includes a first transistor having a gate electrode connected to an Nth scan line and a first electrode connected to a first data line, a gate electrode connected to an Nth emission control signal line, and a first transistor connected to a second electrode of the first transistor. A driving transistor with a second transistor connected to an electrode and a second electrode connected to a first power line, a gate electrode connected to a gate node, and a second electrode of the first transistor and a first electrode connected to the first electrode of the second transistor and a third transistor having a gate electrode connected to the Nth scan line, a first electrode connected to a second electrode of the driving transistor, and a second electrode connected to a gate electrode of the driving transistor, and a gate electrode connected to the N-1th scan line A fourth transistor connected to this, the first electrode connected to the initialization line, the second electrode of the third transistor and the second electrode connected to the gate electrode of the driving transistor, and the gate electrode connected to the Nth emission control signal line, the driving transistor a fifth transistor having a first electrode connected to the second electrode of , a seventh transistor having a gate electrode connected to the Nth emission control signal line and a first electrode connected to a first power line and a second electrode of the second transistor, and a fourth transistor having one end connected to the second electrode of the seventh transistor It may include a capacitor connected to the second electrode of the transistor, and an organic light emitting diode having an anode electrode connected to the second electrode of the fifth transistor and a cathode electrode connected to a second power line.

The sub-pixel includes a first transistor having a gate electrode connected to an Nth scan line and a first electrode connected to a first data line, a gate electrode connected to an Nth emission control signal line, and a first transistor connected to a second electrode of the first transistor. A driving transistor with a second transistor connected to an electrode and a second electrode connected to a first power line, a gate electrode connected to a gate node, and a second electrode of the first transistor and a first electrode connected to the first electrode of the second transistor and a third transistor having a gate electrode connected to the Nth scan line, a first electrode connected to a second electrode of the driving transistor, and a second electrode connected to a gate electrode of the driving transistor, and a gate electrode connected to the N-1th scan line A fourth transistor connected to this, the first electrode connected to the initialization line, the second electrode of the third transistor and the second electrode connected to the gate electrode of the driving transistor, and the gate electrode connected to the Nth emission control signal line, the driving transistor a fifth transistor having a first electrode connected to the second electrode of A transistor, a gate electrode connected to the N-th light emission control signal line, a seventh transistor having a first electrode connected to a first power line and a second electrode of the second transistor, and one end connected to a second electrode of the seventh transistor, It may include a capacitor connected to the second electrode of the fourth transistor, and an organic light emitting diode having an anode electrode connected to the second electrode of the fifth transistor and a cathode electrode connected to a second power line.

The sub-pixel includes a first transistor having a gate electrode connected to an Nth scan line and a first electrode connected to a first data line, a gate electrode connected to an Nth emission control signal line, and a first transistor connected to a second electrode of the first transistor. A driving transistor with a second transistor connected to an electrode and a second electrode connected to a first power line, a gate electrode connected to a gate node, and a second electrode of the first transistor and a first electrode connected to the first electrode of the second transistor and a third transistor having a gate electrode connected to an N-1th scan line, a first electrode connected to a second electrode of the driving transistor, and a second electrode connected to a gate electrode of the driving transistor, and an N+1th emission control signal A fifth transistor having a gate electrode connected to the line and a first electrode connected to a second electrode of the driving transistor, a gate electrode connected to an N-1th scan line, a first electrode connected to an initialization line, and a second electrode connected to the driving transistor A sixth transistor having a second electrode connected to the electrode, a seventh transistor having a gate electrode connected to an Nth emission control signal line, and a first electrode connected to a second electrode of the first power line and the second transistor, and a seventh transistor an organic light emitting diode having one end connected to the second electrode of the can do.

A method of driving an electroluminescent display device according to an exemplary embodiment of the present specification includes a display panel having a display area for displaying an image and a non-display area for not displaying an image, a sub-pixel positioned in the display area, and a sub-pixel positioned in the non-display area A driving method of an electroluminescent display device comprising a voltage transfer unit that transmits a reference voltage to a subpixel, the driving method of the electroluminescent display device comprising: an initialization step for initializing a subpixel; and a threshold voltage of a driving transistor of the subpixel and a sampling step to compensate. During the sampling step, the voltage transfer unit operates in response to a signal applied from the outside of the display panel or a signal generated on the display panel.

The voltage transfer unit is turned on during the first period based on the N-1th scan signal for driving the N-1th subpixels of the N-1th scan line, and the Nth subpixels for driving the Nth subpixels of the Nth scan line are turned on during the first period. Based on the N scan signal, the voltage transfer unit may be turned on during a second period following the first period, and the reference voltage may be transferred to the N-th sub-pixel in the first period and the second period.

The N-th sub-pixel of the display panel may be driven by being divided into an initialization step and a sampling step based on the N-th scan signal and the N-1th scan signal overlapping for at least one horizontal time.

The voltage transfer unit may be turned on based on an N-th scan signal for driving the N-th sub-pixel so that the reference voltage is transmitted to the N-th sub-pixel.

In the N-th sub-pixel of the display panel, the initialization step and the sampling step may be simultaneously performed based on the N-th scan signal and the N-1th scan signal overlapping for at least one horizontal time.

The voltage transfer unit may be turned on based on an N-1 th scan signal for driving the N-1 th sub-pixel so that the reference voltage is transmitted to the N-th sub-pixel.

Although the embodiments of the present specification have been described above with reference to the accompanying drawings, the technical configuration of the above-described specification can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present specification. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present specification is indicated by the following claims rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present specification.

VRD: Nth voltage transfer unit VREF: Reference voltage line
NA: Non-display area AA: Display area
SP: sub-pixel(s), N-th sub-pixels T1 to T7: first to seventh transistors
DT: driving transistor Cst: capacitor
OLED: organic light emitting diode

Claims (17)

a display panel having a display area for displaying an image and a non-display area for not displaying an image;
a sub-pixel positioned in the display area; and
and a voltage transfer unit located in the non-display area and transmitting a reference voltage to the sub-pixels in response to a signal applied from outside the display panel or a signal generated on the display panel;
The sub-pixel is
a first transistor having a gate electrode connected to the Nth scan line and a first electrode connected to a first data line;
a second transistor having a gate electrode connected to an Nth emission control signal line, a first electrode connected to a second electrode of the first transistor, and a second electrode connected to a first power supply line;
a driving transistor having a gate electrode connected to a gate node and a second electrode connected to the second electrode of the first transistor and a first electrode connected to the first electrode of the second transistor;
a third transistor having a gate electrode connected to the Nth scan line, a first electrode connected to a second electrode of the driving transistor, and a second electrode connected to a gate electrode of the driving transistor;
a fourth transistor having a gate electrode connected to an N-1th scan line, a first electrode connected to an initialization line, and a second electrode connected to a second electrode of the third transistor and a gate electrode of the driving transistor;
a fifth transistor having a gate electrode connected to the Nth emission control signal line and a first electrode connected to a second electrode of the driving transistor;
a sixth transistor having a gate electrode connected to the Nth scan line, a first electrode connected to the initialization line, and a second electrode connected to a second electrode of the driving transistor;
a seventh transistor having a gate electrode connected to the Nth emission control signal line and a first electrode connected to a first power line and a second electrode of the second transistor;
a capacitor having one end connected to the second electrode of the seventh transistor and the other end connected to the second electrode of the fourth transistor;
and an organic light emitting diode having an anode electrode connected to the second electrode of the fifth transistor and a cathode electrode connected to a second power line. According to claim 1,
the display panel includes a scan line to which a plurality of sub-pixels are connected;
The voltage transfer unit is disposed for each scan line of the non-display area. According to claim 1,
The voltage transfer unit
An electroluminescent display device operable to output the reference voltage during a sampling period for sampling a threshold voltage of the driving transistor of the sub-pixel. 3. The method of claim 2,
The voltage transfer unit
Turn on or turn off in response to an N-1th scan signal for driving the N-1th subpixels of the N-1th scan line or an Nth scan signal for driving the Nth subpixels of the Nth scan line An electroluminescent display device comprising at least one switching transistor. 3. The method of claim 2,
The voltage transfer unit
a first switching transistor turned on or off in response to an N-1 th scan signal for driving the N-1 th sub-pixels of the N-1 th scan line;
and a second switching transistor turned on or off in response to an N-th scan signal for driving the N-th sub-pixels of the N-th scan line. 6. The method of claim 5,
In the first switching transistor, a gate electrode is connected to the N-1th scan line, a first electrode is connected to a reference voltage line that transmits the reference voltage, and a second electrode is connected to one end of a capacitor included in the sub-pixel. becomes,
In the second switching transistor, a gate electrode is connected to the Nth scan line, a first electrode is connected to the reference voltage line, and a second electrode is connected to one end of the capacitor,
The other end of the capacitor is connected to a gate electrode of a driving transistor included in the sub-pixel. 6. The method of claim 5,
The voltage transfer unit
a switching transistor having a gate electrode connected to the N-th scan line, a first electrode connected to a reference voltage line transmitting the reference voltage, and a second electrode connected to one end of a capacitor included in the sub-pixel,
The other end of the capacitor is connected to a gate electrode of a driving transistor included in the sub-pixel. 6. The method of claim 5,
The voltage transfer unit
a switching transistor having a gate electrode connected to the N-1th scan line, a first electrode connected to a reference voltage line transmitting the reference voltage, and a second electrode connected to one end of a capacitor included in the sub-pixel,
The other end of the capacitor is connected to a gate electrode of a driving transistor included in the sub-pixel. delete a display panel having a display area for displaying an image and a non-display area for not displaying an image;
a sub-pixel positioned in the display area; and
and a voltage transfer unit located in the non-display area and transmitting a reference voltage to the sub-pixels in response to a signal applied from outside the display panel or a signal generated on the display panel;
The sub-pixel is
a first transistor having a gate electrode connected to the Nth scan line and a first electrode connected to a first data line;
a second transistor having a gate electrode connected to an Nth emission control signal line, a first electrode connected to a second electrode of the first transistor, and a second electrode connected to a first power supply line;
a driving transistor having a gate electrode connected to a gate node and a second electrode connected to the second electrode of the first transistor and a first electrode connected to the first electrode of the second transistor;
a third transistor having a gate electrode connected to the Nth scan line, a first electrode connected to a second electrode of the driving transistor, and a second electrode connected to a gate electrode of the driving transistor;
a fourth transistor having a gate electrode connected to an N-1th scan line, a first electrode connected to an initialization line, and a second electrode connected to a second electrode of the third transistor and a gate electrode of the driving transistor;
a fifth transistor having a gate electrode connected to the Nth emission control signal line and a first electrode connected to a second electrode of the driving transistor;
a sixth transistor having a gate electrode connected to the N-1th scan line, a first electrode connected to the initialization line, and a second electrode connected to a second electrode of the driving transistor;
a seventh transistor having a gate electrode connected to the Nth emission control signal line and a first electrode connected to a first power line and a second electrode of the second transistor;
a capacitor having one end connected to the second electrode of the seventh transistor and the other end connected to the second electrode of the third transistor;
and an organic light emitting diode having an anode electrode connected to the second electrode of the fifth transistor and a cathode electrode connected to a second power line. a display panel having a display area for displaying an image and a non-display area for not displaying an image;
a sub-pixel positioned in the display area; and
and a voltage transfer unit located in the non-display area and transmitting a reference voltage to the sub-pixels in response to a signal applied from outside the display panel or a signal generated on the display panel;
The sub-pixel is
a first transistor having a gate electrode connected to the Nth scan line and a first electrode connected to a first data line;
a second transistor having a gate electrode connected to an Nth emission control signal line, a first electrode connected to a second electrode of the first transistor, and a second electrode connected to a first power supply line;
a driving transistor having a gate electrode connected to a gate node and a second electrode connected to the second electrode of the first transistor and a first electrode connected to the first electrode of the second transistor;
a third transistor having a gate electrode connected to an N-1th scan line, a first electrode connected to a second electrode of the driving transistor, and a second electrode connected to a gate electrode of the driving transistor;
a fifth transistor having a gate electrode connected to an N+1th emission control signal line and a first electrode connected to a second electrode of the driving transistor;
a sixth transistor having a gate electrode connected to an N-1th scan line, a first electrode connected to an initialization line, and a second electrode connected to a second electrode of the driving transistor;
a seventh transistor having a gate electrode connected to the Nth emission control signal line and a first electrode connected to a first power line and a second electrode of the second transistor;
a capacitor having one end connected to the second electrode of the seventh transistor and the other end connected to the second electrode of the third transistor;
and an organic light emitting diode having an anode electrode connected to the second electrode of the fifth transistor and a cathode electrode connected to a second power line. In the driving method of the electroluminescent display device manufactured according to claim 1,
an initialization step for initializing the sub-pixels; and
a sampling step for compensating for a threshold voltage of a driving transistor of the sub-pixel;
During the sampling step, the voltage transfer unit operates in response to a signal applied from the outside of the display panel or a signal generated on the display panel. 13. The method of claim 12,
turning on the voltage transfer unit for a first period based on an N-1th scan signal for driving an N-1th sub-pixel of the N-1th scan line;
turning on the voltage transfer unit during a second period following the first period based on an N-th scan signal for driving the N-th sub-pixel of the N-th scan line;
A driving method of an electroluminescent display device for transferring the reference voltage to the N-th sub-pixel in the first period and the second period. 13. The method of claim 12,
The N-th sub-pixel of the display panel is
A driving method of an electroluminescent display device in which the initialization step and the sampling step are separately driven based on an Nth scan signal and an N−1th scan signal that overlap for at least one horizontal time. 15. The method of claim 14,
A driving method of an electroluminescent display device of turning on the voltage transmitting unit based on the N-th scan signal for driving the N-th sub-pixel so that the reference voltage is transmitted to the N-th sub-pixel. 13. The method of claim 12,
The N-th sub-pixel of the display panel is
A method of driving an electroluminescent display device in which the initialization step and the sampling step are simultaneously performed based on the Nth scan signal and the N−1th scan signal overlapping for at least one horizontal time. 17. The method of claim 16,
A driving method of an electroluminescent display device of turning on the voltage transmitting unit based on an N-1th scan signal for driving an N-1th subpixel so that the reference voltage is transmitted to the Nth subpixel.

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