KR102647022B1 - Electroluminescent Display Device - Google Patents

Abstract

The present invention relates to an electroluminescence display device, comprising: a light emitting device; A driving transistor that inputs the Nth driving voltage signal input to the drain electrode to the anode electrode of the light emitting device according to the voltage difference between the gate and the source; first switching means for charging a reference voltage to one end of a capacitor connected to the gate electrode of the driving transistor according to a scan signal; second switching means for charging a data voltage at the other end of the capacitor according to the scan signal; and a third switching means connecting the other end of the capacitor and the source electrode of the driving transistor according to the N-1th driving voltage signal.

Description

Electroluminescent display device

The present invention relates to an electroluminescent display device.

Electroluminescent display devices are roughly divided into inorganic light emitting display devices and organic light emitting display devices depending on the material of the light emitting layer. Among these, the active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light by itself.

An organic light emitting display device arranges pixels, each including OLED, in a matrix form and adjusts the luminance of the pixels according to the gradation of image data. Each pixel basically includes a driving TFT (Thin Film Transistor) that controls the driving current flowing through the OLED according to the gate-source voltage, and one or more switch TFTs for programming the gate-sort voltage of the driving TFT.

Organic light emitting display devices have the advantage of being thinner and lower in power consumption, as well as having a fast response time, high luminous efficiency, brightness, and viewing angle, so they are being applied in a variety of fields.

Accordingly, research is continuing to improve performance and lifespan while maintaining the advantages of organic light emitting display devices.

The present invention provides an electroluminescent display device that can increase the aperture ratio and improve panel life by reducing the number of TFTs included in a pixel.

An electroluminescent display device according to an embodiment of the present invention includes a light emitting element; A driving transistor that inputs the Nth driving voltage signal input to the drain electrode to the anode electrode of the light emitting device according to the voltage difference between the gate and the source; first switching means for charging a reference voltage to one end of a capacitor connected to the gate electrode of the driving transistor according to a scan signal; second switching means for charging a data voltage at the other end of the capacitor according to the scan signal; and a third switching means connecting the other end of the capacitor and the source electrode of the driving transistor according to the N-1th driving voltage signal.

The third switching means may be turned on by the N-1th driving voltage signal, which is a previous signal of the Nth driving voltage signal that turns on the driving transistor.

The third switching means may maintain the turn-on state during the light-emitting period of the light-emitting device.

The driving voltage signal may be a voltage signal that swings between a first level voltage and a second level voltage lower than the first level voltage.

The light emitting device can receive the driving voltage signal at the anode electrode and a third level voltage between the first level and the second level at the cathode electrode.

When the first switching means and the second switching means are turned on, the third switching means maintains the turned-off state so that the capacitor is charged with the data voltage, and when the third switching means is turned on, the first switching means and the The second switching means maintains the turned-off state so that the data voltage stored in the capacitor can be reflected in the potential between the gate and source of the driving transistor.

The driving transistor may be maintained in a turned-off state while the data voltage is charged in the capacitor and the data voltage stored in the capacitor is reflected in the potential between the gate and source of the driving transistor.

An electroluminescent display device according to an embodiment of the present invention includes a data driver that supplies a data voltage and a reference voltage to a data line; A gate driver that supplies a scan signal to the gate line; a driving voltage control unit that supplies a driving voltage signal swinging between a first level voltage and a second level voltage lower than the first level voltage to the driving voltage line; and a display panel having a plurality of pixels connected to the data line, the gate line, and the driving voltage line, wherein each pixel arranged in the Nth pixel row among the pixels includes a gate electrode connected to a first node, a driving TFT that controls a driving current including a source electrode connected to a third node and a drain electrode to which the driving voltage signal is input; a first TFT connected between the first node and the reference power line; a second TFT connected between a second node and the data line; a capacitor with one end connected to the first node and the other end connected to the second node; a third TFT connected between the second node and the third node; and a light emitting element having an anode electrode connected to the third node to receive the driving voltage signal and a cathode electrode receiving a third level voltage between the first level and the second level of the driving voltage signal. do.

The first TFT and the second TFT may include gate electrodes to which the same scan signal is supplied.

The driving TFT receives an Nth driving voltage signal input to the drain electrode; The third TFT may include a gate electrode to which an N-1th driving voltage signal is supplied.

When the first TFT and the second TFT are turned on, the third TFT remains turned off so that the capacitor is charged with the data voltage, and when the third TFT is turned on, the first TFT and the second TFT are turned off. By maintaining this state, the data voltage stored in the capacitor can be reflected in the potentials of the gate and source of the driving TFT.

One frame period is a data writing period in which the data voltage is charged in the capacitor; a data transfer period in which the data voltage stored in the capacitor is reflected in the gate and source potentials of the driving TFT; and a light emission period in which the light emitting element emits light according to the potentials of the gate and source of the driving TFT.

The first TFT and the second TFT may be switched according to the Nth scan signal, and the third TFT may be switched by receiving the N-1th driving voltage signal.

In the data writing period, the Nth scan signal may be input at the on level, the Nth driving voltage signal may be input at the second level, and the N-1th driving voltage signal may also be input at the second level. there is.

In the data transfer period, the Nth scan signal may be input at the off level, the Nth driving voltage signal may be input at the second level, and the N-1th driving voltage signal may be input at the first level. there is.

In the light emission period, the Nth scan signal may be input at the off level, the Nth driving voltage signal may be input at the first level, and the N-1th driving voltage signal may also be input at the first level. .

The Nth scan signal is input to turn on the first TFT and the second TFT during the data writing period, the Nth driving voltage signal is input to the first level from the light emission period, and the N-1th driving voltage signal is input to the first level from the light emission period. A voltage signal may be input to the first level from the data transfer period.

The electroluminescent display device of the present invention can control light emission by using a driving voltage signal that swings between a first level voltage and a second level voltage to control light emission of a pixel. Accordingly, since the light emission of the pixel can be controlled without adding a separate TFT, the aperture ratio can be increased by reducing the number of TFTs included in the pixel, and the panel lifespan can be improved.

The electroluminescent display device of the present invention can reduce the number of pins of the data driver required to supply a conventional high potential voltage signal (EVDD) by supplying a driving voltage to the pixel using a driving voltage signal.

The electroluminescent display device of the present invention inputs a driving voltage signal swinging between the first level voltage and the second level voltage to the anode of the light emitting device, so that when the second level voltage at a low potential level is input, the anode of the light emitting device is connected to the driving device. The source terminal of the transistor can be initialized, and as a result, the influence of the previous frame can be minimized.

1 is a control block diagram of an electroluminescent display device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a pixel included in the electroluminescence display device of FIG. 1.
FIG. 3 is a driving waveform diagram of the pixel of FIG. 2.
FIG. 4A is an equivalent circuit diagram of a pixel corresponding to the data writing period (t1) in FIG. 3.
FIG. 4B is a driving waveform diagram showing the data writing period (t1) and the voltage state of each node in the driving waveform of the pixel of FIG. 3.
FIG. 5A is an equivalent circuit diagram of a pixel corresponding to the data transfer period (t3) of FIG. 3.
FIG. 5B is a driving waveform diagram showing the data transfer period (t3) and the voltage state of each node in the driving waveform of the pixel of FIG. 3.
FIG. 6A is an equivalent circuit diagram of a pixel corresponding to the light emission period (t4) of FIG. 3.
FIG. 6B is a driving waveform diagram showing the emission period (t4) and the voltage state of each node in the driving waveform of the pixel of FIG. 3.
7 to 9 are diagrams showing simulation results of the electroluminescent display device of the present invention.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present specification is complete, and that common knowledge in the technical field to which this specification pertains is provided. It is provided to fully inform those who have the scope of the invention, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

First, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical idea of the present specification.

Like reference numerals refer to substantially like elements throughout the specification.

In this specification, the pixel circuit and gate driver formed on the substrate of the display panel may be implemented as a TFT with an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, but are not limited to this and may also be implemented as a TFT with a p-type MOSFET structure. there is. TFT is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the TFT, carriers begin to flow from the source. The drain is the electrode through which carriers go out of the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of n-type TFT (NMOS), because the carriers are electrons, the source voltage has a lower voltage than the drain voltage to allow electrons to flow from the source to the drain. Since electrons flow from the source to the drain in an n-type TFT, the direction of current flows from the drain to the source. On the other hand, in the case of p-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. Accordingly, in the description of the embodiments of the present specification, one of the source and the drain is described as the first electrode, and the other one of the source and the drain is described as the second electrode.

Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings. In the following embodiments, the description will focus on an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical idea of the present specification is not limited to organic light emitting display devices, but can be applied to inorganic light emitting display devices including inorganic light emitting materials.

In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted.

1 is a diagram showing an electroluminescence display device according to an embodiment of the present invention.

Referring to FIG. 1, an organic light emitting display device according to an embodiment of the present invention includes a display panel 10 on which pixels (PXL) are formed, a data driver 12 for driving data lines 14, and gate lines. It is provided with a gate driver 13 for driving 15, a driving voltage controller 16 for controlling the light emission of the pixels PXL, and a timing controller 11 for controlling the driving timing of each of these components.

The timing controller 11 rearranges digital video data (RGB) input from the outside to match the resolution of the display panel 10 and supplies it to the data driver 12. In addition, the timing controller 11 operates the data driver 12 based on timing signals such as the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the dot clock signal (DCLK), and the data enable signal (DE). A data control signal (DDC) for controlling the operation timing and a gate control signal (GDC) for controlling the operation timing of the gate driver 13 are generated.

The data driver 12 may supply an analog data voltage (V _DATA ) and a reference voltage (V _Ref ) through the data lines 14 of the display panel 10. The data lines 14 may include a supply line of the data voltage (V _DATA ) and a supply line of the reference voltage (V _Ref ). The data driver 12 converts the digital video data (RGB) input from the timing controller 11 into an analog data voltage (V _DATA ) based on the data control signal (DDC) and supplies it to the display panel 10. Additionally, the data driver 12 may generate a reference voltage (V _Ref ) and supply it to the supply line of the reference voltage (V _Ref ).

The gate driver 13 may generate a scan signal (SCAN) based on the gate control signal (GDC). The gate driver 13 may supply a scan signal SCAN to the gate line 15 connected to each pixel row in a row sequential manner. This gate driver 13 may be formed directly on the non-display area of the display panel 10 according to the Gate-Driver In Panel (GIP) method.

The driving voltage control unit 16 generates a driving voltage signal (EVDD) and supplies it to the driving voltage line 17. The driving voltage signal EVDD may be generated as a voltage signal that swings between a first level voltage and a second level voltage lower than the first level voltage. The first level voltage may have a voltage level sufficient to cause the OLED to emit light, and the second level voltage may have a voltage level lower than the third level voltage (EVSS) input to the cathode terminal of the OLED. The driving voltage control unit 16 may supply a driving voltage signal EVDD to at least one driving voltage line 17 connected to each pixel row. This driving voltage control unit 16 may be formed at a position opposite to the gate driver 13 with the display panel 10 interposed therebetween.

In the display panel 10, a plurality of data lines 14 arranged in the vertical direction and a plurality of gate lines 15 and driving voltage lines 17 arranged in the horizontal direction intersect, and each intersection area has a pixel ( PXL) are arranged in a matrix form. Pixels (PXL) arranged on the same horizontal line form one pixel row. Pixels PXL arranged in the same pixel row are connected to the same gate line 15 and driving voltage line 17.

Pixels (PXL) may include OLED. OLED, a self-luminous device, includes an anode electrode and a cathode electrode, and an organic compound layer formed between them. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL). When the power supply voltage is applied to the anode electrode and cathode electrode, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emitting layer (EML) to form excitons, and as a result, the emitting layer (EML) Visible light is generated.

Each of the pixels PXL may be one of a red pixel, a green pixel, a blue pixel, and a white pixel. Red pixels, green pixels, blue pixels, and white pixels may form one unit pixel for color implementation. The color implemented in a unit pixel may be determined according to the emission ratio of the red pixel, green pixel, blue pixel, and white pixel. Meanwhile, white pixels may be omitted from unit pixels.

Figure 2 is a circuit diagram of a pixel included in an electroluminescence display device according to an embodiment of the present invention.

One pixel is disposed in an area where data lines 14 arranged in a vertical direction intersect with gate lines 15 and driving voltage lines 17 arranged in a horizontal direction.

The data line 14 may include a data voltage line supplied with an analog data voltage (V _DATA ) and a reference voltage line supplied with a reference voltage (V _Ref ). A scan signal (SCAN) is supplied to the gate line 15, and a driving voltage signal (EVDD) is supplied to the driving voltage lines 17.

The pixel (PXL) arranged in the i-th pixel row receives the i-th scan signal (SCAN[i]) through the gate line 15, and receives the i-th driving voltage signal (EVDD[) through the driving voltage lines 17. i]) and the i-1 driving voltage signal (EVDD[i-1]), which is the driving voltage signal of the stage immediately preceding the i-th stage, can be input. The driving voltage signal EVDD may be generated as a voltage signal swinging between a high potential first level voltage and a second level voltage lower than the first level voltage.

Each pixel has a light emitting device (OLED), a driving transistor (DR) that inputs the ith driving voltage signal (EVDD[i]) input to the drain electrode to the anode electrode of the light emitting device according to the voltage difference between the gate and source, and a scan. A first switching means (SW1) that provides a path for charging the reference voltage (V _REF ) to one end of the capacitor (Cst) connected to the gate of the driving transistor (DR) according to the signal (SCAN[i]), and a scan signal (SCAN) [i]), a second switching means (SW2) that provides a path for charging the data voltage (V _DATA ) at the other end of the capacitor (Cst), and the i-1 driving voltage signal (EVDD), which is the driving voltage signal of the previous stage. [i-1]), it may include a third switching means (SW3) connecting the other end of the capacitor (Cst) and the source of the driving transistor (DR).

Here, the light emitting device (OLED) receives a driving voltage signal (EVDD) that swings between the first level voltage and the second level voltage to the anode electrode, and the third level voltage between the first level and the second level to the cathode electrode. (EVSS) is entered.

According to an embodiment of the present invention, the pixel (PXL) disposed in the i-th pixel row includes the ith scan signal (SCAN[i]), the ith driving voltage signal (EVDD[i]), and the i-1 driving voltage signal. (EVDD[i-1]) is input.

The ith scan signal (SCAN[i]) is shared by the first switching means (SW1) and the second switching means (SW2), so that the first switching means (SW1) and the second switching means (SW2) are turned on and off at the same time. do. In this way, the first switching means (SW1) and the second switching means (SW2) share the scan signal (SCAN), thereby reducing the number of scan lines by half.

When the first switching means (SW1) and the second switching means (SW2) are turned on, one end of the capacitor (Cst) is connected to the reference voltage line and the other end is connected to the data voltage line. Accordingly, the data voltage (V _DATA ) may be charged in the capacitor (Cst).

When the first switching means (SW1) and the second switching means (SW2) are turned off, the i-1 driving voltage signal (EVDD[i-1]) is input as a first level voltage of high potential and is switched to the third switching means. (SW3) turns on. Accordingly, one end of the capacitor (Cst) is connected to the gate of the driving transistor (DR) and the other end is connected to the source terminal. Accordingly, the data voltage (V _DATA ) charged in the capacitor (Cst) may be reflected in the potential between the gate and source of the driving transistor (DR). According to this principle, the data voltage (V _DATA ) is applied to the driving transistor (DR), so it is possible to write data by applying a positive drive IC. Therefore, compared to applying a negative drive IC, the production cost can be reduced and driving stability can be improved.

When the data voltage (V _DATA ) is reflected in the potential between the gate and source of the driving transistor (DR), the i-th driving voltage signal (EVDD[i]) is applied as a first level voltage of high potential. The i-th driving voltage signal (EVDD[i]) is applied to the anode electrode of the light emitting device (OLED) according to the potential between the gate and source of the driving transistor (DR). Accordingly, the light emitting device can receive the ith driving voltage signal (EVDD[i]) and emit light.

Afterwards, the ith driving voltage signal (EVDD[i]) is converted to the second level voltage. The second level has a voltage level lower than the third level voltage (EVSS) connected to the cathode terminal of the light emitting device (OLED). Accordingly, when the ith driving voltage signal (EVDD[i]) is converted to the second level voltage, the drain node of the driving transistor (DR) is in a relatively higher potential state than the source node, so all power remaining in the source node is drained. It exits toward the node. That is, the source node can be initialized.

FIG. 3 is a waveform diagram showing the driving waveform of the pixel shown in FIG. 2.

Referring to FIG. 3, during one frame period for driving the pixel (PXL) arranged in the i-th pixel row, the data voltage (V _DATA ) is charged in the capacitor (Cst) and the source node of the driving transistor (DR) is initialized. data writing and initialization period (t1), data maintenance period (t2) during which the data voltage (V _DATA ) of the capacitor (Cst) is maintained after data writing is completed, and data voltage (V _DATA ) charged in the capacitor (Cst) ) may include a data transfer period (t3) reflected in the potential between the gate and source of the driving transistor (DR) and a light emission period (t4) during which the light emitting device emits light.

In the data writing and initialization period (t1), the i-1th driving voltage signal (EVDD[i-1]) and the i-th driving voltage signal (EVDD[i]) are applied as second level voltages. The second level voltage has a lower voltage level than the third level voltage (EVSS) connected to the cathode terminal of the light emitting device (OLED). Accordingly, when the ith driving voltage signal (EVDD[i]) is applied as the second level voltage, the light emitting device (OLED) is turned off and the third switching that receives the i-1 driving voltage signal (EVDD[i-1]) is turned off. The means (SW3) is also turned off. The ith scan signal (SCAN[i]) is applied at a high level. In the case of a scan signal, the high level is the on level and the low level is the off level. Accordingly, the first switching means (SW1) and the second switching means (SW2) are turned on at the same time.

In the data retention period (t2), the i-1th driving voltage signal (EVDD[i-1]) and the i-th driving voltage signal (EVDD[i]) are maintained at the second level voltage. Accordingly, the light emitting device (OLED) and the third switching means (SW3) are maintained in the off state. The ith scan signal (SCAN[i]) is applied at a low level. In the case of a scan signal, the high level is the on level and the low level is the off level. Accordingly, in the data writing period t2, the first switching means SW1 and the second switching means SW2 are simultaneously turned off.

In the data transfer period (t3), the i-1th driving voltage signal (EVDD[i-1]) is converted to the first level voltage and the ith driving voltage signal (EVDD[i]) is maintained at the second level voltage. Accordingly, the third switching means (SW3) is turned on and the light emitting device (OLED) is maintained in an off state. The ith scan signal (SCAN[i]) is maintained at a low level. Accordingly, the first switching means (SW1) and the second switching means (SW2) are maintained in an off state.

In the light emission period (t4), the i-1 driving voltage signal (EVDD[i-1]) is maintained at the first level voltage and the ith driving voltage signal (EVDD[i]) is converted to the first level voltage. Accordingly, both the third switching means (SW3) and the light emitting device (OLED) are turned on. The ith scan signal (SCAN[i]) is maintained at a low level. Accordingly, the first switching means (SW1) and the second switching means (SW2) are maintained in an off state.

As described above, according to the embodiment of the driving waveform of the present invention, the Nth scan signal (SCAN) is input so that the first switching means (SW1) and the second switching means (SW2) are turned on in the data writing period (t1). , the Nth driving voltage signal (EVDD[N]) is input at the first level from the light emission period (t4), and the N-1st driving voltage signal (EVDD[N-1]) is input from the data transfer period (t3). It can be entered at the first level.

4 to 6 are diagrams for explaining a method of driving a pixel according to an embodiment of the present invention.

In the pixel according to an embodiment of the present invention, the first to third switching means (SW1 to SW3) and the driving transistor (DR) include an n-type metal-oxide-semiconductor field-effect transistor (MOSFET), a p-type MOSFET, and a complementary CMOS (CMOS). It can be implemented with a metal semiconductor (TFT), etc. In the following embodiment, a case where the first to third switching means (SW1 to SW3) and the driving transistor (DR) are all implemented as n-type will be described.

Accordingly, the pixel of the present invention controls the driving current by including a gate electrode connected to the first node (N1), a source electrode connected to the third node (N3), and a drain electrode to which the driving voltage signal (EVDD) is input. It includes a driving TFT (DR), an anode electrode connected to a third node (N3), a cathode electrode connected to an input terminal of a third level voltage (EVSS), and a light emitting device (OLED) having. A first TFT (SW1) is connected between the first node (N1) and the supply line of the reference voltage (V _REF ), and a second TFT (SW1) is connected between the second node (N2) and the supply line of the data voltage (V _DATA ). SW2) is connected. The third TFT (SW3) is connected between the second node (N2) and the third node (N3). The capacitor Cst has one end connected to the first node N1 and the other end connected to the second node N2.

The gate electrodes of the first TFT (SW1) and the second TFT (SW2) share the same scan line (SCAN[i]). The i-th driving voltage signal (EVDD[i]) is input to the drain electrode of the driving TFT (DR), and the i-1 driving voltage signal (EVDD[i-1]) is supplied to the gate of the third TFT (SW3). do.

FIG. 4A is an equivalent circuit diagram of a pixel corresponding to a data writing period (t1), and FIG. 4B is a driving waveform diagram showing the data writing period (t1) and the voltage state of each node in the driving waveform of the pixel.

In the data writing and initialization period (t1), the i-1th driving voltage signal (EVDD[i-1]) and the i-th driving voltage signal (EVDD[i]) are applied as second level voltages. The second level voltage has a lower voltage level than the third level voltage (EVSS) connected to the cathode terminal of the light emitting device (OLED). When the ith driving voltage signal (EVDD[i]) is applied as a second level voltage, the light emitting device (OLED) is turned off, and when the i-1 driving voltage signal (EVDD[i-1]) is applied as a second level voltage, the light emitting device (OLED) is turned off. The third switching means (SW3) is turned off. When the i-th driving voltage signal EVDD[i] is applied as a second level voltage, the drain node of the driving transistor DR may be in a relatively higher potential state than the source node, and the source node may be initialized.

In the data writing and initialization period (t1), the i-th scan signal (SCAN[i]) is applied at a high level. Accordingly, the first switching means (SW1) and the second switching means (SW2) are turned on at the same time. Accordingly, the light emitting device (OLED) is maintained in an off state and the second node (N2) and the third node (N3) are disconnected. When the first TFT (SW1) is turned on, one end of the capacitor (Cst) is connected to the reference voltage line and the other end is connected to the data line. When the second TFT (SW2) is turned on, the other end of the capacitor (Cst) is connected to the data line. Accordingly, the reference voltage (V _REF ) is applied to the first node (N1) to which the capacitor (Cst) is connected, and the data voltage (V _DATA ) is applied to the second node (N2). Accordingly, the data voltage VDATA may be charged in the capacitor Cst. Here, the reference voltage (V _REF ) can be set to about 7V and the data voltage (VDATA) can be set to about 3 to 9V. Through the above process, the data voltage (V _DATA ) can be charged in the capacitor (Cst) while the light emitting device (OLED) is maintained in an off state during the data writing period (t1).

Afterwards, in the data maintenance period (t2), the i-1th driving voltage signal (EVDD[i-1]) and the i-th driving voltage signal (EVDD[i]) are maintained at the second level voltage. Accordingly, the light emitting device (OLED) and the third switching means (SW3) are maintained in the off state. The ith scan signal (SCAN[i]) is applied at a low level. In the case of a scan signal, the high level is the on level and the low level is the off level. Accordingly, in the data writing period t2, the first switching means SW1 and the second switching means SW2 are simultaneously turned off. When the ith scan signal (SCAN[i]) switches to a low level, the voltage of the first node (N1) and the voltage of the second node (N2) gradually decrease, but the potential difference stored in the capacitor (Cst) can be maintained. there is.

FIG. 5A is an equivalent circuit diagram of a pixel corresponding to a data transfer period (t3), and FIG. 5B is a drive waveform diagram showing the data transfer period (t3) and the voltage state of each node in the pixel's drive waveform.

In the data transfer period (t3), the i-1th driving voltage signal (EVDD[i-1]) is converted to the first level voltage and the ith driving voltage signal (EVDD[i]) is maintained at the second level voltage. Accordingly, the third switching means (SW3) is turned on and the light emitting device (OLED) is maintained in an off state. The ith scan signal (SCAN[i]) is maintained at a low level. Accordingly, the first switching means (SW1) and the second switching means (SW2) are maintained in an off state. When the first TFT (SW1) is turned off, the first node (N1) to which the capacitor (Cst) is connected is connected to the gate electrode of the driving TFT (DR). When the second TFT (SW2) is turned off, the second node (N2) of the capacitor (Cst) is connected to the source electrode of the driving TFT (DR) through the third TFT (SW3). As a result, the light emitting device (OLED) is maintained in an off state and the second node (N2) and the third node (N3) are connected. That is, the gate electrode and source electrode of the driving TFT (DR) are connected through the capacitor (Cst).

Through the above process, the light emitting device (OLED) is maintained in the off state during the data transfer period (t3), and the data voltage (VDATA) stored in the capacitor (Cst) is transmitted between the gate electrode and the source electrode of the driving TFT (DR). It can be reflected as a potential difference.

Figure 6a is an equivalent circuit diagram of a pixel corresponding to the light emission period (t4), and Figure 6b is a driving waveform diagram showing the light emission period (t4) and the voltage state of each node in the driving waveform of the pixel.

In the light emission period (t4), the i-1 driving voltage signal (EVDD[i-1]) is maintained at the first level voltage and the ith driving voltage signal (EVDD[i]) is converted to the first level voltage. Accordingly, both the third switching means (SW3) and the light emitting device (OLED) are turned on. The ith scan signal (SCAN[i]) is maintained at a low level. Accordingly, the first switching means (SW1) and the second switching means (SW2) are maintained in an off state.

When the first TFT (SW1) is turned off, the first node (N1) to which the capacitor (Cst) is connected is connected to the gate electrode of the driving TFT (DR). When the second TFT (SW2) is turned off, the second node (N2) of the capacitor (Cst) is connected to the source electrode of the driving TFT (DR) through the third TFT (SW3), and the voltage stored in the capacitor (Cst) is driven. It is reflected as the voltage between the gate and source of the TFT (DR). The ith driving voltage signal (EVDD[i]) is supplied as a first level voltage and input to the drain of the driving TFT (DR), and the driving TFT (DR) is supplied to the light emitting device (OLED) according to the gate-source voltage. The amount of current of the ith driving voltage signal (EVDD[i]) can be adjusted.

7 to 9 are diagrams showing simulation results of the electroluminescent display device of the present invention.

Figure 7 is a graph showing the results of simulating the voltage change at the source terminal (N3) of the driving TFT (DR) when R, G, and B pixels are driven according to an embodiment of the present invention.

During simulation, the driving voltage signal (EVDD) swings between -4V and 8V for the high potential power supply voltage (EVDD), the third level voltage (EVSS) input to the cathode is -1.5V, and the scan signal (SCAN) is -6V. It was applied at ~10V. When the reference voltage (V _REF ) is set to 7V and the data voltage (VDATA) for R, G, and B pixels is applied to 3~9V, the voltage change at the source terminal (N3) of the driving TFT (DR) is shown in the graph. As shown in .

When the ith scan signal (SCAN[i]) is applied at a high level, the first switching means (SW1) and the second switching means (SW2) are turned on at the same time, and the light emitting device (OLED) is maintained in an off state, so that the second node (N2) and the third node (N3) are disconnected.

When the ith scan signal (SCAN[i]) is applied at a high level, the driving voltage signal (EVDD) is applied at -4V. The driving voltage signal (EVDD) is input to the drain of the driving transistor (DR) and transmitted to the source node. Therefore, the source node (N3) of the driving transistor (DR) is sufficiently lower than the data voltage (V _DATA ) 3 to 9V - Can be initialized to 4V.

Figure 8 is a graph showing the results of simulating gamma characteristics when driving R, G, and B pixels according to an embodiment of the present invention.

During simulation, the driving voltage signal (EVDD) swings between -4V and 8V for the high potential power supply voltage (EVDD), the third level voltage (EVSS) input to the cathode is -1.5V, and the scan signal (SCAN) is -6V. It was applied at ~10V. When the reference voltage (V _REF ) is set to 7V and the data voltage (VDATA) for the R, G, and B pixels is applied at 3 to 9V, the peak luminance is measured by measuring the current value applied to the R, G, and B pixels. Check if you are satisfied.

As a result of the simulation, as shown in the graph in Figure 8, it was confirmed that the peak luminance could be satisfied at 6.6V for the red pixel, 7.0V for the green pixel, and 5.9V for the blue pixel.

Figure 9 is a graph simulating whether black current, which is an effect of the previous frame, occurs when R, G, and B pixels are driven according to an embodiment of the present invention.

During simulation, the driving voltage signal (EVDD) swings between -4V and 8V for the high potential power supply voltage (EVDD), the third level voltage (EVSS) input to the cathode is -1.5V, and the scan signal (SCAN) is -6V. It was applied at ~10V. When the reference voltage (V _REF ) is set to 7V and the data voltage (VDATA) for the R, G, and B pixels is applied at 3 to 9V, the peak luminance is measured by measuring the current value applied to the R, G, and B pixels. Check if you are satisfied.

As a result of the simulation, as shown in the graph of FIG. 9, black current of 1pA or less was measured for all R, G, and B pixels, which was a result that satisfied the standard black current specification of 1pA or less. Black current is a measure of the degree to which the voltage charged when displaying data of the previous frame remains in the pixel. In the present invention, the driving voltage signal (EVDD) input to the light emitting device (OLED) through the driving TFT (DR) swings between a first level voltage of high potential and a second level voltage lower than EVSS (-4V to 8V). . Accordingly, when the driving voltage signal EVDD is input as a second level voltage of -4V, the source node of the driving transistor DR may be initialized to -4V, which is sufficiently lower than the data voltage V _DATA of 3 to 9V. Accordingly, it can be confirmed through simulation results that a clear effect of removing black currants can be obtained.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present specification. Therefore, the technical scope of the present specification is not limited to the content described in the detailed description of the specification, but should be determined by the scope of the patent claims.

10: display panel 11: timing controller
12: data driver 13: gate driver

Claims (17)

light emitting device;
A driving transistor that inputs the Nth driving voltage signal input to the drain electrode to the anode electrode of the light emitting device according to the voltage difference between the gate electrode and the source electrode;
first switching means for charging a reference voltage to one end of a capacitor connected to the gate electrode of the driving transistor according to a scan signal;
second switching means for charging a data voltage at the other end of the capacitor according to the scan signal; and
It includes a third switching means connecting the other end of the capacitor and the source electrode of the driving transistor according to the N-1th driving voltage signal,
The third switching means is turned on by the N-1th driving voltage signal, which is a previous signal of the Nth driving voltage signal that turns on the driving transistor. delete According to paragraph 1,
The third switching means maintains a turn-on state during the light-emitting period of the light-emitting device. light emitting device;
A driving transistor that inputs the Nth driving voltage signal input to the drain electrode to the anode electrode of the light emitting device according to the voltage difference between the gate electrode and the source electrode;
first switching means for charging a reference voltage to one end of a capacitor connected to the gate electrode of the driving transistor according to a scan signal;
second switching means for charging a data voltage at the other end of the capacitor according to the scan signal; and
It includes a third switching means connecting the other end of the capacitor and the source electrode of the driving transistor according to the N-1th driving voltage signal,
The driving voltage signal is a voltage signal swinging between a first level voltage and a second level voltage lower than the first level voltage. According to paragraph 4,
The light emitting device is,
An electroluminescent display device that receives the driving voltage signal at the anode electrode and receives a third level voltage between the first level and the second level at the cathode electrode . According to paragraph 1,
When the first switching means and the second switching means are turned on, the third switching means remains turned off so that the data voltage is charged in the capacitor,
When the third switching means is turned on, the first switching means and the second switching means remain turned off, and the data voltage stored in the capacitor is reflected in the potential between the gate electrode and the source electrode of the driving transistor. Display device. According to clause 6,
The capacitor is charged with the data voltage, and the driving transistor is maintained in a turned-off state while the data voltage stored in the capacitor is reflected in the potential between the gate electrode and the source electrode of the driving transistor. a data driver that supplies a data voltage to the data line and a reference voltage to the reference voltage line;
A gate driver that supplies a scan signal to the gate line;
a driving voltage control unit that supplies a driving voltage signal swinging between a first level voltage and a second level voltage lower than the first level voltage to the driving voltage line; and
A display panel having a plurality of pixels connected to the data line, the gate line, and the driving voltage line,
Among the pixels, each pixel arranged in the Nth pixel row is,
a driving TFT that controls a driving current including a gate electrode connected to a first node, a source electrode connected to a third node, and a drain electrode to which the driving voltage signal is input;
a first TFT connected between the first node and the reference voltage line;
a second TFT connected between a second node and the data line;
a capacitor with one end connected to the first node and the other end connected to the second node;
a third TFT connected between the second node and the third node; and
A light emitting device having an anode electrode connected to the third node and receiving the driving voltage signal, and a cathode electrode receiving a third level voltage between the first level and the second level of the driving voltage signal;
An electroluminescent display device comprising: According to clause 8,
The first TFT and the second TFT include gate electrodes to which the same scan signal is supplied. According to clause 8,
The driving TFT receives an Nth driving voltage signal input to the drain electrode;
The third TFT is an electroluminescent display device including a gate electrode to which an N-1 driving voltage signal is supplied. According to clause 8,
When the first TFT and the second TFT are turned on, the third TFT remains turned off and the data voltage is charged in the capacitor,
When the third TFT is turned on, the first TFT and the second TFT remain turned off, and the data voltage stored in the capacitor is reflected in the potentials of the gate electrode and source electrode of the driving TFT. According to clause 10,
1 frame period is,
a data writing and initialization period in which the capacitor is charged with the data voltage and the source node of the driving TFT is initialized;
a data transfer period during which the data voltage stored in the capacitor is reflected in potentials of the gate electrode and source electrode of the driving TFT; and
An electroluminescent display device comprising a light emission period for causing the light emitting element to emit light according to potentials of a gate electrode and a source electrode of the driving TFT. According to clause 12,
The first TFT and the second TFT are switched according to the Nth scan signal,
The third TFT is an electroluminescence display device that is switched by receiving the N-1 driving voltage signal. According to clause 13,
In the above data entry and initialization period,
The Nth scan signal is input at the on level,
The Nth driving voltage signal is input at the second level,
An electroluminescence display device in which the N-1th driving voltage signal is also input at a second level. According to clause 13,
In the above data delivery period,
The Nth scan signal is input at an off level,
The Nth driving voltage signal is input at the second level,
An electroluminescence display device in which the N-1th driving voltage signal is also input at a first level. According to clause 13,
In the above emission period,
The Nth scan signal is input at an off level,
The Nth driving voltage signal is input at the first level,
An electroluminescence display device in which the N-1th driving voltage signal is also input at a first level. According to clause 13,
The Nth scan signal is input to turn on the first TFT and the second TFT during the data writing period,
The Nth driving voltage signal is input to turn on the driving TFT during the light emission period,
The N-1th driving voltage signal is input to turn on the third TFT during the data transfer period and the light emission period.

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