KR102309843B1 - Organic Light Emitting Display - Google Patents

Abstract

The present invention relates to an organic light emitting display device for reducing power consumption and sufficiently compensating for a threshold voltage of a driving TFT within a predetermined time in a high-resolution model having a short one horizontal period.
In the organic light emitting diode display, each of the pixels disposed in the j-th pixel row (where j is a natural number greater than or equal to 2) and connected to the j-1 th scan line and the j-th scan line is disposed between the node C and the input terminal of the low potential driving voltage. a driving TFT for controlling a driving current applied to the organic light emitting diode including a connected organic light emitting diode, a gate connected to the node A, and a source connected to the node C; an initialization line to which an initialization voltage is supplied; and the node A first scan TFT connected between C and switched according to a j-1th scan driving signal from the j-1th scan line, and a reference line supplied with a reference voltage and the node A, wherein the j a second scan TFT switched according to a j-th scan driving signal from a th scan line, a third scan TFT connected between any one of the data lines and a node B, and switched according to the j-th scan driving signal; , a first emission TFT connected between an input terminal of a high potential driving voltage and a drain of the driving TFT, the first emission TFT being switched opposite to that of the first scan TFT according to the j-1th scan driving signal, and the node A and the node B and a second emission TFT connected therebetween, the second emission TFT being switched oppositely to the second and third switch TFTs according to the j-th scan driving signal, and a storage capacitor connected between the node B and the node C.

Description

Organic Light Emitting Display {Organic Light Emitting Display}

The present invention relates to an active matrix type organic light emitting display device.

The active matrix type organic light emitting diode display includes an organic light emitting diode (hereinafter, referred to as "OLED") that emits light by itself, and has advantages of fast response speed, luminous efficiency, luminance and viewing angle.

OLED, which is a self-luminous device, has a structure as shown in FIG. 1 . The OLED includes an anode electrode and a cathode electrode, and an organic compound layer (HIL, HTL, EML, ETL, EIL) formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the light emitting layer (EML) to form excitons, and as a result, the light emitting layer (EML) is produces visible light.

The organic light emitting display device arranges pixels including OLEDs in a matrix form, and adjusts the luminance of the pixels according to the gray level of video data. Each of the pixels responds to a driving TFT (Thin Film Transistor) that controls the driving current flowing through the OLED according to the gate-source voltage, a capacitor that keeps the gate-source voltage of the driving TFT constant for one frame, and a gate signal. and at least one switch TFT for programming the gate-source voltage of the driving TFT. The driving current is determined by the gate-source voltage of the driving TFT according to the data voltage, and the luminance of the pixel is proportional to the size of the driving current flowing through the OLED.

In such an organic light emitting display device, the threshold voltage of the driving TFT between pixels is different due to process deviation, gate-bias stress over the lapse of driving time, etc., so that the driving current corresponding to the same data voltage is different. there is a problem with

In order to solve this problem, the gate-source voltage of the driving TFT is programmed using a compensation TFT or a compensation capacitor added to each pixel, and the effect of a change in the threshold voltage of the driving TFT on the driving current according to the programming result A variety of pixel structures for internal compensation for removing ? Among these, a recently proposed technique for realizing a small pixel size has adopted a pixel structure in which a reference voltage and a data voltage are alternately applied through the same data line. In this prior art, one horizontal period allocated to driving of pixels corresponding to one horizontal line is divided into two periods, a first period and a second period, and a reference voltage is applied to the corresponding pixel through each data line during the first period. The threshold voltage of the driving TFT is sampled at , and the data voltage is applied to the corresponding pixel through each data line during the second period to program the gate-source voltage of the driving TFT in the pixel to match the desired driving current.

In this prior art, since the reference voltage and the data voltage must be alternately supplied to the pixel through the same data line in one horizontal period, the amount of transition of the signal supplied through each data line increases, thereby increasing power consumption.

As the display panel develops to a higher resolution, one horizontal period is gradually decreasing. When the panel resolution is low, one horizontal period is relatively long, so there is no problem in threshold voltage compensation despite the two-division driving as in the prior art. However, when the panel resolution is high, since one horizontal period is short, the time required for sampling the threshold voltage of the driving TFT may be insufficient when driving in two divisions as in the prior art, which may lead to insufficient compensation.

Accordingly, it is an object of the present invention to provide an organic light emitting display device in which power consumption is reduced and the threshold voltage of a driving TFT can be sufficiently compensated within a predetermined time in a high-resolution model having a short one horizontal period.

In order to achieve the above object, an organic light emitting display device according to an embodiment of the present invention includes a display panel including a plurality of pixels, a gate driving circuit for driving scan lines of the display panel, and a data line of the display panel. and a data driving circuit for driving them. Each of the pixels disposed in the j-th pixel row and connected to the j-1 th scan line and the j-th scan line includes an organic light emitting diode connected between the node C and the input terminal of the low potential driving voltage; , a gate connected to the node A, a driving TFT for controlling a driving current applied to the organic light emitting diode including a source connected to the node C, and an initialization line supplied with an initialization voltage and the node C, A first scan TFT switched according to a j-1th scan driving signal from the j-1th scan line is connected between a reference line supplied with a reference voltage and the node A, a second scan TFT switched according to a j-scan driving signal, a third scan TFT connected between any one of the data lines and a node B, and switched according to the j-th scan driving signal; a first emission TFT connected between an input terminal and a drain of the driving TFT, the first emission TFT being switched opposite to the first scan TFT according to the j-1th scan driving signal, and connected between the node A and the node B; and a second emission TFT that is switched oppositely to the second and third switch TFTs according to a j-th scan driving signal, and a storage capacitor connected between the node B and the node C.

The reference line is provided separately from the data lines, the first to third switch TFTs are implemented as an N-type, and the first and second emission TFTs are implemented as a P-type.

One frame period includes an initialization period in which the initialization voltage from the initialization line is applied to the node C, the reference voltage from the reference line is applied to the node A, and data from any one of the data lines. a sampling & programming period of applying a voltage to the node B to sample the threshold voltage of the driving TFT and storing a compensation voltage including the threshold voltage of the driving TFT as a programming voltage in the storage capacitor; and a light emitting period in which the organic light emitting diode emits light by applying a corresponding driving current to the organic light emitting diode.

The j-1th scan driving signal is applied at a high level during the initialization period, is applied at a low level during the sampling & programming period and the light emission period, and the jth scan driving signal is applied at a high level during the sampling & programming period. is applied at a low level during the initialization period and the light emission period, and the data voltage is applied from the data line to the pixel during the sampling & programming period.

An organic light emitting display device according to another embodiment of the present invention includes a display panel having a plurality of pixels, a gate driving circuit driving scan lines and emission lines of the display panel, and driving data lines of the display panel. A data driving circuit is provided. Each of the pixels disposed in the j-th pixel row (where j is a natural number greater than or equal to 2) and connected to the j-1 th scan line and the j th scan line, and the j-1 th emission line and the j-th emission line is a node C a driving TFT for controlling a driving current applied to the organic light emitting diode including an organic light emitting diode connected between the and low potential driving voltage input terminal, a gate connected to the node A, and a source connected to the node C; a first scan TFT connected between an initialization line to which a voltage is supplied and the node C, and switched according to a j-1th scan driving signal from the j-1th scan line; a reference line to which a reference voltage is supplied; A second scan TFT connected between the node A and switched according to the j-th scan driving signal from the j-th scan line, and connected between any one of the data lines and the node B, the j-th scan driving signal The third scan TFT switched according to a first emission TFT, a second emission TFT connected between the node A and the node B and switched according to a j-th emission driving signal from the j-th emission line, and the node B and the node C and a storage capacitor connected therebetween.

In the present invention, a reference line for supplying a reference voltage is provided separately from a data line to which a data voltage is supplied, and a threshold voltage sampling time required for compensation can be sufficiently secured by simultaneously applying a data voltage and a reference voltage required for compensation to the pixel. . Accordingly, the present invention can realize clear image quality by greatly increasing the accuracy of compensation in a high-resolution model. In addition, the present invention does not need to swing the voltage between the data voltage and the reference voltage on the data line, unlike the prior art, so that power consumption can be greatly reduced.

1 is a view showing an OLED and its light emitting principle.
2 is a view showing an organic light emitting display device according to an embodiment of the present invention.
3 is a view showing a pixel array according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating an equivalent circuit of one pixel included in the pixel array of FIG. 3 ;
5 is a view showing a data signal and a gate signal applied to the pixel of FIG. 4;
6A is an equivalent circuit diagram of a pixel corresponding to an emission period of a previous frame;
6B is an equivalent circuit diagram of a pixel corresponding to an initialization period of a current frame;
6C is an equivalent circuit diagram of a pixel corresponding to a sampling & programming period of a current frame;
6D is an equivalent circuit diagram of a pixel corresponding to an emission period of a current frame;
Fig. 7 is a diagram showing changes in potentials of specific nodes of a pixel corresponding to an initialization period, a sampling & programming period, and a light emission period;
8 is a view showing a pixel array according to another embodiment of the present invention;
9 is a diagram illustrating an equivalent circuit of one pixel included in the pixel array of FIG. 8;
FIG. 10 is a view showing a data signal and a gate signal applied to the pixel of FIG. 9;
11 is a view showing a simulation result of compensating a threshold voltage of a driving TFT in a state in which a white image is displayed;
12 is a view showing a simulation result of compensating a threshold voltage of a driving TFT in a state in which a black image is displayed;

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 2 to 12 .

2 shows an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 2 , in the organic light emitting display device according to the embodiment of the present invention, a display panel 10 in which pixels PXL are arranged in a matrix form, and a data driving circuit for driving data lines 14 ( 12 ), a gate driving circuit 13 for driving the gate lines 15 , and a timing controller 11 for controlling driving timings of the data driving circuit 12 and the gate driving circuit 13 . .

In the display panel 10 , a plurality of data lines 14 and a plurality of gate lines 15 cross each other, and pixels PXL are arranged in a matrix form in each cross area. Each gate line 15 may be composed of one scan line as shown in FIG. 3 or may be composed of one scan line and one emission line as shown in FIG. 8 .

Each pixel PXL may be connected to a corresponding data line 14 and a corresponding gate line 15 . In addition, each pixel PXL may be commonly connected to a reference line to receive the reference voltage Vref through the reference line. Each pixel PXL may be commonly connected to an initialization line to receive the initialization voltage Vinit through the initialization line. In addition, each pixel PXL may be commonly connected to a power line and may receive high potential and low potential driving voltages EVDD and EVSS through the power line. The initialization voltage Vinit may be set within a range sufficiently lower than the low potential driving voltage EVSS to prevent unnecessary light emission of the OLED. The initialization voltage source generating the initialization voltage Vinit and the reference voltage source generating the reference voltage Vref may be built in the data driving circuit 12 or a separate power circuit (not shown). In addition, the driving voltage source generating the high potential and low potential driving voltages EVDD and EVSS may be built in the power circuit.

In the present invention, the reference line is formed separately from the data lines 14 and the reference voltage Vref is supplied to the pixel through the reference line. According to the present invention, a signal line (reference line) for supplying the reference voltage Vref to the pixel PXL and a signal line (data line) for supplying the data voltage to the pixel PXL are physically separated. Accordingly, according to the present invention, power consumption due to voltage swing in the data line as in the prior art, that is, power consumption caused by alternately supplying the reference voltage Vref and the data voltage to the pixel PXL through the same data line at regular intervals can prevent Also, as will be described later, in the present invention, by simultaneously applying the reference voltage Vref and the data voltage to the pixel, the time devoted to sampling the threshold voltage of the driving TFT is secured as long as possible, so that the threshold voltage of the driving TFT is sufficient within a predetermined time. to be compensated

The TFTs constituting the pixel PXL may be implemented as an oxide TFT including an oxide semiconductor layer. The oxide TFT is advantageous in increasing the area of the display panel 10 in consideration of electron mobility, process variation, and the like. However, the present invention is not limited thereto, and the semiconductor layer of the TFT may be formed of amorphous silicon or polysilicon.

The TFTs constituting the pixel PXL may be implemented as CMOS including N-type and P-type as shown in FIG. 4 , or may be implemented as NMOS including only N-type as shown in FIG. 9 . Also, although not shown in the drawings, TFTs constituting the pixel PXL may be implemented as PMOS including only P-type. When the TFTs are implemented in CMOS, the number of signal lines in the pixel array can be reduced, which is advantageous in increasing the aperture ratio, and it is easy to implement a high-resolution panel. On the other hand, when the TFTs are implemented as NMOS (or PMOS), there is an advantage in that the TFT process is unified and the manufacturing process is simplified.

The timing controller 11 rearranges digital video data RGB input from the outside to match the resolution of the display panel 10 and supplies it to the data driving circuit 12 . In addition, the timing controller 11 is a data driving circuit 12 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. A data control signal DDC for controlling the operation timing of , and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13 are generated.

The data driving circuit 12 converts the digital video data RGB input from the timing controller 11 to an analog data voltage based on the data control signal DDC, and then applies the data voltage to the data lines 14 . supply

The gate driving circuit 13 generates scan driving signals Sj-1, Sj, Sj+1, ..., based on the gate control signal GDC, corresponding to the pixel array as shown in FIG. 3, and sequentially ( The scan lines 15j-1, 15j, 15j+1,...) may be supplied in the R#j-1, R#j,...) method. In addition, the gate driving circuit 13 corresponds to the pixel array as shown in FIG. 8 , based on the gate control signal GDC, the scan driving signals Sj-1, Sj, Sj+1, ... and the emission driving signal. (Ej-1, Ej, Ej+1,...) is generated, respectively, and the scan driving signal (Sj-1, Sj, Sj+1,...) is sequentially generated by the line (R#j-1, R# j,...) to supply the scan lines 15j-1, 15j, 15j+1,... It may be supplied to the emission lines 16j-1, 16j, 16j+1,... in a line sequential (R#j-1, R#j,...) manner.

The gate driving circuit 13 may be directly formed on the non-display area of the display panel 10 according to a gate-driver in panel (GIP) method.

[First embodiment]

In the first embodiment of the present invention, each pixel PXL is implemented in CMOS. Hereinafter, the first embodiment will be described with reference to FIGS. 3 to 7 .

3 shows a pixel array according to an embodiment of the present invention. 4 shows an equivalent circuit of one pixel included in the pixel array of FIG. 3 .

Each pixel PXL included in the pixel array of FIG. 3 is connected to two scan lines (eg, 15j-1, 15j) and one data line (eg, 141), and is initialized with a reference line CL1. It is commonly connected to the line CL2.

In the pixel array of FIG. 3 , a connection configuration for a pixel PXL[j,k] disposed in a j-th pixel row and a j-th pixel column (j is a natural number) is illustrated in FIG. 4 .

Referring to FIG. 4 , the pixel PXL[j,k] includes an OLED, a driving TFT (DT), a first scan TFT (ST1), a second scan TFT (ST2), a third scan TFT (ST3), and a first It may have a 6T1C structure (implemented by six TFTs and one capacitor) including the emission TFT ET1 , the second emission TFT ET2 , and the storage capacitor Cst. Here, for the CMOS implementation, the driving TFT DT and the first to third scan TFTs ST1 to ST3 are implemented as an N type, and the first and second emission TFTs ET1 and ET2 are implemented as a P type. can be In addition, although not shown in the drawing, the driving TFT DT and the first to third scan TFTs ST1 to ST3 are implemented as P-type, and the first and second emission TFTs ET1 and ET2 are implemented as N-type. may be implemented.

The OLED emits light by the driving current supplied from the driving TFT (DT). As shown in FIG. 1 , a multi-layered organic compound layer is formed between the anode electrode and the cathode electrode of the OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). The anode electrode of the OLED is connected to the node C, and its cathode electrode is connected to the input terminal of the low potential driving voltage EVSS.

The driving TFT DT controls the driving current applied to the OLED according to its gate-source voltage Vgs. The gate electrode of the driving TFT (DT) is connected to the node A, the drain electrode is connected to the first emission TFT (ET1), and the source electrode is connected to the node C.

The first scan TFT ST1 is switched in response to the j-1 th scan driving signal Sj-1 from the j-1 th scan line 15j-1 to thereby flow a current between the initialization line CL2 and the node C turns on/off. The gate electrode of the first scan TFT ST1 is connected to the j-1th scan line 15j-1, the drain electrode is connected to the initialization line CL2, and the source electrode is connected to the node C.

The second scan TFT ST2 is switched in response to the j-th scan driving signal Sj from the j-th scan line 15j to turn on/off the current flow between the reference line CL1 and the node A. The gate electrode of the second scan TFT ST2 is connected to the j-th scan line 15j, the drain electrode is connected to the reference line CL1, and the source electrode is connected to the node A.

The third scan TFT ST3 is switched in response to the j-th scan driving signal Sj from the j-th scan line 15j to turn on/off the current flow between the data line 14k and the node B. The gate electrode of the third scan TFT ST3 is connected to the j-th scan line 15j, the drain electrode is connected to the data line 14k, and the source electrode is connected to the node B.

The first emission TFT ET1 is switched oppositely to the first scan TFT ST1 in response to the j-1 th scan driving signal Sj-1 from the j-1 th scan line 15j-1 to thereby have a high potential. The driving voltage EVDD is applied to the drain electrode of the driving TFT DT. The gate electrode of the first emission TFT ET1 is connected to the j-1 th scan line 15j-1, the source electrode is connected to the input terminal of the high potential driving voltage EVDD, and the drain electrode of the driving TFT DT ) is connected to

The second emission TFT ET2 is switched oppositely to the second and third scan TFTs ST2 and ST3 in response to the j-th scan driving signal Sj from the j-th scan line 15j, so that the node A and the node B Turns on/off the current flow between them. The gate electrode of the second emission TFT ET2 is connected to the j-th scan line 15j, the source electrode is connected to the node A, and the drain electrode is connected to the node B.

The storage capacitor Cst is connected between the node B and the node C. The storage capacitor Cst is used to sample the threshold voltage of the driving TFT DT, and is used to program the gate-source voltage of the driving TFT DT.

FIG. 5 shows a data signal and a gate signal applied to the pixel of FIG. 4 . 6A to 6D show equivalent circuits of pixels corresponding to the driving periods of FIG. 5 . And, FIG. 7 shows potential changes of specific nodes of the pixel in each driving period of FIG. 5 .

The operation of the pixel PXL shown in FIG. 4 will be described in conjunction with FIGS. 5 to 7 .

One frame period may include an initialization period Ti, a sampling & programming period Ts, and an emission period Te as shown in FIG. 5 .

The j-1th scan driving signal Sj-1 is applied at a high level (H) during the initialization period Ti, and is applied at a low level (L) during the sampling & programming period Ts and the emission period Te. The j-th scan driving signal Sj is applied at a high level (H) during the sampling & programming period (Ts) and at a low level (L) during the initialization period (Ti) and the light emission period (Te). . Then, the data voltage Vdata is applied from the data line to the pixel PXL during the sampling & programming period Ts.

As shown in FIG. 6A , in the light emission period Tx of the previous frame preceding the current frame, the nodes A and B of the pixel PXL are maintained at the j−1th gate voltage Vg(j−1), and the pixel PXL ) is maintained at the j-1 th source voltage (Vs(j-1)). In the light emission period Tx of the previous frame, "Vg(j-1)-Vs(j-1)" is stored in the storage capacitor Cst.

Subsequently, as shown in FIG. 6B , in the initialization period Ti of the current frame, the initialization voltage Vinit from the initialization line CL2 is applied to the node C. Referring to FIG. To this end, during the initialization period Ti, the j-1th scan driving signal Sj-1 is input to a high level H to turn on the first scan TFT ST1, while the first emission TFT ( ET1) is turned off. And, the j-th scan driving signal Sj is input to the low level L to turn off the first and second scan TFTs ST2 and ST3, while turning on the second emission TFT ET2. As a result, as shown in FIGS. 6B and 7 , during the initialization period Ti, the node C is initialized by the initialization voltage Vinit, and the nodes A and B are short-circuited so that “Vg(j-1)-Vs(j- 1) The potential changes to "+Vinit".

Subsequently, in the sampling & programming period Ts as shown in FIG. 6C , the reference voltage Vref from the reference line CL1 is applied to the node A, and at the same time, the data voltage Vdata from the data line 14k is By being applied to the node B, the threshold voltage of the driving TFT DT is sampled and the compensation voltage Vc including the threshold voltage of the driving TFT DT is stored in the storage capacitor Cst as a programming voltage. To this end, in the sampling & programming period Ts, the j-1th scan driving signal Sj-1 is input to the low level L to turn on the first emission TFT ET1, while the first scan Turn off the TFT (ST1). Then, the j-th scan driving signal Sj is input to a high level H to turn on the first and second scan TFTs ST2 and ST3, while turning off the second emission TFT ET2. As a result, as shown in FIGS. 6C and 7 , during the sampling & programming period Ts, a reference voltage Vref higher than the threshold voltage Vth of the driving TFT DT is applied to the node A, and the data voltage ( Vdata) is applied. At this time, the driving TFT DT is turned on due to the application of the reference voltage Vref and the high potential driving voltage EVDD, and a current flows between the drain and the source of the driving TFT DT, and this drain-source current Thus, the potential of the node C rises until the potential difference between the gate and the source of the driving TFT DT becomes the threshold voltage Vth. By this source following, the potential of node C becomes “Vref-Vth”, and the potential difference between both ends of the storage capacitor Cst becomes the compensation voltage Vc corresponding to “Vdata-Vref+Vth”. . This compensation voltage Vc is stored and maintained in the storage capacitor Cst as a programming voltage.

In the sampling & programming period Ts, the reference voltage Vref and the data voltage Vdata are simultaneously applied to the pixel PXL through different signal lines, and the threshold voltage sampling and compensation voltage ( Vc) Programming is done at the same time. Through this, according to the present invention, one horizontal period can be allotted to the threshold voltage sampling of the driving TFT without dividing by two. That is, according to the present invention, sufficient compensation can be achieved by allocating a sufficient time for sampling the threshold voltage of the driving TFT, so that it is possible to respond to a high-resolution model with a short one horizontal period.

Subsequently, in the light emission period Te as shown in FIG. 6D , a driving current according to the compensation voltage Vc stored in the storage capacitor Cst, ie, a programming voltage, is applied to the OLED to emit light. To this end, in the light emission period Te, the j-1th scan driving signal Sj-1 is input to a low level L to turn on the first emission TFT ET1, while the first scan TFT ET1 ST1) is turned off. And, the j-th scan driving signal Sj is input to the low level L to turn on the second emission TFT ET2 while turning off the first and second scan TFTs ST2 and ST3. As a result, during the light emission period Te as shown in FIGS. 6D and 7 , the node A and the node B are maintained at “Vs(j)+Vc”, and the node C is maintained at “Vs(j)”. And, in the light emission period Te, "Vc" is maintained in the storage capacitor Cst.

The relational expression for the driving current Ioled flowing through the OLED in the light emission period Te is expressed as Equation 1 below. The OLED realizes a desired display gradation by emitting light by such a driving current.

In Equation 1, k indicates a proportional constant determined by electron mobility, parasitic capacitance, channel capacitance, and the like of the driving TFT DT. The driving current (Ioled) relational expression is k/2 (Vgs-Vth) ^2, since the gate-source voltage (Vgs) of the driving TFT (DT) set in the sampling & programming period (Ts) includes the Vth component. As shown in 1, the Vth component in the driving current (Ioled) relational expression is erased. Through this, the influence of the threshold voltage Vth change on the driving current Ioled is eliminated.

[Second embodiment]

In the second embodiment of the present invention, each pixel PXL is implemented as an NMOS. Hereinafter, a second embodiment will be described with reference to FIGS. 8 to 10 .

8 shows a pixel array according to another embodiment of the present invention. 9 shows an equivalent circuit of one pixel included in the pixel array of FIG. 8 . Also, FIG. 10 shows a data signal and a gate signal applied to the pixel of FIG. 9 .

Each pixel PXL included in the pixel array of FIG. 8 includes two scan lines (eg, 15j-1, 15j), two emission lines (eg, 16j-1, 16j), and one data line ( For example, while being connected to 141 , it is commonly connected to the reference line CL1 and the initialization line CL2 .

In the pixel array of FIG. 8 , a connection configuration for a pixel (PXL[j,k]) disposed in a j-th pixel row and a j-th pixel column (j is a natural number) is illustrated in FIG. 9 .

Referring to FIG. 9 , the pixel PXL[j,k] includes an OLED, a driving TFT (DT), a first scan TFT (ST1), a second scan TFT (ST2), a third scan TFT (ST3), and a first It may have a 6T1C structure (implemented by six TFTs and one capacitor) including the emission TFT ET1 , the second emission TFT ET2 , and the storage capacitor Cst. Here, for the implementation of the NMOS, the driving TFT DT, the first to third scan TFTs ST1 to ST3, and the first and second emission TFTs ET1 and ET2 may all be implemented as N-type.

The OLED, the driving TFT DT, the first to third scan TFTs ST1 to ST3, and the storage capacitor Cst are connected in the same manner as in FIG. 4 .

The first emission TFT ET1 is switched in response to the j-1 th emission driving signal Ej-1 from the j-1 th emission line 16j-1 to drive the high potential driving voltage EVDD. It is applied to the drain electrode of the TFT (DT). The gate electrode of the first emission TFT ET1 is connected to the j-1 th emission line 16j-1, the source electrode is connected to the input terminal of the high potential driving voltage EVDD, and the drain electrode is connected to the driving TFT ( DT) is connected.

The second emission TFT ET2 turns on/off the current flow between the node A and the node B in response to the j-th emission driving signal Ej from the j-th emission line 16j. The gate electrode of the second emission TFT ET2 is connected to the j-th emission line 16j, the source electrode is connected to the node A, and the drain electrode is connected to the node B.

One frame period may include an initialization period Ti, a sampling & programming period Ts, and an emission period Te as shown in FIG. 10 .

The j-1th scan driving signal Sj-1 is applied at a high level (H) during the initialization period Ti, and is applied at a low level (L) during the sampling & programming period Ts and the emission period Te. . The j-th scan driving signal Sj is applied at a high level H during the sampling & programming period Ts, and is applied at a low level L during the initialization period Ti and the light emission period Te. The j-1th emission driving signal Ej-1 is applied at a low level (L) during the initialization period Ti, and is applied at a high level (H) during the sampling & programming period Ts and the emission period Te. do. And, the j-th emission driving signal Ej is applied at a low level (L) during the sampling & programming period (Ts), and is applied at a high level (H) during the initialization period (Ti) and the emission period (Te), The data voltage Vdata is applied from the data line to the pixel PXL during the sampling & programming period Ts.

The operation of the pixel PXL is the same as described above with reference to FIGS. 5 to 7 . Therefore, the description of the operation of this pixel is omitted.

11 and 12 are diagrams showing simulation results of compensating the threshold voltage of the driving TFT in a state in which a white image and a black image are displayed, respectively.

11 and 12 , the voltage at the node C (the source-side voltage of the driving TFT) is automatically compensated according to the threshold voltage variation ΔVth according to the above-described internal compensation operation. Accordingly, a grayscale distortion (distortion) caused by a change in the threshold voltage Vth of the driving TFT DT is automatically compensated.

According to the experiment, the threshold voltage compensation ratio of the driving TFT based on the white image was 97.27% on average, and the threshold voltage compensation ratio of the driving TFT based on the black image was found to be 98.96% on average.

As described above, in the present invention, a reference line for supplying a reference voltage is provided separately from a data line to which a data voltage is supplied, and the threshold voltage sampling time required for compensation is reduced by simultaneously applying the data voltage and the reference voltage required for compensation to the pixel. enough can be obtained. Accordingly, the present invention can realize clear image quality by greatly increasing the accuracy of compensation in a high-resolution model. In addition, the present invention does not need to swing the voltage between the data voltage and the reference voltage on the data line, unlike the prior art, so that power consumption can be greatly reduced.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: data line 15: gate line

Claims (8)

a display panel provided with a plurality of pixels;
a gate driving circuit for driving scan lines of the display panel; and
a data driving circuit for driving data lines of the display panel;
Each of the pixels arranged in the j-th pixel row (j is a natural number greater than or equal to 2) and connected to the j-1th scan line and the j-th scan line,
an organic light emitting diode connected between the node C and the input terminal of the low potential driving voltage;
a driving TFT including a gate connected to the node A and a source connected to the node C to control a driving current applied to the organic light emitting diode;
a first scan TFT connected between an initialization line supplied with an initialization voltage and the node C, and switched according to a j-1th scan driving signal from the j-1th scan line;
a second scan TFT connected between a reference line to which a reference voltage is supplied and the node A and switched according to a j-th scan driving signal from the j-th scan line;
a third scan TFT connected between any one of the data lines and a node B and switched according to the j-th scan driving signal;
a first emission TFT connected between the input terminal of the high potential driving voltage and the drain of the driving TFT, the first emission TFT being switched opposite to that of the first scan TFT according to the j-1th scan driving signal;
a second emission TFT connected between the node A and the node B and switched oppositely to the second and third switch TFTs according to the j-th scan driving signal;
and a storage capacitor connected between the node B and the node C. The method of claim 1,
The reference line is provided separately from the data lines,
and the first to third switch TFTs are implemented as an N-type, and the first and second emission TFTs are implemented as a P-type. The method of claim 1,
One frame period is
an initialization period for applying the initialization voltage from the initialization line to the node C;
The reference voltage from the reference line is applied to the node A, and a data voltage from any one of the data lines is applied to the node B to sample the threshold voltage of the driving TFT and a sampling & programming period for storing a compensation voltage including a threshold voltage as a programming voltage in the storage capacitor; and
and a light emitting period in which the organic light emitting diode emits light by applying a driving current according to the programming voltage to the organic light emitting diode. 4. The method of claim 3,
the j-1th scan driving signal is applied at a high level during the initialization period and is applied at a low level during the sampling & programming period and the light emission period;
the j-th scan driving signal is applied at a high level during the sampling & programming period and is applied at a low level during the initialization period and the light emission period;
and the data voltage is applied to the pixel from the data line during the sampling & programming period. a display panel provided with a plurality of pixels;
a gate driving circuit for driving scan lines and emission lines of the display panel; and
a data driving circuit for driving data lines of the display panel;
Each of the pixels arranged in the j-th pixel row (j is a natural number greater than or equal to 2) and connected to the j-1 th scan line and the j-th scan line, and the j-1 th emission line and the j-th emission line,
an organic light emitting diode connected between the node C and the input terminal of the low potential driving voltage;
a driving TFT including a gate connected to the node A and a source connected to the node C to control a driving current applied to the organic light emitting diode;
a first scan TFT connected between an initialization line supplied with an initialization voltage and the node C, and switched according to a j-1th scan driving signal from the j-1th scan line;
a second scan TFT connected between a reference line to which a reference voltage is supplied and the node A and switched according to a j-th scan driving signal from the j-th scan line;
a third scan TFT connected between any one of the data lines and a node B and switched according to the j-th scan driving signal;
a first emission TFT connected between an input terminal of a high potential driving voltage and a drain of the driving TFT, the first emission TFT being switched according to a j-1 th emission driving signal from the j-1 th emission line;
a second emission TFT connected between the node A and the node B and switched according to a j-th emission driving signal from the j-th emission line;
a storage capacitor connected between the node B and the node C;
One frame period is
an initialization period for applying the initialization voltage from the initialization line to the node C;
The reference voltage from the reference line is applied to the node A, and a data voltage from any one of the data lines is applied to the node B to sample the threshold voltage of the driving TFT and a sampling & programming period for storing a compensation voltage including a threshold voltage as a programming voltage in the storage capacitor; and
and a light emitting period in which the organic light emitting diode emits light by applying a driving current according to the programming voltage to the organic light emitting diode;
the j-1th scan driving signal is applied at a high level during the initialization period and is applied at a low level during the sampling & programming period and the light emission period;
the j-th scan driving signal is applied at a high level during the sampling & programming period and is applied at a low level during the initialization period and the light emission period;
the j-1th emission driving signal is applied at a low level during the initialization period, and is applied at a high level during the sampling & programming period and the light emission period;
the j-th emission driving signal is applied at a low level during the sampling & programming period and is applied at a high level during the initialization period and the light emission period;
The data voltage is applied to the pixel from the data line during the sampling & programming period. 6. The method of claim 5,
The reference line is provided separately from the data lines,
and the first to third switch TFTs and the first and second emission TFTs are embodied in an N type. delete delete

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