KR101920492B1 - Organic light emitting diode display device - Google Patents

Abstract

An organic light emitting diode display device includes: an organic light emitting diode (OLED) emitting light by a driving current flowing between an input terminal of a high potential driving voltage and an input terminal of a low potential driving voltage; A driving TFT connected between the input terminal of the high potential driving voltage and the organic light emitting diode and controlling an amount of driving current applied to the organic light emitting diode according to a gate voltage applied to the first node; And an initializing TFT for initializing a gate voltage of the driving TFT by applying an initialization voltage to the first node according to a previous stage scan signal; The initialization TFT is directly connected to the first node.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode (OLED) display device, and more particularly, to an organic light emitting diode display device for improving image quality.

2. Description of the Related Art In recent years, development of various flat panel displays (FPD) has been accelerated. Particularly, the organic light emitting diode display device has advantages of high response speed, high luminous efficiency, high luminance and wide viewing angle by using a self-luminous element which emits light by itself.

The organic light emitting diode display device has an organic light emitting diode as shown in FIG. The organic light emitting diode has organic compound layers (HIL, HTL, EML, ETL, EIL) formed between the anode electrode and the cathode electrode.

The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

The organic light emitting diode display device arranges the pixels including the organic light emitting diode in a matrix form and controls the brightness of the pixels according to the gray level of the video data. Particularly, in an active matrix organic light emitting diode display device using a TFT (Thin Film Transistor) as a switching element, a pixel is selected by selectively turning on a TFT serving as an active element, and the pixel is held in a storage capacitor Thereby maintaining the light emission of the pixel.

2 is a circuit diagram showing one pixel equivalently in an active matrix type organic light emitting diode display.

2, the pixel includes an organic light emitting diode (OLED), a switch TFT (ST), a driver TFT (DT), and a storage capacitor (Cst).

The switch TFT (ST) turns on in response to a scan pulse from the gate line (GL), thereby conducting a current path between the source electrode and the drain electrode. The switch TFT (ST) applies a data voltage from the data line (DL) to the gate electrode of the driver TFT (DT) and the storage capacitor (Cst) during the turn-on period. The driving TFT DT controls the current flowing in the organic light emitting diode OLED according to the gate-source voltage Vgs of its own. The storage capacitor Cst keeps the gate potential of the driving TFT DT constant for a predetermined period. The organic light emitting diode OLED has a structure as shown in FIG. 1 and is connected between the drain electrode of the driving TFT DT and the ground voltage source GND.

The brightness of the pixel as shown in Fig. 2 is proportional to the driving current flowing through the organic light emitting diode OLED, and this driving current depends on the gate-source voltage of the driving TFT DT and the threshold voltage of the driving TFT DT.

The threshold voltage of the driving TFTs varies from pixel to pixel due to various causes such as process variation, deterioration with time, and the like. Recently, a technique of changing the pixel structure to compensate for the threshold voltage deviation of the driving TFTs between pixels and performing an initializing operation and a sampling operation prior to the light emission of the pixels every frame has been used. In the initializing operation, the gate voltage of the driving TFT is initialized to a predetermined value, and in the sampling operation subsequent to the initializing operation, the threshold voltage of the driving TFT is reflected to the gate voltage of the driving TFT.

In order for the threshold voltage deviation of the driving TFTs between pixels to be effectively compensated, the gate voltage of the driving TFT must be sufficiently initialized to a desired predetermined value within the initialization period. However, in the conventional pixel structure, the initial path to the gate electrode of the driving TFT is long, so that the parasitic capacitor is greatly affected. The greater the effect of the parasitic capacitor on the initialization path, the lower the response characteristic of the pixel. That is, when the display image is changed from black gradation to white gradation (or from white gradation to black gradation), if the parasitic capacitance on the initialization path is large, the previous frame data held in the gate electrode of the driving TFT can not be sufficiently initialized It affects the frame data. As a result, if the gate voltage of the driving TFT is not sufficiently initialized due to the influence of the parasitic capacitance, the response speed is lowered and the image quality of the display image is deteriorated.

Accordingly, it is an object of the present invention to provide an organic light emitting diode display device capable of improving the image quality of a display image by reducing the initialization path of the driving TFT, thereby increasing the response speed of the pixel.

According to an aspect of the present invention, there is provided an organic light emitting diode display comprising: an organic light emitting diode (OLED) emitting light by a driving current flowing between an input terminal of a high potential driving voltage and an input terminal of a low potential driving voltage; A driving TFT connected between the input terminal of the high potential driving voltage and the organic light emitting diode and controlling an amount of driving current applied to the organic light emitting diode according to a gate voltage applied to the first node; And an initializing TFT for initializing a gate voltage of the driving TFT by applying an initialization voltage to the first node according to a previous stage scan signal; The initialization TFT is directly connected to the first node.

The initialization voltage may be selected from a reference voltage and a low-potential driving voltage.

The initializing TFT includes: a gate electrode connected to a previous scan line to which the previous scan signal is applied; A source electrode connected to an input terminal of the reference voltage; And a drain electrode directly connected to the first node.

The initializing TFT includes: a gate electrode connected to a previous scan line to which the previous scan signal is applied; A source electrode connected to an input terminal of the low potential driving voltage; And a drain electrode directly connected to the first node.

A first switch TFT for switching a current path between the data line and the second node according to the current stage scan signal; A second switch TFT for switching a current path between a third node connected to a drain electrode of the driving TFT and the first node in accordance with the current stage scan signal; A third switch TFT for applying the reference voltage to the second node according to the current edge emission signal; A fourth switch TFT for switching a current path between the third node and the anode electrode of the organic light emitting diode according to the current end emission signal; A fifth switch TFT for switching a current path between an input terminal of the reference voltage and an anode electrode of the organic light emitting diode according to the current stage scan signal; And a storage capacitor connected between the first node and the second node.

The first frame period, the second frame period, the second frame period, the second frame period, the second frame period, the second frame period, the first frame period, A sampling period, and a light emitting period subsequent to the sampling period.

Wherein the previous stage scan signal is generated at an activation level in the first and second initialization periods and at a deactivation level in the sampling period and the light emission period; Wherein the current stage scan signal is generated at an activation level in the sampling period and at a deactivation level in the first and second initialization periods and the light emission period; The current stage emission signal is generated at an activation level in the first initialization period and the light emission period, and is generated at a deactivation level in the second initialization period and the sampling period.

The organic light emitting diode display device according to the present invention includes initializing TFTs directly connected to the gate electrodes of the driving TFTs for respective pixels to reduce the initialization path of the driving TFTs so as to increase the response speed of the pixels and improve the image quality of the display image .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining the principle of light emission of a general organic light emitting diode display device. FIG.
2 is an equivalent circuit diagram of a pixel in a conventional organic light emitting diode display.
3 is a block diagram showing an organic light emitting diode display device according to an embodiment of the present invention.
4 is an equivalent circuit diagram showing an example of a pixel arranged in an nth horizontal pixel line;
FIG. 5 is a diagram showing waveforms of scan signals and emission signals applied to the pixel of FIG. 4;
FIGS. 6A to 6D are diagrams showing equivalent circuits of pixels for each operation period, which are divided through FIG. 5;
7 is a waveform diagram showing a potential change of the first node in each operation period.
8 is a graph showing a simulation result of a current change applied to an organic light emitting diode when a display image is changed from a black gradation to a white gradation in comparison with a conventional one.
FIG. 9 is a diagram showing a response speed between black gradation and white gradation based on FIG.
10 is an equivalent circuit diagram showing another example of pixels arranged in the nth horizontal pixel line;

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 3 to 10. FIG.

3 is a block diagram illustrating an organic light emitting diode display device according to an embodiment of the present invention.

3, an organic light emitting diode display device according to an embodiment of the present invention includes a display panel 10 in which pixels P are arranged in a matrix form, a data driver (not shown) for driving the data lines 14 A scan driver 13A for driving the scan lines 15; an emission driver 13B for driving the emission lines 16; And a timing controller 11 for controlling the operation.

The display panel 10 includes a plurality of data lines 14, scan lines 15 and emission lines 16 intersecting with the data lines 14, signal lines 14, The pixels P are arranged in each of the intersecting regions. Each of the pixels P is supplied with a high potential driving voltage Vdd, a low potential driving voltage Vss and a reference voltage Vref. Each of the pixels P may be connected to one data line 14, two neighboring scan lines 15, and one emission line 16 as shown in FIGS. The high-potential driving voltage (Vdd) is generated at a constant DC level by the high-potential driving voltage source. The low-potential driving voltage Vss is generated at a constant DC level by the low-potential driving voltage source. The reference voltage Vref is generated at a constant DC level by the reference voltage source. The reference voltage Vref can be generated at a voltage level higher than the black gradation voltage and lower than the white gradation voltage. Each of the pixels P includes an initializing TFT directly connected to the gate electrode of the driving TFT so as to reduce the initializing path compared to the prior art and to set the gate voltage of the driving TFT to the reference voltage Vref or the low- (Vss).

The timing controller 11 arranges the digital video data RGB input from the outside according to the resolution of the display panel 10 and supplies the data to the data driver 12. [ The timing controller 11 also controls the timing of the data driver 12 based on the timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK and the data enable signal DE. A data control signal DDC for controlling the operation timing, a scan control signal SDC for controlling the operation timing of the scan driver 13A and an emission control signal for controlling the operation timing of the emission driver 13B Signal EDC.

The data driver 12 converts the digital video data RGB into an analog data voltage (hereinafter, referred to as a data voltage) according to the data control signal DDC and supplies it to the data lines 14.

The scan driver 13A generates a scan signal in accordance with the scan control signal SDC and supplies the scan signal to the scan lines 15. [ The scan driver 13A includes a shift register for shifting the scan signal. The shift register can be formed directly on the display panel 10 according to the GIP (Gate Driver IC In Pane) method.

The emission driver 13B generates an emission signal according to the emission control signal EDC and supplies it to the emission lines 16. [ The emission driver 13B includes a shift register for shifting the emission signal. The shift register can be formed directly on the display panel 10 according to the GIP (Gate In Panel) method.

Fig. 4 shows an example of a pixel P arranged on the nth horizontal pixel line (n is a positive integer).

4, a pixel P according to an embodiment of the present invention includes an organic light emitting diode OLED, a driving TFT DT, a reset TFT Tint directly connected to the gate electrode of the driving TFT DT, A plurality of switch TFTs ST1 to ST5, and a storage capacitor Cst. Here, the TFTs DT, Tint and ST1 to ST5 may all be implemented as a P-type MOSFET (Metal-Oxide Semiconductor Field Effect Transistor).

The organic light emitting diode OLED emits light by a driving current flowing between the input terminal of the high potential driving voltage Vdd and the input terminal of the low potential driving voltage Vss. The cathode electrode of the organic light emitting diode OLED is connected to the input terminal of the low potential driving voltage Vss. The organic light emitting diode (OLED) has a structure as shown in FIG.

The driving TFT DT is connected between the input terminal of the high potential driving voltage Vdd and the organic light emitting diode OLED and is driven by the driving voltage applied to the anode electrode of the organic light emitting diode OLED according to the potential of the first node N1. The amount of current is controlled. The gate electrode of the driving TFT DT is connected to the first node N1, the source electrode thereof is connected to the input terminal of the high potential driving voltage Vdd, and the drain electrode thereof is connected to the third node N3.

The initializing TFT Tint applies the reference voltage Vref to the first node N1 in accordance with the previous stage scan signal SCAN [n-1] to set the gate voltage of the driving TFT DT to the reference voltage Vref Initialize. The gate electrode of the initialization TFT Tint is connected to the previous scan line 15n-1, the source electrode thereof is connected to the input terminal of the reference voltage Vref, and the drain electrode thereof is connected to the first node N1. The initializing TFT Tint is directly connected to the first node N1 to which the gate electrode of the driving TFT DT is connected, thereby reducing the initialization path compared to the prior art. If the initialization path is shortened, the influence of the parasitic capacitance on the initialization path is reduced, so that the gate voltage of the driving TFT DT can be quickly initialized to the reference voltage Vref within a desired time. This leads to an improvement in the response speed of pixels and an improvement in image quality.

The first switch TFT (ST1) switches the current path between the data line 14 and the second node N2 in accordance with the current stage scan signal SCAN [n]. The gate electrode of the first switch TFT (ST1) is connected to the current stage scan line (15n), the source electrode is connected to the data line (14), and the drain electrode is connected to the second node (N2).

The second switch TFT (ST2) switches the current path between the first node (N1) and the third node (N3) according to the current stage scan signal (SCAN [n]). The gate electrode of the second switch TFT (ST2) is connected to the current stage scan line 15n, the source electrode thereof is connected to the third node N3, and the drain electrode thereof is connected to the first node N1.

The third switch TFT ST3 applies the reference voltage Vref to the second node N2 in accordance with the current terminal emission signal EM [n]. The gate electrode of the third switch TFT (ST3) is connected to the current end emission line (16n), the source electrode is connected to the input terminal of the reference voltage (Vref), and the drain electrode is connected to the second node (N2).

The fourth switch TFT (ST4) switches the current path between the third node N3 and the anode electrode of the organic light emitting diode OLED according to the current end emission signal EM [n]. The gate electrode of the fourth switch TFT (ST4) is connected to the current end emission line (16n), the source electrode is connected to the third node (N3), and the drain electrode is connected to the anode electrode of the organic light emitting diode do.

The fifth switch TFT ST5 switches the current path between the input terminal of the reference voltage Vref and the anode electrode of the organic light emitting diode OLED according to the current stage scan signal SCAN [n]. The gate electrode of the fifth switch TFT ST5 is connected to the current stage scan line 15n and the source electrode thereof is connected to the input terminal of the reference voltage Vref and the drain electrode thereof is connected to the anode electrode of the organic light emitting diode OLED do.

The storage capacitor Cst is connected between the first node N1 and the second node N2. The storage capacitor Cst stabilizes the gate voltage of the driving TFT DT.

FIG. 5 shows the waveforms of scan signals SCAN [n-1], SCAN [n] and emission signal EM [n] applied to the pixel of FIG.

5, the operation of the pixel P according to an exemplary embodiment of the present invention is performed on the waveform of the scan signals SCAN [n-1], SCAN [n] and the emission signal EM [n] Accordingly, it can be described as an initialization period T1, a sampling period T2, and a light emission period T3. The initialization period T1 may be divided into a first initialization period T1A and a second initialization period T1B. In FIG. 5, 'Td1' and 'Td2' indicate transient periods. 5, 'H' indicates a deactivation level capable of turning off the TFT of the pixel, and 'L' indicates an activation level capable of turning on the TFT of the pixel.

The previous stage scan signal SCAN [n-1] is generated at the activation level L in the first and second initialization periods T1A and T1B and is inactivated at the sampling period T2 and the light emission period T3 Level (H). The current stage scan signal SCAN [n] is generated at the activation level L in the sampling period T2 and is set at the inactive level (L) during the first and second initialization periods T1A and T1B and the light emission period T3 H). The current stage emission signal EM [n] is generated at the activation level L in the first initializing period T1A and the light emitting period T3, and the second initializing period T1B and the sampling period T2 ) To a deactivation level (H).

FIGS. 6A to 6D show equivalent circuits of pixels for each operation period, which are divided through FIG. 7 is a waveform diagram showing the potential change of the first node in each operation period. The specific operation of the pixels in each operation period will be described with reference to FIGS. 5 to 7. FIG.

6A, during the first initialization period T1A, the initialization TFT Tint is turned on in response to the previous stage scan signal SCAN [n-1] of the activation level L, The first, second and fifth switch TFTs ST1, ST2 and ST5 are turned off in response to the current stage scan signal SCAN [n] EM [n]), the third and fourth switch TFTs ST3 and ST4 are turned on.

As a result, during the first initializing period T1A, the potential VN1 of the first node N1 is changed to the reference voltage Vref. At this time, since the reference voltage Vref is also applied to the second node N2 connected to the first node N1 through the capacitor Cst, the potential VN1 of the first node N1 becomes higher (Vref).

6B, during the second initialization period T1B, the initializing TFT Tint is turned on in response to the previous stage scan signal SCAN [n-1] of the activation level L, The first to fifth switch TFTs ST1 to ST5 are all turned off in response to the current stage scan signal SCAN [n] and the current stage emission signal EM [n].

As a result, during the second initialization period T1B, the second node N2 is floated and the potential VN1 of the first node N1 maintains the reference voltage Vref, which is the initialization level.

6C, during the sampling period T2, the initialization TFT Tint is turned off in response to the previous stage scan signal SCAN [n-1] of the inactivation level H, The first, second and fifth switch TFTs ST1, ST2 and ST5 are turned on in response to the current stage scan signal SCAN [n] of the inactive level H, [n]), the third and fourth switch TFTs ST3 and ST4 are turned off.

As a result, during the sample, the potential VN1 of the first node N1 is lower than the potential of the diode connection (the gate electrode and the drain electrode of the driving TFT DT are shorted, or the first node N1, (Vdd-Vth) obtained by subtracting the threshold voltage (Vth) of the driving TFT (DT) from the high potential driving voltage (Vdd) by means of the third node (N3) At the same time, the potential of the second node N2 is programmed to the data voltage Vdata.

In the sampling period T2, the sampled first calculation value Vdd-Vth is held at the first node N1 by the storage capacitor Cst and the programmed data voltage Vdata is stored in the storage capacitor Cst Lt; RTI ID = 0.0 > N2. ≪ / RTI >

6D, the initialization TFT Tint is turned off in response to the previous scan signal SCAN [n-1] of the inactive level H during the light emission period T3, and the inactive level H The first, second and fifth switch TFTs ST1, ST2 and ST5 are turned off in response to the current stage scan signal SCAN [n] of the activation level L, [n]), the third and fourth switch TFTs ST3 and ST4 are turned on.

As a result, the potential of the second node N2 is changed from the data voltage Vdata that was held immediately before to the reference voltage Vref. A value obtained by subtracting the reference voltage Vref from the second calculated value Vdata-Vref corresponding to this variation, that is, the data voltage Vdata, is reflected on the potential VN1 of the first node N1. Accordingly, the potential VN1 of the first node N1 is set to a compensation value {(Vdd-Vth) - (Vdata-Vref) obtained by subtracting the second calculated value Vdata-Vref from the first calculated value Vdd- }.

The potential VN1 of the first node N1 is set to the compensation value Vdd-Vth- (Vdata-Vref), and the fourth switch TFT ST4 is turned on, so that the organic light emitting diode OLED A driving current Ioled which is not influenced by the threshold voltage Vth of the driving TFT DT flows as shown in the following equation (C).

Here, 'μ' denotes the mobility of the driving TFT DT, 'Cox' denotes the parasitic capacitance of the driving TFT DT, 'W' denotes the channel width of the driving TFT DT, Vth 'is the threshold voltage of the driving TFT DT,' Vdd 'is the high-level driving voltage, and' Vdd 'is the driving voltage of the driving TFT DT. 'Vdata' denotes a data voltage, and 'Vref' denotes a reference voltage.

FIG. 8 shows a simulation result of the current change applied to the organic light emitting diode when the display image is changed from the black gradation to the white gradation. 8, the horizontal axis represents time and the vertical axis represents drive current. FIG. 9 shows the response speed between black gradation and white gradation based on FIG. 8 in comparison with the conventional method.

According to the related art, since the initialization path is long, the gate voltage of the driving TFT is not sufficiently initialized due to the influence of the parasitic capacitance, and the response speed of gray-gray is degraded. According to the related art, when the display image is changed from the black gradation to the white gradation as shown in Fig. 8, the time (response time) for reaching 90% white gradation is very long as about 1.45 frames as shown in Fig.

On the other hand, according to the present invention, by connecting the initializing TFT directly to the gate electrode of the driving TFT, the initialization path is reduced as compared with the prior art, and the influence of the parasitic capacitance on the initialization path is minimized to make the gate voltage of the driving TFT rapidly Initialize. According to the present invention, the response speed of gray to gray is improved and the display quality is enhanced. According to the present invention, when the display image is changed from the black gradation to the white gradation as shown in FIG. 8, the time (response time) for reaching 90% of the white gradation is very short as about 0.75 frames as shown in FIG.

Fig. 10 shows another example of the pixel P arranged on the nth horizontal pixel line (n is a positive integer). The pixel P in Fig. 10 is different from the pixel P in Fig. 4 only in the connection configuration of the initialization TFT (Tint), and the rest (connection configuration, operation, and the like) is substantially the same.

10, a pixel P according to another embodiment of the present invention includes an organic light emitting diode OLED, a driving TFT DT, a reset TFT Tint directly connected to the gate electrode of the driving TFT DT, A plurality of switch TFTs ST1 to ST5, and a storage capacitor Cst.

The initialization TFT Tint applies the low potential driving voltage Vss to the first node N1 in accordance with the previous stage scan signal SCAN [n-1] to change the gate voltage of the driving TFT DT to the low potential driving voltage (Vss). The gate electrode of the initialization TFT Tint is connected to the previous stage scan line 15n-1, the source electrode thereof is connected to the input terminal of the low potential driving voltage Vss, and the drain electrode thereof is connected to the first node N1 . The initializing TFT Tint is directly connected to the first node N1 to which the gate electrode of the driving TFT DT is connected, thereby reducing the initialization path compared to the prior art. If the initialization path becomes shorter, the influence of the parasitic capacitance on the initialization path is reduced, so that the gate voltage of the driving TFT DT can be quickly initialized to the low potential driving voltage Vss within a desired time. This leads to an improvement in the response speed of pixels and an improvement in image quality.

The connection structure and operation of the organic light emitting diode (OLED), the driver TFT (DT), the plurality of switch TFTs (ST1 to ST5), and the storage capacitor (Cst) are substantially the same as in FIG.

As described above, the organic light emitting diode display device according to the present invention includes the initializing TFT directly connected to the gate electrode of the driving TFT for each pixel to reduce the initialization path of the driving TFT, thereby increasing the response speed of the pixel, Can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, in the embodiment of the present invention, only the case where the TFT is implemented as a P-type MOSFET has been described. However, it is needless to say that the technical idea of the present invention is not limited to this and can also be applied to an N-type MOSFET. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Data driver 13A: Scan driver
13B: Emission driver 14: Data line
15: Gate line 16: Emission line

Claims (7)

An organic light emitting diode emitting light by a driving current flowing between an input terminal of a high potential driving voltage and an input terminal of a low potential driving voltage;
A driving TFT connected between the input terminal of the high potential driving voltage and the organic light emitting diode and controlling an amount of driving current applied to the organic light emitting diode according to a gate voltage applied to the first node;
An initialization TFT for initializing a gate voltage of the driving TFT by applying an initialization voltage selected from one of a reference voltage and the low-potential driving voltage to the first node according to a previous scan signal;
A second switch TFT for switching a current path between a third node connected to a drain electrode of the driving TFT and the first node according to a current short scan signal; And
And a fifth switch TFT for switching a current path between an input terminal of the reference voltage and an anode electrode of the organic light emitting diode according to the current stage scan signal;
And the initializing TFT is directly connected to the first node. delete The method according to claim 1,
In the initialization TFT,
A gate electrode connected to a previous scan line to which the previous scan signal is applied;
A source electrode connected to an input terminal of the reference voltage; And
And a drain electrode directly connected to the first node. The method according to claim 1,
In the initialization TFT,
A gate electrode connected to a previous scan line to which the previous scan signal is applied;
A source electrode connected to an input terminal of the low potential driving voltage; And
And a drain electrode directly connected to the first node. The method according to claim 1,
A first switch TFT for switching a current path between the data line and the second node in accordance with the current stage scan signal;
A third switch TFT for applying the reference voltage to the second node according to the current edge emission signal;
A fourth switch TFT for switching a current path between the third node and the anode electrode of the organic light emitting diode according to the current end emission signal; And
And a storage capacitor connected between the first node and the second node. 6. The method of claim 5,
The first frame period, the second frame period, the second frame period, the second frame period, the second frame period, the second frame period, the first frame period, A sampling period, and a light emission period subsequent to the sampling period. The method according to claim 6,
Wherein the previous stage scan signal is generated at an activation level in the first and second initialization periods and at a deactivation level in the sampling period and the light emission period;
Wherein the current stage scan signal is generated at an activation level in the sampling period and at a deactivation level in the first and second initialization periods and the light emission period;
Wherein the current stage emission signal is generated at an activation level in the first initialization period and the light emission period and is generated at a deactivation level in the second initialization period and the sampling period.

Images