KR102358043B1 - Electroluminescent Display Device - Google Patents

Abstract

The electroluminescent display device according to the embodiment of the present specification includes a display panel in which a plurality of pixels are connected to a data line to which a data voltage is supplied, a first power line to which an initialization voltage is supplied, and a second power line to which a high potential power voltage is supplied. be prepared Here, among the pixels, each pixel disposed on the nth horizontal pixel line (n is a natural number) has a gate electrode connected to a node N2, and a first electrode and a second electrode connected to the nodes N1 and N3, respectively, a driving element generating a driving current according to a gate-source voltage; a switch element T1 connected between the node N1 and the data line; a switch element T2 connected between the node N1 and the second power line; a switch element T5 connected between the node N3 and the node N4; and the node N4 and the input terminal of the low potential power supply voltage.

Description

Electroluminescent Display Device

The present specification relates to an electroluminescent display device.

The electroluminescent display device is roughly classified into an inorganic light emitting display device and an organic light emitting display device according to the material of the light emitting layer. Among them, the active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has a fast response speed, luminous efficiency, luminance and The viewing angle is a big advantage.

The organic light emitting display device arranges pixels including OLEDs in a matrix form, and adjusts the luminance of the pixels according to the grayscale of image data. Each of the pixels includes a driving TFT (Thin Film Transistor) that controls a driving current flowing through the OLED according to the gate-source voltage, and one or more switch TFTs for programming the gate-sort voltage of the driving TFT, the driving current Adjusts the display gradation (luminance) with the amount of light emitted by the OLED in proportion to .

In order to realize a uniform image quality without a difference in luminance and color between pixels, the driving characteristics of the pixel, such as the threshold voltage of the driving TFT, must be the same in all pixels. However, there may be variations in driving characteristics between pixels due to process variations. In addition, the deterioration progress rate between the pixels is different according to the driving time of the display device, so that the difference in driving characteristics between the pixels may increase. The amount of driving current flowing to the OLED may be changed due to such a driving characteristic deviation, and as a result, image quality may be non-uniform among pixels.

Accordingly, an internal compensation circuit for compensating for a difference in driving characteristics between pixels is applied to an organic light emitting diode display to improve image quality and lifespan of the display device. An internal compensation circuit may be applied within the pixel. The organic light emitting display uses a compensation circuit in a pixel to sample a gate-source voltage of a driving TFT that varies according to a threshold voltage of the driving TFT, and compensates for a change in the threshold voltage of the driving TFT with the sampled voltage.

A specific node connected to one electrode of the driving TFT in the internal compensation circuit may be connected to the data line through the switch TFT. The switch TFT may be turned on only during a specific period for sampling the gate-source voltage of the driving TFT in one frame, and may be turned off during the remaining periods except for the specific period. A specific node of the internal compensation circuit may float during the remainder of the period during which the switch TFT remains turned off. In this case, since the data voltage to be written in other pixels is continuously supplied to the data line, a specific node of the internal compensation circuit may be affected by voltage coupling when the potential of the data line is changed. Voltage coupling is caused by parasitic capacitors formed between certain nodes of the internal compensation circuit and the data lines. When the potential of a specific node of the internal compensation circuit changes due to the voltage coupling, the gate-source voltage of the driving TFT changes, and accordingly, the luminance of the corresponding pixel may be distorted and display quality may be deteriorated.

Accordingly, the present specification provides an electroluminescent display device in which display quality is not deteriorated even when a specific node of a pixel is affected by voltage coupling by a data line.

The electroluminescent display device according to the embodiment of the present specification includes a display panel in which a plurality of pixels are connected to a data line to which a data voltage is supplied, a first power line to which an initialization voltage is supplied, and a second power line to which a high potential power voltage is supplied. be prepared Here, among the pixels, each pixel disposed on the nth horizontal pixel line (n is a natural number) has a gate electrode connected to a node N2, and a first electrode and a second electrode connected to the nodes N1 and N3, respectively, a driving element generating a driving current according to a gate-source voltage; a switch element T1 connected between the node N1 and the data line; a switch element T2 connected between the node N1 and the second power line; a switch element T5 connected between the node N3 and the node N4; and a light emitting element connected between the node N4 and an input terminal of a low potential power supply voltage and emitting light according to the driving current, wherein the switch element T2 is turned off for PWM (Pulse Width Modulation) driving. remains on.

According to the electroluminescent display device of the present specification, the switch element T2 for supplying a high potential power voltage to the source electrode of the driving element in each pixel, and the switch element T5 for blocking the current flow between the driving element and the light emitting element for PWM driving is switched according to different emission signals. Through this, while the switch element T5 is turned off for PWM driving, the switch element T2 is turned on, and the potential of the source electrode of the driving element is fixed to the high-potential power supply voltage. Accordingly, since the gate-source voltage and the driving current of the driving device do not change despite a change in the potential of the data line during PWM driving, display quality may be improved.

Effects according to the present specification are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present specification.
2 is a diagram illustrating a pixel array of an electroluminescence display according to an embodiment of the present specification.
3 is a diagram illustrating an equivalent circuit of the pixel shown in FIG. 2 .
FIG. 4 is a waveform diagram illustrating driving signals input to the pixel of FIG. 3 and potential changes of specific pixel nodes according thereto.
5 is a waveform diagram showing that during the PWM driving period, emission signal 1 is input at an on level and emission signal 2 is input at an off level at least once according to a preset duty ratio.
6A is an equivalent circuit diagram illustrating an operation of a pixel during the initialization period of FIG. 4 .
6B is an equivalent circuit diagram illustrating an operation of a pixel during the sampling period of FIG. 4 .
6C is an equivalent circuit diagram illustrating an operation of a pixel during the light emission period of FIG. 4 .
6D is an equivalent circuit diagram illustrating an operation of a pixel during the PWM driving period of FIG. 4 .
FIG. 7 is a diagram illustrating potentials of specific nodes of a pixel corresponding to an initialization period, a sampling period, and an emission period of FIG. 4 .
8 is a diagram illustrating another equivalent circuit of the pixel shown in FIG. 2 .
FIG. 9 is a waveform diagram illustrating driving signals input to the pixel of FIG. 8 and potential changes of specific pixel nodes according thereto.

Advantages and features of the present specification, and a method for achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present specification to be complete, and common knowledge in the technical field to which this specification belongs It is provided to fully inform those who have the scope of the specification. The scope of the rights in this specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and thus the present specification is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in the description of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'next to', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

Like reference numerals refer to like elements throughout.

Each feature of the various embodiments of the present specification may be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship. may be

In the present specification, the pixel circuit formed on the substrate of the display panel may be implemented as a TFT having a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, but the technical spirit of the present invention is not limited thereto. A TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of a p-type TFT (PMOS), since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed according to the applied voltage. Accordingly, in the description of the embodiment of the present specification, any one of the source and the drain is described as a first electrode, and the other one of the source and the drain is described as a second electrode.

Hereinafter, various embodiments of the present specification will be described in detail with reference to the accompanying drawings. The component names used in the following description are selected in consideration of the ease of writing the specification, and may be different from the component names of the actual product. In the following embodiments, the electric field display will be mainly described with an organic light emitting display including an organic light emitting material. However, the technical spirit of the present invention is not limited to an organic light emitting display device, and may be applied to an inorganic light emitting display device including an inorganic light emitting material.

1 is an electroluminescent display device according to an embodiment of the present specification. 2 is a pixel array of an electroluminescence display according to an embodiment of the present specification. 3 is a gate driver for driving the pixel array of FIG. 2 .

1 to 3 , an electroluminescent display device according to the present specification includes a display panel 10 including pixels PXL, and a display panel driving circuit 12 for driving signal lines connected to the pixels PXL. , 13), and a timing controller 11 for controlling the display panel driving circuits 12 and 13.

The display panel driving circuits 12 and 13 write input image data DATA to the pixels PXL of the display panel 10 . The display panel driving circuits 12 and 13 include a source driver 12 driving the data lines 14 connected to the pixels PXL, and a gate driving the gate lines 15 connected to the pixels PXL. A driver 13 is included.

In the display panel 10 , a plurality of data lines 14 and a plurality of gate lines 15 cross each other, and the pixels PXL are arranged in a matrix form. The pixels PXL may include an OLED. OLED, which is a self-luminous device, includes an anode electrode and a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection Layer, EIL). When a power voltage is applied to the anode and cathode electrodes, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the light emitting layer (EML) to form excitons, and as a result, the light emitting layer (EML) is produces visible light.

The display panel 10 may include an active area AA having a pixel array and a non-display area outside the active area AA. The pixel array is provided with a plurality of horizontal pixel lines L1 to L4 as shown in FIG. 2 , horizontally adjacent to each other on each horizontal pixel line L1 to L4 and commonly connected to the gate lines 15 . A plurality of pixels PXL are disposed. Here, each of the horizontal pixel lines L1 to L4 does not mean a physical signal line, but a set of pixels corresponding to one line implemented by horizontally adjacent pixels PXL. The pixel array may include an initialization power line 16 that supplies the initialization voltage Vinit to the pixels PXL, and a high potential power line 17 that supplies the high potential power voltage EVDD to the pixels PXL. have. Also, the pixels PXL may be connected to the low potential power voltage EVSS.

Each of the gate lines 15 includes a first gate line 15a to which the scan signal SC is supplied, a second gate line 15b to which the emission signal 1 EM1 is supplied, and an emission signal 2 EM2 . includes a third gate line 15c to which is supplied. Each pixel PXL disposed on the n-th horizontal pixel line L(n) includes an n-th scan signal SC(n) and an n-th emission signal allocated to the n-th horizontal pixel line L(n). In addition to 1,2 (EM1(n), EM2(n)), the n-1th scan signal SC(n-1) allocated to the n-1th horizontal pixel line L(n-1) is further supplied can be

Each of the pixels PXL may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel. A red pixel, a green pixel, a blue pixel, and a white pixel may constitute one unit pixel for color realization. The color implemented in the unit pixel may be determined according to emission ratios of the red pixel, the green pixel, the blue pixel, and the white pixel. Meanwhile, a white pixel may be omitted from the unit pixel. Each of the pixels PXL has one data line 14 , one first gate line 15a , one second gate line 15b , one third gate line 15c , and an initialization power line 16 . ), a high potential power line 17, etc. may be connected. Each of the pixels PXL may be further connected to the first gate line 15a disposed on the previous horizontal pixel line.

Each of the pixels PXL may include a driving element, a light emitting element, and a plurality of switch elements. Among the switch elements, there are a switch element T2 that supplies a high potential power supply voltage (EVDD) to a specific node of the driving element, and a switch element T5 that blocks current flow between the driving element and the light emitting element for PWM (Pulse Width Modulation) driving. may be included (see FIG. 3 ). PWM driving is for controlling the light emitting duty of the light emitting device within one frame. The off period of the switch element T5 for PWM driving may be determined according to a preset PWM (Pulse Width Modulation) duty ratio. The on/off timings of the switch element T2 and the switch element T5 are designed to be different from each other so that the gate-source voltage of the driving element does not fluctuate during PWM driving due to voltage coupling with the data line 14 . Accordingly, while the switch element T5 is turned off for PWM driving, the switch element T2 may be maintained in an on state, and the potential of a specific node of the driving element may be fixed to the high potential power supply voltage EVDD during PWM driving. The switch element T2 and the switch element T5 may be respectively connected to different gate lines, that is, the second gate line 15b and the third gate line 15c so that the on/off timings are different.

The source driver 12 converts the input image data DATA received from the timing controller 11 in every frame into a data voltage Vdata and then supplies the data voltage Vdata to the data lines 14 . . The source driver 12 outputs the data voltage Vdata using a digital-to-analog converter that converts the input image data DATA into a gamma compensation voltage.

A multiplexer may be further disposed between the source driver 12 and the data lines 14 of the display panel 10 . The multiplexer divides the data voltage output from the source driver 12 through one output channel into a plurality of data lines, thereby reducing the number of output channels of the source driver 12 compared to the number of data lines. The multiplexer may be omitted depending on the resolution and use of the display device.

The source driver 12 may further include a power generator. The power generator may generate and supply the initialization voltage Vinit to the initialization power line 16 , and generate and supply the high potential power supply voltage EVDD to the high potential power line 17 . The power generator may further generate a low potential power voltage EVSS. Meanwhile, the power generator may be electrically connected to the source driver 12 through a conductive film or the like after being mounted on the outside of the source driver 12 . In order to prevent unnecessary light emission of the OLED during the initialization period and the sampling period, the initialization voltage Vinit may be designed within a voltage range sufficiently lower than the operating point voltage of the OLED.

The gate driver 13 includes a first gate driver generating the scan signals SC( 1 ) to SC( 4 ) of FIG. 2 , and the emission signals 1 of FIG. 2 , EM1 ( 1 ) to EM1 ( 4 ). ) and a third gate driver generating the emission signals 2 EM2( 1 ) to EM2( 4 ) of FIG. 2 .

The first gate driver has as many stages as the horizontal pixel lines L1 to L4 , and outputs scan signals SC( 1 ) to SC( 4 ) under the control of the timing controller 11 . The first gate driver is implemented as a shift register and transmits the scan signals SC(1) to SC(4) through a plurality of first output nodes to the first gate lines 15a(1) to 15a ( 4)) can be supplied sequentially.

The second gate driver has as many stages as the horizontal pixel lines L1 to L4 , and outputs emission signals 1 EM1 ( 1 ) to EM1 ( 4 ) under the control of the timing controller 11 . The second gate driver is implemented as a shift register and transmits the emission signals 1 to EM1(4) to the second gate lines 15b(1) to 15b(4) through a plurality of second output nodes. ) can be supplied sequentially.

The third gate driver has as many stages as the horizontal pixel lines L1 to L4 and outputs the emission signals 2 EM2( 1 ) to EM2( 4 ) under the control of the timing controller 11 . The third gate driver is implemented as a shift register and transmits the emission signals 2 EM2(1) to EM2(4) to the third gate lines 15c(1) to 15c(4) through a plurality of third output nodes. ) can be supplied sequentially.

In order to simplify the configuration of the gate driver 13 , each of the first output nodes may be commonly connected to two adjacent horizontal pixel lines. In the case of the pixel PXL as shown in FIG. 4 , two scan signals having different ON timings are required. For example, two scan signals applied to the pixels PXL of the n-th horizontal pixel line Ln are an n-1 th scan signal SC(n-1) and an nth scan signal SC(n). ), since the pixels PXL of the n-th horizontal pixel line Ln can be driven by a single gate driver, there is an advantage in that the configuration of the gate driver 13 can be simplified. In this case, since the nth scan signal SC(n) and the n−1th scan signal SC(n−1) are gate signals continuously output from a single gate driver, the pulse widths are the same and the phases are the same. can be different.

The gate driver 13 may be directly formed on the non-display area of the display panel 10 together with the pixel array through a gate-driver in panel (GIP) process, but is not limited thereto. After the gate driver 13 is manufactured as an IC type, it may be bonded to the display panel 10 through a conductive film.

The timing controller 11 receives digital data DATA of an input image and a timing signal synchronized with the digital data DATA from the host system. The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. The host system may be any one of a television (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The timing controller 11 multiplies the input frame frequency by i (i is a positive integer greater than 0) to control the operation timing of the display panel driving circuits 12 and 13 with a frame frequency of the input frame frequency × i Hz. have. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase-Alternating Line) scheme.

The timing controller 11 includes a data timing control signal DDC for controlling the operation timing of the source driver 12 based on the timing signals Vsync, Hsync, DE received from the host system, and the gate driver 13 . A gate timing control signal GDC for controlling the operation timing is generated.

The data timing control signal DDC includes a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the sampling start timing of the source driver 12 . The source sampling clock is a clock for shifting the data sampling timing. If the signal transmission interface between the timing controller 11 and the source driver 12 is a mini LVDS (Low Voltage Differential Signaling) interface, the source start pulse and the source sampling clock may be omitted.

The gate timing control signal GDC includes a gate start pulse, a gate shift clock, and a gate output enable signal. In the case of the GIP circuit, the gate output enable signal (Gate Output Enable) may be omitted. The gate start pulse is generated at the beginning of each frame period and is input to the shift register of each of the gate drivers 13 . The gate start pulse is a process in which scan signals SC(1) to SC(4) and emission signals EM1(1) to EM1(4), EM2(1) to EM2(4) are output every frame period. Control the start timing. The gate shift clock is input to the shift register of the gate driver 13 to control shift timing of the gate signal.

FIG. 3 is an equivalent circuit of the pixel shown in FIG. 2 .

Referring to FIG. 3 , the pixel PXL according to the exemplary embodiment of the present specification includes an OLED, a plurality of thin film transistors (TFTs) T1 to T6 , and a storage capacitor Cst. The TFTs T1 to T6 and DT may be implemented as PMOS-type LTPS TFTs, and through this, desired response characteristics may be secured. However, the technical spirit of the present specification is not limited thereto. For example, at least one TFT among the switch TFTs T1 to T6 may be implemented as an NMOS type oxide TFT having good off-current characteristics, and the remaining TFTs may be implemented as a PMOS type LTPS TFT having good response characteristics.

Hereinafter, a connection configuration of one pixel PXL disposed on the n-th horizontal pixel line will be described in detail.

The OLED is a light emitting device that emits light according to a driving current adjusted according to the gate-source voltage (Vgs) of the driving TFT (DT). The anode electrode of the OLED is connected to the node N4, and the cathode electrode of the OLED is connected to the input terminal of the low potential power supply voltage (EVSS). An organic compound layer is provided between the anode electrode and the cathode electrode.

The driving TFT (DT) is a driving element that adjusts the driving current flowing through the OLED according to the gate-source voltage. The driving TFT DT includes a gate electrode connected to a node N2, a first electrode connected to a node N1, and a second electrode connected to a node N3.

The first switch TFT T1 is connected between the data line 14 and the node N1 and is a switch element that is switched according to the n-th scan signal SC(n). The gate electrode of the first switch TFT T1 is connected to the n-th first gate line 15a(n) to which the n-th scan signal SC(n) is applied, and the first switch TFT T1 The electrode is connected to the data line 14, and the second electrode of the first switch TFT T1 is connected to the node N1.

The second switch TFT T2 is connected between the high potential power line 17 and the node N1, and is a switch element that is switched according to the n-th emission signal 1 EM1(n). The gate electrode of the second switch TFT T2 is connected to the n-th second gate line 15b(n) to which the n-th emission signal 1 EM1(n) is applied, and the gate electrode of the second switch TFT T2 is The first electrode is connected to the high potential power line 17, and the second electrode of the second switch TFT T2 is connected to the node N1.

The third switch TFT T3 is connected between the node N2 and the node N3 and is a switch element that is switched according to the nth scan signal SC(n). The gate electrode of the third switch TFT T3 is connected to the n-th first gate line 15a(n) to which the n-th scan signal SC(n) is applied, and the first gate electrode of the third switch TFT T3 is applied. The electrode is connected to the node N3, and the second electrode of the third switch TFT T3 is connected to the node N2.

The fourth switch TFT T4 is connected between the node N2 and the initialization power line 16 and is a switch element that is switched according to the n-1 th scan signal SC(n-1). The gate electrode of the fourth switch TFT T4 is connected to the n−1 th first gate line 15a (n−1) to which the n−1 th scan signal SC(n−1) is applied, and a fourth A first electrode of the switch TFT T4 is connected to the node N2 , and a second electrode of the fourth switch TFT T4 is connected to the initialization power supply line 16 .

The fifth switch TFT T5 is connected between the node N3 and the node N4 and is a switch element that is switched according to the nth emission signal 2 EM2(n). The gate electrode of the fifth switch TFT T5 is connected to the n-th third gate line 15c(n) to which the n-th emission signal 2 EM2(n) is applied, and the gate electrode of the fifth switch TFT T5 is The first electrode is connected to the node N3, and the second electrode of the fifth switch TFT T5 is connected to the node N4.

The sixth switch TFT T6 is connected between the node N4 and the initialization power line 16 and is a switch element that is switched according to the nth scan signal SC(n). The gate electrode of the sixth switch TFT T6 is connected to the n-th first gate line 15a(n) to which the n-th scan signal SC(n) is applied, and the first gate electrode of the sixth switch TFT T6 is applied. The electrode is connected to the node N4 , and the second electrode of the sixth switch TFT T6 is connected to the initialization power supply line 16 .

The storage capacitor Cst is connected between the high potential power line 17 and the node N2.

Meanwhile, the third and fourth switch TFTs T3 and T4 having one electrode connected to the node N2 may be designed in a dual gate structure so that leakage current can be suppressed when turned off. In the dual gate structure, two gate electrodes are connected to each other to have the same potential. According to the dual gate structure, since the channel length is increased compared to the single gate structure, the off resistance is increased and the off current is reduced, so that operation stability can be secured.

FIG. 4 is a waveform diagram illustrating driving signals input to the pixel of FIG. 3 and potential changes of specific pixel nodes according thereto. FIG. 5 is a waveform diagram showing that during the PWM driving period, emission signal 1 is input to an on level and emission signal 2 is input to an off level at least once according to a preset duty ratio. 6A to 6B illustrate pixel operations during the initialization period, sampling period, light emission period, and PWM driving period of FIG. 4 . 7 is a diagram illustrating potentials of specific nodes of a pixel corresponding to the initialization period, sampling period, and light emission period of FIG. 4 .

Referring to FIG. 4 , one frame period for driving each pixel PXL disposed on the n-th horizontal pixel line Ln includes an initialization period (①), a sampling period (②) following the initialization period (①), It may include a light emission period (③) following the sampling period (②), and a PWM driving period (④) following the light emission period (③).

Referring to FIG. 4 , in the initialization period (①), the n-1 th scan signal SC(n-1) is input to the on level ON, and the nth scan signal SC(n)) and the n th scan signal SC(n) The emission signal 1 (EM1(n)) and the n-th emission signal 2 (EM2(n)) are input at an off level (OFF). The initialization period (①) is for resetting the node N2 to the initialization voltage Vinit.

Referring to FIG. 6A , the fourth switch TFT T4 is turned on in response to the n−1th scan signal SC(n−1) of the on level ON during the initialization period ①. The initialization voltage Vinit is applied to the node N2 when the fourth switch TFT T4 is turned on. Accordingly, during the initialization period (①), the potential of the node N2 becomes the initialization voltage Vinit as shown in FIG. 7 .

Referring to FIG. 6A , the first switch TFT T1 is turned off in response to the n-th scan signal SC(n) of the OFF level (OFF) during the initialization period (①) and the n-th switch of the OFF level (OFF) is turned off. Since the second switch TFT T2 is turned off in response to the emission signal 1 EM1(n), the node N1 is floated. Since the node N1 and the node N2 are coupled by a parasitic capacitor, the potential of the node N1 is affected by the initialization voltage Vinit applied to the node N2 during the initialization period (①), as shown in FIG. ) is a specific voltage (Vx) lower than that.

Referring to FIG. 6A , since the fifth switch TFT T5 is turned off in response to the n-th emission signal 2 EM2(n) of the off-level OFF during the initialization period ①, the node N3 is floated . Since the node N1 and the node N3 are coupled by the parasitic capacitor, the potential of the node N3 is also affected by the initialization voltage Vinit applied to the node N2 during the initialization period (①), as shown in FIG. 7 , the high potential power supply voltage EVDD ) may be a specific voltage (Vx) lower than that.

Referring to FIG. 6A , the third switch TFT T3 and the sixth switch TFT T6 are further turned off in response to the nth scan signal SC(n) of the off level OFF during the initialization period (①). do.

Referring to FIG. 4 , in the sampling period (②), the n-th scan signal SC(n) is input to the on level (ON), and the n-th scan signal SC(n-1)) and the n-th scan signal SC(n-1) The emission signal 1 (EM1(n)) and the n-th emission signal 2 (EM2(n)) are input at an off level (OFF). The sampling period ② is for sampling the threshold voltage of the driving TFT DT.

Referring to FIG. 6B , the first switch TFT T1 and the third switch TFT T3 are turned on in response to the n-th scan signal SC(n) of the on level ON during the sampling period (②). . When the first switch TFT T1 is turned on, the potential of the node N1 is changed from the specific voltage Vx to the data voltage Vdata as shown in FIG. 7 . Then, when the third switch TFT T3 is turned on, the gate electrode and the second electrode of the driving TFT DT are short-circuited, so that the driving TFT DT is diode-connected. When a current flows through the driving TFT DT while the driving TFT DT is diode-connected, the threshold voltage Vth of the driving TFT DT is sampled and stored in the nodes N2 and N3. That is, "Vdata-Vth" is stored in the nodes N2 and N3 as shown in FIG. 7 . The gate-source voltage Vgs of the driving TFT DT is a voltage between the node N1 and the node N2. Accordingly, the gate-source voltage Vgs of the driving TFT DT becomes the threshold voltage of the driving TFT DT during the sampling period ②.

Referring to FIG. 6B , the sixth switch TFT T6 is further turned on in response to the n-th scan signal SC(n) of the on level ON during the sampling period (②). When the sixth switch TFT T6 is turned on, the potential of the node N4 is reset to the initialization voltage Vinit, and operation stability is increased.

Referring to FIG. 6B , the fourth switch TFT T4 is turned off in response to the n-1 th scan signal SC(n-1) of the off level OFF during the sampling period (②). And, in response to the n-th emission signal 1 (EM1(n)) of the off-level (OFF) during the sampling period (②), the second switch TFT (T2) maintains the turned-off state, the off-level (OFF) In response to the n-th emission signal 2 EM2(n), the fifth switch TFT T5 maintains a turned-off state.

Referring to FIG. 4 , in the light emission period (③), the n-th scan signal SC(n-1) and the n-th scan signal SC(n) are input to an OFF level (OFF), and the n-th scan signal SC(n-1) The emission signal 1 (EM1(n)) and the n-th emission signal 2 (EM2(n)) are input at an on level (ON). The light emission period (3) is for emitting OLED according to the driving current flowing through the driving TFT (DT).

Referring to FIG. 6C , the second switch TFT T2 is turned on in response to the n-th emission signal 1 EM1(n) of the on-level ON during the light emission period ③, and the n-th emission signal In response to 2 (EM2(n)), the fifth switch TFT T5 is turned on. During the light emitting period (③), the potential of the node N1 is changed from the data voltage Vdata to the high potential power supply voltage EVDD by turning on the second switch TFT T2 as shown in FIG. 7 . As shown in FIG. 7 , the potential of the node N2 maintains “Vdata-Vth” stored in the sampling period (②) by the storage capacitor Cst during the light emission period (③). Accordingly, a driving current proportional to the square of "(EVDD-Vdata)" obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs flows through the driving TFT DT during the light emission period (③). Due to the driving current, the potential of the node N3 may be raised to near the high potential power supply voltage EVDD during the light emission period (③) as shown in FIG. 7 . The driving current is applied to the OLED via the fifth switch TFT (T5).

During the light emission period (③), the driving current (Ioled) flowing through the OLED becomes a function that is independent of the threshold voltage (Vth) of the driving TFT (DT) as in Equation 1 and.

[Equation 1]

Here, K is a constant value determined by the mobility, channel ratio, parasitic capacitance, etc. of the driving TFT DT, and Vth is the threshold voltage of the driving TFT DT.

Referring to FIG. 6C , the fourth switch TFT T4 maintains the turned-off state in response to the n-1 th scan signal SC(n-1) of the off level OFF during the light emission period ③. In addition, the first, third, and fifth switch TFTs T1, T3, and T5 are turned off in response to the n-th scan signal SC(n) of the off level OFF during the light emission period (③).

Referring to FIG. 4 , in the PWM driving period (④), the n-1 th scan signal SC(n-1) and the nth scan signal SC(n) are input to the OFF level OFF. In addition, the n-th emission signal 2 (EM2(n)) may be maintained at the off level (OFF), or after being input to the off level (OFF) as shown in FIG. 5 , the on/off level may be further repeated at least once more have. On the other hand, the n-th emission signal 1 (EM1(n)) is maintained at the on level (ON). The PWM driving period (④) is to block the driving current applied to the OLED at least once or more according to the preset PWM duty ratio.

In the PWM driving period (④), the n-th emission signal 2 (EM2(n)) may be maintained at the off level (OFF), and the on level (ON) and the off level (OFF) are set a plurality of times as shown in FIG. 5 . may alternate. The length of time during which the n-th emission signal 2 (EM2(n)) is maintained at the off level (OFF) in the PWM driving period (④) may vary according to the PWM duty ratio. As the time during which the n-th emission signal 2 (EM2(n)) is maintained at the off level (OFF) in the PWM driving period (④) becomes longer, the emission duty of the OLED becomes shorter. Due to the PWM driving period (④), the emission duty ratio of the OLED may be determined within the range of 20% to 90%. If the OLED repeatedly turns on and off with a constant light emission duty ratio in this way, there is an advantage in that an afterimage can be minimized when expressing low grayscale.

Referring to FIG. 6D , in the PWM driving period (④), the fifth switch TFT T5 is turned off in response to the n-th emission signal 2 EM2(n) of the OFF level, but the second switch TFT (T2) maintains the turned-on state in response to the n-th emission signal 1 (EM1(n)) of the on level (ON). When the second switch TFT T2 is turned on, the potential of the node N1 is fixed to the high potential power supply voltage EVDD during the PWM driving period ?. Therefore, even if the potential of the data line 14 is changed by the data voltage Vdata' to be written in another pixel in the PWM driving period (4), the potential of the node N1 is fixed to the high potential power supply voltage EVDD. Voltage coupling by line 14 is not affected. In this way, when the potential of the node N1 is fixed to the high potential power supply voltage EVDD during the PWM driving period ④, the gate-source voltage Vgs of the driving TFT DT and the Since the driving current does not fluctuate, display quality can be improved.

Referring to FIG. 6D , the fourth switch TFT T4 maintains a turn-off state in response to the n-1 th scan signal SC(n-1) having an off level OFF during the PWM driving period ④. . And, in response to the n-th scan signal SC(n) of the off level (OFF) during the PWM driving period (④), the first, third, and fifth switch TFTs (T1, T3, T5) maintain the turned-off state do.

8 is a diagram illustrating another equivalent circuit of the pixel shown in FIG. 2 . Also, FIG. 9 is a waveform diagram illustrating driving signals input to the pixel of FIG. 8 and potential changes of specific pixel nodes according thereto. 8 and 9 are diagrams for explaining an example in which a specific node of a pixel is affected by voltage coupling by a data line, thereby degrading display quality.

Compared to the pixel PXL of FIG. 3 , in the pixel PXL of FIG. 8 , the second and fifth switch TFTs T2 and T5 are switched according to the same n-th emission signal EM(n) different from One frame period for driving the pixel PXL of FIG. 8 may also include an initialization period (①), a sampling period (②), a light emission period (③), and a PWM driving period (④) as in FIG. 9 . The operation of the pixel PXL of FIG. 8 during the initialization period (①), the sampling period (②), and the light emission period (③) is substantially the same as described above with reference to FIGS. 6A to 6C .

However, the operation of the pixel PXL of FIG. 8 during the PWM driving period ④ is different from that described above with reference to FIG. 6D . This will be described in detail as follows. During the PWM driving period (④), the second and fifth switch TFTs T2 and T5 are turned off according to the n-th emission signal EM(n) of the OFF level, The first switch TFT T1 is turned off according to the n-th scan signal SC(n) to float the node N1. Accordingly, when the potential of the data line 14 is changed by the data voltage Vdata' to be written to another pixel in the PWM driving period (4), the potential of the node N1 is influenced by voltage coupling by the data line 14 By the voltage coupling, the potential change ΔA of the node N1 is different from the potential change ΔB of the node N2. In this way, when the potential change ΔA of the node N1 and the potential change ΔB of the node N2 are different during the PWM driving period (④), the gate-source voltage Vgs and the driving current of the driving TFT DT change. As a result, the display quality is deteriorated. This display quality deterioration phenomenon occurs when light emission is resumed according to the n-th emission signal EM(n) of the on-level ON during the PWM driving period ④. In addition, if the potential of the node N1 is changed during the PWM driving period (④) of the nth frame, the effect also affects the n+1th frame, so that the display quality of the n+1th frame may also be deteriorated.

The electroluminescent display device according to the embodiment of the present specification may be described as follows.

The electroluminescent display device according to the embodiment of the present specification includes a display panel in which a plurality of pixels are connected to a data line to which a data voltage is supplied, a first power line to which an initialization voltage is supplied, and a second power line to which a high potential power voltage is supplied. be prepared Here, among the pixels, each pixel disposed on the nth horizontal pixel line (n is a natural number) has a gate electrode connected to a node N2, and a first electrode and a second electrode connected to the nodes N1 and N3, respectively, a driving element generating a driving current according to a gate-source voltage; a switch element T1 connected between the node N1 and the data line; a switch element T2 connected between the node N1 and the second power line; a switch element T5 connected between the node N3 and the node N4; and a light emitting element connected between the node N4 and an input terminal of a low potential power supply voltage and emitting light according to the driving current, wherein the switch element T2 is turned off for PWM (Pulse Width Modulation) driving. remains on.

In each pixel arranged on the n-th horizontal pixel line, the switch element T2 is switched according to the n-th emission signal 1, and the switch element T5 is an n-th emitter having an on/off period different from that of the n-th emission signal 1 switch according to signal 2

In each pixel arranged on the n-th horizontal pixel line, one frame period includes: an initialization period for initializing the node N2; a sampling period for sampling a threshold voltage of the driving element following the initialization period; a light emission period in which the light emitting element emits light following the sampling period; and a PWM driving period for stopping light emission of the light emitting device following the light emission period.

During the PWM driving period, the n-th emission signal 1 is maintained at an on level, and the n-th emission signal 2 is maintained at an off level, or after being input to an off level, the on/off level is further increased at least once Repeat.

In each pixel disposed on the n-th horizontal pixel line, the potential of the node N1 is fixed to the high potential power supply voltage during the PWM driving period.

In each pixel disposed on the n-th horizontal pixel line, the n-th emission signal 1 and the n-th emission signal 2 are input at an off level during the initialization period and the sampling period, and are turned on to an on level during the emission period. is input

Each pixel disposed on the n-th horizontal pixel line,

a switch element T3 connected between the node N2 and the node N3;

a switch element T4 connected between the node N2 and the first power line;

a switch element T6 connected between the node N4 and the first power line; and

and a storage capacitor connected between the node N2 and the second power line.

In each pixel arranged on the n-th horizontal pixel line, the switch element T1, the switch element T3, and the switch element T6 are switched according to an n-th scan signal, and the switch element T4 is out of phase with the n-th scan signal It is switched according to the previous n-1th scan signal.

In each pixel disposed on the n-th horizontal pixel line, the n-1 th scan signal is input at an on level during the initialization period, and is input at an off level during the sampling period, the light emission period, and the PWM driving period; , the nth scan signal is input at an on level during the sampling period, and is input at an off level during the initialization period, the light emission period, and the PWM driving period.

In each pixel disposed on the n-th horizontal pixel line, during the sampling period, the driving element is diode-connected, and a gate-source voltage of the driving element becomes a threshold voltage of the driving element.

As described above, according to the electroluminescent display device of the present specification, the switch element T2 for supplying a high potential power voltage to the source electrode of the driving element in each pixel, and the current flow between the driving element and the light emitting element for PWM driving The blocking switch element T5 is switched according to different emission signals. Through this, while the switch element T5 is turned off for PWM driving, the switch element T2 is turned on, and the source electrode potential of the driving element is fixed to the high potential power supply voltage. Accordingly, since the gate-source voltage and the driving current of the driving device do not change despite the potential change of the data line during PWM driving, display quality may be improved.

Those skilled in the art from the above description will be aware that various changes and modifications can be made without departing from the technical spirit of the present specification. Accordingly, the technical scope of the present specification should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: source driver 13: gate driver

Claims (10)

A display panel comprising: a plurality of pixels connected to a data line to which a data voltage is supplied, a first power line to which an initialization voltage is supplied, and a second power line to which a high potential power voltage is supplied;
Each pixel disposed on the nth horizontal pixel line (n is a natural number) among the pixels,
a driving element having a gate electrode connected to a node N2, a first electrode and a second electrode connected to the nodes N1 and N3, respectively, and generating a driving current according to a gate-source voltage;
a switch element T1 connected between the node N1 and the data line;
a switch element T2 connected between the node N1 and the second power line;
a switch element T5 connected between the node N3 and the node N4; and
a light emitting device connected between the node N4 and an input terminal of a low potential power supply voltage and emitting light according to the driving current;
The switch element T2 maintains an on state while the switch element T5 is turned off for PWM (Pulse Width Modulation) driving. The method of claim 1,
The switch element T2 is switched according to the n-th emission signal 1,
The switch element T5 is switched according to an n-th emission signal 2 having an on/off period different from the n-th emission signal 1 . 3. The method of claim 2,
1 frame period,
an initialization period for initializing the node N2;
a sampling period for sampling a threshold voltage of the driving element following the initialization period;
a light emission period in which the light emitting element emits light following the sampling period; and
and a PWM driving period for stopping light emission of the light emitting device following the light emitting period. 4. The method of claim 3,
During the PWM driving period, the n-th emission signal 1 is maintained at an on level, and the n-th emission signal 2 is maintained at an off level, or after being input to an off level, the on/off level is further increased at least once Repeating electroluminescent display. 5. The method of claim 4,
The electric potential of the node N1 is fixed to the high potential power supply voltage during the PWM driving period. 5. The method of claim 4,
The n-th emission signal 1 and the n-th emission signal 2 are input at an off level during the initialization period and the sampling period, and are input at an on level during the light emission period. 4. The method of claim 3,
Each pixel disposed on the n-th horizontal pixel line,
a switch element T3 connected between the node N2 and the node N3;
a switch element T4 connected between the node N2 and the first power line;
a switch element T6 connected between the node N4 and the first power line; and
The electroluminescent display device further comprising a storage capacitor connected between the node N2 and the second power line. 8. The method of claim 7,
The switch element T1, the switch element T3, and the switch element T6 are switched according to an nth scan signal,
The switch element T4 is switched according to an n-1 th scan signal having a phase ahead of the n th scan signal. 9. The method of claim 8,
The n-1th scan signal is input at an on level during the initialization period and is input at an off level during the sampling period, the light emission period, and the PWM driving period,
The nth scan signal is input at an on level during the sampling period and is input at an off level during the initialization period, the light emission period, and the PWM driving period. 10. The method of claim 9,
During the sampling period,
The driving element is diode-connected,
The gate-source voltage of the driving element becomes a threshold voltage of the driving element.

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