KR102458909B1 - Electroluminescent Display Device - Google Patents

Abstract

The present invention includes an electroluminescent display device connected to a data line to which a data voltage is supplied to a plurality of pixels, a first power line to which a high potential power voltage is supplied, and a second power line to which an initialization voltage is supplied. Each pixel arranged on the n-th horizontal pixel line includes: a driving transistor having a gate electrode, a source electrode, and a drain electrode connected to the node N2, the first power line, and the node N3, respectively; a first transistor T1 connected between the node N2 and the node N3 and switched according to an nth scan signal SC(n); a second transistor T2 connected between the data line and the node N1 and switched according to an nth scan signal SC(n); a fourth transistor connected between the node N3 and the second power line, the fourth transistor being switched according to an n-1 th scan signal that has a phase ahead of the n th scan signal; a light emitting device connected between the node N3 and a low-potential power supply voltage; and a storage capacitor connected between the node N1 and the node N2.

Description

Electroluminescent Display Device

The present invention relates to an electroluminescent display device.

The electroluminescent display device is roughly classified into an organic light emitting display device or an inorganic light emitting display device according to the type of light emitting device.

The organic light emitting display device includes an organic light emitting diode (hereinafter, referred to as "OLED") that emits light by itself, and the inorganic light emitting display device (hereinafter, the LED display device) emits light by itself. includes An organic light emitting display device or an LED display device arranges pixels including light emitting devices in a specific pattern and adjusts the luminance of the pixels according to the gray level of image data. Each of the pixels includes a thin film transistor (TFT) for controlling a driving current flowing through the light emitting device according to a gate-source voltage, and one or more TFTs for programming a gate-source voltage of the driving transistor, and the driving current Adjusts the display gradation (luminance) with the amount of light emitted from the light emitting device in proportion to .

Recently, interest in and development of LED display devices is increasing. LEDs can output higher luminance grayscales than OLEDs, and have excellent reliability against heat, moisture, and oxygen. In addition, the LED display device may implement a zero bezel in which the bezel is not visually recognized. Therefore, when a tiling display is implemented by combining a plurality of LED display devices, the boundary between the display devices is not visible, so that a clear image can be implemented as a large screen.

For zero bezel, the distance between all pixels in the tiling display must be constant. That is, there is a need for a technique for implementing such that the distance between the light emitting devices located in the inner region of the display device and the distance between the light emitting devices positioned at the outermost portion of the display devices have the same value. In particular, the higher the resolution of the display device, the smaller the pixels and the shorter the distance between the light emitting devices. This means that the area of the non-light emitting part, which is an area other than the area occupied by the light emitting device, is reduced by that much. Accordingly, it is necessary to simplify the circuit portion located in the non-light emitting portion.

Accordingly, an object of the present invention is to provide an electroluminescent display device in which the area of the non-light emitting part is minimized.

Another object of the present invention is to provide an electroluminescent display device that compensates for a change in driving characteristics of a pixel in real time regardless of an EVDD voltage drop, but has excellent contrast ratio characteristics.

In order to solve the above object, an electroluminescent display device according to the present invention provides a data line to which a data voltage is supplied to a plurality of pixels, a first power line to which a high potential power voltage is supplied, and a second power supply to which an initialization voltage is supplied. and an electroluminescent display connected to the line. Each pixel arranged on the n-th horizontal pixel line includes: a driving transistor having a gate electrode, a source electrode, and a drain electrode connected to the node N2, the first power line, and the node N3, respectively; a first transistor connected between the node N2 and the node N3 and switched according to an nth scan signal; a second transistor connected between the data line and the node N1 and switched according to an nth scan signal; a fourth transistor connected between the node N3 and the second power line, the fourth transistor being switched according to an n-1 th scan signal that has a phase ahead of the n th scan signal; a light emitting device connected between the node N3 and a low-potential power supply voltage; and a storage capacitor connected between the node N1 and the node N2. Here, in the first period for resetting the node N3, the first transistor is turned off according to the nth scan signal of the off level, and the fourth transistor is turned on according to the n-1th scan signal of the on level.

In the present invention, since the current applied to the light emitting device is not affected by the high potential power supply voltage (EVDD), it is possible to realize uniform image quality over the entire screen without designing the EVDD wiring using a low-resistance material, and high-resolution and large-screen electroluminescence. A display device can be implemented.

In addition, according to the present invention, since the current applied to the light emitting device is not affected by the threshold voltage deviation for each pixel, the luminance and color of the pixels can be uniformly maintained over the entire screen.

In addition, since the present invention drives the pixel using the previous gate signal, the configuration of the gate driver can be simplified, and narrow bezel can be easily implemented.

In addition, the present invention can control the light emitting device not to emit light during the initialization period and the compensation period. In particular, even if the initialization voltage is not set lower than the low-potential power supply voltage, the contrast ratio can be improved.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention.
2 is an exemplary embodiment of a light emitting device included in each pixel of an electroluminescent display device.
3A and 3B are diagrams illustrating the configuration of a pixel array of an electroluminescent display device according to an exemplary embodiment of the present invention.
4 is a diagram illustrating an example of a gate driver for driving the pixel array of FIG. 3A or 3B.
5 is an equivalent circuit of the pixel shown in FIG. 3A or 3B according to an exemplary embodiment.
6 is a waveform diagram illustrating potential changes of driving signals input to the pixel of FIG. 5 .
7A to 7F are equivalent circuit diagrams of pixels corresponding to each section of FIG. 6 .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be embodied in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Each feature of the various embodiments of the present invention can be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. The component names used in the following description are selected in consideration of the ease of writing the specification, and may be different from the component names of the actual product. Hereinafter, for convenience of description, a case in which the electroluminescent display device is implemented as a display device including an inorganic light emitting material, for example, an LED display device, will be described as an example. The technical spirit of the present invention is not limited to the LED display device, and may be applied to a display device including an organic light emitting material, for example, an organic light emitting display device.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention. 2 is a view showing an embodiment of a light emitting device included in each pixel of an electroluminescent display device. 3 is a view showing a pixel array of an electroluminescent display device according to an embodiment of the present invention.

1 to 3 , an electroluminescent display device according to the present invention includes a display panel 10 including a plurality of pixels PXL, and a display panel driving circuit for driving signal lines connected to each pixel PXL. 12 and 13 , and a timing controller 11 for controlling the display panel driving circuits 12 and 13 .

The display panel driving circuits 12 and 13 write input image data DATA to the pixel PXL of the display panel 10 . The display panel driving circuits 12 and 13 include a source driver 12 driving the data lines 14 connected to the pixel PXL, and a gate driver 12 driving the gate lines 15 connected to the pixel PXL. 13).

A plurality of data lines 14 and a plurality of gate lines 15 cross each other in the display panel 10 , and the pixel PXL is located adjacent to where the data lines 14 and the gate lines 15 cross each other. can be placed in The pixel PXL may include an LED light emitting device 130 as shown in FIG. 2 .

The light emitting device 130 according to an example includes a light emitting layer EL, a first electrode E1 , and a second electrode E2 .

The light emitting layer EL emits light according to recombination of electrons and holes according to a current flowing between the first electrode E1 and the first electrode E1 and the second electrode E2 . The light emitting layer EL according to an example includes a first semiconductor layer 131 , an active layer 133 , and a second semiconductor layer 135 .

The first semiconductor layer 131 provides electrons to the active layer 133 . The first semiconductor layer 131 according to an example may be made of an n-GaN-based semiconductor material, and the n-GaN-based semiconductor material may be GaN, AlGaN, InGaN, AlInGaN, or the like. Here, Si, Ge, Se, Te, or C may be used as the impurity used for doping the first semiconductor layer 131 .

The active layer 133 is provided on one side of the first semiconductor layer 131 . The active layer 133 has a multi-quantum well (MQW) structure having a well layer and a barrier layer having a band gap higher than that of the well layer. The active layer 133 according to an example may have a multi-quantum well structure such as InGaN/GaN.

The second semiconductor layer 135 is provided on the active layer 133 to provide holes to the active layer 133 . The second semiconductor layer 135 according to an example may be made of a p-GaN-based semiconductor material, and the p-GaN-based semiconductor material may be GaN, AlGaN, InGaN, AlInGaN, or the like. Here, Mg, Zn, Be, or the like may be used as an impurity used for doping the second semiconductor layer 135 .

The light emitting device 130 emits light according to recombination of electrons and holes according to a current flowing between the first electrode E1 and the second electrode E2 . In this case, the light generated from the light emitting device 130 is emitted to the outside through each of the first and second electrodes E1 and E2 to display an image. The first electrode E1 of the light emitting device 130 may be referred to as an anode electrode, and the second electrode E2 may be referred to as a cathode electrode.

A plurality of horizontal pixel lines L1 to L4 are provided in a pixel array of the display panel 10 as shown in FIG. 3A or 3B , and horizontally adjacent gates on each of the horizontal pixel lines L1 to L4 A plurality of pixels PXL commonly connected to the lines 15a, 15b, and 15c are disposed. Here, each of the horizontal pixel lines L1 to L4 does not mean a physical signal line, but a pixel block corresponding to one line implemented by a plurality of horizontally adjacent pixels PXL. In the pixel array, a first power line 17 for supplying a high potential power voltage EVDD to each pixel PXL, and a second power line 16 for supplying an initialization voltage Vinit to each pixel PXL. this may be included. In addition, each pixel PXL may be commonly connected to the low potential power voltage EVSS.

The gate lines 15 shown in FIGS. 3A and 3B include the first gate line 15a and the second gate line 15b to which the scan signal SC is supplied, and the second gate line 15b to which the emission signal EM is supplied. 3 gate lines 15c. Each pixel PXL disposed on the n-th horizontal pixel line L(n) includes an n-th scan signal SC(n) and an n-th emission allocated to the n-th horizontal pixel line L(n). In addition to the signal EM(n), an n-1 th scan signal SC(n-1) allocated to the n-1 th horizontal pixel line L(n-1) is further supplied.

As shown in FIG. 3A , the second gate line 15b connected to one pixel PXL included in the n-th horizontal pixel line L(n) is connected to the horizontally adjacent second gate line 15b. may have a configuration connected to one pixel PXL included in the n−1th horizontal pixel line L(n−1) without a physical connection. Alternatively, as shown in FIG. 3B , each pixel PXL included in the n-th horizontal pixel line L(n) physically shares one second gate line 15b, but the second gate line Reference numeral 15b may have a structure electrically connected to the output terminal of the previous stage G-STGn-1 included in the first gate driver 13A. The pixel array of the organic light emitting diode display according to an embodiment of the present invention is not limited to the above structure, and may be implemented in other configurations in consideration of an aperture ratio or RC delay characteristics.

The second gate line 15b(n) included in the n-th horizontal pixel line L(n) is the first gate line 15a( n-1)), the second gate line 15b(n) is preferably disposed close to the n-1th horizontal pixel line L(n-1).

Each pixel PXL may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel to implement various colors. A red pixel, a green pixel, a blue pixel, and a white pixel may constitute one unit pixel. The color implemented in the unit pixel may be determined according to emission ratios of the red pixel, the green pixel, the blue pixel, and the white pixel.

The source driver 12 converts input image data DATA received from the timing controller 11 every frame into a data voltage Vdata, and then supplies the data voltage Vdata to the data lines 14 . . The source driver 12 outputs the data voltage Vdata using a digital-to-analog converter that converts the input image data DATA into a gamma compensation voltage.

The source driver 12 may generate the initialization voltage Vinit and supply it to the second power line 16 , and generate and supply the high potential power voltage EVDD to the first power line 17 . To this end, the source driver 12 may further include a power generator (not shown). The power generator may further generate a low potential power voltage EVSS. After being mounted on the outside of the source driver 12 , the power generator may be electrically connected to the source driver through a conductive film or the like.

The gate driver 13 may be directly formed on the substrate of the display panel 10 together with the pixel array through a gate-driver in panel (GIP) process, but is not limited thereto. After the gate driver 13 is manufactured as an IC type, it may be bonded to the display panel 10 through a conductive film.

4 , the gate driver 13 may include a first gate driver 13A and a second gate driver 13B.

The first gate driver 13A has as many first stages G-STG1 to G-STGn as the number of horizontal pixel lines L1 to Ln, and scan signals SC( 1) to SC(n)) are output to select the horizontal pixel lines L1 to Ln in which the data voltage Vdata is charged. The first gate driver 13A is implemented as a shift register and transmits the scan signals SC(1) to SC(n) through the first output nodes to the first gate lines 15a(1) to 15a. (n)) or the second gate lines 15b(1) to 15b(n) may be sequentially supplied.

The second gate driver 13B has as many second stages E-STG1 to E-STGn as the number of horizontal pixel lines L1 to Ln, and the emission signals EM under the control of the timing controller 11 . (1) to EM(n)) are output to control the emission timing of the horizontal pixel lines L1 to Ln charged with the data voltage Vdata. The second gate driver 13B includes a shift register and an inverter, and transmits the emission signals EM( 1 ) to EM(n) through the second output nodes to the third gate lines 15c( 1 ) to 15c ( n)) can be supplied sequentially.

Referring to FIG. 4 , G-DUM, E-DUM, G-MNT, and E-MNT denote a dummy stage, and L Dummy denotes a dummy pixel line. In addition, VGH and VGL applied to the stages denote driving power, VGH denotes a gate high voltage, and VGL denotes a gate low voltage. The dummy stage and the dummy pixel line may be selectively included or excluded. The pixels of the dummy pixel line are similar to the pixels PXL of the horizontal pixel line, but may be configured not to emit light. That is, the dummy pixel line may not include a light emitting device, may be configured not to receive a data voltage, or may be configured not to receive a scan signal and an emission signal.

Two output nodes including any one of the first output nodes and the second output nodes of the gate driver 13 may be connected to each horizontal pixel line L1 to Ln. In particular, in order to simplify the configuration of the gate driver 13 , each of the first output nodes may be commonly connected to two adjacent horizontal pixel lines. The pixels PXL of each of the horizontal pixel lines L1 to Ln require a plurality of gate signals having different ON timings. For example, the pixel PXL corresponding to the n-th horizontal pixel line Ln needs two scan signals and one emission signal. At this time, the two scan signals are an n-1th scan signal SC(n-1) and an nth scan signal SC(n), which are output of one driver, and the one emission signal is an nth scan signal SC(n). It can be implemented with the emission signal EM(n). Accordingly, since the single pixel PXL can be driven only by two drivers, there is an advantage in that the configuration of the gate driver 13 is simplified. In this case, the nth scan signal SC(n) and the n−1th scan signal SC(n−1) have the same pulse width and different phases.

The timing controller 11 receives digital data DATA of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. The host system may be any one of a television (Television) system, a set-top box, a navigation system, a DVD player, a personal computer (PC), and a phone system.

The timing controller 11 multiplies the input frame frequency by i to control the operation timing of the display panel driving circuits 12 and 13 with the frame frequency of the input frame frequency × i (i is a positive integer greater than 0) Hz. have. The input frame frequency is 60 Hz in the NTSC (National Television Tandards Committee) scheme and 50 Hz in the PAL (Phase-Alternating Line) scheme.

The timing controller 11 includes a data timing control signal DDC for controlling the operation timing of the source driver 12 based on the timing signals Vsync, Hsync, DE received from the host system, and the gate driver 13 . A gate timing control signal GDC for controlling the operation timing is generated.

5 is an equivalent circuit of the pixel shown in FIG. 3A or 3B according to an exemplary embodiment.

Referring to FIG. 5 , the pixel PXL of the present invention includes a light emitting device 130 , a plurality of transistors T1 to T5 , DT and a storage capacitor C . The plurality of transistors T1 to T5 and DT may be implemented as a PMOS type (P-channel metal oxide semiconductor) TFT, through which desired response characteristics may be secured. However, the technical spirit of the present invention is not limited thereto. For example, at least one transistor among the plurality of transistors T1 to T5 is implemented as an NMOS type (N-channel Metal Oxide Semiconductor) TFT having good off-current characteristics, and the remaining The transistors may be implemented as PMOS type TFTs with good response characteristics.

Hereinafter, a connection configuration of one pixel PXL disposed on the n-th horizontal pixel line L(n) will be described in detail.

The light emitting device 130 emits light with an amount of current adjusted according to the gate-source voltage Vgs of the driving transistor DT. The anode electrode of the light emitting device 130 is connected to the drain electrode of the third transistor T3 , and the cathode electrode of the light emitting device 130 is connected to the low potential power voltage EVSS.

The driving transistor DT is a driving device that controls a current flowing through the light emitting device according to the gate-source voltage Vgs. The driving transistor DT includes a gate electrode connected to the node N2 , a source electrode connected to the first power line 17 , and a drain electrode connected to the node N3 .

The first transistor T1 is connected between the node N2 and the node N3 and is switched according to the nth scan signal SC(n). The gate electrode of the first transistor T1 is connected to the n-th first gate line 15a(n) to which the n-th scan signal SC(n) is applied, and the source electrode of the first transistor T1 is a node It is connected to N3, and the drain electrode of the first transistor T1 is connected to the node N2.

The second transistor T2 is connected between the data line 14 and the node N1 and is switched according to the nth scan signal SC(n). The gate electrode of the second transistor T2 is connected to the n-th first gate line 15a(n) to which the n-th scan signal SC(n) is applied, and the source electrode of the second transistor T2 is the data It is connected to the line 14, and the drain electrode of the second transistor T2 is connected to the node N1.

The third transistor T3 is connected between the node N3 and the light emitting device 130 and is switched according to the nth emission signal EM(n). The gate electrode of the third transistor T3 is connected to the n-th third gate line 15c(n) to which the n-th emission signal EM(n) is applied, and the source electrode of the third transistor T3 is It is connected to the node N3 , and the drain electrode of the third transistor T3 is connected to the anode electrode of the light emitting device 130 .

The fourth transistor T4 is connected between the node N3 and the second power line 16 and is switched according to the n-1 th scan signal SC(n-1). The gate electrode of the fourth transistor T4 is connected to the n-th second gate line 15b(n) to which the n-1 th scan signal SC(n-1) is applied, and the gate electrode of the fourth transistor T4 is The source electrode is connected to the second power supply line 16 , and the drain electrode of the fourth transistor T4 is connected to the node N3 .

The fifth transistor T5 is connected between the node N1 and the second power line 16 and is switched according to the nth emission signal EM(n). The gate electrode of the fifth transistor T5 is connected to the n-th third gate line 15c(n) to which the n-th emission signal EM1(n) is applied, and the source electrode of the fifth transistor T5 is It is connected to the second power line 16 , and the drain electrode of the fifth transistor T5 is connected to the node N1 .

The storage capacitor C is connected between the node N1 and the node N2.

6 is a waveform diagram illustrating potential changes of driving signals input to the pixel illustrated in FIG. 5 . 7A to 7F are equivalent circuit diagrams of pixels respectively corresponding to the 0th section (A) to the 5th section (F) of FIG. 6 .

Referring to FIG. 6 , each pixel PXL disposed on the n-th horizontal pixel line Ln is driven according to a 0 th period A to a fifth period F.

The first period (B) and the second period (C) are initialization periods for resetting a specific node. And the third period D is a compensation period for sampling a threshold voltage (Vth) of the driving transistor DT. And the fourth section (E) is a holding section in which the voltage of each node is maintained in the same state as that of the third section (D), which is the previous section. In addition, the fifth section (F) and the first section (A) are light-emitting sections in which the light emitting device 130 emits light.

A data voltage Vdata is applied through the data line 14 . The data voltage Vdata shown in FIG. 6 represents a signal applied to the nth horizontal pixel line L(n).

The nth scan signal SC(n) is connected to each pixel PXL included in the nth horizontal pixel line L(n) and the n+1th horizontal pixel line L(n+1). The low voltage is output for a period longer by α than the time 1H corresponding to one horizontal pixel line.

The n-1 th scan signal SC(n-1) is each pixel PXL included in the n-1 th horizontal pixel line L(n-1) and the nth horizontal pixel line L(n). is connected with The n-th scan signal SC(n-1) has a phase ahead of the n-th scan signal SC(n), and the duty ratio and the cycle are the n-th scan signals SC(n). )) is the same as The duty ratio is the ratio of the time maintained at the high voltage to the time maintained at the low voltage. Also, the pulse of the n-1th scan signal SC(n-1) overlaps the pulse of the nth scan signal SC(n) by α.

When the transistor included in each pixel PXL is a PMOS type TFT, the duty ratio of the nth emission signal EM(n) is less than 1, and the nth scan signal SC(n) and the n-1 th scan signal SC(n) and n−1 th The duty ratio of the scan signal SC(n-1) is greater than 1.

Referring to FIGS. 6 and 7A , the nth scan signal SC(n) and the n-1th scan signal SC(n-1) are input to the OFF level during the 0th section A, and , the nth emission signal EM(n) is input at an on level ON.

During the 0th period A, the fifth transistor T5 is turned on in response to the nth emission signal EM(n) of the on level ON. Accordingly, the initialization voltage Vinit is applied to the node N1 and maintained at the same voltage as in the previous section. Meanwhile, in response to the nth scan signal SC(n) of the off level OFF, the second transistor T2 is turned off and the node N1 is maintained at the initialization voltage Vinit.

During the 0th period A, the third transistor T3 is turned on in response to the nth emission signal EM(n). Accordingly, the third transistor T3 is maintained in a turned-on state so that the light emitting device 130 can emit light following the fifth period F. On the other hand, so that the light emitting device 130 can maintain a light emitting state, the first transistor T1 and the fourth transistor T4 are respectively an nth scan signal SC(n) and an n-1th scan signal SC( It remains turned off in response to n-1)).

The initialization voltage Vinit is a voltage lower than the high potential power supply voltage EVDD and may be set to a voltage higher than the low potential power supply voltage EVSS. During the 0th period A, the gate-source voltage Vgs of the driving transistor DT is less than the threshold voltage Vth of the driving transistor DT, so the driving transistor DT satisfies the turn-on condition.

Referring to Table 1, during the 0th section (A), the potential of the node N1 becomes the initialization voltage (Vinit), and the potentials of the nodes N2 and N3 are maintained at the voltages in the fifth section (F), which is the immediately preceding section. .

6 and 7B , in the first section B, the nth scan signal SC(n) and the nth emission signal EM(n) are input at an off level (OFF), and the nth scan signal SC(n) The -1 scan signal SC(n-1) is input at the on level ON.

During the first period B, the fourth transistor T4 is turned on in response to the n−1th scan signal SC(n−1) of the on level ON. Accordingly, the node N3 is reset to the initialization voltage Vinit. In addition, the third transistor T3 is turned off in response to the nth emission signal EM(n). Accordingly, the light emitting device 130 stops light emission and the node N3 is maintained at the initialization voltage Vinit.

In particular, the third transistor T3 controls the initialization voltage Vinit of the node N3 not to be applied to the anode electrode of the light emitting device 130 . That is, the third transistor T3 controls the light emitting device 130 not to emit light due to the initialization voltage Vinit. When the light emitting device 130 is an inorganic device (eg, LED), the threshold voltage (Vth), which is the minimum voltage to start light emission, may be lower than the threshold voltage (Vth) of the organic device (eg, OLED). have. Accordingly, the light emitting device 130 may emit light even with the initialization voltage Vinit, and a light leakage phenomenon may occur. The electroluminescent display device of the present invention can control the light emitting device 130 not to emit light at an unintended time regardless of the type of the light emitting device 130 .

Meanwhile, during the first period B, the first transistor T1 and the second transistor T2 are maintained in a turned-off state, and the fifth transistor T5 is turned off and the n-th emission signal EM is at an off level (OFF). In response to (n)), it changes to the turned-off state. Accordingly, the nodes N1 and N2 across the storage capacitor C are maintained at the voltages during the previous period.

6 and 7C , in the second section C, the nth scan signal SC(n) and the n−1th scan signal SC(n−1) are input to the on level ON, and , the nth emission signal EM(n) is input to the off level OFF.

During the second period C, the first transistor T1 is turned on in response to the n-th scan signal SC(n) of the on level ON. As the first transistor T1 is turned on, the gate electrode and the drain electrode of the driving transistor DT are short-circuited, so that the driving transistor DT is diode-connected. Meanwhile, the fourth transistor T4 is turned on in response to the n-1th scan signal SC(n-1), and the third transistor T3 is turned on in response to the nth emission signal EM(n). As is maintained in the turned off state, a current path is formed from the second power line 16 to the node N2 . Accordingly, during the second period C, the nodes N2 and N3 are reset to the initialization voltage Vinit.

Also, the third transistor T3 blocks the connection between the node N3 and the light emitting device 130 so that the nodes N2 and N3 can be completely reset to the initialization voltage Vinit during the second period C.

On the other hand, the second transistor T2 is turned on in response to the n-th scan signal SC(n) of the on-level (ON), and the n-th emission signal (EM(n)) of the off-level (OFF) is turned on. Correspondingly, the fifth transistor T5 is maintained in a turned off state. Accordingly, the node N1 increases from the initialization voltage Vinit to the data voltage Vdata, and the fifth transistor T5 controls the initialization voltage Vinit not to flow during the second period C, so that the node N1 is The data voltage Vdata is maintained.

Referring to FIGS. 6 and 7D , in the third section D, the nth scan signal SC(n) is input to the on level ON, and the n−1th scan signal SC(n-1)) and the nth emission signal EM(n) is input at an off level OFF.

During the third period D, the second transistor T2 and the fifth transistor T5 are maintained in the same state as in the previous period, and accordingly, the node N1 is maintained at the data voltage Vdata. Meanwhile, the nth scan signal SC(n) is maintained at the same on level ON as in the previous section, so that the first transistor T1 is maintained in the turned-on state. On the other hand, the fourth transistor T4 is turned off in response to the n−1th scan signal SC(n−1) of the off level OFF. Accordingly, the threshold voltage Vth of the driving transistor DT is compensated by the diode connection of the driving transistor DT, so that the potentials of the nodes N2 and N3 become “EVDD + Vth”.

During the third period D, the third transistor T3 is maintained in the turned-off state as in the previous period, and the light emitting device 130 does not emit light.

Referring to FIGS. 6 and 7E , in the fourth section (E), the nth scan signal SC(n), the n−1th scan signal SC(n−1), and the nth emission signal EM( n)) is input as an off level (OFF).

During the fourth period E, the first to fifth transistors T1 to T5 are turned off. Accordingly, the node N1, the node N2, and the node N3 are maintained in the potential state of the previous section.

6 and 7F, in the fifth section (F; light emission section), the n-th scan signal SC(n) and the n-1 scan signal SC(n-1) are off-level (OFF). is input, and the nth emission signal EM(n) is input at an on level ON. Although the 0th section (A) and the 5th section (F) have been separately described to help understanding of the driving method, the 0th section (A) is substantially the same as the fifth section (F).

During the fifth period F, the second transistor T2 is maintained in the turned-off state, while the fifth transistor T5 is turned on, and the potential of the node N1 is changed from the data voltage Vdata to the initialization voltage Vinit. descend to

Meanwhile, during the fifth period (F), the node N2 is in a floating state and is coupled to the node N1 through the storage capacitor (C). Accordingly, a value equal to “Vdata - Vinit”, which is a change in the potential of the node N1, is reflected in the node N2. As a result, the potential of the node N2 during the fifth section (F) is lowered by “Vdata - Vinit” compared to “EVDD + Vth” during the fourth section E, which is the immediately preceding section. That is, during the fifth period F, the potential of the node N2 becomes “EVDD + Vth - Vdata + Vinit”. Meanwhile, during the fifth period F, the potential of the node N3 is proportional to the data voltage Vdata and may vary according to device characteristics of the driving transistor DT.

Through the series of processes described above, the gate-source voltage Vgs of the driving transistor DT that determines the amount of driving current of the light emitting device 130 is set. At this time, the driving current I as shown in Equation 1 below flows through the light emitting device 130 .

[Equation 1]

Here, K is a constant value determined by the mobility, channel ratio, parasitic capacitance, etc. of the driving transistor DT, and Vth is the threshold voltage Vth of the driving transistor DT.

As can be seen from Equation 1, the driving current I of the light emitting device 130 is not affected by the high potential power voltage EVDD as well as the threshold voltage Vth of the driving transistor DT. In the embodiment of the present invention, since the driving current I of the light emitting device 130 is not affected by the high potential power voltage EVDD, there is no low resistance design of the first power line 17 or the first power line 17 ), it is possible to make the luminance and color of pixels uniform across the screen without forming a mesh. In addition, the embodiment of the present invention can solve the light leakage problem without setting the potential of the initialization voltage Vinit to be lower than the low potential power supply voltage EVSS. Accordingly, the present invention is very advantageous in realizing a uniform image quality in a high-resolution panel having a small pixel size. In addition, the present invention has the effect of providing a panel of a large screen with improved luminance and image quality.

Table 1 is a table summarizing the ideal voltages of the nodes N1, N2, and N3 in the 0th section (A) to the 5th section (F).

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: source driver 13: gate driver
130: light emitting element

Claims (13)

The data line 14 to which the data voltage Vdata is supplied to the plurality of pixels PXL, the first power line 17 to which the high potential power voltage EVDD is supplied, and the second to which the initialization voltage Vinit is supplied. and a display panel connected to the power line 16;
Each pixel PXL disposed on the nth horizontal pixel line Ln,
a driving transistor DT having a gate electrode, a source electrode, and a drain electrode connected to the node N2, the first power line 17, and the node N3, respectively;
a first transistor T1 connected between the node N2 and the node N3 and switched according to an nth scan signal SC(n);
a second transistor T2 connected between the data line and the node N1 and switched according to the nth scan signal SC(n);
It is connected between the node N3 and the second power line 16, and is switched according to an n-1th scan signal SC(n-1) having a phase ahead of the nth scan signal SC(n). a fourth transistor T4;
a light emitting device 130 connected between the node N3 and the low potential power voltage EVSS; and
a storage capacitor (C) connected between the node N1 and the node N2;
In a first period (B) for resetting the node N3, the first transistor T1 is turned off according to the n-th scan signal SC(n) of an off level, and the fourth transistor T4 is turned off. is turned on according to the n-1th scan signal SC(n-1) of the on level,
An electroluminescence display in which at least a portion overlaps a section in which the n-1 th scan signal SC(n-1) is maintained at a low voltage and a section in which the nth scan signal SC(n) is maintained at a low voltage Device. The method of claim 1,
The n-1th scan signal SC(n-1) has the same duty ratio and the same cycle as the nth scan signal SC(n). delete The method of claim 1,
The pixel includes a third transistor T3 connected between the node N3 and the light emitting device 130 and switched according to the n-th emission signal EM(n), and a second power line 16 and and a fifth transistor (T5) connected between the node N1 and switched according to the nth emission signal (EM(n)). 5. The method of claim 4,
During the first period (B), the third transistor T3 is turned off according to the n-th emission signal EM(n) of the off level, and an electric field for controlling the light emitting device 130 not to emit light. luminescent display. 5. The method of claim 4,
During the first period B, the second transistor T2 is turned off according to the n-th scan signal SC(n) of an off-level, and the fifth transistor T5 is turned off according to the n-th scan signal SC(n) of an off-level. An electroluminescent display device that is turned off according to the emission signal EM(n). 5. The method of claim 4,
In the second section (C) after the first section (B),
The first transistor T1 and the second transistor T2 are turned on according to the n-th scan signal SC(n) of an on level, and the fourth transistor T4 is turned on according to the n-th scan signal SC(n) of an on level. -1 An electroluminescent display device that is turned on according to the scan signal SC(n-1). 8. The method of claim 7,
The third transistor (T3) and the fifth transistor (T5) are turned off according to an nth emission signal EM(n) of an off level. 5. The method of claim 4,
In the third section (D) after the first section (B),
The first transistor T1 and the second transistor T2 are turned on according to the nth scan signal SC(n) of an on level, and the fourth transistor T4 is turned on according to the nth scan signal SC(n) of an on level. -1 An electroluminescent display device that is turned off according to a scan signal SC(n-1). 10. The method of claim 9,
The third transistor T3 and the fifth transistor T5 are turned off according to the nth emission signal EM(n) of an off level. 5. The method of claim 4,
In the fourth section (E) after the first section (B),
The first transistor T1 and the second transistor T2 are turned off according to the nth scan signal SC(n) of an off level, and the fourth transistor T4 is turned off according to the nth scan signal SC(n) of an off level. An electroluminescent display device that is turned off according to an n-1 scan signal SC(n-1). 12. The method of claim 11,
In a fifth section (F) for emitting light of the light emitting device 130 after the fourth section (E),
The first transistor T1 , the second transistor T2 , and the fourth transistor T4 are maintained in the state in the fourth period E, and the third transistor T3 and the fifth transistor T4 are maintained. The transistor T5 is turned on in response to the n-th emission signal EM(n) having an on level. 13. The method of claim 12,
In all sections except the fifth section (F), the third transistor (T3) is turned off.

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