KR102626519B1 - Organic light emitting diode display device - Google Patents

Abstract

In the present invention, a compensation transistor is connected to the gate of the driving transistor to compensate for the change in gate voltage of the driving transistor due to the leakage current in the off state of the switching transistor connected to the gate of the driving transistor.
Accordingly, the change in voltage between the gate and source of the driving transistor can be compensated and kept constant, thereby improving the change in luminance of the light emitting diode.
Additionally, as current leakage through the switching transistor can be compensated for, all transistors can be manufactured through the same process, thereby improving process efficiency.

Description

Organic light emitting diode display device}

The present invention relates to an organic light emitting device display device, and more specifically, to an organic light emitting device display device that can improve luminance changes caused by leakage current of a switching transistor.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), organic Various flat display devices such as organic light emitting diode (OLED) displays are being used.

Among these flat panel displays, organic light emitting display devices are widely used because they have the advantages of miniaturization, weight reduction, thinness, and low-power operation.

Generally, an organic light emitting diode display device receives a clock from an external system at a normal driving frequency of 60 Hz and operates according to this driving frequency.

In such a case, the display device operates at substantially the same driving frequency not only for images with large changes in images, such as moving images, but also for images with small changes in images, such as still images, so power consumption increases.

To improve this, the so-called Variable Refresh Rate (VRR) driving method is proposed, which reduces power consumption by driving the display device at a low driving frequency lower than the normal driving frequency of 60Hz when the image change is not large. It has been done.

However, when operating at a low driving frequency, the voltage (Vgs) between the gate and source of the driving transistor changes due to the off current of the switching transistor, causing a problem in which the luminance changes. This will be described with reference to FIG. 1 .

Figure 1 is an equivalent circuit diagram schematically showing an example of the pixel structure of a conventional organic light emitting diode display device.

Referring to FIG. 1, a conventional organic light emitting display device is a display device in which a so-called source follower type compensation circuit is applied to compensate for the threshold voltage deviation of the driving transistor (T2), and each pixel (P) has a compensation circuit applied thereto. It consists of a switching transistor (T1), a driving transistor (T2), an initialization transistor (T4), a light emission control transistor (T3), a light emitting diode (OD), and first and second capacitors (C1, C2).

When the VRR method is applied to a display device equipped with a pixel (P) of this structure, it is driven at a normal frequency of 60 Hz in the normal driving mode, and data refresh for the pixel (P) is performed every frame.

Meanwhile, when the change in the image is not large, it is driven in a low-frequency driving mode. In this case, data refresh is performed during a specific refresh frame, and during at least one holding frame between the current refresh frame and the next refresh frame. The data refresh operation is stopped and the data refreshed in the current frame is maintained in the pixel.

However, in the low-frequency driving mode, the lower the frequency, the longer the data holding time, and the data voltage written to the pixel (P) is lowered by the off current (off current) of the switching transistor (T1), that is, the leakage current (IL). A problem arises. Accordingly, the gate-source voltage (Vgs) of the driving transistor (T2) decreases, causing a problem in which the luminance of light emitted from the light emitting diode (OD) decreases. Moreover, when the switching transistor (T1) is formed using the LTPS (Low Temperature Poly-Silicon) method, the off-current characteristics of the switching transistor (T1) are not good, and the leakage current (IL) increases, resulting in a large decrease in luminance. .

The object of the present invention is to provide a method for improving luminance changes caused by leakage current of a switching transistor.

In order to achieve the above-mentioned problem, the present invention includes a switching transistor connected to the first scan wire and the data wire; a driving transistor whose gate is connected to the drain of the switching transistor at a first node; a light emitting diode connected to the source of the driving transistor during the light emission period; a first capacitor connected between the first node and the second node; An organic light emitting display device is provided including a compensation transistor connected between the drain of the driving transistor and the first node and in an off state during the light emission period.

Here, an initialization transistor connected to the second node and a gate connected to a second scan line; a light emission control transistor connected between the drain of the driving transistor and a driving voltage input terminal; It may further include a second capacitor connected between the second node and the driving voltage input terminal, and the second scan wire may be connected to the gate of the compensation transistor.

The gate of the compensation transistor may receive an off voltage during the light emission period.

The off-state resistance value of the compensation transistor may be the same as the off-state resistance value of the switching transistor.

In another aspect, the present invention includes a first switching transistor connected to a first scan wire and a data wire; a driving transistor whose source is connected to the drain of the first switching transistor at a second node; a light emitting diode connected to the source of the driving transistor during the light emission period; a second switching transistor connected between the drain and gate of the driving transistor, the gate of which is connected to a second scan wire; a capacitor connected to the gate of the driving transistor at a first node; An organic light emitting display device is provided including a compensation transistor connected between the first node and the second node and in an off state during the light emission period.

Here, a first light emission control transistor connected to the drain of the driving transistor at a third node; an initialization transistor connected to the capacitor at a fourth node and having a gate connected to the second scan line; It further includes a second light emission control transistor connected between the source of the driving transistor and the light emitting diode, wherein the fourth node is connected to a fifth node between the light emission control transistor and the light emitting diode, and the first node and the fourth node are connected to the fifth node. The capacitor may be connected between nodes.

The gate of the compensation transistor may receive an off voltage during the light emission period.

The off-state resistance value of the compensation transistor may be the same as the off-state resistance value of the second switching transistor.

In the present invention, a compensation transistor is connected to the gate of the driving transistor to compensate for the change in gate voltage of the driving transistor due to the leakage current in the off state of the switching transistor connected to the gate of the driving transistor.

Accordingly, the change in voltage between the gate and source of the driving transistor can be compensated and kept constant, thereby improving the change in luminance of the light emitting diode.

Additionally, as current leakage through the switching transistor can be compensated for, all transistors can be manufactured through the same process, thereby improving process efficiency.

1 is an equivalent circuit diagram schematically showing an example of the pixel structure of a conventional organic light emitting diode display device.
Figure 2 is a block diagram schematically showing an organic light emitting diode display device according to a first embodiment of the present invention.
Figure 3 is a diagram schematically showing the arrangement of a refresh frame and a holding frame when the organic light emitting diode display device according to the first embodiment of the present invention is driven in a low frequency drive mode.
Figure 4 is an equivalent circuit diagram schematically showing an example of a pixel structure according to the first embodiment of the present invention.
Figure 5 is a timing diagram schematically showing the waveform of a driving signal that drives a pixel during a refresh frame in the first embodiment of the present invention.
Figures 6 and 7 are diagrams showing the relationship between light emission current over time in the conventional art and the first embodiment of the present invention, respectively.
Figure 8 is an equivalent circuit diagram schematically showing the pixel structure of an organic light emitting diode display device according to a second embodiment of the present invention.
Figure 9 is a timing diagram schematically showing the waveform of a driving signal that drives a pixel during a refresh frame in the second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First embodiment>

Figure 2 is a block diagram schematically showing an organic light emitting display device according to a first embodiment of the present invention, and Figure 3 is a block diagram showing the organic light emitting device display device according to a first embodiment of the present invention driven in a low frequency drive mode. This is a diagram schematically showing the arrangement of the refresh frame and holding frame in this case.

Referring to FIG. 2, the organic light emitting display device 100 according to this embodiment includes a display panel 110 in which a plurality of pixels (P) are arranged in a matrix form and a driving circuit that drives the display panel 110. It can be included. Additionally, the driving circuit that drives the display panel 110 may include a data driving circuit 120, a gate driving circuit 130, and a timing control circuit 140.

The organic light emitting display device 100 configured in this way is an organic light emitting display device that operates in a VRR method.

In this regard, when displaying an image with large changes in the image, such as a video, the display device 100 is driven in a normal driving mode according to a driving frequency of 60 Hz, for example, input from an external system. In this case, all frames correspond to refresh frames, and data (i.e., data voltage) is written to the corresponding pixel (P) during each frame.

On the other hand, when displaying an image with little change in the image, such as a still image, the display device 100 is driven in a low-frequency drive mode according to a low frequency lower than the normal driving frequency, thereby reducing power consumption. do. In such a low-frequency driving mode, as shown in FIG. 3, a specific frame becomes a refresh frame (Fr) depending on the corresponding low frequency, and a holding frame (Fh) consisting of at least one holding frame (Fh) is provided between neighboring refresh frames (Fr). A section (HP) is defined. At this time, data is written to the corresponding pixel (P) during the refresh frame (Fr), and the data refresh operation is stopped in the subsequent holding period (HP).

Looking at the display panel 110 again with reference to FIG. 2, various wirings that transmit driving signals for driving the pixels P are formed in the display panel 110.

In this regard, for example, a plurality of data lines DL that transmit data voltages may extend along the direction of each column line and be connected to the pixels P of the corresponding column line.

Meanwhile, a plurality of first and second scan wires (SL1 and SL2), which respectively transmit the first and second scan voltages, extend along the direction of each row line and are connected to the pixel (P) of the corresponding row line. Additionally, a light emission control wire (EL) may be formed that extends in parallel with the scan wires (SL1, SL2) and transmits the light emission control voltage to the corresponding pixel (P).

The timing control circuit 140 controls the driving timing of the data driving circuit 120 and the gate driving circuit 130.

In this regard, the timing control circuit 140 may rearrange digital data (RGB) input from an external system to match the resolution of the display panel 110 and supply it to the data driving circuit 120. In addition, the timing control circuit 140 operates the data driving circuit 120 based on timing signals such as the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the clock signal (CLK), and the data enable signal (DE). A data control signal (DCS) for controlling the operation timing of and a gate control signal (GCS) for controlling the operation timing of the gate driving circuit 130 can be generated.

The data driving circuit 120 can drive the data line DL. In this regard, the data driving circuit 120 may convert input digital data (RGB) into an analog data voltage based on the data control signal (DCS) and supply it to the corresponding data line (DL).

The gate driving circuit 130 can drive the first and second scan wires (SL1 and SL2) and the light emission control wire (EL). In this regard, the gate driving circuit 130 may generate the first and second scan voltages and the emission control voltage based on the gate control signal (GCS). This gate driving circuit 130 supplies the first scan voltage to the first scan wire (SL1) in a line sequential manner, supplies the second scan voltage to the second scan wire (SL2) in a line sequential manner, and emits light. The control voltage can be supplied to the emission control wiring (EL) in a line sequential manner.

Hereinafter, the structure of the pixel P formed in the display panel 110 will be described with reference to FIG. 4 . Figure 4 is an equivalent circuit diagram schematically showing an example of a pixel structure according to the first embodiment of the present invention.

Referring to FIG. 4, the pixel (P) of this embodiment has a so-called source follower type compensation circuit applied, and each pixel (P) includes a switching transistor (T1), a driving transistor (T2), and an initialization transistor ( T3), a light emission control transistor (T4), a light emitting diode (OD), and the first and second capacitors (C1, C2). Furthermore, the pixel P of this embodiment may be additionally equipped with a compensation transistor T5 to compensate for the leakage current IL1, which is the off-state current of the switching transistor T1.

The switching transistor (T1) is turned on in response to the first scan voltage (Vsc1) applied through the first scan line (SL1) of the corresponding row line, and accordingly, the reference voltage (Vref) or the reference voltage (Vref) provided through the data line (DL) The data voltage (Vdata) can be applied to the driving transistor (T2). The source of the switching transistor T1 may be connected to the data line DL, the gate may be connected to the gate line GL, and the drain may be connected to the gate of the driving transistor T2, that is, the first node N1. .

The driving transistor (T2) controls the light-emitting current applied to the organic light-emitting diode (OLED) by the gate-source voltage (Vgs). For this purpose, the gate of the driving transistor (T2) is connected to the first node (N1), the source is connected to the first electrode (i.e. anode) of the light emitting diode (OD), that is, the second node (N2), and the drain is connected to the second node (N2). It can be connected to the drain of the light emission control transistor (T4), that is, the third node (N3).

The initialization transistor (T3) is turned on in response to the second scan voltage (Vsc2) applied through the second scan wire (SL2) of the row line, and accordingly, the initialization voltage (Vini) transmitted from the initialization voltage (Vini) input terminal is turned on. This can be applied to the second node (N2). The gate of the initialization transistor T3 may be connected to the second scan line SL2, the source may be connected to the initialization voltage Vini input terminal, and the drain may be connected to the second node N2.

The light emission control transistor (T4) responds to the light emission control voltage (Ve) applied through the light emission control wiring (EL) of the row line, and connects the input terminal of the first driving voltage (Vdd), which is a high potential driving voltage, and the driving transistor (T2). Controls the current path between the liver. The gate of the light emission control transistor T4 may be connected to the light emission control line EL, the drain may be connected to the first driving voltage (Vdd) input terminal, and the source may be connected to the third node N3.

The light emitting diode (OD) is an organic light emitting diode made of organic materials and emits light by the light emitting current supplied from the driving transistor (T2). The anode, which is the first electrode of the light emitting diode (OD), may be connected to the source of the driving transistor (T2), and the cathode, which is the second electrode, may be connected to the input terminal of the second driving voltage (Vss), which is a low-potential driving voltage.

The first capacitor C1 is connected between the first node N1 and the second node N2. This first capacitor (C1) maintains the gate-source voltage (Vgs) of the driving transistor (T2) until the next refresh frame. In particular, the first capacitor (C1) samples the threshold voltage (Vth) of the driving transistor (T2) according to the source follower compensation method.

The second capacitor (C2) is connected between the first driving voltage (Vdd) input terminal and the second node (N2), and has a series connection relationship with the first capacitor (C1).

When the potential of the first node (N1) changes due to the data voltage (Vdata) in the data writing period, the first and second capacitors (C1, C2) as described above distribute this change as a voltage to the second node (N2). It is possible to perform the function of reflecting.

Meanwhile, as a characteristic configuration of this embodiment, the compensation transistor T5, which compensates for the change in the gate-source voltage (Vgs) of the driving transistor (T2) due to the leakage current (IL1) through the switching transistor (T1), is the first node. It is connected between (N1) and the third node (N3). Accordingly, a function of compensating for voltage changes caused by the first leakage current (IL1), which is a leakage current that leaks in the off state of the switching transistor (T1), is performed.

To this end, the compensation transistor T5 may be controlled to be in an off state together during the period when the switching transistor T1 is in an off state. In particular, the compensation transistor T5 may be controlled to be in an off state together during the period in which the switching transistor T1 is in an off state after data writing. It can be controlled.

At this time, the compensation transistor (T5) is preferably configured to have substantially the same off-current characteristics as the switching transistor (T1). For example, the compensation transistor (T5) and the switching transistor (T1) have substantially the same resistance in the off state. It can be configured to have a value.

When configured in this way, a leakage current (IL2) path is created from the third node (N3) to the first node (N1) through the compensation transistor (T5).

Therefore, when the first leakage current (IL1) leaking from the first node (N1) occurs through the switching transistor (T1), the leakage amount of the first leakage current (IL1) is transmitted through the compensation transistor (T5). A second leakage current IL2 that leaks (i.e. flows into) the first node N1 is generated, so that the leakage current in the first node N1 can be substantially offset and compensated.

As such, in the low-frequency driving mode, the gate voltage of the driving transistor (T2), which is the voltage of the first node (N1), drops due to the first leakage current (IL1) through the switching transistor (T1) during the long holding period (HP). This can be prevented, and the voltage (Vgs) between the gate and source of the driving transistor (T2) can be maintained. Accordingly, it is possible to effectively improve luminance degradation caused by the leakage current IL1 of the switching transistor T1.

The drain of the compensation transistor T5 may be connected to the first node N1, the source may be connected to the third node N3, and the gate may be connected to the second scan line SL2. Meanwhile, as another example, the gate of the compensation transistor T5 may be connected to the off-voltage input terminal to continuously receive the off-voltage, and in this case, the compensation transistor T5 is continuously maintained in an off state.

Hereinafter, a method of driving a pixel according to this embodiment will be described with reference to FIG. 5 . Figure 5 is a timing diagram schematically showing the waveform of a driving signal that drives a pixel during a refresh frame in the first embodiment of the present invention.

Referring to FIG. 5, in the refresh frame (Fr), an initialization period (ti), a sampling period (ts), a data writing period (tp), and an emission period (te) may be sequentially defined.

First, during the initialization period (ti), the high level second scan voltage (Vsc2), which is the turn-on level, is applied to the second scan line (SL2), and in response to this, the initialization transistor (T3) is turned on to increase the initialization voltage (Vini). It is supplied to the second node (N2). Accordingly, the source voltage of the driving transistor (T2), which is the voltage of the second node (N2), has the potential of the initialization voltage (Vini).

Meanwhile, during the initialization period (ti), the first scan voltage (Vsc1) of the high level, which is the turn-on level, is applied to the first scan line (SL1), and in response to this, the switching transistor (T1) is turned on to turn on the data line (DL). The reference voltage (Vref) provided through is supplied to the first node (N1). Accordingly, the gate voltage of the driving transistor (T2), which is the voltage of the first node (N2), has the potential of the reference voltage (Vref).

Next, a high-level light emission control voltage (Ve), which is a turn-on level, is applied to the light emission control line (EL) during the sampling period (ts), and in response to this, the light emission control transistor (T4) is turned on and the first driving voltage (Vdd) is applied. ) is applied to the drain of the driving transistor (T2). Meanwhile, during this period (ts), the first scan line (SL1) is also turned on and the reference voltage (Vref) is applied to the first node (N1). As a result, current flows between the source and drain of the driving transistor (T2) in the turned-on state, causing the potential of the second node (N2) to rise. At this time, the driving transistor (T2) is turned off, that is, until it is turned off. The potential of the second node (N2) increases until the potential becomes (Vref-Vth). Accordingly, during the sampling period (ts), the threshold voltage (Vth) of the driving transistor (T2) is sampled and stored in the first capacitor (C1).

Next, during the data writing period tp, the data voltage Vdata is provided through the data line DL and applied to the first node N1. Accordingly, the voltage change (i.e., Vdata-Vref) of the first node (N1) is reflected in the second node (N2) according to the voltage distribution relationship between the first and second capacitors (C1 and C2). In this way, during the data writing period tp, the data voltage Vdata can be written (i.e., programmed) to the corresponding pixel and stored.

Next, during the light emission period (te), the high level light emission control voltage (Ve) is applied again to turn on the light emission control transistor (T4), and at this time, the voltage between the gate and source of the driving transistor (T2) (Vgs) is generated. The light-emitting current is applied to the light-emitting diode (OD), causing the light-emitting diode (OD) to emit light.

In driving such a pixel, the switching transistor (T1) is in an off state until the next refresh frame after the data writing period (tp), and in this off state, the first leakage current (IL1) is generated and the first node (N1) The voltage drops. In particular, in the low-frequency driving mode, as the switching transistor T1 is turned off for a long time, the amount of the first leakage current IL1 increases, resulting in a drop in the voltage Vgs between the gate and source of the driving transistor T2. This increases. Accordingly, as shown in FIG. 6, conventionally, the light emitting current (IOLED) applied to the light emitting diode (OD) decreases by approximately 30% as time passes, causing a problem in which the luminance decreases by the amount of the light emitting current decrease. I do it.

On the other hand, according to this embodiment, a compensation transistor (T5) is connected to the first node (N1) and is additionally configured to have a similarly off state when the switching transistor (T1) is in the off state.

When configured in this way, a leakage current (IL2) path is created to the first node (N1) through the compensation transistor (T5).

Therefore, the second leakage current (IL2) leaks to the first node (N1) through the compensation transistor (T5) equal to the amount of the first leakage current (IL1) leaking from the first node (N1) through the switching transistor (T1). ) occurs, so that the current leakage at the first node (N1) can be compensated.

As such, in the low-frequency driving mode, the gate voltage of the driving transistor (T2), which is the voltage of the first node (N1), is prevented from falling due to the first leakage current (IL1) through the switching transistor (T1) during a long holding period. This allows the voltage (Vgs) between the gate and source of the driving transistor (T2) to be maintained. Therefore, as shown in FIG. 7, in this embodiment, even as time passes, the light emission current (IOLED) applied to the light emitting diode (OD) is maintained without substantially decreasing, and is maintained without substantially reducing the current leakage of the switching transistor (T1). The decrease in luminance can be effectively improved.

Moreover, as current leakage can be compensated for as described above, the efficiency of the manufacturing process can also be improved.

In this regard, for example, in order to improve the off-current characteristics of the switching transistor (T1), the switching transistor (T1) is formed using a semiconductor with excellent off-characteristics, unlike the other transistors (T2 to T4) in the pixel. You might consider, for example, manufacturing other transistors (T2 to T4) using a semiconductor formed by the LTPS method and using an oxide semiconductor with excellent off-current characteristics for the switching transistor (T1). there is.

However, when using a hybrid structure using transistors of different types, both a process for manufacturing LTPS-type transistors and a process for manufacturing oxide semiconductor-type transistors are required, which causes a problem of reduced manufacturing efficiency. I do it.

On the other hand, if the compensation transistor T5 is additionally configured as in this embodiment, all transistors T1 to T5 configured in the pixel can be manufactured using the same LTPS method, thereby improving manufacturing efficiency.

<Second Embodiment>

The above-described first embodiment was described as an example of applying a compensation transistor to an organic light emitting diode display device having a source follower compensation circuit for the threshold voltage.

Meanwhile, in the second embodiment, a case where a compensation transistor is applied to an organic light emitting display device having a diode connection compensation circuit will be described.

FIG. 8 is an equivalent circuit diagram schematically showing the pixel structure of an organic light emitting diode display device according to a second embodiment of the present invention, and FIG. 9 is a diagram showing a driving signal for driving a pixel during a refresh frame in the second embodiment of the present invention. This is a timing diagram schematically showing the waveform.

Looking at the pixel (P) to which the diode connection compensation circuit for the threshold voltage is applied, each pixel (P) includes a first switching transistor (T1), a driving transistor (T2), an initialization transistor (T3), and first and second light emission control transistors ( T4, T5), a second switching transistor (T6), a light emitting diode (OD), and a capacitor (C). Moreover, the pixel P of this embodiment may be additionally equipped with a compensation transistor T7 to compensate for the first leakage current IL1 of the second switching transistor T6.

The first switching transistor (T1) is turned on in response to the first scan voltage (Vsc1) applied through the first scan line (SL1) of the corresponding row line, and accordingly the data voltage (Vdata) provided through the data line (DL) ) can be applied to the driving transistor (T2). The source of this switching transistor (T1) is connected to the data line (DL), the gate is connected to the first scan line (SL1), and the drain is connected to the source of the driving transistor (T2), that is, the second node (N2). You can.

The driving transistor (T2) controls the light-emitting current applied to the light-emitting diode (OD) by the gate-source voltage (Vgs). The gate of the driving transistor T2 may be connected to the first node N1, and the drain may be connected to the third node N3.

The initialization transistor (T3) is turned on in response to the second scan voltage (Vsc2) applied through the second scan line (SL2) of the corresponding row line, and accordingly, the initialization voltage (Vini) is connected to the fourth node (N4) and the fourth node (N4). It can be authorized to 5 nodes (N5). The gate of this initialization transistor (T3) is connected to the second scan line (SL2), the source is connected to the initialization voltage (Vini) input terminal, and the drain is connected to the fourth node (N4) and the fifth node (N5). You can.

The first light emission control transistor (T4) responds to the first light emission control voltage (Ve1) applied through the first light emission control wire (EL1) of the row line, and connects the first driving voltage (Vdd) input terminal and the driving transistor (T2) to the first driving voltage (Vdd) input terminal. ) Controls the current path between The gate of the first light emission control transistor (T4) is connected to the first light emission control wire (EL1), the drain is connected to the first driving voltage (Vdd) input terminal, and the source is the drain of the driving transistor (T2), i.e. Can be connected to 3 nodes (N3).

The second light emission control transistor (T5) responds to the second light emission control voltage (Ve2) applied through the second light emission control wire (EL2) of the row line, and generates a current between the light emitting diode (OD) and the driving transistor (T2). Control the path. The gate of the second light emission control transistor T5 is connected to the second light emission control wire EL2, the source is connected to the first electrode, that is, the fifth node N5, of the light emitting diode OD, and the drain is driven. It may be connected to the source of the transistor T2, that is, the second node N2.

The light emitting diode (OD) is an organic light emitting diode made of organic materials and emits light by the light emitting current supplied from the driving transistor (T2). The first electrode of the light emitting diode (OD) may be connected to the fifth node (N5), and the second electrode may be connected to the second driving voltage (Vss) input terminal.

The second switching transistor (T6) is connected between the gate and source of the driving transistor (T2) (i.e., between the first node (N1) and the third node (N3)) and is connected to the driving transistor (T2) according to the diode connection compensation method. The moon turn voltage (Vth) is sampled. The gate of the second switching transistor T6 is connected to the second scan line SL2.

The capacitor C is connected between the first node N1 and the fourth node N4. This capacitor (C) stores and maintains the gate voltage and threshold voltage (Vth) of the driving transistor (T2) until the next refresh frame.

Meanwhile, as a characteristic configuration of this embodiment, the compensation transistor T7, which compensates for the change in the gate-source voltage (Vgs) of the driving transistor (T2) due to the leakage current (IL1) through the second switching transistor (T6), is It is connected between the first node (N1) and the second node (N3). Accordingly, a function of compensating for voltage changes caused by the first leakage current IL1, which is a leakage current that leaks in the off state of the second switching transistor T6, is performed.

To this end, the compensation transistor (T7) can be controlled to be in an off state during the time that the second switching transistor (T6) is in an off state, especially during the period in which the second switching transistor (T6) is in an off state after data writing. It can be controlled to be in an off state.

At this time, the compensation transistor T7 is preferably configured to have substantially the same off-current characteristics as the second switching transistor T6. For example, the compensation transistor T7 and the second switching transistor T6 are substantially turned off. It can be configured to have the same resistance value in each state.

When configured in this way, a leakage current (IL2) path is created from the first node (N1) to the second node (N2) through the compensation transistor (T7).

Therefore, when the first leakage current (IL1) leaking to the first node (N1) occurs through the second switching transistor (T6), the compensation transistor (T7) is increased by the amount of leakage of the first leakage current (IL1). Through this, a second leakage current (IL2) leaking from the first node (N1) is generated, so that the leakage current from the first node (N1) can be substantially offset and compensated.

As such, in the low-frequency driving mode, the gate voltage of the driving transistor (T2), which is the voltage of the first node (N1), increases due to the first leakage current (IL1) through the second switching transistor (T6) during a long holding period. This can prevent this, and the voltage (Vgs) between the gate and source of the driving transistor (T2) can be maintained. Accordingly, the increase in luminance caused by the leakage current IL1 of the second switching transistor T6 can be effectively improved.

The drain of this compensation transistor (T7) may be connected to the second node (N2), the source may be connected to the first node (N1), and the gate may be connected to the off voltage (Voff) input terminal. In this case, the compensation transistor (T7) remains continuously off.

Hereinafter, a method of driving a pixel according to this embodiment will be described with reference to FIG. 9 .

Referring to FIG. 9, an initialization period (ti), a sampling/data writing period (tsp), and an emission period (te) may be sequentially defined in the refresh frame (Fr).

First, during the initialization period (ti), the high level second scan voltage (Vsc2), which is the turn-on level, is applied to the second scan wire (SL2), and accordingly, the initialization voltage (Vini) is applied to the fourth and fifth nodes (N4, N5). ) is supplied to.

At this time, the sixth transistor (T6) connected to the second scan line (SL2) is turned on, and the driving transistor (T2) is in a diode state in which the drain and gate are directly connected.

Meanwhile, the first light emission control voltage Ve1 at a high level, which is a turn-on level, is applied to the first light emission control wire EL1 during at least an early part of the initialization period ti, and the first driving voltage Vdd is accordingly applied to the first light emission control line EL1. It is applied to the third node (N3) and the first node (N1).

Next, during the sampling/data writing period (tse), the first scan voltage (Vsc1) of high level, which is the turn-on level, is applied to the first scan wire (SL1), and during this period, the second scan voltage (Vsc2) is at the turn-on level. will be maintained.

Accordingly, the data voltage (Vdata) provided through the data line (DL) is applied to the second node (N2). Then, the driving transistor (T2) is in a diode state, and the first node (N1) has a potential of (Vdata + Vth), which is as high as the threshold voltage (Vth) of the driving transistor (T2) compared to the second node (N2). You will have Therefore, during the sampling/data writing period (tse), the threshold voltage (Vth) of the driving transistor (T2) is sampled and the data voltage (Vdata) is written, and this threshold voltage (Vth) and data voltage (Vdata) are stored in the capacitor (C). ) is stored in

Next, the high level second light emission control voltage Ve2 is applied to turn on the second light emission control transistor T5, and after a predetermined time, the high level first light emission control voltage Ve1 is applied to turn the first light emission control transistor T5 on. (T4) is turned on, and a light-emitting current is applied to the light-emitting diode (OD) according to the gate-source voltage (Vgs) of the driving transistor (T2), causing the light-emitting diode (OD) to emit light.

In such pixel driving, the second switching transistor (T6) is in an off state until the next refresh frame after the data writing period (tsp), and in this off state, the first leakage current of the second switching transistor (T6) is (IL1) occurs and the voltage of the first node (N2) increases. In particular, in the low-frequency driving mode, the second switching transistor (T6) is turned off for a long time, thereby increasing the amount of leakage current (IL1) to the first node (N1), thereby reducing the gate-source of the driving transistor (T2). The increase in voltage (Vgs) increases.

On the other hand, according to this embodiment, a compensation transistor (T7) is connected between the first node (N1) and the second node (N2) and has a similarly off state in the off state of the second switching transistor (T6). It is composed.

When configured in this way, a leakage current (IL2) path is created from the first node (N3) to the second node (N1) through the compensation transistor (T7).

Therefore, the second leakage current leaking from the first node (N1) through the compensation transistor (T7) is equal to the amount of the first leakage current (IL1) leaking to the first node (N1) through the second switching transistor (T6). (IL2) occurs, and current leakage at the first node (N1) can be compensated.

As such, in the low-frequency driving mode, the gate voltage of the driving transistor (T2), which is the voltage of the first node (N1), increases due to the first leakage current (IL1) through the second switching transistor (T6) during a long holding period. This can prevent this, and the voltage (Vgs) between the gate and source of the driving transistor (T2) can be maintained. Therefore, in this embodiment, even as time passes, the light emission current applied to the light emitting diode (OD) is maintained without substantially increasing, and the increase in luminance due to current leakage of the second switching transistor (T6) can be effectively improved. .

Moreover, as current leakage can be compensated for as described above, the efficiency of the manufacturing process can also be improved.

As described above, according to embodiments of the present invention, a compensation transistor is installed at the gate of the driving transistor to compensate for the change in gate voltage of the driving transistor due to the leakage current in the off state of the switching transistor connected to the gate of the driving transistor. It connects.

Accordingly, the change in voltage between the gate and source of the driving transistor can be compensated and kept constant, thereby improving the change in luminance of the light emitting diode.

Additionally, as current leakage through the switching transistor can be compensated for, all transistors can be manufactured through the same process, thereby improving process efficiency.

The above-described embodiment of the present invention is an example of the present invention, and free modification is possible within the scope included in the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention within the scope of the appended claims and their equivalents.

100: liquid crystal display device 110: display panel
120: data driving circuit 130: gate driving circuit
140: Timing control circuit P: Pixel
T1: switching transistor T2: driving transistor
T3: Initialization transistor T4: Light emission control transistor
C1: first capacitor C2: second capacitor
OD: light emitting diode IL1: first leakage current
IL2: Second leakage current DL: Data wiring
SL1: 1st scan wiring SL2: 2nd scan wiring
EL: Light emission control wiring Vref: Reference voltage
Vdata: data voltage Vini: initialization voltage
Vsc1: 1st scan voltage Vsc2: 2nd scan voltage
Ve: light emission control voltage Vdd: first driving voltage
Vss: Second driving voltage Fr: Refresh frame
Fh: Holding frame FP: Holding section

Claims (9)

a switching transistor connected to the first scan wire and the data wire;
a driving transistor whose gate is connected to the drain of the switching transistor at a first node;
a light emitting diode connected to the source of the driving transistor during the light emission period;
a first capacitor connected between the first node and the second node;
A compensation transistor connected between the drain of the driving transistor and the first node and in an off state during the light emission period.
Including,
During the sampling period in which the threshold voltage of the driving transistor is sampled and stored in the first capacitor, the compensation transistor is in an off state.
Organic light emitting display device.
According to claim 1,
an initialization transistor connected to the second node and whose gate is connected to a second scan line;
a light emission control transistor connected between the drain of the driving transistor and a driving voltage input terminal;
Further comprising a second capacitor connected between the second node and the driving voltage input terminal,
The second scan wire is connected to the gate of the compensation transistor.
Organic light emitting display device.
According to claim 1,
The gate of the compensation transistor receives an off voltage during the light emission period.
Organic light emitting display device.
According to claim 1,
The off-state resistance value of the compensation transistor is the same as the off-state resistance value of the switching transistor.
Organic light emitting display device.
a first switching transistor connected to the first scan wire and the data wire;
a driving transistor whose source is connected to the drain of the first switching transistor at a second node;
a light emitting diode connected to the source of the driving transistor during the light emission period;
a second switching transistor connected between the drain and gate of the driving transistor, the gate of which is connected to a second scan wire;
a capacitor connected to the gate of the driving transistor at a first node;
A compensation transistor connected between the first node and the second node and in an off state during the light emission period.
An organic light emitting display device comprising:
According to claim 5,
a first light emission control transistor connected to the drain of the driving transistor at a third node;
an initialization transistor connected to the capacitor at a fourth node and having a gate connected to the second scan line;
Further comprising a second light emission control transistor connected between the source of the driving transistor and the light emitting diode,
The fourth node is connected to the fifth node between the second light emission control transistor and the light emitting diode, and the capacitor is connected between the first node and the fourth node.
Organic light emitting display device.
According to claim 5,
The gate of the compensation transistor receives an off voltage during the light emission period.
Organic light emitting display device.
According to claim 5,
The off-state resistance value of the compensation transistor is the same as the off-state resistance value of the second switching transistor.
Organic light emitting display device. According to claim 1,
During the initialization period when the initialization voltage is applied to the second node, the compensation transistor is in an on state.
Organic light emitting display device.

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