CN114093320A

CN114093320A - Pixel circuit, pixel driving method and display device

Info

Publication number: CN114093320A
Application number: CN202111425480.2A
Authority: CN
Inventors: 卢昭阳; 李荣荣
Original assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Current assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Priority date: 2021-11-26
Filing date: 2021-11-26
Publication date: 2022-02-25

Abstract

The disclosure relates to a pixel circuit, a pixel driving method and a display device. The pixel circuit includes a light emitting element, a capacitor structure, a driving transistor, and first to sixth switching elements, the first switching element being configured to respond to a first scan signal to apply a first power supply signal to a first terminal of the driving transistor; the second switching element, the third switching element and the fourth switching element are used for responding to a second scanning signal, respectively connecting the first end of the driving transistor with the control end of the driving transistor and the first end of the capacitor structure, respectively, applying a data signal to the second end of the capacitor structure and applying a reference signal to the second end of the driving transistor; the fifth switching element and the sixth switching element are used for responding to a third scanning signal, connecting the first end of the light-emitting element with the second end of the driving transistor and connecting the first end of the light-emitting element with the second end of the capacitor structure; the second end of the light-emitting element is connected with a second power supply signal. The scheme can improve the display uniformity.

Description

Pixel circuit, pixel driving method and display device

Technical Field

The disclosure belongs to the technical field of display, and particularly relates to a pixel circuit, a pixel driving method and a display device.

Background

Currently, in an OLED display panel, a 2T1C circuit is often used for a pixel circuit, that is: the OLED display comprises two transistors and a capacitor, wherein the two transistors are a switching transistor and a driving transistor respectively, and a power supply signal line is used for supplying power to the OLED display, so that the OLED display has the condition of non-uniform display.

Disclosure of Invention

The present disclosure provides a pixel circuit, a pixel driving method, and a display device, which can improve display uniformity.

A first aspect of the present disclosure provides a pixel circuit including a light emitting element, a capacitor structure, a driving transistor, and first to sixth switching elements, wherein,

the first switching element for responding to a first scan signal to apply a first power supply signal to the first terminal of the driving transistor;

the second switching element is used for responding to a second scanning signal so as to connect the first end of the driving transistor with the control end of the driving transistor and the first end of the capacitor structure respectively;

the third switching element for responding to the second scan signal to apply a data signal to the second terminal of the capacitor structure;

the fourth switching element for responding to the second scanning signal to apply a reference signal to the second terminal of the driving transistor;

the fifth switching element for responding to a third scanning signal to connect the first terminal of the light emitting element with the second terminal of the driving transistor;

the sixth switching element is used for responding to the third scanning signal so as to connect the first end of the light-emitting element with the second end of the capacitor structure;

and the second end of the light-emitting element is connected with a second power supply signal.

In an exemplary embodiment of the present disclosure, the first to sixth switching elements respectively include first to sixth transistors; wherein the content of the first and second substances,

the control end of the first transistor is connected with the first scanning signal, the first end of the first transistor is connected with the first power supply signal, and the second end of the first transistor is connected with the first end of the driving transistor;

the control end of the second transistor is connected with the second scanning signal, the first end of the second transistor is connected with the first end of the driving transistor, and the second end of the second transistor is connected with the first node;

the control end of the third transistor is connected with the second scanning signal, the first end of the third transistor is connected with the data signal, and the second end of the third transistor is connected with the second node;

the control end of the fourth transistor is connected with the second scanning signal, the first end of the fourth transistor is connected with the reference signal, and the second end of the fourth transistor is connected with the third node;

a control end of the fifth transistor is connected with the third scanning signal, a first end of the fifth transistor is connected with the third node, and a second end of the fifth transistor is connected with the fourth node;

a control end of the sixth transistor is connected to the third scanning signal, a first end of the sixth transistor is connected to the fourth node, and a second end of the sixth transistor is connected to the second node;

the control end of the driving transistor is connected with the first node, and the second end of the driving transistor is connected with the third node;

a first end of the capacitor structure is connected with the first node, and a second end of the capacitor structure is connected with the second node;

the first end of the light emitting element is connected to the fourth node.

In an exemplary embodiment of the present disclosure, the driving transistor and the first to sixth transistors are all oxide thin film transistors.

In an exemplary embodiment of the present disclosure, the driving transistor and the first to sixth transistors are both N-type thin film transistors;

the first power signal is a direct current high level signal, and the second power signal is a direct current low level signal.

In an exemplary embodiment of the present disclosure, the light emitting element is an organic light emitting diode, an anode of the organic light emitting diode is connected to the fourth node, and a cathode of the organic light emitting diode is connected to a second power signal.

In an exemplary embodiment of the present disclosure, a scanning direction of the pixel circuits is from a 1 st row to a last row; wherein the content of the first and second substances,

the first scanning signal is provided by an Nth row scanning signal line, the second scanning signal is provided by an N +1 th row scanning signal line, and the third scanning signal is provided by an N +2 th row scanning signal line, wherein N is a positive integer greater than or equal to 1.

A second aspect of the present disclosure provides a pixel driving method for driving the aforementioned pixel circuit, wherein the pixel driving method includes:

in a reset phase, turning on the first to fourth switching elements by the first scan signal and the second scan signal, and simultaneously turning off the fifth and sixth switching elements by the third scan signal;

in a compensation phase, turning off the first, fifth and sixth switching elements using the first scan signal and the third scan signal, and simultaneously, turning on the second to fourth switching elements using the second scan signal;

in a light emitting stage, the first, fifth, and sixth switching elements are turned on by the first scan signal and the third scan signal, and at the same time, the second to fourth switching elements are turned off by the second scan signal.

In an exemplary embodiment of the present disclosure, the first power signal is a dc high level signal, and the second power signal is a dc low level signal; wherein the content of the first and second substances,

in the reset phase, the first scanning signal and the second scanning signal are at a high level, and the third scanning signal is at a low level;

in the compensation stage, the first scanning signal and the third scanning signal are at a low level, and the second scanning signal is at a high level;

in the light emitting period, the first scan signal and the third scan signal are at a high level, and the second scan signal is at a low level.

A second aspect of the present disclosure provides a display device including a substrate having a display area and a plurality of pixel groups located in the display area, wherein the pixel groups include:

the pixel circuit described above;

a first scanning signal line electrically connected to the first switching element for providing the first scanning signal;

a first power supply signal line electrically connected to the first switching element for supplying the first power supply signal;

a second scanning signal line electrically connected to the second to fourth switching elements, respectively, for providing the second scanning signal;

a third scanning signal line electrically connected to the fifth and sixth switching elements, respectively, for providing the third scanning signal;

a data signal line connected to the third switching element, for supplying the data signal;

a reference signal line connected to the fourth switching element for providing the reference signal;

and a second power signal line connected to a second terminal of the light emitting element for supplying a second power signal.

In an exemplary embodiment of the present disclosure, the substrate further has a non-display region disposed around the display region;

the display device further comprises a gate driving circuit located in the non-display area, and the gate driving circuit is connected with the first scanning signal line, the second scanning signal line and the third scanning signal line.

The pixel circuit, the pixel driving method and the display device can be used for realizing pixel compensation. The pixel circuit can comprise a light-emitting element, a capacitor structure, a driving transistor and first to sixth switching elements, and the six switching elements and the driving transistor are controlled to be switched on or switched off by scanning signals to realize a circuit resetting stage, a compensation stage and a light-emitting stage; the pixel circuit can eliminate the bad factors such as threshold voltage Vth, OLED aging and the like in the light-emitting stage, so that the display problem of the 2T1C circuit can be solved, the display picture effect can be enhanced, the high brightness uniformity is ensured, and the service life of the OLED can be prolonged.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 shows a module connection schematic diagram of a pixel circuit according to a first embodiment of the disclosure.

Fig. 2 shows a schematic diagram of a pixel circuit according to a first embodiment of the disclosure.

Fig. 3 shows a flowchart of a pixel driving method according to the second embodiment of the disclosure.

Fig. 4 shows a driving timing diagram of the pixel circuit in fig. 2.

Fig. 5 shows an equivalent circuit diagram of the pixel circuit in fig. 2 in a reset phase.

Fig. 6 shows an equivalent circuit diagram of the pixel circuit of fig. 2 in the compensation stage.

Fig. 7 shows an equivalent circuit diagram of the pixel circuit in fig. 2 at a light emitting stage.

Fig. 8 is a schematic diagram illustrating a connection relationship between a pixel circuit and a gate driving circuit in a display device according to a third embodiment of the disclosure.

Description of reference numerals:

11-a first switching element; 12-a second switching element; 13-a third switching element; 14-a fourth switching element; 15-a fifth switching element; 16-a sixth switching element; 17-a first scanning signal line; 18-a first power supply signal line; 19-a second scanning signal line; 20-a third scanning signal line; 21-data signal lines; 22-reference signal line; 23-second power supply signal line; 24-a gate drive circuit;

an L-light emitting element; a C-capacitor structure; DT-drive transistor; t1 — first transistor; t2 — second transistor; t3 — third transistor; t4 — fourth transistor; t5 — fifth transistor; t6 — sixth transistor; sn-first scanning signal; sn + 1-second scanning signal; sn + 2-third scanning signal; VDD — a first power supply signal; Data-Data signal; vref-reference signal; VSS-second power supply signal; g-a first node; a-a second node; s-a third node; b-a fourth node.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

In the present disclosure, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the disclosure.

Example one

The embodiment of the disclosure provides a pixel circuit for realizing pixel compensation. As shown in fig. 1, the pixel circuit may include a light emitting element L, a capacitor structure C, a driving transistor DT, a first switching element 11, a second switching element 12, a third switching element 13, a fourth switching element 14, a fifth switching element 15, and a sixth switching element 16.

It should be understood that the light emitting element L and the capacitor structure C each have a first terminal and a second terminal, and the driving transistor DT has a control terminal in addition to the first terminal and the second terminal; the relationship among the first to sixth switching elements, the light emitting element L, the capacitor structure C, and the driving transistor DT is as follows.

The first switching element 11 is operable to apply a first power supply signal VDD to a first terminal of the driving transistor DT in response to the first scan signal Sn.

And a second switching element 12 operable to respond to the second scan signal Sn +1 to connect the first terminal of the driving transistor DT to the control terminal of the driving transistor DT and the first terminal of the capacitive structure C, respectively. Specifically, the first switching element 11 responds to the first scan signal Sn while the second switching element 12 responds to the second scan signal Sn +1, so that the first power supply signal VDD is applied to the control terminal of the driving transistor DT and the first terminal of the capacitance structure C.

And a third switching element operable to respond to the second scan signal Sn +1 to apply the Data signal Data to the second terminal of the capacitance structure C.

And a fourth switching element operable to respond to the second scan signal Sn +1 to apply the reference signal Vref to the second terminal of the driving transistor DT.

And a fifth switching element operable to connect the first terminal of the light emitting element L to the second terminal of the driving transistor DT in response to the third scan signal Sn +2, and the second terminal of the light emitting element L to the second power signal VSS.

And a sixth switching element operable to respond to the third scan signal Sn +2 to connect the first terminal of the light emitting element L with the second terminal of the capacitor structure C.

In the embodiment of the disclosure, the six switching elements and the driving transistors are controlled to be turned on or off by three scanning signals, so that a circuit reset stage, a compensation stage and a light-emitting stage can be realized; the pixel circuit can eliminate the threshold voltage Vth of the driving transistor DT, the aging of the light-emitting device L and other bad factors in the light-emitting stage, so that the display problem of the 2T1C circuit can be solved, the display picture effect can be enhanced, the high brightness uniformity is ensured, the damage to the light-emitting device L can be reduced, and the service life of the light-emitting device L is prolonged.

Illustratively, the first scan signal Sn is provided by the nth row scan signal line, the second scan signal Sn +1 is provided by the N +1 th row scan signal line, and the third scan signal Sn +2 is provided by the N +2 th row scan signal line, wherein the scan direction of the present embodiment is from row 1 to the last row, that is, the first scan signal Sn precedes the second scan signal Sn +1, and the second scan signal Sn +1 precedes the third scan signal Sn +2, by using three adjacent scan signal lines to respectively and correspondingly provide the first to third scan signals, the circuit structure design can be simplified, the number of control signal wires can be reduced, and the pixel aperture ratio can be increased.

Wherein N is a positive integer greater than or equal to 1.

Exemplarily, as shown in fig. 1 and 2 in combination, the first switching element 11 includes a first transistor T1, the second switching element 12 includes a second transistor T2, the third switching element 13 includes a third transistor T3, the fourth switching element 14 includes a fourth transistor T4, the fifth switching element 15 includes a fifth transistor T5, and the sixth switching element 16 includes a sixth transistor T6.

It should be understood that the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are identical to the driving transistor DT, and each have a first terminal, a second terminal and a control terminal. The control terminal of each transistor corresponds to the gate of the transistor, one of the first terminal and the second terminal corresponds to the source of the transistor, and the other corresponds to the drain of the transistor.

For example, the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 of the embodiments of the present disclosure may all be oxide thin film transistors, that is: the active layer of each transistor may be made of an Oxide, for example, a metal Oxide material such as IZGO (Indium Gallium Zinc Oxide) may be used, and compared with an a-Si (amorphous silicon) thin film transistor, the IGZO thin film transistor has 3 advantages in performance, namely, high precision, low power consumption, and high touch performance, and the main supply targets are electronic display products such as a tablet computer and a super notebook.

In addition, compared with a Low Temperature Polycrystalline Silicon (LTPS) thin film transistor, the IGZO thin film transistor does not need to be irradiated with laser to crystallize a semiconductor layer, so that the IGZO thin film transistor has the characteristic of easily enlarging the size of a glass substrate.

For example, each transistor may be of the bottom-gate type, i.e.: the gate of the transistor is located below the active layer (on the side close to the glass substrate) to enable proper thinning of the product, but is not limited thereto, and each transistor may also be of a top gate type, as the case may be.

In addition, each transistor may be an enhancement type transistor or a depletion type transistor, which is not particularly limited in the embodiments of the present disclosure.

For example, all transistors in the pixel circuit may be N-type thin film transistors, that is: the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 may all be N-type thin film transistors, and the driving voltage of each transistor corresponds to a high level voltage; accordingly, the first power signal VDD may be a dc high level signal, and the second power signal VSS may be a dc low level signal.

It should be understood that the transistors in the pixel circuit are not limited to the aforementioned N-type thin film transistors, but may be all P-type thin film transistors. When each transistor is a P-type thin film transistor: the driving voltage of each transistor may correspond to a low level voltage; based on this, the first power signal VDD may be a dc low level signal, and the second power signal VSS may be a dc high level signal.

Illustratively, the light emitting element L may be a current-driven type light emitting element which is controlled to emit light by a current flowing through the driving transistor DT, for example: the light emitting device L may be an Organic Light Emitting Diode (OLED), that is, the pixel circuit may be applied to an OLED display device.

In the pixel circuit, when each transistor is an N-type thin film transistor, the first end of the light emitting element L is an anode of the OLED, and the second end of the light emitting element L is a cathode of the OLED. In the pixel circuit, when each transistor is a P-type thin film transistor, the first end of the light emitting element L is the cathode of the OLED, and the second end of the light emitting element L is the anode of the OLED.

The connection relationship of the structures in the pixel circuit will be described in detail with reference to fig. 2, in which the transistors are all N-type thin film transistors, the first power signal VDD is a dc high level signal, the second power signal VSS is a dc low level signal, the first end of the light emitting element L is the anode of the OLED, and the second end of the light emitting element L is the cathode of the OLED.

The first transistor T1 has a control terminal connected to the first scan signal Sn, a first terminal connected to the first power signal VDD, and a second terminal connected to the first terminal of the driving transistor DT.

The second transistor T2 has a control terminal connected to the second scan signal Sn +1, a first terminal connected to the first terminal of the driving transistor DT, and a second terminal connected to the first node G.

A control terminal of the third transistor T3 is connected to the second scan signal Sn +1, a first terminal thereof is connected to the Data signal Data, and a second terminal thereof is connected to the second node a.

A control terminal of the fourth transistor T4 is connected to the second scan signal Sn +1, a first terminal thereof is connected to the reference signal Vref, and a second terminal thereof is connected to the third node S.

A control terminal of the fifth transistor T5 is connected to the third scan signal Sn +2, a first terminal thereof is connected to the third node S, and a second terminal thereof is connected to the fourth node B.

A control terminal of the sixth transistor T6 is connected to the third scan signal Sn +2, a first terminal thereof is connected to the fourth node B, and a second terminal thereof is connected to the second node a.

The control terminal of the driving transistor DT is connected to the first node G, and the second terminal is connected to the third node S.

The first end of the capacitor structure C is connected to the first node G, and the second end is connected to the second node a.

A first end of the light emitting element L is connected to the fourth node B; specifically, the anode of the organic light emitting diode is connected to the fourth node B, and the cathode of the organic light emitting diode is connected to the second power signal VSS.

Based on this, the pixel circuit of the embodiment of the disclosure adopts a 7T1C structure to realize a circuit reset stage, a compensation stage and a light emitting stage, so that the design eliminates the influence of factors such as threshold voltage Vth, OLED aging and VDD difference on display, and simultaneously simplifies the design of the circuit structure, thereby reducing the occupied area thereof, and further facilitating the realization of high PPI (pixel density) display design.

Example two

Based on the pixel circuit mentioned in the first embodiment, a second embodiment of the present disclosure further provides a pixel driving method, which is shown in fig. 1 and fig. 3 and includes:

step S300, in the reset phase, the first switching element 11, the second switching element 12, the third switching element 13, and the fourth switching element 14 are turned on by the first scan signal Sn and the second scan signal Sn +1, and the fifth switching element 15 and the sixth switching element 16 are turned off by the third scan signal Sn + 2;

step S302, in the compensation phase, the first switching element 11, the fifth switching element 15, and the sixth switching element 16 are turned off by using the first scan signal Sn and the third scan signal Sn +2, and the second switching element 12, the third switching element 13, and the fourth switching element 14 are turned on by using the second scan signal Sn + 1;

in step S304, in the light emitting stage, the first switching element 11, the fifth switching element 15, and the sixth switching element 16 are turned on by the first scan signal Sn and the third scan signal Sn +2, and at the same time, the second switching element 12, the third switching element 13, and the fourth switching element 14 are turned off by the second scan signal Sn + 1.

The pixel driving method (i.e., operation) corresponding to the pixel circuit in fig. 2 will be described in detail with reference to the operation timing diagram of the pixel circuit shown in fig. 4.

The operation timing diagram of the pixel circuit shown in fig. 4 illustrates the level states of the first scan signal Sn, the second scan signal Sn +1, and the third scan signal Sn +2 in three periods.

At the reset phase t 1: referring to fig. 4 and 5, the first scan signal Sn and the second scan signal Sn +1 are at a high level, and the third scan signal Sn +2 is at a low level, so that the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned on, and the fifth transistor T5 and the sixth transistor T6 are all turned off; based on this, the first power supply signal VDD is applied to the first node G through the first transistor T1 and the second transistor T2, that is: the first node G writes the Vdd voltage; the Data signal Data is applied to the second node a through the third transistor T3, that is: vdata voltage is written into the second node A; the reference signal Vref is applied to the third node S through the fourth transistor T4, that is: the Vref voltage is written into the third node S, and the specific voltage is as follows:

VA is Vdata, VG is Vdd, VS is Vref; where VA is the voltage at the second node a, VG is the voltage at the first node G, and VS is the voltage at the third node S.

In the compensation phase t 2: referring to fig. 4 and 6, the first and third scan signals Sn and Sn +2 are at a low level, and the second scan signal Sn +1 is at a high level, so that the first, fifth, and sixth transistors T1, T5, and T6 are all in an off state, and the second, third, and fourth transistors T2, T3, and T4 are all in an on state.

Based on this, since the fourth transistor T4 is turned on, the reference signal Vref is applied to the third node S through the fourth transistor T4, that is: the third node S writes the Vref voltage, at which time, the driving transistor DT is turned on, and the first node G starts to leak since the second transistor T2 is turned on, the driving transistor DT is turned off when the first node G voltage leaks to Vref + Vth, and further, since the third transistor T3 is turned on, the Data signal Data is applied to the second node a through the third transistor T3, that is: the Vdata voltage is written into the second node A, and the specific voltage is as follows:

VA is Vdata, VG is Vref + Vth, VS is Vref, VC is VG-VA is Vref + Vth-Vdata; where VA is a voltage at the second node a, VG is a voltage at the first node G, VS is a voltage at the third node S, Vth is a threshold voltage of the driving transistor DT, and VC is a voltage of the capacitor structure C.

In the light emitting period T3, referring to fig. 4 and 7, the first scan signal Sn and the third scan signal Sn +2 are at a high level, the second scan signal Sn +1 is at a low level, so that the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are in an on state, the second transistor T2, the third transistor T3 and the fourth transistor T4 are in an off state, and based on this, since the fifth transistor T5 and the sixth transistor T6 are turned on, the voltage written in the second node a, the third node S and the fourth node B is Voled + Vss, at this time, the voltage variation of the second node a is equal to Voled + Vss-Vdata, and due to the coupling effect of the capacitor structure C, the voltage variation at the first node G should be equal to the voltage variation at the second node a, at this time, the voltage at the first node G + Vref (Voled + Vss) is as follows:

VS＝VA＝VB＝Voled+Vss，VG＝Vref+Vth+(Voled+Vss－Vdata)；

where VA is the voltage at the second node A, VG is the voltage at the first node G, VS is the voltage at the third node S, VB is the voltage at the fourth node B, Vth is the threshold voltage of the driving transistor DT, Voled is the voltage of the OLED (i.e., the light emitting element L), and Vss is the corresponding voltage at the second power signal VSS.

On the basis, according to the current calculation formula of the OLED:

in the light emitting stage t3, the voltage VG at the first node G and the voltage VS at the third node S are substituted into the current calculation formula of the OLED, so as to obtain the following formula:

wherein, mu_nFor electron mobility, C_OXThe capacitance per unit area of the transistor is W/L represents the ratio of the width to the length of a channel of the transistor, and the parameters are relatively stable; based on this, it can be understood from the current calculation formula of the OLED that the OLED current is only related to the voltage Vdata of the data signal and the voltage Vref of the reference signal, μ_n·C_OXW/L is a constant related to process and drive design. Finally, the driving current drives the organic light emitting diode OLED (light emitting element L) to emit light through the fifth transistor T5.

In summary, in the exemplary embodiment, the driving current of the OLED has no relation with the threshold voltage Vth of the driving transistor DT, the voltage Voled of the light emitting element L, and the voltage VDD of the first power signal VDD, and thus the threshold voltage of the driving transistor DT, the lifetime degradation of the light emitting element L, and the difference of the first power signal VDD do not affect the source current, i.e., the driving current I of the organic light emitting diode OLED_OledThe influence is generated, the uniformity and the stability of the driving current are ensured, so that the brightness of the OLED display device is more uniform, the generation of residual shadows is reduced, and the display effect is enhanced.

EXAMPLE III

Based on the foregoing description, the third embodiment further provides a display device, which can be an OLED display device. The display device may include a substrate and a plurality of pixel groups, and the substrate may be made of glass, but is not limited thereto, and may also be Polyimide (PI) as the case may be.

The substrate may have a display area, and the plurality of pixel groups are located in the display area. The pixel group may include a pixel circuit, and details of the first embodiment are specifically referred to, and will not be repeated herein. As shown in fig. 1 and 8, the pixel group may further include:

a first scanning signal line 17 electrically connectable to the first switching element 11 for supplying a first scanning signal Sn;

a first power supply signal line 18 electrically connected to the first switching element 11 for supplying a first power supply signal VDD;

a second scanning signal line 19 electrically connected to the second switching element 12, the third switching element 13, and the fourth switching element 14, respectively, for supplying a second scanning signal Sn + 1;

a third scanning signal line 20 electrically connected to the fifth switching element 15 and the sixth switching element 16, respectively, for supplying a third scanning signal Sn + 2;

a Data signal line 21 connected to the third switching element 13, for supplying a Data signal Data;

a reference signal line 22 connected to the fourth switching element 14 for supplying a reference signal Vref;

the second power signal line 23 is connected to a second terminal of the light emitting element L, and supplies a second power signal VSS.

Exemplarily, the substrate further has a non-display region disposed around the display region; as shown in fig. 8, the display device further includes a gate driving circuit 24 located in the non-display region, and the gate driving circuit 24 is connected to the first scanning signal line 17, the second scanning signal line 19, and the third scanning signal line 20.

As can be seen, the display device of the present embodiment adopts a GDL (gate Driver less) technology, which is a technology with less gate driving circuits, and the driving circuits of the scan signal lines (i.e., the gate driving circuits) are fabricated on the non-display area of the substrate, so that the driving circuits can replace an external Integrated Circuit (IC) to drive the scan signal lines.

The GDL technology can reduce the bonding process of the external IC, thereby increasing the productivity and reducing the product cost, and the display device of the embodiment is more suitable for manufacturing narrow-frame or frameless display products. In addition, the GDL technology is adopted to manufacture the grid drive circuit on the thin film transistor array substrate, thereby saving the space and the cost of the drive IC.

The display device of the embodiment of the disclosure can be an AMOLED (Active-matrix organic light-emitting diode) display, and has the advantages of thin body, power saving, bright color, strong image quality, and the like, and is widely applied. Such as: OLED televisions, mobile phones, notebook computer screens, etc., are gradually dominating in the field of flat panel displays.

In the description herein, references to the description of the terms "some embodiments," "exemplary," etc. mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or exemplary is included in at least one embodiment or exemplary of the present disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present disclosure have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure, and therefore all changes and modifications that are intended to be covered by the claims and the specification of this disclosure are within the scope of the patent disclosure.

Claims

1. A pixel circuit includes a light emitting element, a capacitor structure, a driving transistor, and first to sixth switching elements,

2. The pixel circuit according to claim 1, wherein the first to sixth switching elements respectively include first to sixth transistors; wherein the content of the first and second substances,

the first end of the light emitting element is connected to the fourth node.

3. The pixel circuit according to claim 2, wherein the driving transistor and the first to sixth transistors are oxide thin film transistors.

4. The pixel circuit according to claim 3, wherein the driving transistor and the first to sixth transistors are both N-type thin film transistors;

5. The pixel circuit according to claim 4, wherein the light emitting element is an organic light emitting diode, an anode of the organic light emitting diode is connected to the fourth node, and a cathode of the organic light emitting diode is connected to a second power signal.

6. The pixel circuit according to any one of claims 1 to 5, wherein a scanning direction of the pixel circuit is from a 1 st row to a last row; wherein the content of the first and second substances,

7. A pixel driving method for driving the pixel circuit according to claim 1, the pixel driving method comprising:

8. The pixel driving method according to claim 7, wherein the first power supply signal is a dc high signal, and the second power supply signal is a dc low signal; wherein the content of the first and second substances,

9. A display device comprising a substrate having a display area and a plurality of pixel groups located in the display area, the pixel groups comprising:

the pixel circuit according to claim 1;

10. The display device according to claim 9,

the substrate is also provided with a non-display area arranged around the display area;