KR20210084097A - Display device - Google Patents

Abstract

A display device includes a display panel and a driving circuit, and pixels contained in the display panel includes a driving transistor, a light emitting device, first to fifth switching transistors (T1 to T5), and first and second storage capacitors (Cst1, Cst2). T1 supplies a pixel driving voltage to the driving transistor, T2 connects the driving transistor and the light emitting device, T3 diode-connects the driving transistor, T4 supplies an initialization voltage to the driving transistor, T5 supplies a data voltage to an anode electrode of the light emitting device, Cst1 stores a threshold voltage of the driving transistor, and Cst2 is connected in series with the first storage capacitor to divide the data voltage. The driving circuit drives a pixel by dividing one frame into an initialization period, a sensing period, a data writing period, and a light emission period.

Description

display device {DISPLAY DEVICE}

This specification relates to a display device, and more particularly, to a display device including an internal compensation pixel circuit.

The flat panel display includes a liquid crystal display (LCD), an electroluminescence display, a field emission display (FED), a quantum dot display panel (QD), and the like. . The electroluminescent display is divided into an inorganic light emitting display and an organic light emitting display according to the material of the light emitting layer. Pixels of the organic light emitting diode display include organic light emitting diodes (OLEDs), which are light emitting devices that emit light by themselves, and emit light to display an image.

An active matrix type organic light emitting display panel including an OLED has an advantage in that a response speed is fast and luminous efficiency, luminance, and a viewing angle are large.

In an organic light emitting display device, pixels including an OLED and a driving transistor are arranged in a matrix form, and the luminance of an image implemented in the pixel is adjusted according to a gray level of video data. The driving transistor controls the driving current flowing through the OLED according to the voltage applied between its gate electrode and the source electrode. The amount of light emitted by the OLED is determined according to the driving current, and the brightness of the image is determined according to the amount of light emitted by the OLED.

In the driving transistor, electrical characteristics deteriorate over time, so that a difference may occur between pixels. The electric characteristic deviation between the pixels is a major factor in degrading the image quality by emitting light with different luminance even when the same image data is applied to the pixels.

In order to compensate for variations in electrical characteristics between pixels, an internal compensation method for sampling and compensating for the threshold voltage and/or electron mobility of the driving transistor is employed by adding an internal compensation circuit composed of a plurality of transistors and capacitors to each pixel. is becoming

However, in the case of an internal compensation circuit that needs to perform threshold voltage sensing within one horizontal period, compensation performance deteriorates due to insufficient threshold voltage sensing time, making it difficult to employ in high-resolution or high-frequency models.

The embodiments disclosed in this specification take this situation into account, and an object of this specification is to provide an internal compensation pixel circuit capable of securing a sufficiently long time for sensing a threshold voltage of a driving transistor.

Another object of the present specification is to provide a pixel circuit capable of sensing a threshold voltage of a driving transistor in a sufficient time regardless of an operating frequency by separating a data writing period and a sensing period.

In a display device according to an exemplary embodiment, the display device includes a display panel and a driving circuit, and pixels included in the display panel include a driving transistor, a light emitting device, first to fifth switching transistors T1 to T5 , and first and second transistors. It may include second storage capacitors Cst1 and Cst2.

T1 supplies a pixel driving voltage to the driving transistor, T2 connects the driving transistor and the light emitting device, T3 connects the driving transistor with a diode, T4 supplies an initialization voltage to the driving transistor, and T5 is the anode electrode of the light emitting device may supply a data voltage, Cst1 may store a threshold voltage of the driving transistor, and Cst2 may be connected in series with the first storage capacitor to distribute the data voltage.

The driving circuit may drive a pixel by dividing one frame into an initialization period, a sensing period, a data writing period, and an emission period.

By separating the data writing period and the threshold voltage sensing period, the sensing time can be set longer regardless of the length of one horizontal period, which improves the performance of compensating for the threshold voltage of the driving transistor, and is used in display devices that drive high resolution and high frequency be able to do

Also, it is possible to reduce a deviation for compensating for the threshold voltage of the driving transistor even for a low grayscale data voltage, thereby improving display quality.

1 illustrates an organic light emitting diode display as functional blocks;
2 shows a pixel circuit composed of 6 transistors and 2 capacitors,
3 shows signals related to the driving of the pixel circuit of FIG. 2;
FIG. 4 shows the operation of the initialization period for initializing the pixel circuit of FIG. 2;
5 is a diagram illustrating an operation of a sensing period for sensing a threshold voltage of a driving transistor in the pixel circuit of FIG. 2;
6 is a diagram illustrating an operation of a data writing period in which a data voltage is written into the pixel circuit of FIG. 2;
7 shows the operation of the light emitting period for emitting OLED in the pixel circuit of FIG.
8 is a diagram illustrating an improvement in threshold voltage compensation deviation in a plurality of grayscales.

Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the contents of this specification may unnecessarily obscure or obstruct the understanding of the contents, the detailed description thereof will be omitted.

In the display device, the pixel circuit and the gate driving circuit may include at least one of an N-channel transistor (NMOS) and a P-channel transistor (PMOS). A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from source to drain. In the case of an N-channel transistor, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an N-channel transistor, the direction of current flows from drain to source. In the case of a P-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a P-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may be changed according to an applied voltage. Accordingly, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

A scan signal (or gate signal) applied to the pixels swings between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, while turned-off in response to the gate-off voltage. In the case of the N-channel transistor, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of the P-channel transistor, the gate-on voltage may be the gate low voltage VGL, and the gate-off voltage may be the gate high voltage VGH.

Each of the pixels of the organic light emitting diode display includes an OLED, which is a light emitting device, and a driving device for driving the OLED by supplying a current to the OLED according to a gate-source voltage (Vgs). An OLED includes an anode, a cathode, and an organic compound layer formed between the electrodes. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (Electron Injection layer, EIL) and the like, but is not limited thereto. When a current flows in the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML) to form excitons, and as a result, the light emitting layer (EML) can emit visible light. have.

The driving device may be implemented as a transistor such as a metal oxide semiconductor field effect transistor (MOSFET). Although the driving transistor should have uniform electrical characteristics among the pixels, there may be differences between the pixels due to process variations and device characteristics variations, and may change with the lapse of display driving time. In order to compensate for the deviation in the electrical characteristics of the driving transistor, an internal compensation method and/or an external compensation method may be applied to the organic light emitting diode display. In the following examples, the internal compensation method is applied.

1 illustrates an organic light emitting diode display as a block. The display device of FIG. 1 may include a display panel 10 , a timing controller 11 , a data driving circuit 12 , a gate driving circuit 13 , and a power supply unit 16 .

The timing controller 11 , the data driving circuit 12 , the gate driving circuit 13 , and the power supply unit 16 of FIG. 1 may be all or partly integrated in the drive IC, and the data driving circuit 12 and the gate driving circuit (13) may be merged to form one driving circuit.

On the screen on which the input image is displayed on the display panel 10 , a plurality of data lines 14 arranged in a column direction (or a vertical direction) and a plurality of data lines 14 arranged in a row direction (or a horizontal direction) are arranged on the screen on which the input image is displayed. The gate lines 15 intersect each other, and pixels PXL are arranged in a matrix form in each intersecting area to form a pixel array.

The gate line 15 applies a data voltage supplied to the data line 14 to the pixels, and supplies a scan signal, a light emitting signal, and the like for emitting light to the pixels.

The display panel 100 supplies a first power line for supplying the pixel driving voltage (or high potential power voltage) VDD to the pixels PXL and a low potential power voltage VSS to the pixels PXL. It may further include a second power line to initialize the pixel circuit, an initialization voltage line for supplying an initialization voltage Vini for initializing the pixel circuit, and the like. The first/second power line and the initialization voltage line are connected to the power source 16 . The second power line may be formed in the form of a transparent electrode covering the plurality of pixels PXL.

Touch sensors may be disposed on the pixel array of the display panel 10 . The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors are on-cell type or add-on type, in-cell type touch disposed on the screen AA of the display panel PXL or embedded in a pixel array. It can be implemented with sensors.

In the pixel array, pixels PXL disposed on the same horizontal line are connected to any one of the data lines 14 and any one (or two or more) of the gate lines 15 to form a pixel line. The pixel PXL is electrically connected to the data line 14 in response to the scan signal and the emission signal applied through the gate line 15 , receives a data voltage, and emits the OLED with a current corresponding to the data voltage. The pixels PXL disposed on the same pixel line simultaneously operate according to the scan signal and the emission signal applied from the same gate line 15 .

One pixel unit may be composed of three sub-pixels including a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or four sub-pixels including a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. , but not limited thereto. Each subpixel may be implemented as a pixel circuit including an internal compensation circuit. Hereinafter, a pixel means a sub-pixel.

The pixel PXL receives the pixel driving voltage VDD, the initialization voltage Vini, and the low-potential power supply voltage VSS from the power source 16 , and includes a driving transistor, an OLED, and an internal compensation circuit as shown in FIG. 2 . can

The timing controller 11 supplies the image data RGB transmitted from the external host system to the data driving circuit 12 . The timing controller 11 receives timing signals, such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a dot clock (DCLK) from the host system, and includes the data driving circuit 12 and Control signals for controlling the operation timing of the gate driving circuit 13 are generated. The control signals include a gate control signal GCS for controlling an operation timing of the gate driving circuit 13 and a data control signal DCS for controlling an operation timing of the data driving circuit 12 .

The data driving circuit 12 samples digital video data RGB input from the timing controller 11 based on the data control signal DCS, latches it, and converts it into parallel data, and through channels according to the gamma reference voltage It is converted into an analog data voltage, and the data voltage is supplied to the pixels PXL through an output channel and data lines 14 . The data voltage may be a value corresponding to the gray level to be expressed by the pixel. The data driving circuit 12 may include a plurality of source driver ICs.

Each source drive IC constituting the data driving circuit 12 may include a shift register, a latch, a level shifter, a DAC, and a buffer. The shift register shifts the clock input from the timing controller 11 to sequentially output the clock for sampling, and the latch samples digital video data or pixel data at the timing of the sampling clock sequentially input from the shift register and latches it. The sampled pixel data is output simultaneously, the level shifter shifts the voltage of the pixel data input from the latch into the input voltage range of the DAC, and the DAC converts the pixel data from the level shifter into a data voltage based on the gamma compensation voltage. and the data voltage output from the DAC is supplied to the data line 14 through the buffer.

The gate driving circuit 13 generates a scan signal and a light emission signal based on the gate control signal GCS, but generates the scan signal and the light emission signal in a row-sequential manner during the active period to generate a gate line 15 connected to each pixel line. are provided sequentially. The scan signal and the light emission signal of the gate line 15 are synchronized with the supply of the data voltage of the data line 14 . The scan signal and the emission signal swing between the gate-on voltage VGL and the gate-off voltage VGH.

The gate driving circuit 13 may be composed of a plurality of gate drive integrated circuits each including a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a pixel, an output buffer, and the like. have. Alternatively, the gate driving circuit 13 may be directly formed on the lower substrate of the display panel 10 using a GIP (Gate Drive IC in Panel) method. In the case of the GIP method, the level shifter may be mounted on a printed circuit board (PCB), and the shift register may be formed on a lower substrate of the display panel 10 .

The power supply unit 16 adjusts the DC input voltage provided from the host using a DC-DC converter to adjust the gate-on voltage required for the operation of the data driving circuit 12 and the gate driving circuit 13 . (VGL). A gate-off voltage VGH is generated, and a pixel driving voltage VDD, an initialization voltage Vini, and a low-potential power supply voltage VSS required for driving the pixel array are generated.

The host system may be an application processor (AP) in a mobile device, a wearable device, a virtual/augmented reality device, and the like. Alternatively, the host system may be a main board such as a television system, a set-top box, a navigation system, a personal computer, and a home theater system, but is not limited thereto.

FIG. 2 shows a pixel circuit including six transistors and two capacitors, and includes an internal compensation circuit.

The pixel circuit of FIG. 2 includes a driving transistor DT, an OLED, five switching transistors T1 to T5, and two storage capacitors Cst1 and Cst2. In the pixel circuit of FIG. 2 , the transistor is implemented as an N-channel transistor, but is not limited thereto.

Since it is an N-channel transistor, the gate-on voltage that turns on the transistor is the gate high voltage VGH, and the gate-off voltage that turns off the transistor is the gate low voltage VGL.

The first switching transistor T1 supplies power to the driving transistor DT by connecting the fourth node N4 that is the drain electrode of the driving transistor DT and the first power line supplying the pixel driving voltage VDD. For this purpose, the gate electrode is connected to the third gate line for supplying the emission signal EM, one of the first electrode and the second electrode is connected to the first power line and the other is connected to the fourth node N4. Connected.

The second switching transistor T2 is for connecting the driving transistor DT and the OLED by connecting the third node N3 which is the source electrode of the driving transistor DT and the second node N2 which is the anode electrode of the OLED. , the gate electrode is connected to the third gate line supplying the emission signal EM, one of the first electrode and the second electrode is connected to the third node N3, and the other is connected to the anode electrode (or the first electrode) of the OLED. 2 node (N2)).

The third switching transistor T3 is for diode-connecting the driving transistor DT by connecting the fourth node N4 and the first node N1 that is the gate electrode of the driving transistor DT, and the gate electrode is the first It is connected to the first gate line that supplies the scan signal SCAN1 , one of the first electrode and the second electrode is connected to the first node N1 and the other is connected to the fourth node N4 .

The fourth switching transistor T4 connects an initialization voltage line supplying the initialization voltage Vini and the third node N3 to supply an initialization voltage to the third node N3, and a gate electrode of the first scan It is connected to the first gate line that supplies the signal SCAN1 , one of the first electrode and the second electrode is connected to the third node N3 and the other is connected to the initialization voltage line.

The fifth switching transistor T5 is for supplying the data voltage Vdata to the second node N2 by connecting the second node N2 that is the anode electrode of the OLED and the data line supplying the data voltage Vdata. , the gate electrode is connected to a second gate line that supplies the second scan signal SCAN2 , one of the first electrode and the second electrode is connected to the second node N2 and the other is connected to the data line .

The driving transistor DT is used to generate a current for emitting an OLED corresponding to the data voltage Vdata, a gate electrode is connected to the first node N1, and any one of the first electrode and the second electrode is The third node is connected to the node N3 and the other is connected to the fourth node N4.

The OLED emits light according to the current generated by the driving transistor DT. The anode electrode is connected to the second node N2 and the cathode electrode is connected to the second power line supplying the low potential power voltage VSS.

The first storage capacitor Cst1 stores the threshold voltage Vth of the driving transistor DT and reflects the data voltage Vdata to the first node N1 that is the gate electrode of the driving transistor DT. It is connected between the first node N1 and the second node N2.

The second storage capacitor Cst2 is connected between the fourth node N4 and the first power line supplying the pixel driving voltage VDD, and is connected in series with the first storage capacitor Cst1 to obtain the data voltage Vdata. is distributed to be applied to the first node N1, which is the gate electrode of the driving transistor DT.

FIG. 3 shows signals related to driving of the pixel circuit of FIG. 2 . The pixel circuit of FIG. 2 is controlled by first and second scan signals SCAN1 and SCAN2 and a light emission signal EM.

The driving circuit drives the pixel circuit of FIG. 2 by dividing one frame into an initialization period t1, a sensing period t2, a data writing period t3, and a light emission period t3.

The initialization period t1 is a time for initializing major components of the pixel to receive the data voltage Vdata of the current frame while the OLED of the pixel is emitting light with the data voltage Vdata of the previous frame.

In the initialization period t1 , the light emission signal EM maintains the gate high voltage VGH, which is the gate-on voltage, and the first scan signal SCAN1 is the gate-on voltage from the gate-off voltage VGL. is changed to the gate high voltage VGH, and the second scan signal SCAN2 maintains the gate low voltage VGL, which is the gate-off voltage.

Accordingly, the first and second switching transistors T1 and T2 maintain the turn-on state, and the third and fourth switching transistors T3 and T4 are turned from the turn-off state to the turn-on state, and the first and second switching transistors T1 and T2 are turned on. 5 The switching transistor T5 maintains a turned-off state.

In the sensing period t2 , the emission signal EM changes from the gate high voltage VGH, which is the gate-on voltage, to the gate low voltage VGL, which is the gate-off voltage, and the first scan signal SCAN1 is the gate-on voltage. The high voltage VGH is maintained, and the second scan signal SCAN2 maintains the gate low voltage VGL, which is the gate-off voltage.

Accordingly, the first and second switching transistors T1 and T2 change from the turn-on state to the turn-off state, and the third and fourth switching transistors T3 and T4 maintain the turn-on state, and 5 The switching transistor T5 maintains a turned-off state.

In the data writing period t3 , the emission signal EM maintains the gate low voltage VGL, which is the gate-gate-off voltage, and the first scan signal SCAN1 maintains the gate-high voltage VGH, which is the gate-on voltage, , the second scan signal SCAN2 is changed from a gate low voltage VGL that is a gate-off voltage to a gate high voltage VGH that is a gate-on voltage.

Accordingly, the first and second switching transistors T1 and T2 maintain the turn-off state, the third and fourth switching transistors T3 and T4 maintain the turn-on state, and the fifth switching transistor ( T5) is changed from the turn-off state to the turn-on state.

In the emission period t4 , the emission signal EM is changed from the gate low voltage VGL, which is the gate-gate-off voltage, to the gate-high voltage, VGH, which is the gate-on voltage, and the first scan signal SCAN1 is the gate-on voltage. The gate high voltage VGH is changed to the gate low voltage VGL, which is the gate gate-off voltage, and the second scan signal SCAN2 is changed from the gate high voltage VGH, which is the gate-on voltage, to the gate low voltage VGL, which is the gate-off voltage. is changed to

Accordingly, the first and second switching transistors T1 and T2 are changed from a turn-off state to a turn-on state, and the third and fourth switching transistors T3 and T4 are turned from a turn-on state to a turn-off state. , and the fifth switching transistor T5 is changed from a turn-on state to a turn-off state.

FIG. 4 illustrates an operation of an initialization period for initializing the pixel circuit of FIG. 2 .

In the initialization period t1, the first and second switching transistors T1 and T2 are turned on by the light emission signal EM that is the gate high voltage VGH, and the first scan is changed to the gate high voltage VGH. The third and fourth switching transistors T3 and T4 are turned on by the signal SCAN1, and the fifth switching transistor T5 is turned on by the second scan signal SCAN2 that is the gate low voltage VGL. turns off

The pixel driving voltage VDD is supplied to the first and fourth nodes N1 and N4 by the first and third switching transistors T1 and T3 in the turn-on state, and the fourth and third switching transistors T1 and T3 in the turn-on state. The initialization voltage Vini is supplied to the second and third nodes N2 and N3 by the two transistors T4 and T2.

FIG. 5 illustrates an operation during a sensing period for sensing a threshold voltage of a driving transistor in the pixel circuit of FIG. 2 .

In the sensing period t2, the first and second switching transistors T1 and T2 are turned off by the light emission signal EM changed to the gate low voltage VGL, and the first scan of the gate high voltage VGH The third and fourth switching transistors T3 and T4 are turned on by the signal SCAN1, and the fifth switching transistor T5 is turned on by the second scan signal SCAN2 that is the gate low voltage VGL. turns off

The third node N3 maintains the initialization voltage Vini by the fourth switching transistor T4 in the turned-on state. The driving transistor DT is diode-connected by the third switching transistor T3 in the turned-on state, and the driving transistor DT is turned on, so that a current flows from the fourth node N4 to the third node N3. flowing, the potential of the first node N1 gradually falls from the pixel driving voltage VDD, and is higher than the initialization voltage Vini, which is the potential of the third node N3, by the threshold voltage Vth of the driving transistor DT ( Vini + Vth).

Also, in the sensing period t2 , the second and fifth switching transistors T2 and T5 are turned off to float the second node N2 to maintain the initialization voltage Vini. Accordingly, a potential difference between the first node N1 and the second node N2 that are both electrodes of the first storage capacitor Cst1 becomes the threshold voltage Vth of the driving transistor DT, and thus the first storage capacitor Cst1 ), the threshold voltage Vth of the driving transistor DT is stored.

FIG. 6 illustrates an operation of a data writing period in which a data voltage is written into the pixel circuit of FIG. 2 . The data writing period t3 corresponds to 1H, which is one horizontal period.

In the data writing period t3 , the first and second switching transistors T1 and T2 are maintained to be turned off by the light emitting signal EM that is the gate low voltage VGL, and the first and second switching transistors T1 and T2 are turned off by the second voltage of the gate high voltage VGH. The third and fourth switching transistors T3 and T4 are turned on by the first scan signal SCAN1 and the fifth switching transistor T3 and T4 are turned on by the second scan signal SCAN2 that is changed to the gate high voltage VGH. T5) is turned on.

The third node N3 maintains the initialization voltage Vini by the fourth switching transistor T4 in the turned-on state. However, the data voltage Vdata is supplied by the fifth switching transistor T5 that is changed to the turn-on state so that the second node N2 is changed from the initialization voltage Vini to the data voltage Vdata.

Since the first node N1 and the second node N2 are separated from each other, the potential change of the second node N2, which is one electrode of the first storage capacitor Cst1, is changed to the other side of the first storage capacitor Cst1. It is reflected in the first node N1 which is an electrode.

Since the first storage capacitor Cst1 and the second storage capacitor Cst2 are connected in series, the potential change Vdata-Vini of the second node N2, which is one electrode of the first storage capacitor Cst1, is 1 is reflected in the ratio Cst1/(Cst1+Cst2) to the first node N1, which is the other electrode of the storage capacitor Cst1, so that the potential of the second node N2 is (Vini+Vth)-(Vini-Vdata) It becomes xCst1/(Cst1+Cst2).

FIG. 7 shows the operation of the light emission period in which the OLED emits light in the pixel circuit of FIG. 2 .

In the light emission period t4 , the first and second switching transistors T1 and T2 are turned on by the light emission signal EM changed to the gate high voltage VGH, and the first switching transistors T1 and T2 are turned on to the gate low voltage VGL. The third and fourth switching transistors T3 and T4 are turned off by the scan signal SCAN1 , and the fifth switching transistor T5 is turned off by the second scan signal SCAN2 converted to the gate low voltage VGL turns off

The pixel driving voltage VDD is supplied to the fourth node N4 by the first and second switching transistors T1 and T2 changed to the turn-on state, and the third node N3 is the anode electrode of the OLED. It is connected to the second node N2. At the beginning of the light emission period t4 , the third node N3 temporarily drops from the initialization voltage Vini to the data voltage Vdata that is the potential of the second node N2 .

The potential of the first node N1 that is the gate electrode of the driving transistor DT is (Vini+Vth)-(Vini-Vdata)xCst1/(Cst1+Cst2), and the third node N1 that is the source electrode of the driving transistor DT is The potential of N3 becomes the data voltage Vdata. The potential of the gate electrode of the driving transistor DT is higher than the potential of the source electrode, so that the driving transistor DT is turned on. Accordingly, a current path is formed from the first power line through the first switching transistor T1, the driving transistor DT, and the second switching transistor T2 to the OLED, and the gate electrode ( A current proportional to the voltage difference between N1) and the source electrode N3 flows through the OLED.

The gate-source voltage Vgs of the driving transistor DT is ((Vini+Vth)-(Vini-Vdata)xCst1/(Cst1+Cst2)-Vdata)=((Vini-Vdata)xCst2/(Cst1+Cst2) +Vth) and the driving current I_OLED flowing from the driving transistor DT to emit OLED light is proportional to the square of the gate-source voltage Vgs minus the threshold voltage Vth. can be expressed together.

As shown in Equation 1, since the threshold voltage Vth component of the driving transistor DT is erased in the relational expression of the driving current I_OLED, the threshold voltage is compensated even if the threshold voltage of the driving transistor DT is changed. The OLED may emit light with a current corresponding to the data voltage Vdata input through the data line.

In order to accurately express low grayscale luminance as a duty ratio of the emission signal EM, the emission signal EM is between the gate-on voltage VGH and the gate-off voltage VGL during the emission period t4. to swing at a predetermined duty ratio, the first and second switching transistors T1 and T2 may repeat on/off operations.

FIG. 8 shows that the threshold voltage compensation deviation is improved in a plurality of grayscales. In FIG. 8, the prior art is a result of a pixel circuit sensing a threshold voltage while supplying a data voltage for one horizontal period, and the embodiment is shown in FIG. This is the result of driving the 2-pixel circuit in the driving sequence of FIG.

In the simulation results of FIG. 8, it can be seen that the compensation deviation is reduced regardless of the low gray level or the high gray level compared to the results of the examples of FIGS. 2 and 3 and the prior art, and in particular, it can be seen that the compensation deviation is reduced by 30% or more at the low gray level. can

If a pixel circuit and driving sequence that needs to finish supplying data voltage and sensing threshold voltage within 1 horizontal period are applied to a high-resolution and high-frequency driving model, 1 horizontal period is shortened, making it impossible to properly sense the threshold voltage within 1 horizontal period. Accordingly, the compensation deviation may increase.

On the other hand, in order to sense the threshold voltage of the driving transistor DT in the sensing period t2 as in the pixel circuit of FIG. 2 and the driving sequence of FIG. 3 of this specification, the data voltage is independent of the data voltage at the source electrode of the driving transistor DT. Since the initialization voltage, which is an independent power source, is applied, the length of the sensing period t2 is not limited and the threshold voltage is detected more accurately by using a longer time for detecting the threshold voltage, and compensation deviation can be reduced.

The display device described in the specification may be described as follows.

According to an exemplary embodiment, a display device includes: a display panel including a plurality of pixels; and supplying a first scan signal, a second scan signal, and a light emitting signal through a gate line connected to pixels of each horizontal line of the display panel in synchronization with supplying the data voltage through the data line to drive the display panel. and a driving circuit.

Each pixel includes a driving transistor for generating a current corresponding to the data voltage; a light emitting element emitting light by an electric current; a first switching transistor for supplying a pixel driving voltage to the driving transistor; a second switching transistor for connecting the driving transistor and the light emitting device; a third switching transistor for diode-connecting the driving transistor; a fourth switching transistor for supplying an initialization voltage to the driving transistor; a fifth switching transistor for supplying a data voltage to the anode electrode of the light emitting device; a first storage capacitor for storing a threshold voltage of the driving transistor; and a second storage capacitor connected in series with the first storage capacitor to divide the data voltage.

In an embodiment, the driving circuit may drive a pixel by dividing one frame into an initialization period, a sensing period, a data writing period, and a light emission period.

In an embodiment, the driving circuit may supply an initialization voltage to a source electrode and an anode electrode of the driving transistor and a pixel driving voltage to a gate electrode of the driving transistor in the initialization period.

In one embodiment, the driving circuit, in the initialization period, turns on the first and second switching transistors by the light emission signal, turns on the third and fourth switching transistors according to the first scan signal, and The fifth switching transistor may be turned off by the second scan signal.

In an embodiment, the driving circuit may charge the gate electrode of the driving transistor to the initialization voltage and the threshold voltage during the sensing period.

In one embodiment, the driving circuit, in the sensing period, turns off the first and second switching transistors by the light emission signal, turns on the third and fourth switching transistors by the first scan signal, and The fifth switching transistor may be turned off by the second scan signal.

In an embodiment, the driving circuit may supply a data voltage to the anode electrode in the data writing period, distribute the voltage change of the anode electrode to the first and second storage capacitors connected in series, and reflect it on the gate electrode of the driving transistor. have.

In one embodiment, the driving circuit turns off the first and second switching transistors by the light emitting signal and turns on the third and fourth switching transistors by the first scan signal in the data writing period; The fifth switching transistor may be turned on by the second scan signal.

In an embodiment, the driving circuit may form a current path connecting the driving element from a power line supplying the pixel driving voltage to the driving transistor through the driving transistor during the light emission period, and the light emitting element may emit light with a current corresponding to the data voltage. .

In an embodiment, the driving circuit turns on the first and second switching transistors according to the light emission signal and turns off the third and fourth switching transistors according to the first scan signal in the light emission period, The fifth switching transistor may be turned off by the second scan signal.

In an embodiment, the driving circuit may cause the light emitting signal to swing at a predetermined duty ratio between the gate-on voltage and the gate-off voltage during the light emission period.

In an embodiment, the driving transistor may have a gate electrode connected to a first node, a first electrode connected to a third node, and a second electrode connected to a fourth node.

In the first switching transistor, a gate electrode may receive a light emitting signal, one of the first electrode and the second electrode may receive a pixel driving voltage, and the other may be connected to the fourth node.

In the second switching transistor, a gate electrode may receive a light emitting signal, one of the first electrode and the second electrode may be connected to the third node and the other one may be connected to the anode electrode.

In the third switching transistor, a gate electrode may receive the first scan signal, one of the first electrode and the second electrode may be connected to the first node, and the other one may be connected to the fourth node.

In the fourth switching transistor, the gate electrode may receive the first scan signal, one of the first electrode and the second electrode may be connected to the third node, and the other may receive the initialization voltage.

In the fifth switching transistor, a gate electrode may receive the second scan signal, one of the first electrode and the second electrode may be connected to the anode electrode, and the other may receive the data voltage.

The first storage capacitor may be connected between the first node and the anode electrode, and the second storage capacitor may have one of the first electrode and the second electrode connected to the first node and the other receiving the pixel driving voltage.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: data line 15: gate line
16: power generation unit

Claims (12)

a display panel including a plurality of pixels; and
In synchronization with supplying the data voltage through the data line, the display panel is driven by supplying the first scan signal, the second scan signal, and the emission signal through the gate line connected to the pixels of each horizontal line of the display panel. Consists of a driving circuit that
Each pixel is
a driving transistor for generating a current corresponding to the data voltage;
a light emitting device that emits light by the current;
a first switching transistor for supplying a pixel driving voltage to the driving transistor;
a second switching transistor for connecting the driving transistor and the light emitting device;
a third switching transistor for diode-connecting the driving transistor;
a fourth switching transistor for supplying an initialization voltage to the driving transistor;
a fifth switching transistor for supplying the data voltage to the anode electrode of the light emitting device;
a first storage capacitor for storing a threshold voltage of the driving transistor; and
and a second storage capacitor connected in series with the first storage capacitor to divide the data voltage. According to claim 1,
and the driving circuit divides one frame into an initialization period, a sensing period, a data writing period, and a light emission period to drive the pixel. 3. The method of claim 2,
and the driving circuit supplies the initialization voltage to the source electrode and the anode electrode of the driving transistor and the pixel driving voltage to the gate electrode of the driving transistor in the initialization period. 4. The method of claim 3,
the driving circuit, in the initialization period, turns on the first and second switching transistors by the light emitting signal and turns on the third and fourth switching transistors by the first scan signal, and turning off the fifth switching transistor by the second scan signal. 4. The method of claim 3,
and the driving circuit charges the gate electrode of the driving transistor to the initialization voltage and the threshold voltage during the sensing period. 6. The method of claim 5,
The driving circuit, in the sensing period, turns off the first and second switching transistors by the light emission signal and turns on the third and fourth switching transistors by the first scan signal, and turning off the fifth switching transistor by the second scan signal. 6. The method of claim 5,
In the data writing period, the driving circuit supplies the data voltage to the anode electrode and distributes the voltage change of the anode electrode to the first and second storage capacitors connected in series to the gate electrode of the driving transistor. A display device, characterized in that it reflects. 8. The method of claim 7,
In the data writing period, the driving circuit turns off the first and second switching transistors by the light emitting signal and turns on the third and fourth switching transistors by the first scan signal, and turning on the fifth switching transistor according to the second scan signal. 8. The method of claim 7,
The driving circuit is configured to form a current path connecting the driving element from a power line supplying the pixel driving voltage to the driving transistor through the driving transistor during the light emission period to emit light from the light emitting element with a current corresponding to the data voltage. A display device, characterized in that. 10. The method of claim 9,
the driving circuit turns on the first and second switching transistors by the light emission signal during the light emission period and turns off the third and fourth switching transistors according to the first scan signal; and turning off the fifth switching transistor by the second scan signal. 3. The method of claim 2,
and the driving circuit causes the light emission signal to swing at a predetermined duty ratio between the gate-on voltage and the gate-off voltage during the light emission period. According to claim 1,
In the driving transistor, the gate electrode is connected to a first node, a first electrode is connected to a third node, and a second electrode is connected to a fourth node,
In the first switching transistor, a gate electrode receives the light emitting signal, one of the first electrode and the second electrode receives the pixel driving voltage, and the other is connected to the fourth node;
In the second switching transistor, a gate electrode receives the light emitting signal, one of a first electrode and a second electrode is connected to the third node and the other is connected to the anode electrode;
In the third switching transistor, a gate electrode receives the first scan signal, one of a first electrode and a second electrode is connected to the first node and the other is connected to the fourth node,
In the fourth switching transistor, a gate electrode receives the first scan signal, one of a first electrode and a second electrode is connected to the third node and the other receives the initialization voltage;
In the fifth switching transistor, a gate electrode receives the second scan signal, one of a first electrode and a second electrode is connected to the anode electrode and the other receives the data voltage;
the first storage capacitor is connected between the first node and the anode electrode;
and the second storage capacitor, wherein one of the first electrode and the second electrode is connected to the first node and the other receives the pixel driving voltage.

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