KR20240010736A - Pixel circuit and electroluminescent display using the same - Google Patents

Abstract

The present invention relates to a pixel circuit and an electroluminescence display device using the same, which drives only the first driving element among the first and second driving elements in a first luminance range up to a preset peak luminance, and drives only the first driving element than the peak luminance. The first and second driving elements are driven in a second high luminance range to increase the amount of current flowing to the light emitting element.

Description

Pixel circuit and electroluminescent display device using the same {PIXEL CIRCUIT AND ELECTROLUMINESCENT DISPLAY USING THE SAME}

The present invention relates to a pixel circuit capable of high dynamic range (hereinafter “HDR”) operation and an electroluminescent display device using the same.

Electroluminescent displays are roughly divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness, and viewing angle. There is an advantage.

The pixels of an organic light emitting display device include an OLED and a driving element that drives the OLED by supplying current to the OLED according to a gate-source voltage. An OLED organic light emitting display device includes an anode and a cathode, and an organic compound layer formed between the electrodes. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL). When current flows through the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emitting layer (EML) to form excitons, and as a result, the emitting layer (EML) generates visible light. .

In order to increase the luminance of pixels in an organic light emitting display device, the driving current of the pixel can be increased by increasing the channel width of the transistor used as a driving element in the pixel. However, this method increases not only the luminance of high gray levels but also the luminance of low gray levels, which may reduce the expressiveness of low gray levels. This method has limitations in improving the dynamic range of pixels and may reduce low gray level expression.

The present invention provides a pixel circuit capable of HDR operation by increasing the brightness of high gray levels without increasing the brightness of low gray levels, and an electroluminescent display device using the same.

The pixel circuit of the present invention includes a light-emitting element, first and second driving elements connected to the light-emitting element to supply current to the light-emitting element, and the first and second driving elements in a first luminance range up to a preset peak luminance. It includes a switch circuit that drives only the first driving element among the driving elements and drives the first and second driving elements in a second luminance range higher than the peak luminance to increase the amount of current flowing to the light emitting element.

The electroluminescent display device of the present invention includes a display panel including a plurality of subpixels, and a display panel driving circuit that writes pixel data of an input image to the subpixels.

Each of the subpixels includes the pixel circuit.

The present invention uses a pixel circuit applying current steering to express a normal luminance range up to a predetermined peak luminance without increasing the luminance of low gray levels, and to express high luminance higher than the peak luminance. Therefore, the electroluminescent display device of the present invention can perform HDR operation without reducing low gray level expression.

1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention.
Figure 2 is a circuit diagram showing a pixel circuit according to the first embodiment of the present invention.
FIG. 3 is a waveform diagram showing the driving waveform of the pixel circuit shown in FIG. 2.
Figure 4 is a waveform diagram showing the data voltage applied to the first data line in the normal luminance range.
Figure 5 is a waveform diagram showing data voltages applied to the first and second data lines in a high brightness range.
FIG. 6 is a circuit diagram showing the current flowing into the light emitting device shown in FIG. 2 in the normal luminance range.
FIG. 7 is a circuit diagram showing the current flowing to the light emitting device shown in FIG. 2 in a high brightness range.
Figure 8 is a circuit diagram showing a pixel circuit according to a second embodiment of the present invention.
FIG. 9 is a waveform diagram showing the driving waveform of the pixel circuit shown in FIG. 8.
Figure 10 is a circuit diagram showing a pixel circuit according to a third embodiment of the present invention.
FIG. 11 is a waveform diagram showing the driving waveform of the pixel circuit shown in FIG. 10.
Figure 12 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present invention.
FIG. 13 is a waveform diagram showing the driving waveform of the pixel circuit shown in FIG. 12.
Figure 14 is a diagram showing a gamma curve of a field emission display device according to an embodiment of the present invention.
15 and 16 are diagrams showing low-gray luminance characteristics of a field emission display device according to an embodiment of the present invention.
Figure 17 is a circuit diagram showing the pixel circuit of a comparative example.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. Only the embodiments are intended to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “comprises,” “includes,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two components is described as 'on top', 'on top', 'on the bottom', 'next to ~', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the electroluminescence display device of the present invention, the pixel circuit includes a driving element and a switch element. The driving element and the switch element may be implemented with one or more transistors of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor on the display panel may be implemented as a thin film transistor (TFT). The transistor may be implemented as an oxide transistor with an oxide semiconductor pattern or a low temperature poly-silicon (LTPS) transistor with a semiconductor pattern. A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor (NMOS), because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor (NMOS), the direction of current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor (PMOS), current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal of the transistor used as switch elements swings between the gate on voltage and the gate off voltage. The gate-on voltage is set to the voltage at which the transistor turns on, and the gate-off voltage is set to the voltage at which the transistor turns off. In the case of an n-channel transistor (NMOS), the gate-on voltage can be the gate high voltage (VGH), and the gate-off voltage can be the gate low voltage (VGL), which is lower than the gate high voltage (VGH). there is. In the case of a p-channel transistor (PMOS), the gate-on voltage may be the gate low voltage (VGL) and the gate-off voltage may be the gate high voltage (VGH).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings. In the following embodiments, the electroluminescent display device will be described focusing on an organic light emitting display device including an organic light emitting material, but is not limited thereto.

1 is a diagram showing an electroluminescent display device according to an embodiment of the present invention.

Referring to FIG. 1, an electroluminescent display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The screen of the display panel 100 includes a pixel array (AA) that displays an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 104 crossing the data lines 102, and pixels arranged in a matrix form.

Each pixel may be divided into red subpixel, green subpixel, and blue subpixel to implement color. Each of the pixels may further include a white subpixel. Each of the subpixels 101 includes a pixel circuit to which current steering is applied, as shown in FIGS. 6 and 7 . The present invention proposes a pixel circuit that emits light at a higher luminance than a preset existing electroluminescence display device and is capable of implementing HDR without an increase in luminance of low gray levels. Hereinafter, “pixel” may be interpreted as having the same meaning as subpixel.

The pixel array AA includes a plurality of pixel lines L1 to Ln. Pixel lines L1 to Ln include subpixels 101 arranged in line 1 of the pixel array. Pixels placed in one pixel line share gate lines 104. Subpixels 101 arranged in one pixel line are connected to different data lines 102. Subpixels arranged vertically along the data line direction share the same data line. The display panel driving circuits 110 and 120 write one frame data of the input image to pixels during one frame period. Pixel data of the input image is written to subpixels of 1 pixel line for 1 horizontal period (FIG. 3, 1H). One horizontal period is equal to one frame period divided by the total number of pixel lines in the pixel array. In Figure 3, FR(N) is the Nth (N is a positive integer) frame period, and FR(N+1) is the N+1th frame period.

Touch sensors may be disposed on the display panel 100. Touch input can be sensed using separate touch sensors or sensed through pixels. Touch sensors can be implemented as on-cell type or add-on channel (Add on type) placed on the screen of the display panel or as in-cell type touch sensors built into the pixel array. You can.

The display panel driving circuits 110 and 120 include a data driver 110 and a gate driver 120. A demultiplexer (DEMUX), not shown, may be placed between the data driver 110 and the data lines 102.

The display panel driving circuits 110 and 120 address the pixel lines of the display panel 100 under the control of a timing controller (TCON) 130, write data of the input image to the pixels, and drive the pixels. It emits light. The display panel driving circuits 110 and 120 may further include a touch sensor driving unit for driving touch sensors. The touch sensor driver is omitted in FIG. 1. In a mobile device or wearable device, the data driver 110, timing controller 130, etc. may be integrated into one integrated circuit.

The data driver 110 uses a digital to analog converter (hereinafter referred to as DAC) to convert the digital data of the input image received from the timing controller 130 every frame period into a gamma compensation voltage to produce a data signal. The voltage (hereinafter referred to as “data voltage”) is output. Data voltage is applied to the pixels through data line 102.

The demultiplexer, omitted in the drawing, is disposed between the data driver 110 and the data lines 102 using a plurality of switch elements and distributes the data voltage output from the data driver 110 to the data lines 102. Since one channel of the data driver 110 is distributed to a plurality of data lines by the demultiplexer, the number of data lines 102 can be reduced.

In some embodiments, the data driver 110 may output a gate-on voltage (VGH) and a gate-off voltage (VGL) to be applied to the emission control line through some channels. The data voltage Vdata output from the data driver 110 may be a voltage in the range of 0 to 19 [V]. The gate-on voltage (VGH) may be 28 [V] and the gate-off voltage (VGL) may be -5 [V]. This voltage example is only an example and is subject to change.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed directly on the bezel area of the display panel 100 along with a transistor array in the active area. The gate driver 120 outputs a gate signal to the gate lines 104 under the control of the timing controller 130. The gate signal swings between the gate-on voltage (VGH) and the gate-off voltage (VGL). The gate driver 120 can sequentially supply the signals to the gate lines 104 by shifting the gate signals using a shift register. The gate signal may include first and second scan signals (SCAN, SENSE) and signals of the emission control line.

The timing controller 130 receives digital video data (DATA) of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (DCLK), and a data enable signal (DE). The host system may be any one of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, or wearable device.

The timing controller 130 provides a data timing control signal to control the operation timing of the data driver 110 based on timing signals (Vsync, Hsync, DE) received from the host system, and a switch control to control the operation timing of the demultiplexer. The operation timing of the display panel driver circuits 110 and 120 can be controlled by generating a gate timing control signal for controlling the operation timing of the gate driver 120. The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120. The level shifter converts the low level voltage of the gate timing control signal to the gate low voltage (VGL) and the high level voltage of the gate timing control signal to the gate high voltage (VGH). .

The timing controller 130 analyzes the luminance of each pixel data of the input image and controls the display panel driving circuits 110 and 120 to the normal luminance driving mode when the luminance of the pixel data is below a predetermined peak luminance. The brightness of the subpixel 101 in which pixel data is written can be controlled to be below the peak brightness. In the normal luminance driving mode, the subpixels 100 are driven with luminance ranging from the lowest luminance to a predetermined peak luminance. The timing controller 130 analyzes the brightness of each pixel data of the input image, and when the brightness of the pixel data is higher than the peak brightness, the timing controller 130 controls the display panel driving circuits 110 and 120 to the high brightness driving mode to display the subpixel 101. The brightness can be controlled to a high brightness higher than the peak brightness. In the high brightness driving mode, the subpixels 100 are driven with a luminance ranging from the peak luminance to the maximum luminance of the pixel.

In a preliminary experiment, a grayscale vs. luminance table of pixel data can be established by measuring the luminance of each pixel. When power is applied to the display device of the present invention, the grayscale vs. luminance table stored in the memory may be loaded into the memory within the timing controller 130. The timing controller 130 can determine the luminance of each pixel data by reading the pixel data value of the received input image, that is, the luminance corresponding to the gray level, using the gray level vs. luminance table.

The timing controller 130 may compare the MSB (Most Significant Bit) of the pixel data with a preset luminance reference value to classify the luminance of each pixel into a normal luminance range and a high luminance range. For example, when the pixel data is 8 bit data, if the pixel data is 1110XXXX2 or higher, the luminance of the pixel to which this pixel data is written is in the high luminance range, and if it is lower than 1110XXXX2, the luminance of the pixel to which this pixel data is written is in the normal luminance range. You can. Here, X is LSB (Least Significant Bit) of 0 or 1.

The timing controller 130 may control the display panel driving circuits 110 and 120 by generating a control signal to control the auxiliary driving element (DR2 in FIG. 2) to be turned on in the high brightness range. Due to this additional control signal, a pin may be added to the package of the timing controller 130, and a wire for transmitting the additional control signal may be added between the timing controller 130 and the display panel driving circuits 110 and 120. You can.

Each of the subpixels 100 of the present invention may include two driving elements that drive one light-emitting element. Each of the driving elements may be implemented as a transistor with a metal oxide semiconductor field effect transistor (MOSFET) structure. When the subpixel 101 is driven in the normal luminance range under the control of the timing controller 130, the display panel driving circuits 110 and 120 drive either one of the two driving elements to convert the current flowing through the light emitting element into the normal driving current. Adjust within the range. On the other hand, the display panel driving circuits 110 and 120 drive the two driving elements when the subpixel 100 is driven in the high brightness range under the control of the timing controller 130 to keep the current flowing in the light emitting element within the normal driving current range. By adjusting to a higher current, the subpixel 101 is driven to a high brightness range.

Each driving element of the subpixels 101 must have uniform electrical characteristics among all pixels, but there may be differences between pixels due to process deviation and variation in device characteristics and may change over display driving time. In order to compensate for this deviation in the electrical characteristics of the driving element, an internal compensation method and an external compensation method can be applied to the electroluminescence display device. The internal compensation method samples the threshold voltage (Vth) of the driving element, which changes depending on the electrical characteristics of the driving element, and compensates the data voltage by the threshold voltage (Vth). The external compensation method senses the voltage of a pixel that changes according to the electrical characteristics of the driving device, and modulates the data of the input image in an external circuit based on the sensed voltage to compensate for the difference in the electrical characteristics of the driving device between pixels.

The external compensation method uses a sensing circuit to sense the threshold voltage of the driving element in sensing mode and selects a compensation value according to the deviation or change over time in the threshold voltage between subpixels to compensate for the threshold voltage deviation or change over time of the driving element. You can. Sensing modes can be divided into before and after product shipment.

The sensing circuit includes a reference voltage line (or sensing line, hereinafter referred to as “Vref line”) connected to each of the subpixels 101, a sample and holder that samples the current from the Vref line as a voltage, and a sample & may include an analog to digital convertor (hereinafter referred to as “ADC”) that converts the voltage sampled by the holder into digital data. The timing controller 130 may select a compensation value according to the data received from the ADC, add the selected compensation value to the pixel data, and transmit the pixel data whose threshold voltage of the driving element has been compensated to the data driver 110. The sample & holder of the sensing circuit and the ADC may be integrated within the IC (Integrated Circuit) of the data driver 110.

Hereinafter, the operation of the pixel circuit will be explained focusing on the driving mode for displaying pixel data of the input image. Operations for sensing mode are omitted.

Figure 2 is a circuit diagram showing a pixel circuit according to the first embodiment of the present invention. FIG. 3 is a waveform diagram showing the driving waveform of the pixel circuit shown in FIG. 2.

Referring to Figures 2 and 3, the pixel circuit includes a light emitting element (OLED), driving elements (DT1, DT2), a switch circuit 20, and capacitors (Cst1, Cst2). The driving elements DT1 and DT2 and the switch circuit 20 may be implemented as n-channel transistors in FIG. 3, but are not limited thereto. The light emitting device (OLED) can be implemented as OLED.

The switch circuit 20 drives only the first driving element DT1 in a normal luminance range (NLR) up to a preset peak luminance, and drives the first and second driving elements DT1 and DT1 in a high luminance range (HLR) above the peak luminance. DT2) is simultaneously driven to increase the amount of current flowing to the light emitting device (OLED). The switch circuit 20 may include first to third switch elements S1 to S3.

High-potential supply voltage (EVDD), low-potential supply voltage (EVSS), reference voltage (Vref), and data voltage (Vdata) for each of the pixel circuits. Scan signals (SCAN, SENSE), etc. are supplied. The high-potential power supply voltage (EVDD) can be set to a direct current voltage higher than the low-potential power supply voltage (EVSS) and the reference voltage (Vref). The reference voltage (Vref) may be set to a direct current voltage lower than the high-potential power supply voltage (EVDD) and equal to or higher than the low-potential power supply voltage (EVSS). The low potential supply voltage (EVSS) can be ground voltage (GND) or 0V. The reference voltage (Vref) may be 2V, but is not limited thereto.

A light emitting device (OLED) includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light emitting device (OLED) may be connected to the driving devices (DT) through the first node (n1), and the cathode of the light emitting device (OLED) may be connected to the EVSS electrode 106. A low-potential power supply voltage (EVSS) is applied to the EVSS electrode 106. The first node n1 includes the second electrode of the first driving element DT1, the second electrode of the second driving element DT2, the first electrode of the first capacitor Cst1, and the first electrode of the second capacitor Cst2. 1 electrode, and is connected to the anode of the light emitting device (OLED).

A low potential voltage (VSS) is applied to the cathode of the light emitting device (OLED) through the EVSS electrode 106. The light emitting device (OLED) emits light by current generated according to the gate-source voltage (Vgs) of the driving devices (DT1 and DT2).

Each of the driving elements DT1 and DT2 supplies current generated according to the gate-source voltage Vgs to the light emitting element OLED. The first capacitor Cst1 is connected between the first node n1 and the second node n2. The gate-source voltage (Vgs) of the first driving element (DT1) is charged in the first capacitor (Cst1). The second capacitor Cst2 is connected between the first node n1 and the third node n3. The gate-source voltage (Vgs) of the second driving element (DT2) is charged in the second capacitor (Cst2).

The first driving element DT1 is driven in the normal luminance range (NLR) to supply current to the light emitting element OLED. In the normal luminance range (NLR), the second driving element (DT2) remains in the off state and is not driven. The light emitting device (OLED) emits light with a current flowing through the first driving device (DT1) in the normal luminance range (NLR). The first driving element DT1 is connected to the anode of the light emitting element OLED through a gate connected to the second node n2, a first electrode (or drain) connected to the EVDD line 103, and the first node n1. It includes a connected second electrode (or source). A high potential power supply voltage (EVDD) is applied to the EVDD line (103). The second node n2 is connected to the second electrode of the first switch element S1, the gate of the first driving element DT1, and the second electrode of the first capacitor Cst1.

The second driving element DT2 is an auxiliary driving element that is driven only in the high brightness range (HLR) and increases the amount of current of the light emitting element (OLED). In the high brightness range (HLR), the data voltage (Vdata) is simultaneously applied to the gates of the first and second driving elements (DT2), causing the light emitting element ( OLED) can emit light with high brightness. The second driving element DT2 is connected to the anode of the light emitting element OLED through the gate connected to the third node n3, the first electrode (or drain) connected to the EVDD line 103, and the first node n1. It includes a connected second electrode (or source).

The first switch element (S1) is turned on according to the gate-on voltage (VGH) of the first scan signal (SCAN) and outputs data of the input image in the normal luminance range (NLR) and the high luminance range (HLR). A voltage (Vdata) is supplied to the second node (n2). The data voltage (Vdata) of the input image is the analog voltage of pixel data converted through the DAC of the data driver 110. The gate of the first driving element DT1 is connected to the second node n2. The first switch element S1 includes a gate connected to the first gate line 1041, a first electrode connected to the first data line 1021, and a second electrode connected to the second node n2. The first scan signal SCAN is applied to the first gate line 1041. In FIGS. 2 and 3, “DATA1” represents the voltage of the first data line 1021.

The second switch element (S2) is turned on according to the gate-on voltage (VGH) of the first scan signal (SCAN) in the normal luminance range (NLR) and supplies the black grayscale voltage (Vdata_black) to the third node (n3). do. The black gray level voltage (Vdata_black) is the voltage at the lowest gray level, that is, when the pixel data is 000000002. In the normal luminance range (NLR), a black gray level voltage unrelated to the pixel data of the input image is applied to the second data line 1022 to control the second driving element DT2 to be in an off state.

The second switch element (S2) is turned on according to the gate-on voltage (VGH) of the first scan signal (SCAN) in the high brightness range (HLR) to transmit the data voltage (Vdata) of the input image to the third node (n3). supply. The gate of the second driving element DT2 is connected to the third node n3. The data voltage (Vdata) of the input image is the analog voltage of pixel data converted through the DAC of the data driver 110. In the high brightness range (HLR), the data voltage (Vdata) applied to the second data line 1022 may be the same as the data voltage (Vdata) applied to the first data line 1021, but is not limited thereto. The second switch element S2 includes a gate connected to the first gate line 1041, a first electrode connected to the second data line 1022, and a second electrode connected to the third node n3. In FIGS. 2 and 3, “DATA2” represents the voltage of the second data line 1022.

The third switch element S3 is turned on according to the gate-on voltage VGH of the second scan signal SENSE and supplies the reference voltage Vref to the first node n1. The second scan signal (SENSE) is synchronized with the first scan signal (SCAN). The second scan signal (SENSE) rises and polls simultaneously with the first scan signal (SCAN). The first node n1 is connected to the gates of the driving elements DT1 and DT2 and the first electrodes of the capacitors Cst1 and Cst2. The third switch element S3 includes a gate connected to the second gate line 1042, a first electrode connected to the first node n1, and a second electrode connected to the Vref line 105. The second scan signal SENSE is applied to the second gate line 1042.

Referring to FIG. 3, the high-potential power supply voltage (EVDD), reference voltage (Vref), and low-potential power supply voltage (EVSS) are direct currents that maintain a constant voltage regardless of the normal luminance range (NLR) and high luminance range (HLR). It is voltage.

In the normal luminance range (NLR), the voltage (DATA1) of the first data line 1021 is the data voltage (Vdata) of the input image, and the voltage (DATA2) of the second data line 1022 is unrelated to the pixel data of the input image. One black gray scale voltage (Vdata_black). The first and second scan signals (SCAN, SENSE) are synchronized with the data voltage (Vdata) of the input image. Accordingly, the current generated by the gate-source voltage (Vgs) of the first driving device (DT1) is supplied to the light emitting device (OLED) in the normal luminance range (HLR). At this time, the light emitting device (OLED) emits light by the current (I _OLED ) corresponding to the gray level value of the pixel data. The current (I _OLED ) flowing through the light emitting device (OLED) in the normal luminance range (NLR) is expressed in Equation 1.

Here, μ is the mobility of the first driving element (DT1), Cox is the parasitic capacitance of the first driving element (DT1), W ₁ /L ₁ is the channel ratio of the first driving element (DT1), and Vth is the first driving element (DT1). Indicates the threshold voltage of each device (DT1). W ₁ is the channel width of the first driving element DT1. L ₁ is the channel length of the driving element (DT1).

In the high brightness range (HLR), the data driver 110 supplies the data voltage (Vdata) of the input image to the first data line 1021 and simultaneously supplies the data voltage of the input image to the second data line 102. Here, the data voltage Vdata of the first and second data lines 1021 and 1022 may be set to the same voltage at the same gray level. Additionally, if the channel ratio of the first driving element DT1 and the channel ratio of the second driving element DT2 are different, the data voltage Vdata applied to the second data line 1022 at the same gray level is the first data line 1021. ) may be different from the data voltage applied to ). The first and second scan signals (SCAN, SENSE) are synchronized with the data voltage (Vdata) of the input image. Accordingly, in the high brightness range (HLR), the first and second driving elements (DT1, DT2) supply current generated by the gate-source voltage (Vgs) to the light emitting element (OLED). At this time, the light emitting device (OLED) emits light by the current (I _OLED ) as shown in Equation 2 corresponding to the gray level value of the pixel data. As shown in Equation 2, the current (I _OLED ) increases due to the effect of increasing the channel width (W ₁ , W ₂ ) of the driving elements (DT1, DT2), so that the light emitting element (OLED) can emit light with a high brightness exceeding the peak brightness. there is.

Here, μ is the mobility of the first and second driving elements (DT1, DT2), Cox is the parasitic capacitance of the first and second driving elements (DT1, DT2), and Vth is the mobility of the first and second driving elements (DT1, DT2). Indicates the threshold voltage of DT2), respectively. W ₁ is the channel width of the first driving element DT1, and W ₂ is the channel width of the second driving element DT2. L ₁ is the channel length of the first driving element DT1, and L ₂ is the channel length of the second driving element DT2.

The pixel circuit of the present invention can emit light at a luminance higher than the peak luminance without increasing the luminance of low gray levels by selecting the number of driving elements that supply current to the light emitting elements driven in the normal luminance range (NLR) and the high luminance range (HLR). . As a result, the electroluminescence display device of the present invention is capable of HDR driving without an increase in luminance at low frequencies.

Figure 4 is a waveform diagram showing the data voltage applied to the first data line in the normal luminance range (NLR). Figure 5 is a waveform diagram showing data voltages applied to the first and second data lines in the high brightness range (HLR). As shown in FIG. 4, the pixel circuit of the present invention emits light with a current from the first driving element DT1 in the normal luminance range (NLR) from the lowest luminance (or black gray level luminance) to the peak luminance (Lp). The luminance of the device (OLED) can express low and medium gray levels of pixel data. There is no increase in luminance of low gray levels, including black levels, in the normal luminance range (NLR). Peak luminance (Lp) may be set to 500 [nit], but is not limited to this. As shown in FIG. 5, the pixel circuit of the present invention uses current from the first and second driving elements DT1 and DT2 in a high luminance range (HLR) that is higher than the peak luminance (Lp) and up to the maximum luminance (Lhdr). High grayscale of pixel data is expressed with the luminance of the light-emitting device (OLED). The maximum gray level (Lhdr) can be set to 1,300 [nit], but is not limited to this.

FIG. 6 is a circuit diagram showing the current (I _OLED ) flowing into the light emitting device (OLED) shown in FIG. 2 in the normal luminance range (NLR). In FIG. 6 , the current (I _OLED ) of the light emitting device (OLED) is substantially equal to the drain-source current (Ids1) of the first driving device (DT1). FIG. 7 is a circuit diagram showing the current (I _OLED ) flowing into the light emitting device (OLED) shown in FIG. 2 in the high brightness range (HLR). In FIG. 7, the current (I _OLED ) of the light emitting device (OLED) is substantially the drain-source current (Ids1) of the first driving device (DT1) and the drain-source current (Ids2) of the second driving device (DT2). is equal to the sum of In FIGS. 6 and 7 , arrows indicate current (I _OLED ) flowing into the light emitting device (OLED).

Figure 8 is a circuit diagram showing a pixel circuit according to a second embodiment of the present invention. FIG. 9 is a waveform diagram showing the driving waveform of the pixel circuit shown in FIG. 8.

Referring to Figures 8 and 9, the pixel circuit includes a light emitting element (OLED), driving elements (DT1, DT2), a switch circuit 20, and capacitors (Cst, Cem). The driving elements DT1 and DT2 and the switch circuit 20 may be implemented as n-channel transistors in FIG. 8, but are not limited thereto. The light emitting device (OLED) can be implemented as OLED.

The switch circuit 20 drives only the first driving element (DT1) in a normal luminance range (NLR) up to a preset peak luminance (Lp), and drives the first and second driving elements (DT1) in a high luminance range (HLR) higher than the peak luminance (Lp). 2 driving elements (DT1, DT2) are driven simultaneously to increase the amount of current flowing to the light emitting element (OLED). The switch circuit 20 may include first to fourth switch elements S1 to S4.

The anode of the light emitting device (OLED) may be connected to the driving devices (DT) through the first node (n1), and the cathode of the light emitting device (OLED) may be connected to the EVSS electrode 106. A low-potential power supply voltage (EVSS) is applied to the EVSS electrode 106. The first node (n1) is connected to the second electrode of the first driving element (DT1), the second electrode of the second driving element (DT2), the first electrode of the third switch element (S3), and the first capacitor (Cst). It is connected to the first electrode and the anode of the light emitting device (OLED).

A low potential voltage (VSS) is applied to the cathode of the light emitting device (OLED) through the EVSS electrode 106. The light emitting device (OLED) emits light by current generated according to the gate-source voltage (Vgs) of the driving devices (DT1 and DT2).

Each of the driving elements DT1 and DT2 supplies current generated according to the gate-source voltage Vgs to the light emitting element OLED. The first capacitor Cst is connected between the first node n1 and the second node n2. The gate-source voltage (Vgs) of the driving elements (DT1 and DT2) is charged in the first capacitor (Cst). The second capacitor (Cem) is connected between the EVDD line 103 and the third node (n3). The second capacitor (Cem) holds the voltage of the third node (n3) while the second switch element (S2) is turned on for a short time and then remains off for one frame period, thereby turning the third node (S2) on. n3) suppresses unwanted voltage fluctuations.

Gates of the first and second driving elements DT1 and DT2 are commonly connected to the second node n2. The first driving element DT1 is driven in the normal luminance range (NLR) to supply current to the light emitting element OLED. In the normal luminance range (NLR), the current path between the second driving element (DT2) and the EVDD line 103 is blocked by the fourth switch element (S4), so that the second driving element (DT2) is not driven. No. The light emitting device (OLED) emits light with a current flowing through the first driving device (DT1) in the normal luminance range (NLR). The first driving element DT1 includes a gate connected to the second node n2, a first electrode connected to the EVDD line 103, and a second electrode connected to the first node n1.

The second driving element DT2 is an auxiliary driving element that is driven only in the high brightness range (HLR) and increases the amount of current of the light emitting element (OLED). In the high brightness range (HLR), the data voltage (Vdata) is simultaneously applied to the gates of the first and second driving elements (DT2), causing the light emitting element ( OLED) can emit light with high brightness. The second driving element DT2 includes a gate connected to the second node n2, a first electrode connected to the second electrode of the fourth switch element S4, and a second electrode connected to the first node n1. .

The first switch element (S1) is turned on according to the gate-on voltage (VGH) of the first scan signal (SCAN) to change the data voltage (Vdata) of the input image in the normal luminance range (NLR) and the high luminance range (HLR). It is supplied to the second node (n2). The first switch element S1 includes a gate connected to the first gate line 1041, a first electrode connected to the data line 1023, and a second electrode connected to the second node n2. The first scan signal SCAN is applied to the first gate line 1041. In FIGS. 8 and 9, “DATA” represents the voltage of the data line 1023.

The second switch element (S2) is turned on according to the gate-on voltage (VGH) of the first scan signal (SCAN) in the normal luminance range (NLR) and supplies the gate-off voltage (VGL) to the third node (n3). do. The gate-off voltage VGL is set to a voltage at which the second driving element DT2 turns off and is applied to the light emission control line 1024. When the voltage of the third node (n3) is lowered to the gate-off voltage (VGL), the fourth switch element (S4) is turned off and the gap between the EVDD line 103 and the first electrode of the second driving element (DT2) is turned off. Since the current path is blocked, current cannot be generated through the second driving element DT2. In FIGS. 8 and 9, “EMCTRL” represents the voltage of the emission control line 1024.

The second switch element (S2) is turned on according to the gate-on voltage (VGH) of the first scan signal (SCAN) in the high brightness range (HLR) and supplies the gate-on voltage (VGH) to the third node (n3). . When the voltage of the third node (n3) increases to the gate-on voltage (VGH), the fourth switch element (S4) is turned on and connects the EVDD line 103 to the first electrode of the second driving element (DT2). do. The second driving element (DT2) is turned on according to the gate-on voltage (VGH) applied to its gate through the second switch element (S2) in the high brightness range (HLR), and the amount of current flowing to the light emitting element (OLED) increases. The second switch element S2 includes a gate connected to the first gate line 1041, a first electrode connected to the emission control line 1024, and a second electrode connected to the third node n3.

The emission control line 1024 may be formed as a wire in a direction parallel to the data line 1023. Some channels in the IC of the data driver 110 may be connected to the emission control line 1024. The data driver 110 supplies a gate-off voltage (VGL) to the light emission control line 1024 under the control of the timing controller 130 in the normal brightness driving mode, and provides a gate-on voltage to the light emission control line 1024 in the high brightness driving mode. (VGH) can be supplied.

The third switch element S3 is turned on according to the gate-on voltage VGH of the second scan signal SENSE and supplies the reference voltage Vref to the first node n1. The second scan signal (SENSE) is synchronized with the first scan signal (SCAN). The second scan signal SENSE is applied to the second gate line 1042. The third switch element S3 includes a gate connected to the second gate line 1042, a first electrode connected to the first node n1, and a second electrode connected to the Vref line 105.

The fourth switch element S4 is turned off according to the gate-on voltage (VGH) of the third node (n2) in the normal luminance mode (NLR), while the gate of the third node (n2) in the high luminance mode (HLR) is turned off. It turns on according to the on voltage (VGH). The fourth switch element S4 includes a gate connected to the third node n3, a first electrode connected to the EVDD line 103, and a second electrode connected to the first electrode of the second driving element DT2.

Referring to FIG. 9, the high-potential power supply voltage (EVDD), reference voltage (Vref), and low-potential power supply voltage (EVSS) are direct currents that maintain a constant voltage regardless of the normal luminance range (NLR) and high luminance range (HLR). It is voltage.

In the normal luminance range (NLR) and high luminance range (HLR), the voltage (DATA) of the data line 1023 is the data voltage (Vdata) of the input image. The first and second scan signals (SCAN, SENSE) are synchronized with the data voltage (Vdata) of the input image.

In the normal luminance range (NLR), the voltage (EMCTRL) of the emission control line 1024 is the gate-off voltage (VGL). Accordingly, in the normal luminance range (NLR), the fourth switch element (S4) is turned off and the current path between the second driving element (DT2) and the EVDD line 103 is blocked. In the normal luminance range (NLR), the current (IOLED) of Equation 1 generated by the gate-source voltage (Vgs) only in the first driving device (DT1) flows to the light emitting device (OLED).

In the high brightness range (HLR), the voltage (EMCTRL) of the emission control line 1024 changes to the gate-on voltage (VGH). Accordingly, in the high brightness range (HLR), the fourth switch element (S4) is turned on to form a current path between the second driving element (DT2) and the EVDD line 103. In the high brightness range (HLR), the current (IOLED) of Equation 2 generated by the gate-source voltage (Vgs) of the first and second driving elements (DT1 and DT2) flows to the light emitting element (OLED).

Figure 10 is a circuit diagram showing a pixel circuit according to a third embodiment of the present invention. FIG. 11 is a waveform diagram showing the driving waveform of the pixel circuit shown in FIG. 10.

10 and 11, the pixel circuit includes a light emitting element (OLED), driving elements (DT1 and DT2), a switch circuit 20, and a capacitor (Cst). The driving elements DT1 and DT2 and the switch circuit 20 may be implemented as n-channel transistors in FIG. 10, but are not limited thereto. The light emitting device (OLED) can be implemented as OLED.

The switch circuit 20 drives only the first driving element (DT1) in a normal luminance range (NLR) up to a preset peak luminance (Lp), and drives the first and second driving elements (DT1) in a high luminance range (HLR) higher than the peak luminance (Lp). 2 driving elements (DT1, DT2) are driven simultaneously to increase the amount of current flowing to the light emitting element (OLED). The switch circuit 20 may include first to third switch elements S11 to S13.

The anode of the light emitting device (OLED) may be connected to the driving devices (DT) through the first node (n1), and the cathode of the light emitting device (OLED) may be connected to the EVSS electrode 106. The light emitting device (OLED) emits light by current generated according to the gate-source voltage (Vgs) of the driving devices (DT1 and DT2).

Each of the driving elements DT1 and DT2 supplies current generated according to the gate-source voltage Vgs to the light emitting element OLED. The capacitor Cst is connected between the first node n1 and the second node n2. The capacitor Cst is charged with the gate-source voltage Vgs of the driving elements DT1 and DT2.

Gates of the first and second driving elements DT1 and DT2 are commonly connected to the second node n2. The first driving element DT1 is driven in the normal luminance range (NLR) to supply current to the light emitting element OLED. In the normal luminance range (NLR), the current path between the second driving element (DT2) and the EVDD line 103 is blocked by the third switch element (S13), so that the second driving element (DT2) is not driven. The light emitting device (OLED) emits light with a current flowing through the first driving device (DT1) in the normal luminance range (NLR). The first driving element DT1 includes a gate connected to the second node n2, a first electrode connected to the EVDD line 103, and a second electrode connected to the first node n1.

The second driving element DT2 is an auxiliary driving element that is driven only in the high brightness range (HLR) and increases the amount of current of the light emitting element (OLED). In the high brightness range (HLR), the data voltage (Vdata) is simultaneously applied to the gates of the first and second driving elements (DT2), causing the light emitting element ( OLED) can emit light with high brightness. The second driving element DT2 includes a gate connected to the second node n2, a first electrode connected to the second electrode of the third switch element S13, and a second electrode connected to the first node n1. .

The first switch element (S11) is turned on according to the gate-on voltage (VGH) of the first scan signal (SCAN) to change the data voltage (Vdata) of the input image in the normal luminance range (NLR) and the high luminance range (HLR). It is supplied to the second node (n2). The first switch element S11 includes a gate connected to the first gate line 1041, a first electrode connected to the data line 1023, and a second electrode connected to the second node n2. The first scan signal SCAN is applied to the first gate line 1041. In FIGS. 10 and 11, “DATA” represents the voltage of the data line 1023.

The second switch element S12 is turned on according to the gate-on voltage VGH of the second scan signal SENSE and supplies the reference voltage Vref to the first node n1. The second scan signal SENSE is applied to the second gate line 1042. The second scan signal (SENSE) is synchronized with the first scan signal (SCAN). The second switch element S12 includes a gate connected to the second gate line 1042, a first electrode connected to the first node n1, and a second electrode connected to the Vref line 105.

The third switch element S13 is turned off according to the gate-off voltage (VGL) on the light emission control line 1043 in the normal luminance range (NLR) to increase the current between the EVDD line 103 and the second driving element DT2. Block the pass. If the current path between the EVDD line 103 and the first electrode of the second driving element DT2 is blocked, current cannot be generated through the second driving element DT2. 10 and 11, “EMCTRL” represents the voltage of the emission control line 1043. The emission control line 1043 is formed in a direction parallel to the gate lines 1041 and 1041.

The third switch element S13 is turned on according to the gate-on voltage (VGH) on the light emission control line 1043 in the high brightness range (HLR) to connect the EVDD line 103 to the first electrode of the second driving element DT2. Connect to When the current path between the EVDD line 103 and the first electrode of the second driving element DT2 is connected, the second driving element DT2 transmits its own power through the second switch element S2 in the high brightness range (HLR). It turns on according to the gate-on voltage (VGH) applied to the gate, increasing the amount of current flowing to the light emitting device (OLED). The third switch element S13 includes a gate connected to the emission control line 1043, a first electrode connected to the EVDD line 103, and a second electrode connected to the first electrode of the second driving element DT2.

The gate driver 120 supplies a gate-off voltage (VGL) to the emission control line 1043 under the control of the timing controller 130 in the normal luminance driving mode. The gate driver 120 supplies the gate-on voltage (VGH) to the emission control line 1043 under the control of the timing controller 130 in the high-brightness driving mode.

Referring to FIG. 11, the high-potential power supply voltage (EVDD), reference voltage (Vref), and low-potential power supply voltage (EVSS) are direct current voltages that maintain a constant voltage regardless of the normal luminance range (NLR) and high luminance range (HLR). It is voltage.

In the normal luminance range (NLR) and high luminance range (HLR), the voltage (DATA) of the data line 1023 is the data voltage (Vdata) of the input image. The first and second scan signals (SCAN, SENSE) are synchronized with the data voltage (Vdata) of the input image.

In the normal luminance range (NLR), the voltage (EMCTRL) of the emission control line 1043 is the gate-off voltage (VGL). Accordingly, in the normal luminance range (NLR), the third switch element (S13) is turned off and the current path between the second driving element (DT2) and the EVDD line 103 is blocked. In the normal luminance range (NLR), only the first driving element (DT1) supplies the current (I _OLED ) equal to Equation 1 to the light emitting element (OLED).

In the high brightness range (HLR), the voltage (EMCTRL) of the emission control line 1043 changes to the gate-on voltage (VGH). Accordingly, in the high brightness range (HLR), the third switch element (S13) is turned on to form a current path between the first electrode of the second driving element (DT2) and the EVDD line 103. In the high brightness range (HLR), the first and second driving elements (DT1, DT2) supply the current (I _OLED ) as shown in Equation 2 to the light emitting element (OLED).

Figure 12 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present invention. FIG. 13 is a waveform diagram showing the driving waveform of the pixel circuit shown in FIG. 12.

Referring to Figures 12 and 13, the pixel circuit includes a light emitting element (OLED), driving elements (DT1, DT2), a switch circuit 20, and a capacitor (Cst). The driving elements DT1 and DT2 and the switch circuit 20 may be implemented as n-channel transistors in FIG. 12, but are not limited thereto. The light emitting device (OLED) can be implemented as OLED.

The switch circuit 20 drives only the first driving element (DT1) in a normal luminance range (NLR) up to a preset peak luminance (Lp), and drives the first and second driving elements (DT1) in a high luminance range (HLR) higher than the peak luminance (Lp). 2 driving elements (DT1, DT2) are driven simultaneously to increase the amount of current flowing to the light emitting element (OLED). The switch circuit 20 may include first to fourth switch elements S11, S22 to S24.

The anode of the light emitting device (OLED) may be connected to the driving devices (DT) through the first node (n1), and the cathode of the light emitting device (OLED) may be connected to the EVSS electrode 106. The light emitting device (OLED) emits light by current generated according to the gate-source voltage (Vgs) of the driving devices (DT1 and DT2).

Each of the driving elements DT1 and DT2 supplies current generated according to the gate-source voltage Vgs to the light emitting element OLED. The capacitor Cst is connected between the first node n1 and the second node n2. The capacitor Cst is charged with the gate-source voltage Vgs of the driving elements DT1 and DT2.

Gates of the first and second driving elements DT1 and DT2 are commonly connected to the second node n2. The first driving element DT1 is driven in the normal luminance range (NLR) to supply current to the light emitting element OLED. In the normal luminance range (NLR), the current path between the second driving element (DT2) and the EVDD line 103 is blocked by the fourth switch element (S24), so that the second driving element (DT2) is not driven. The light emitting device (OLED) emits light with a current flowing through the first driving device (DT1) in the normal luminance range (NLR). The first driving element DT1 includes a gate connected to the second node n2, a first electrode connected to the EVDD line 103, and a second electrode connected to the first node n1.

The second driving element DT2 is an auxiliary driving element that is driven only in the high brightness range (HLR) and increases the amount of current of the light emitting element (OLED). In the high brightness range (HLR), the data voltage (Vdata) is simultaneously applied to the gates of the first and second driving elements (DT2), causing the light emitting element ( OLED) can emit light with high brightness. The second driving element DT2 includes a gate connected to the second node n2, a first electrode connected to the second electrode of the fourth switch element S24, and a second electrode connected to the first node n1. .

The first switch element (S11) is turned on according to the gate-on voltage (VGH) of the first scan signal (SCAN) to change the data voltage (Vdata) of the input image in the normal luminance range (NLR) and the high luminance range (HLR). It is supplied to the second node (n2). The first switch element S11 includes a gate connected to the first gate line 1041, a first electrode connected to the data line 1023, and a second electrode connected to the second node n2. The first scan signal SCAN is applied to the first gate line 1041. In FIGS. 12 and 13, “DATA” represents the voltage of the data line 1023.

The second switch element (S22) is turned off according to the gate-off voltage (VGL) on the second light emission control line 1043 in the normal luminance range (NLR) to turn off the first light emission control line 1024 and the third node (n3). ) blocks the current pass between the When the current path between the first light emission control line 1024 and the third node n3 is blocked, the fourth switch element S24 is turned off. When the fourth switch element (S24) is in the off state, the current path between the EVDD line 103 and the first electrode of the second driving element (DT2) is blocked, so that a current may be generated through the second driving element (DT2). I can't. In FIGS. 12 and 13, “EMCTRL1” represents the voltage of the first emission control line 1024. “EMCTRL2” represents the voltage of the second emission control line 1043. The first emission control line 1024 is formed in a direction parallel to the data line 1023. The second emission control line 1043 is formed in a direction parallel to the gate lines 1041 and 1041 . Accordingly, the first emission control line 1024 and the second emission control line 1043 intersect.

The second switch element (S22) is turned on in accordance with the gate-on voltage (VGH) on the second light emission control line 1043 in the high brightness range (HLR) and turns on the gate-on voltage (VGH) from the first light emission control line 1024. ) is supplied to the third node (n3). The fourth switch element (S24) is turned on according to the gate-on voltage (VGH) from the first light emission control line 1024 to generate a current between the EVDD line 103 and the first electrode of the second driving element (DT2). Form a pass. The second driving element DT2 may generate current when connected to the EVDD line through the fourth switch element S24. In the high brightness range (HLR), the second driving element (DT2) is turned on according to the gate-on voltage (VGH) applied to its gate through the second switch element (S22) and the amount of current flowing to the light emitting element (OLED) increases.

The second switch element S22 includes a gate connected to the second emission control line 1043, a first electrode connected to the first emission control line 1024, and a second electrode connected to the third node n3. The fourth switch element S24 includes a gate connected to the third node n3, a first electrode connected to the EVDD line 103, and a second electrode connected to the first electrode of the second driving element DT2.

The data driver 110 supplies the gate-off voltage (VGL) to the first emission control line 1024 under the control of the timing controller 130 in the normal luminance driving mode. The data driver 110 supplies the gate-on voltage (VGH) to the first emission control line 1024 under the control of the timing controller 130 in the high brightness driving mode. The gate driver 120 supplies the gate-off voltage (VGL) to the second emission control line 1043 under the control of the timing controller 130 in the normal luminance driving mode. The gate driver 120 supplies the gate-on voltage (VGH) to the second emission control line 1043 under the control of the timing controller 130 in the high-brightness driving mode.

The third switch element S23 is turned on according to the gate-on voltage VGH of the second scan signal SENSE and supplies the reference voltage Vref to the first node n1. The second scan signal SENSE is applied to the second gate line 1042. The second scan signal (SENSE) is synchronized with the first scan signal (SCAN). The third switch element S23 includes a gate connected to the second gate line 1042, a first electrode connected to the first node n1, and a second electrode connected to the Vref line 105.

Referring to FIG. 13, the high-potential power supply voltage (EVDD), reference voltage (Vref), and low-potential power supply voltage (EVSS) are direct current voltages that maintain a constant voltage regardless of the normal luminance range (NLR) and high luminance range (HLR). It is voltage.

In the normal luminance range (NLR) and high luminance range (HLR), the voltage (DATA) of the data line 1023 is the data voltage (Vdata) of the input image. The first and second scan signals (SCAN, SENSE) are synchronized with the data voltage (Vdata) of the input image.

In the normal luminance range (NLR), the voltage (EMCTRL) of the first and second emission control lines (1024, 1043) is the gate-off voltage (VGL). Accordingly, in the normal luminance range (NLR), the second and fourth switch elements (S22, S24) are turned off and the current path between the second driving element (DT2) and the EVDD line 103 is blocked. In the normal luminance range (NLR), only the first driving element (DT1) supplies the current (I _OLED ) equal to Equation 1 to the light emitting element (OLED).

In the high brightness range (HLR), the voltage (EMCTRL) of the first and second emission control lines (1024, 1043) changes to the gate-on voltage (VGH). Accordingly, in the high brightness range (HLR), the second and fourth switch elements (S22, S24) are turned on to form a current path between the first electrode of the second driving element (DT2) and the EVDD line 103. . In the high brightness range (HLR), the first and second driving elements (DT1, DT2) supply the current (I _OLED ) as shown in Equation 2 to the light emitting element (OLED).

Figure 14 is a diagram showing a gamma curve of a field emission display device according to an embodiment of the present invention.

Referring to FIG. 14 , the first gamma curve 401 represents the luminance of gray levels in the data voltage (Vdata) versus pixel current (I _OLED ) characteristics in the normal luminance driving mode. The second gamma curve 402 represents the luminance of gray levels in the data voltage (Vdata) versus pixel current (I _OLED ) characteristics in the high luminance driving mode. The first gamma curve 401 expresses grayscale from lowest luminance to peak luminance (Lp). The second gamma curve 402 expresses grayscale levels higher than the peak luminance (Lp) up to the maximum luminance (Lhdr).

In the case of the existing pixel circuit (comparative example) shown in FIG. 17, when the luminance is increased by increasing the channel width of the transistor used as the driving element, the low gray level luminance increases and the low gray level expression deteriorates. The pixel circuit of the comparative example shown in FIG. 17 includes three transistors (M1, M2, DT), one capacitor (Cst), and a light emitting element (OLED). In contrast, the pixel circuits of the present invention can not only express the luminance of high gray levels at a higher luminance than the peak luminance using the second gamma curve 402, but also can express low gray levels by lowering the luminance of low gray levels using the first gamma curve 401. can be improved.

Figures 15 and 16 are diagrams showing the low gray scale luminance of the present invention in linear scale (FIG. 15) and log scale (FIG. 16). FIG. 15 shows the luminance characteristics of the pixel circuit of the present invention and the comparative example (FIG. 17) at gray levels 8 to 20. FIG. 16 shows the luminance characteristics of the pixel circuit of the present invention and the comparative example (FIG. 17) at 8 gray levels or less. In FIGS. 15 and 16, “Comparative Example 1” is an example in which the maximum luminance of the comparative example shown in FIG. 17 is 1,000 [nit], and “Comparative Example 2” is an example in which the maximum luminance of the comparative example shown in FIG. 17 is 1,300 [nit]. This is an example of raising it to ].

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

20: switch circuit
100: display panel 110: data driver
120: Gate driver 130: Timing controller
101: Subpixel 102, 1021~1023: Data line
1024, 1043: Light emission control line 104, 1041, 1042: Gate line
DT1, DT2: driving elements S1, S2, S3: switch elements
Cst, Cst1, Cst2, Cem: capacitor OLED: light emitting device

Claims (7)

light emitting device;
first and second driving elements connected to the light-emitting device to supply current to the light-emitting device; and
Only the first driving element among the first and second driving elements is driven in a first luminance range up to a preset peak luminance, and the first and second driving elements are driven in a second luminance range higher than the peak luminance. It includes a switch circuit that increases the amount of current flowing to the light emitting element,
The first driving element includes a gate connected to a second node, a first electrode connected to a first power line supplied with a high potential power supply voltage, and a second electrode connected to the anode of the light emitting element through the first node,
The second driving element is a pixel including a gate connected to a second node, a first electrode connected to the first power line through the switch circuit, and a second electrode connected to the anode of the light emitting element through the first node. Circuit. According to claim 1,
The first and second driving elements are connected to the anode of the light-emitting element via the first node, and the cathode of the light-emitting element is connected to an electrode supplied with a low-potential power voltage,
The switch circuit blocks a current path between the first power line and the first electrode of the second driving element in the first luminance range, and blocks the first power line and the second driving element in the second luminance range. Connect the first electrode of
A pixel circuit in which the high-potential power supply voltage is a direct current voltage higher than the low-potential power supply voltage. According to claim 2,
The switch circuit is
A first switch element including a gate connected to a first gate line to which a first scan signal is applied, a first electrode connected to a data line to which a data voltage of an input image is supplied, and a second electrode connected to the second node;
a second switch element including a gate connected to the first gate line, a first electrode connected to the light emission control line, and a second electrode connected to a third node;
A gate connected to a second gate line to which a second scan signal synchronized with the first scan signal is applied, a first electrode connected to the first node, and a second electrode connected to a second power line to which a predetermined reference voltage is applied. A third switch element including; and
A fourth switch element including a gate connected to the third node, a first electrode connected to the first power line, and a second electrode connected to the first electrode of the second driving element,
A gate-off voltage is supplied to the emission control line in the first luminance range, and a gate-on voltage is applied to the emission control line in the second luminance range,
The fourth switch element is turned off according to the gate-off voltage on the third node in the first luminance range and turned on according to the gate-on voltage on the third node in the second luminance range,
A pixel circuit wherein the reference voltage is a direct current voltage lower than the high-potential power supply voltage and higher than the low-potential power supply voltage. According to claim 3,
a first capacitor connected between the first node and the second node; and
A pixel circuit further comprising a second capacitor connected between the first power line and the third node. According to claim 2,
The switch circuit is
A first switch element including a gate connected to a first gate line to which a first scan signal is applied, a first electrode connected to a data line to which a data voltage of an input image is supplied, and a second electrode connected to the second node;
A gate connected to a second gate line to which a second scan signal synchronized with the first scan signal is applied, a first electrode connected to the first node, and a second electrode connected to a second power line to which a predetermined reference voltage is applied. A second switch element including; and
It includes a gate connected to a light emission control line, a first electrode connected to the first power line, and a third switch element connected to the first electrode of the second driving element,
A gate-off voltage is supplied to the emission control line in the first luminance range, and a gate-on voltage is applied to the emission control line in the second luminance range,
The third switch element is turned off according to the gate-off voltage in the first luminance range and turned on according to the gate-on voltage in the second luminance range,
A pixel circuit wherein the reference voltage is a direct current voltage lower than the high-potential power supply voltage and higher than the low-potential power supply voltage. According to claim 2,
The switch circuit is
A first switch element including a gate connected to a first gate line to which a first scan signal is applied, a first electrode connected to a data line to which a data voltage of an input image is supplied, and a second electrode connected to the second node;
a second switch element including a gate connected to a first emission control line, a second electrode connected to a second emission control line crossing the first emission control line, and a second electrode connected to a third node;
A gate connected to a second gate line to which a second scan signal synchronized with the first scan signal is applied, a first electrode connected to the first node, and a second electrode connected to a second power line to which a predetermined reference voltage is applied. A third switch element including; and
A fourth switch element including a gate connected to the third node, a first electrode connected to the first power line, and a second electrode connected to the first electrode of the second driving element,
A gate-off voltage is supplied to the first and second emission control lines in the first luminance range, and a gate-on voltage is applied to the first and second emission control lines in the second luminance range,
The second switch element is turned off according to the gate-off voltage in the first luminance range and turned on according to the gate-on voltage in the second luminance range,
The fourth switch element is turned on at the same time when the second switch element is turned on to form a current path between the first power line and the first electrode of the second driving element,
A pixel circuit wherein the reference voltage is a direct current voltage lower than the high-potential power supply voltage and higher than the low-potential power supply voltage. The method of claim 5 or 6,
A pixel circuit further comprising a capacitor connected between the first node and the second node.