KR102658433B1 - Pixel circuit and electroluminescent display using the same - Google Patents

Abstract

The present invention relates to a pixel circuit and an electroluminescence display device using the same, which is connected between the gate electrode of a driving transistor and the source electrode of the driving transistor, and is connected between the gate electrode of the driving transistor and the second electrode by a data transfer rate control signal. The storage capacitor capacity can be adjusted.

Description

Pixel circuit and electroluminescent display device using the same {PIXEL CIRCUIT AND ELECTROLUMINESCENT DISPLAY USING THE SAME}

The present invention relates to a pixel circuit capable of high dynamic range (hereinafter “HDR”) operation and an electroluminescent display device using the same.

Electroluminescent displays are roughly divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness, and viewing angle. There is an advantage.

Pixels of an organic light emitting display device include an OLED and a driving transistor that drives the OLED by supplying current to the OLED according to a gate-source voltage. An OLED organic light emitting display device includes an anode and a cathode, and an organic compound layer formed between the electrodes. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL). When current flows through the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emitting layer (EML) to form excitons, and as a result, the emitting layer (EML) generates visible light. .

In the recent TV market, the share of premium OLED TVs using OLED is increasing, and OLED TVs have the advantage of deep and clear picture quality compared to LCD TVs. Additionally, OLED TV has the advantage of high brightness and a completely black screen.

However, high luminance and high dynamic range (HDR) driving is increasingly required.

In order to meet this demand, the driving current of the pixel can be increased by increasing the channel width of the transistor used as a driving element in the pixel. However, this method increases not only the luminance of high gray levels but also the luminance of low gray levels, which may reduce the expressiveness of low gray levels.

The present invention is intended to solve the above problems. The purpose of the present invention is to provide a pixel circuit capable of expressing rich data in low gray levels by changing the data transfer rate, and an electroluminescent display device using the same.

The pixel circuit of the present invention includes a light-emitting device, a driving transistor connected to the light-emitting device to control a current flowing through the light-emitting device, and a capacity of a storage capacitor between the gate electrode and the source electrode of the driving transistor by a data transfer rate control signal. It may include a storage capacity control unit that adjusts.

It may further include a storage capacitor disposed between the gate electrode of the driving transistor and the second electrode of the driving transistor and connected in parallel with the storage capacity adjustment unit.

The storage capacity control unit may be composed of one selection transistor and one control capacitor.

The storage capacity control unit may be composed of a plurality of selection transistors and a plurality of control capacitors.

The electroluminescent display device of the present invention includes a display panel including a plurality of subpixels, and a display panel driving circuit that writes pixel data of an input image to the subpixels and outputs a data transfer rate control signal, the subpixels Each includes the pixel circuit.

In the present invention, the capacity of the storage capacitor between the gate electrode and the source electrode of the driving transistor can be adjusted by a data transfer rate control signal, so HDR driving can be performed without reducing low gray level expression.

The display device can be driven in a daytime viewing mode by increasing the capacity of the storage capacitor by the storage capacity adjusting unit, and the display device can be driven in a night viewing mode by decreasing the capacity of the storage capacitor by the storage capacity adjusting unit. In other words, it can be driven with dual gamma in day viewing mode and night viewing mode.

In the case of night viewing mode gamma, the data voltage range can be driven wider than that of daytime viewing mode gamma, enabling deep and clear image quality for low-gradation expressions in night viewing mode.

1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention.
Figure 2 is a circuit diagram showing a pixel circuit according to the first embodiment of the present invention.
Figure 3 is a circuit diagram showing a pixel circuit according to a second embodiment of the present invention.
Figure 4 is a circuit diagram showing a pixel circuit according to a third embodiment of the present invention.
Figure 5 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present invention.
Figure 6 is a circuit diagram showing a pixel circuit according to a fifth embodiment of the present invention.
Figure 7 is a circuit diagram showing a pixel circuit according to the sixth embodiment of the present invention.
Figure 8 is a circuit diagram showing a pixel circuit according to the seventh embodiment of the present invention.
Figure 9 is a circuit diagram showing a pixel circuit according to the eighth embodiment of the present invention.
Figure 10 is a graph comparing pixel driving timing and data transfer rate variations according to a comparative example and the present invention.
Figure 11 is a graph showing day/night mode gamma dualization according to change in capacity of a storage capacitor in a pixel circuit according to an embodiment of the present invention.
FIG. 12 is a graph showing the linear scale of a gamma curve in a low gray level area in a pixel circuit according to an embodiment of the present invention.
FIG. 13 is a graph showing the log scale of a gamma curve in a low gray level area in a pixel circuit according to an embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms. The embodiments only serve to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “comprises,” “includes,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two components is described as 'on top', 'on top', 'at the bottom', 'next to ~', ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the electroluminescence display device of the present invention, the pixel circuit includes a driving element and a switch element. The driving element and the switch element may be implemented with one or more transistors of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor on the display panel may be implemented as a thin film transistor (TFT). The transistor may be implemented as an oxide transistor with an oxide semiconductor pattern or a low temperature poly-silicon (LTPS) transistor with a semiconductor pattern. A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor (NMOS), because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor (NMOS), the direction of current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage to allow holes to flow from the source to the drain. In a p-channel transistor (PMOS), current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal of the transistor used as switch elements swings between the gate on voltage and the gate off voltage. The gate-on voltage is set to the voltage at which the transistor turns on, and the gate-off voltage is set to the voltage at which the transistor turns off. In the case of an n-channel transistor (NMOS), the gate-on voltage can be the gate high voltage (VGH), and the gate-off voltage can be the gate low voltage (VGL), which is lower than the gate high voltage (VGH). there is. In the case of a p-channel transistor (PMOS), the gate-on voltage may be the gate low voltage (VGL) and the gate-off voltage may be the gate high voltage (VGH).

Hereinafter, a pixel circuit and an electroluminescent display device using the same according to various embodiments of the present invention will be described in more detail with reference to the attached drawings. In the following embodiments, the electroluminescent display device will be described focusing on an organic light emitting display device including an organic light emitting material, but is not limited thereto.

1 is a diagram showing an electroluminescent display device according to an embodiment of the present invention.

Referring to FIG. 1, an electroluminescent display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The screen of the display panel 100 includes a pixel array (AA) that displays an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 104 crossing the data lines 102, and pixels arranged in a matrix form.

Each pixel may be divided into red sub-pixel, green sub-pixel, and blue sub-pixel to implement color. Each of the pixels may further include a white subpixel.

The present invention proposes a pixel circuit that emits light at higher luminance and can express rich data at low gray levels compared to existing electroluminescence displays. Hereinafter, “pixel” may be interpreted as having the same meaning as subpixel.

The pixel array AA includes a plurality of pixel lines L1 to Ln. Pixel lines L1 to Ln include subpixels 101 arranged in line 1 of the pixel array. Pixels placed in one pixel line share gate lines 104. Subpixels 101 arranged in one pixel line are connected to different data lines 102. Subpixels arranged vertically along the data line direction share the same data line. The display panel driving circuits 110 and 120 write one frame data of the input image to pixels during one frame period. Pixel data of the input image is written to subpixels of 1 pixel line for 1 horizontal period. One horizontal period is equal to one frame period divided by the total number of pixel lines in the pixel array.

Touch sensors may be disposed on the display panel 100. Touch input can be sensed using separate touch sensors or sensed through pixels. Touch sensors can be implemented as on-cell type or add-on channel (Add on type) placed on the screen of the display panel or as in-cell type touch sensors built into the pixel array. You can.

The display panel driving circuits 110 and 120 include a data driver 110 and a gate driver 120. A demultiplexer (DEMUX), not shown, may be placed between the data driver 110 and the data lines 102.

The display panel driving circuits 110 and 120 address the pixel lines of the display panel 100 under the control of a timing controller (TCON) 130, write data of the input image to the pixels, and drive the pixels. It emits light. The display panel driving circuits 110 and 120 may further include a touch sensor driving unit for driving the touch sensors. The touch sensor driver is omitted in FIG. 1. In a mobile device or wearable device, the data driver 110, timing controller 130, etc. may be integrated into one integrated circuit.

The data driver 110 uses a digital to analog converter (hereinafter referred to as DAC) to convert the digital data of the input image received from the timing controller 130 every frame period into a gamma compensation voltage to produce a data signal. The voltage (hereinafter referred to as “data voltage”) is output. Data voltage is applied to the pixels through data line 102.

As shown in FIGS. 2, 4, 6, and 8, the data driver 110 transmits the data transfer rate control signals (CTRL, CTRL_1, CTRL_n) output from the timing controller 130 to the display panel 100. It can be supplied to the formed data transfer rate control line.

The demultiplexer, omitted in the drawing, is disposed between the data driver 110 and the data lines 102 using a plurality of switch elements and distributes the data voltage output from the data driver 110 to the data lines 102. Since one channel of the data driver 110 is distributed to a plurality of data lines by the demultiplexer, the number of data lines 102 can be reduced.

In some embodiments, the data driver 110 may output a gate-on voltage (VGH) and a gate-off voltage (VGL) to be applied to the emission control line through some channels. The data voltage Vdata output from the data driver 110 may be a voltage in the range of 0 to 19 [V]. The gate-on voltage (VGH) may be 28 [V] and the gate-off voltage (VGL) may be -5 [V]. This voltage example is only an example and is subject to change.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed directly on the bezel area of the display panel 100 along with a transistor array in the active area. The gate driver 120 outputs a gate signal to the gate lines 104 under the control of the timing controller 130. The gate signal swings between the gate-on voltage (VGH) and the gate-off voltage (VGL). The gate driver 120 can sequentially supply the signals to the gate lines 104 by shifting the gate signals using a shift register. The gate signal may include first and second scan signals (SCAN, SENSE) and signals of the emission control line.

As shown in FIGS. 3, 5, 7, and 9, the gate driver 120 transmits the data transfer rate control signals (CTRL, CTRL_1, CTRL_n) output from the timing controller 130 to the display panel 100. It can be supplied to the formed data transfer rate control line.

The timing controller 130 receives digital video data (DATA) of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (DCLK), and a data enable signal (DE). The host system may be any one of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, or wearable device.

The timing controller 130 provides a data timing control signal to control the operation timing of the data driver 110 based on timing signals (Vsync, Hsync, DE) received from the host system, and a switch control to control the operation timing of the demultiplexer. The operation timing of the display panel driver circuits 110 and 120 can be controlled by generating a gate timing control signal for controlling the operation timing of the gate driver 120. The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120. The level shifter converts the low level voltage of the gate timing control signal to the gate low voltage (VGL) and the high level voltage of the gate timing control signal to the gate high voltage (VGH). .

The timing controller 130 may output a data transfer rate control signal to adjust the data transfer rate according to the day or night viewing mode. The data transfer rate control signal may be supplied to a data transfer rate control line formed on the display panel 100 through the data driver 110 or the gate driver 120. The data transfer rate control signal may set the data transfer rate to be high in the daytime viewing mode, and set the data transfer rate to be relatively low in the nighttime viewing mode compared to the daytime viewing mode.

The day viewing mode or the night viewing mode can be selected by the user, and the surrounding brightness is sensed by an illuminance sensor that senses the surrounding brightness, and if the surrounding brightness is relatively bright, the day viewing mode is set, and if the surrounding brightness is relatively dark, the You can set it to night viewing mode.

Additionally, the timing controller 130 can output various data rate control signals in the night viewing mode to adjust the data rate to various levels.

Therefore, high luminance can be provided in daytime viewing mode, and rich image quality can be provided at low gray levels in nighttime viewing mode.

Each of the subpixels 101 of the present invention includes a driving transistor that drives a light emitting device, two switching transistors, a storage capacitor, and a data transfer rate that is adjusted by varying the capacity of the storage capacitor according to the data transfer rate control signal. It may include a storage capacity control unit for. Each transistor may be implemented as a transistor with a MOSFET (metal oxide semiconductor field effect transistor) structure. Each of the subpixels 101 can adjust the capacity of the storage capacitor of the subpixel 101 under the control of the timing controller 130, thereby adjusting the data transfer rate. As the capacity of the storage capacitor increases, the data transfer rate may increase, and as the capacity of the storage capacitor decreases, the data transfer rate may decrease. That is, as shown in [Equation 1], the data transfer rate (K) is proportional to the capacity of the storage capacitor [K = {Vgs / (Vdata - Vref)} x 100].

Here, Vgs is the voltage between the gate/source of the driving transistor in the light emission period, Vdata is the data voltage applied to the data line in the writing period, and Vref is the reference voltage applied to the reference voltage line in the writing period.

The electrical characteristics of each driving transistor of the subpixels 101 must be uniform across all pixels, but there may be differences between pixels due to process deviation and device characteristic deviation and may change over driving time. In order to compensate for the deviation in the electrical characteristics of the driving transistor, an internal compensation method and an external compensation method can be applied to the electroluminescence display device. The internal compensation method samples the threshold voltage (Vth) of the driving transistor, which changes depending on the electrical characteristics of the driving element, and compensates the data voltage by the threshold voltage (Vth). The external compensation method senses the voltage of the pixel that changes according to the electrical characteristics of the driving transistor, and modulates the data of the input image in an external circuit based on the sensed voltage to compensate for the deviation in the electrical characteristics of the driving elements between pixels.

The external compensation method uses a sensing circuit to sense the threshold voltage of the driving transistor in sensing mode and selects a compensation value according to the deviation or change over time in the threshold voltage between subpixels to compensate for the threshold voltage deviation or change over time of the driving transistor. You can. Sensing modes can be divided into before and after product shipment.

The sensing circuit includes a reference voltage line (or sensing line, hereinafter referred to as “Vref line”) connected to each of the subpixels 101, a sample and holder that samples the current from the Vref line as a voltage, and a sample & may include an analog to digital convertor (hereinafter referred to as “ADC”) that converts the voltage sampled by the holder into digital data. The timing controller 130 may select a compensation value according to the data received from the ADC, add the selected compensation value to the pixel data, and transmit the pixel data whose threshold voltage of the driving element has been compensated to the data driver 110. The sample & holder of the sensing circuit and the ADC may be integrated within the IC (Integrated Circuit) of the data driver 110.

Hereinafter, the configuration and operation of the pixel circuit will be explained focusing on the driving mode for displaying pixel data of the input image. Operations for sensing mode are omitted.

Figure 2 is a circuit diagram showing a pixel circuit according to the first embodiment of the present invention.

As shown in FIG. 2, the pixel circuit according to the first embodiment of the present invention includes a light emitting element (OLED), a driving transistor (DT), two switching transistors (T1, T2), a storage capacitor (Cst), and It may include a storage capacity adjuster 10 that adjusts the capacity of the storage capacitor (Cst) according to the data transfer rate control signal (CTRL). The storage capacity control unit 10 may include a control capacitor C1 and a selection transistor T3.

The driving transistor (DT), the two switching transistors (T1, T2), and the selection transistor (T3) may be implemented as n-channel transistors, but are not limited to this, and may be implemented as p-channel transistors.

Each of the pixel circuits will be supplied with a high-potential power supply voltage (EVDD), a low-potential power supply voltage (EVSS), a reference voltage (Vref), a data voltage (Vdata), a scan signal (Scan), and a data transfer rate control signal (CTRL). You can. The high-potential power supply voltage (EVDD) can be set to a direct current voltage higher than the low-potential power supply voltage (EVSS) and the reference voltage (Vref). The reference voltage (Vref) may be set to a direct current voltage lower than the high-potential power supply voltage (EVDD) and equal to or higher than the low-potential power supply voltage (EVSS). The low potential supply voltage (EVSS) can be ground voltage (GND) or 0V. The reference voltage (Vref) may be 2V, but is not limited thereto.

A light emitting device (OLED) includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light emitting device (OLED) may be connected to the second electrode of the driving transistor (DT), and the cathode of the light emitting device (OLED) may be connected to a low potential power supply voltage (EVSS) supply line.

The gate electrode of the first switching transistor (T1) is connected to a gate line that supplies a scan signal (Scan), and the first electrode of the first switching transistor (T1) is connected to a data line that supplies a data voltage (Vdata). , the second electrode of the first switching transistor (T1) is connected to the gate electrode of the driving transistor (DT).

The gate electrode of the second switching transistor (T2) is connected to the gate line that supplies the scan signal (Scan), the first electrode of the second switching transistor (T2) is connected to the second electrode of the driving transistor (DT), The second electrode of the second switching transistor T2 is connected to a reference voltage supply line that supplies the reference voltage Vref.

The gate electrode of the driving transistor (DT) is connected to the second electrode of the first switching transistor (T1), and the first electrode of the driving transistor (DT) is a high potential power supply voltage supply line that supplies the high potential power supply voltage (EVDD). and the second electrode of the driving transistor (DT) is connected to the anode of the light emitting device (OLED) and the first electrode of the two switching transistors (T2).

The first electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor DT, and the second electrode of the storage capacitor Cst is connected to the second electrode of the driving transistor DT.

The storage capacity control unit 10 includes a selection transistor T3 and a control capacitor C1, and is connected to the storage capacitor Cst between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT. connected in parallel.

That is, the gate electrode of the selection transistor T3 of the storage capacity adjusting unit 10 is connected to the data transfer rate control signal supply line that supplies the data transfer rate control signal CTRL, and the first electrode of the selection transistor T3 is connected to the data transfer rate control signal supply line. It is connected to the gate electrode of the driving transistor (DT), and the second electrode of the selection transistor (T3) is connected to the first electrode of the control capacitor (C1).

The first electrode of the control capacitor C1 of the storage capacity adjusting unit 10 is connected to the second electrode of the selection transistor T3, and the second electrode of the control capacitor C1 is connected to the second electrode of the storage capacitor Cst. It is connected to the electrode and the second electrode of the driving transistor (DT).

The selection transistor (T3) is turned on or off according to the data transfer rate control signal (CTRL). When the selection transistor (T3) is turned on, the storage capacitor (Cst) and the control capacitor (C1) has a structure connected in parallel between the gate electrode of the driving transistor (DT) and the second electrode of the driving transistor (DT).

Accordingly, when the selection transistor T3 is turned on, the capacity of the storage capacitor increases, and when the selection transistor T3 is turned off, the capacity of the storage capacitor decreases.

That is, in the daytime viewing mode, the data transfer rate control signal (CTRL) is output at a high level to turn on the selection transistor (T3), and in the night viewing mode, the data transfer rate control signal (CTRL) is output at a low level. The selection transistor (T3) is turned off. Then, the data transfer rate may be set high in the daytime viewing mode, and the data transfer rate may be set relatively lower in the nighttime viewing mode than in the daytime viewing mode.

In the pixel circuit according to the first embodiment of the present invention, as shown in FIG. 2, the data transfer rate control signal supply line that supplies the data transfer rate control signal (CTRL) is parallel to the gate line that supplies the scan signal (Scan). It can be placed like this. Accordingly, the pixel circuit according to the first embodiment of the present invention can supply the data transfer rate control signal CTRL through the gate driver 120.

In addition, Figure 2 shows that the first switching transistor (T1) and the second switching transistor (T2) are controlled by a single scan signal (Scan), but this is not limited to this, and the first switching transistor (T1) is controlled by a scan signal (Scan). It is controlled by (Scan), and the second switching transistor (T2) can be controlled by a sensing signal (Sense).

Figure 3 is a circuit diagram showing a pixel circuit according to a second embodiment of the present invention.

The pixel circuit according to the second embodiment of the present invention has the same configuration as the pixel circuit according to the first embodiment of the present invention, but viewed from the arrangement of the data rate control signal supply line that supplies the data rate control signal (CTRL). There is a difference from the first embodiment of the invention.

That is, a light emitting element (OLED), a driving transistor (DT), two switching transistors (T1, T2), a storage capacitor (Cst), and a control capacitor (C1) and a selection transistor (T3) of the storage capacity control unit 10. Their connection relationship is the same as the configuration and operation of the pixel circuit according to the first embodiment of the present invention, so description of their connection relationship is omitted.

As shown in FIG. 3, a data transfer rate control signal supply line supplying the data transfer rate control signal CTRL may be arranged in parallel with a data line supplying the data voltage Vdata. Accordingly, the pixel circuit according to the second embodiment of the present invention can supply the data transfer rate control signal (CTRL) through the data driver 110.

Likewise, in Figure 3, the first switching transistor (T1) and the second switching transistor (T2) are shown to be controlled by one scan signal (Scan), but this is not limited to this, and the first switching transistor (T1) is controlled by a scan signal. It is controlled by (Scan), and the second switching transistor (T2) can be controlled by a sensing signal (Sense).

Figure 4 is a circuit diagram showing a pixel circuit according to a third embodiment of the present invention.

The pixel circuit according to the third embodiment of the present invention has the same configuration as the pixel circuit according to the first embodiment of the present invention, but the storage capacitor Cst is omitted.

That is, the pixel circuit according to the third embodiment of the present invention, as shown in FIG. 4, includes first and second switching transistors (T1 and T2), a driving transistor (DT), and a storage capacity adjustment unit 10. is provided.

The gate electrode of the first switching transistor (T1) is connected to a gate line that supplies a scan signal (Scan), and the first electrode of the first switching transistor (T1) is connected to a data line that supplies a data voltage (Vdata). , the second electrode of the first switching transistor (T1) is connected to the gate electrode of the driving transistor (DT).

The gate electrode of the second switching transistor (T2) is connected to the gate line that supplies the scan signal (Scan), the first electrode of the second switching transistor (T2) is connected to the second electrode of the driving transistor (DT), The second electrode of the second switching transistor T2 is connected to a reference voltage supply line that supplies the reference voltage Vref.

The gate electrode of the driving transistor (DT) is connected to the second electrode of the first switching transistor (T1), and the first electrode of the driving transistor (DT) is a high potential power supply voltage supply line that supplies the high potential power supply voltage (EVDD). and the second electrode of the driving transistor (DT) is connected to the anode of the light emitting device (OLED) and the first electrode of the two switching transistors (T2).

The storage capacity control unit 10 includes a selection transistor T3 and a control capacitor C1, and is connected between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT.

The gate electrode of the selection transistor T3 of the storage capacity adjusting unit 10 is connected to a data transfer rate control signal supply line that supplies the data transfer rate control signal CTRL, and the first electrode of the selection transistor T3 is a driving transistor. It is connected to the gate electrode of (DT), and the second electrode of the selection transistor (T3) is connected to the first electrode of the control capacitor (C1).

The first electrode of the control capacitor C1 of the storage capacity adjusting unit 10 is connected to the second electrode of the selection transistor T3, and the second electrode of the control capacitor C1 is connected to the second electrode of the driving transistor DT. connected to the electrode.

The selection transistor (T3) is turned on or off according to the data transfer rate control signal (CTRL), and when the selection transistor (T3) is turned on, the control capacitor (C1) is connected to the driving transistor (DT). It has a structure connected between the gate electrode and the second electrode of the driving transistor (DT).

Therefore, when the selection transistor (T3) is turned on, the capacity of the storage capacitor increases by the capacity of the control capacitor (C1) and the capacity of the parasitic capacitor (Cgs) between the gate/source of the driving transistor (DT), and the selection transistor When (T3) is turned off, the capacity of the storage capacitor is reduced by the parasitic capacitor capacity (Cgs) between the gate and source of the driving transistor (DT).

That is, in the daytime viewing mode, the data transfer rate control signal (CTRL) is output at a high level to turn on the selection transistor (T3), and in the night viewing mode, the data transfer rate control signal (CTRL) is output at a low level. The selection transistor (T3) is turned off. Then, the data transfer rate may be set high in the daytime viewing mode, and the data transfer rate may be set relatively lower in the nighttime viewing mode than in the daytime viewing mode.

When the selection transistor (T3) is turned on, the data voltage (Vdata) is charged in the parasitic capacitor (Cgs) between the control capacitor (C1) and the gate/source of the driving transistor (DT), and the selection transistor (T3) is turned on. -When turned off, the data voltage (Vdata) is charged only to the parasitic capacitor (Cgs) between the gate/source of the driving transistor (DT).

In the pixel circuit according to the third embodiment of the present invention, as shown in FIG. 4, the data transfer rate control signal supply line that supplies the data transfer rate control signal (CTRL) is parallel to the gate line that supplies the scan signal (Scan). It can be placed like this. Accordingly, the pixel circuit according to the third embodiment of the present invention can supply the data transfer rate control signal CTRL through the gate driver 120.

In addition, Figure 4 shows that the first switching transistor (T1) and the second switching transistor (T2) are controlled by one scan signal (Scan), but this is not limited to this, and the first switching transistor (T1) is controlled by a single scan signal (Scan). It is controlled by (Scan), and the second switching transistor (T2) can be controlled by a sensing signal (Sense).

Figure 5 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present invention.

The pixel circuit according to the fourth embodiment of the present invention has the same configuration as the pixel circuit according to the third embodiment of the present invention, but viewed from the arrangement of the data rate control signal supply line that supplies the data rate control signal (CTRL). There is a difference from the third embodiment of the invention.

Therefore, description of the connection relationship between the light emitting device (OLED), driving transistor (DT), two switching transistors (T1, T2), control capacitor (C1), and selection transistor (T3) will be omitted.

As shown in FIG. 5, a data transfer rate control signal supply line supplying the data transfer rate control signal CTRL may be arranged in parallel with a data line supplying the data voltage Vdata. Accordingly, the pixel circuit according to the fourth embodiment of the present invention can supply the data transfer rate control signal (CTRL) through the data driver 110.

Likewise, in Figure 5, the first switching transistor (T1) and the second switching transistor (T2) are shown to be controlled by one scan signal (Scan), but this is not limited to this, and the first switching transistor (T1) is controlled by a scan signal. It is controlled by (Scan), and the second switching transistor (T2) can be controlled by a sensing signal (Sense).

The pixel circuits according to the first to fourth embodiments of the present invention described so far are characterized in that the storage capacity adjustment unit 10 includes one adjustment capacitor C1 and one selection transistor T3. However, the storage capacity control unit is not limited to this and may include an array including a plurality of control capacitors and a plurality of selection transistors.

This embodiment will be described in more detail as follows.

Figure 6 is a circuit diagram showing a pixel circuit according to a fifth embodiment of the present invention.

As shown in FIG. 6, the pixel circuit according to the fifth embodiment of the present invention includes a light emitting element (OLED), a driving transistor (DT), two switching transistors (T1, T2), a storage capacitor (Cst), and It may include a storage capacity control unit 20 having a plurality of control capacitors (C1 to Cn) and a plurality of selection transistors (T3_1 to T3_n).

The driving transistor (DT), two switching transistors (T1, T2), and a plurality of selection transistors (T3) may be implemented as n-channel transistors, but are not limited to this, and may be implemented as p-channel transistors.

Each of the pixel circuits will be supplied with a high-potential power supply voltage (EVDD), a low-potential power supply voltage (EVSS), a reference voltage (Vref), a data voltage (Vdata), a scan signal (Scan), and a data transfer rate control signal (CTRL). You can. The high-potential power supply voltage (EVDD) can be set to a direct current voltage higher than the low-potential power supply voltage (EVSS) and the reference voltage (Vref). The reference voltage (Vref) may be set to a direct current voltage lower than the high-potential power supply voltage (EVDD) and equal to or higher than the low-potential power supply voltage (EVSS). The low potential supply voltage (EVSS) can be ground voltage (GND) or 0V. The reference voltage (Vref) may be 2V, but is not limited thereto.

A light emitting device (OLED) includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light emitting device (OLED) may be connected to the second electrode of the driving transistor (DT), and the cathode of the light emitting device (OLED) may be connected to a low potential power supply voltage (EVSS) supply line.

The gate electrode of the first switching transistor (T1) is connected to a gate line that supplies a scan signal (Scan), and the first electrode of the first switching transistor (T1) is connected to a data line that supplies a data voltage (Vdata). , the second electrode of the first switching transistor (T1) is connected to the gate electrode of the driving transistor (DT).

The gate electrode of the second switching transistor (T2) is connected to the gate line that supplies the scan signal (Scan), the first electrode of the second switching transistor (T2) is connected to the second electrode of the driving transistor (DT), The second electrode of the second switching transistor T2 is connected to a reference voltage supply line that supplies the reference voltage Vref.

The gate electrode of the driving transistor (DT) is connected to the second electrode of the first switching transistor (T1), and the first electrode of the driving transistor (DT) is a high potential power supply voltage supply line that supplies the high potential power supply voltage (EVDD). and the second electrode of the driving transistor (DT) is connected to the anode of the light emitting device (OLED) and the first electrode of the two switching transistors (T2).

The first electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor DT, and the second electrode of the storage capacitor Cst is connected to the second electrode of the driving transistor DT.

The storage capacity control unit 20 is composed of an array including a plurality of control capacitors (C1 to Cn) and a plurality of selection transistors (T3_1 to T3_n).

The storage capacity adjusting unit 20 is connected in parallel to the storage capacitor Cst between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT.

The storage capacity control unit 20 includes a plurality of pairs in which one control capacitor (one of C1 to Cn) and one selection transistor (one of T3_1 to T3_n) are connected in series. Each pair of control capacitors (one of C1 to Cn) and a selection transistor (one of T3_1 to T3_n) are connected in parallel, and each of the plurality of selection transistors (T3_1 to T3_n) receives a different data transfer rate control signal (CTRL_1 to CTRL_n). is controlled by

The gate electrode of each selection transistor (T3_1 to T3_n) of the storage capacity adjusting unit 20 is connected to one of a plurality of data transfer rate control signal supply lines that supply a plurality of data transfer rate control signals (CTRL_1 to CTRL_n), The first electrode of each selection transistor (T3_1 to T3_n) is connected to the gate electrode of the driving transistor (DT), and the second electrode of each selection transistor (T3_1 to T3_n) is one of the plurality of control capacitors (C1 to Cn). is connected to the first electrode of the regulating capacitor.

The first electrode of each control capacitor C1 to Cn of the storage capacity control unit 20 is connected to the second electrode of one of the plurality of selection transistors T3_1 to T3_n, and each control capacitor C1 to Cn is connected to the second electrode of one of the plurality of selection transistors T3_1 to T3_n. The second electrode of Cn) is connected to the second electrode of the storage capacitor (Cst).

Here, each control capacitor (C1 to Cn) may have the same capacity or different capacity. If the capacities of each control capacitor (C1 to Cn) are different, the data transmission rate can be adjusted more diversely.

When the plurality of selection transistors (T3_1 to T3_n) are all turned on, the plurality of control capacitors (C1 to Cn) are connected between the gate electrode of the driving transistor (DT) and the second electrode of the driving transistor (DT). It has a structure that is connected in parallel with the storage capacitor (Cst). Therefore, the capacity of the storage capacitor has the largest value.

When all of the plurality of selection transistors (T3_1 to T3_n) are turned off, the capacity of the storage capacitor is as low as the storage capacitor (Cst).

Therefore, as the number of selection transistors that are turned on among the plurality of selection transistors (T3_1 to T3_n) increases, the capacity of the storage capacitor increases, and the selection transistors that are turned off among the plurality of selection transistors (T3_1 to T3_n) increase. As the number of transistors increases, the capacity of the storage capacitor decreases.

In the daytime viewing mode, all of the plurality of data transfer rate control signals (CTRL_1 to CTRL_N) are output at a high level to turn on all of the plurality of selection transistors (T3_1 to T3_n), and in the night viewing mode, the plurality of data transfer rate control signals (CTRL_1 to CTRL_N) are all output at a high level. At least one of the control signals (CTRL_1 to CTRL_N) is output at a low level to turn off at least one of the plurality of selection transistors (T3_1 to T3_n).

Then, in the daytime viewing mode, the data transmission rate is set high and the video signal can be displayed with high brightness. In addition, in the night viewing mode, the data transmission rate is set to be relatively lower than in the daytime viewing mode, but the capacity of the storage capacitor is adjusted to various levels by adjusting the number of selection transistors that are turned off among the plurality of selection transistors (T3_1 to T3_n). reduce. Therefore, since a wide data voltage range can be used for low gray levels in night viewing mode, deep and clear image quality can be provided.

In the pixel circuit according to the fifth embodiment of the present invention, as shown in FIG. 6, data transfer rate control signal supply lines that supply a plurality of data transfer rate control signals (CTRL_1 to CTRL_n) supply a scan signal (Scan). It can be arranged parallel to the gate line. Accordingly, the pixel circuit according to the fifth embodiment of the present invention can supply a plurality of data transfer rate control signals (CTRL_1 to CTRL_n) through the gate driver 120.

In addition, Figure 6 shows that the first switching transistor (T1) and the second switching transistor (T2) are controlled by a single scan signal (Scan), but this is not limited to this, and the first switching transistor (T1) is controlled by a single scan signal (Scan). It is controlled by (Scan), and the second switching transistor (T2) can be controlled by a sensing signal (Sense).

Figure 7 is a circuit diagram showing a pixel circuit according to the sixth embodiment of the present invention.

The pixel circuit according to the sixth embodiment of the present invention has the same configuration as the pixel circuit according to the fifth embodiment of the present invention, but viewed from the arrangement of the data rate control signal supply line that supplies the data rate control signal (CTRL). There is a difference from the fifth embodiment of the invention.

That is, a light emitting device (OLED), a driving transistor (DT), two switching transistors (T1, T2), a storage capacitor (Cst), and a plurality of control capacitors (C1 to Cn) of the storage capacity adjustment unit 20, and The connection relationship between the plurality of selection transistors T3_1 to T3_n is the same as the configuration and operation of the pixel circuit according to the fifth embodiment of the present invention, so description of their connection relationship is omitted.

As shown in FIG. 7, a plurality of data rate control signal supply lines supplying a plurality of data rate control signals CTRL_1 to CTRL_n may be arranged in parallel with a data line supplying a data voltage Vdata. Accordingly, the pixel circuit according to the sixth embodiment of the present invention can supply a plurality of data transfer rate control signals (CTRL_1 to CTRL_n) through the data driver 110.

Likewise, in Figure 7, the first switching transistor (T1) and the second switching transistor (T2) are shown to be controlled by a single scan signal (Scan), but this is not limited to this, and the first switching transistor (T1) is controlled by a scan signal. It is controlled by (Scan), and the second switching transistor (T2) can be controlled by a sensing signal (Sense).

Figure 8 is a circuit diagram showing a pixel circuit according to the seventh embodiment of the present invention.

The pixel circuit according to the seventh embodiment of the present invention has the same configuration as the pixel circuit according to the fifth embodiment of the present invention, but the storage capacitor (Cst) is omitted.

As shown in FIG. 8, the pixel circuit according to the seventh embodiment of the present invention includes first and second switching transistors (T1, T2), a driving transistor (DT), and a storage capacity adjustment unit 20. do.

The gate electrode of the first switching transistor (T1) is connected to a gate line that supplies a scan signal (Scan), and the first electrode of the first switching transistor (T1) is connected to a data line that supplies a data voltage (Vdata). , the second electrode of the first switching transistor (T1) is connected to the gate electrode of the driving transistor (DT).

The gate electrode of the second switching transistor (T2) is connected to the gate line that supplies the scan signal (Scan), the first electrode of the second switching transistor (T2) is connected to the second electrode of the driving transistor (DT), The second electrode of the second switching transistor T2 is connected to a reference voltage supply line that supplies the reference voltage Vref.

The gate electrode of the driving transistor (DT) is connected to the second electrode of the first switching transistor (T1), and the first electrode of the driving transistor (DT) is a high potential power supply voltage supply line that supplies the high potential power supply voltage (EVDD). and the second electrode of the driving transistor (DT) is connected to the anode of the light emitting device (OLED) and the first electrode of the two switching transistors (T2).

The storage capacity control unit 20 is composed of an array including a plurality of control capacitors (C1 to Cn) and a plurality of selection transistors (T3_1 to T3_n).

The storage capacity adjusting unit 20 is connected between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT.

The storage capacity control unit 20 includes a plurality of pairs in which one control capacitor (one of C1 to Cn) and one selection transistor (one of T3_1 to T3_n) are connected in series. Each pair of control capacitors (one of C1 to Cn) and a selection transistor (one of T3_1 to T3_n) are connected in parallel, and each of the plurality of selection transistors (T3_1 to T3_n) receives a different data transfer rate control signal (CTRL_1 to CTRL_n). is controlled by

The gate electrode of each selection transistor (T3_1 to T3_n) of the storage capacity adjusting unit 20 is connected to one of a plurality of data transfer rate control signal supply lines that supply a plurality of data transfer rate control signals (CTRL_1 to CTRL_n), The first electrode of each selection transistor (T3_1 to T3_n) is connected to the gate electrode of the driving transistor (DT), and the second electrode of each selection transistor (T3_1 to T3_n) is one of the plurality of control capacitors (C1 to Cn). is connected to the first electrode of the regulating capacitor.

The first electrode of each control capacitor C1 to Cn of the storage capacity control unit 20 is connected to the second electrode of one of the plurality of selection transistors T3_1 to T3_n, and each control capacitor C1 to Cn is connected to the second electrode of one of the plurality of selection transistors T3_1 to T3_n. The second electrode of Cn) is connected to the second electrode of the driving transistor (DT).

Here, each control capacitor (C1 to Cn) may have the same capacity or different capacity. If the capacities of each control capacitor (C1 to Cn) are different, the data transmission rate can be adjusted more diversely.

When the plurality of selection transistors (T3_1 to T3_n) are all turned on, the plurality of control capacitors (C1 to Cn) are connected in parallel between the gate electrode of the driving transistor (DT) and the second electrode of the driving transistor (DT). It has a connected structure.

Therefore, when the plurality of selection transistors (T3_1 to T3_n) are all turned on, the capacity of the plurality of control capacitors (C1 to Cn) and the capacity of the parasitic capacitor (Cgs) between the gate/source of the driving transistor (DT) The capacity of the storage capacitor equal to the sum has the largest value.

When all of the plurality of selection transistors (T3_1 to T3_n) are turned off, the capacity of the storage capacitor is reduced due to the parasitic capacitance (Cgs) between the gate and source of the driving transistor (DT).

In addition, as the number of selection transistors that are turned on among the plurality of selection transistors (T3_1 to T3_n) increases, the capacity of the storage capacitor increases, and the selection transistors that are turned on among the plurality of selection transistors (T3_1 to T3_n) increase. As the number of transistors increases, the capacity of the storage capacitor decreases.

In the daytime viewing mode, all of the plurality of data transfer rate control signals (CTRL_1 to CTRL_N) are output at a high level to turn on all of the plurality of selection transistors (T3_1 to T3_n), and in the night viewing mode, the plurality of data transfer rate control signals (CTRL_1 to CTRL_N) are all output at a high level. At least one of the control signals (CTRL_1 to CTRL_N) is output at a low level to turn off at least one of the plurality of selection transistors (T3_1 to T3_n).

Then, in the daytime viewing mode, the data transmission rate is set high and the video signal can be displayed with high brightness. In addition, in the night viewing mode, the data transmission rate is set to be relatively lower than in the daytime viewing mode, but the capacity of the storage capacitor is adjusted to various levels by adjusting the number of selection transistors that are turned off among the plurality of selection transistors (T3_1 to T3_n). reduce. Therefore, since a wide data voltage range can be used for low gray levels in night viewing mode, deep and clear image quality can be provided.

As shown in FIG. 8, the pixel circuit according to the seventh embodiment of the present invention has a plurality of data transfer rate control signal supply lines that supply a plurality of data transfer rate control signals (CTRL_1 to CTRL_n) and a scan signal (Scan). It can be arranged parallel to the gate line that supplies. Accordingly, the pixel circuit according to the seventh embodiment of the present invention can supply the plurality of data transfer rate control signals (CTRL_1 to CTRL_n) through the gate driver 120.

In addition, Figure 8 shows that the first switching transistor (T1) and the second switching transistor (T2) are controlled by a single scan signal (Scan), but this is not limited to this, and the first switching transistor (T1) is controlled by a scan signal. It is controlled by (Scan), and the second switching transistor (T2) can be controlled by a sensing signal (Sense).

Figure 9 is a circuit diagram showing a pixel circuit according to the eighth embodiment of the present invention.

The pixel circuit according to the eighth embodiment of the present invention has the same configuration as the pixel circuit according to the seventh embodiment of the present invention, but provides a plurality of data transfer rate control signals (CTRL_1 to CTRL_n). There is a difference from the seventh embodiment of the present invention in the arrangement of the signal supply lines.

That is, the connection relationship between the light emitting element (OLED), the driving transistor (DT), the two switching transistors (T1, T2), and the storage capacity adjusting unit 20 is the configuration and configuration of the pixel circuit according to the seventh embodiment of the present invention. The operation is the same, so description of their connection relationship is omitted.

As shown in FIG. 9, a plurality of data transfer rate control signal supply lines for a plurality of data transfer rate control signals CTRL_1 to CTRL_n may be arranged in parallel with a data line supplying the data voltage Vdata. Accordingly, the pixel circuit according to the eighth embodiment of the present invention can supply a plurality of data transfer rate control signals (CTRL_1 to CTRL_n) through the data driver 110.

Pixel circuits according to an embodiment of the present invention control the data transfer rate, so not only can they express with high luminance, but also reduce the luminance of low gray levels, thereby improving low gray level expression in various ways.

Figure 10 is a graph comparing pixel driving timing and data transfer rate variations according to the present invention. The comparative example in FIG. 10 refers to a general pixel circuit.

It is assumed that the combined capacity of the control capacitors (C1 to Cn) and the storage capacitor (Cst) in the pixel circuit according to each embodiment of the present invention is equal to the capacity of the storage capacitor (Cst) of a general pixel circuit.

In Figure 10, the gate voltage (Vg) and source voltage (Vs) of the driving transistor of the comparative example are indicated with dotted lines, and the gate voltage (Vg) and source voltage (Vs) of the driving transistor of the present invention are indicated with solid lines.

As described above, when all of the selection transistors (T3, T3_1 to T3_n) are turned on in the pixel circuits of the embodiments of the present invention, the combined capacity of the control capacitors (C1 to Cn) and the storage capacitor (Cst) of the present invention Since the capacity of the storage capacitor (Cst) of the pixel circuit of the comparative example is the same, when at least one of the selection transistors (T3, T3_1 to T3_n) is turned off in the pixel circuit of the embodiments of the present invention, the entire storage The capacitor capacity is smaller than the capacity of the storage capacitor (Cst) of the pixel circuit of the comparative example.

Accordingly, when at least one of the selection transistors T3 and T3_1 to T3_n in the pixel circuits of the embodiments of the present invention is turned off, the gate/source voltage (Vgs) of the driving transistor DT of the pixel circuit of the comparative example is turned off. ), the gate/source voltage (Vgs) of the driving transistor (DT) of the embodiments of the present invention is relatively lower than that of ).

In this way, since the gate/source voltage (Vgs) of the driving transistor (DT) is adjusted according to the capacity of the storage capacitor, the data transfer rate is also controlled, as mentioned in [Equation 1].

FIG. 11 is a graph showing day/night mode gamma dualization according to a change in capacity of a storage capacitor in a pixel circuit according to an embodiment of the present invention, and FIG. 12 is a graph showing gamma of a low gray level region in a pixel circuit according to an embodiment of the present invention. It is a graph showing the linear scale of the gamma curve, and FIG. 13 is a graph showing the log scale of the gamma curve in the low-gray area in the pixel circuit according to an embodiment of the present invention. am.

11 to 13, ⓐ represents a case where the capacity of the storage capacitor is increased by the storage capacity controllers 10 and 20, and ⓑ represents a case where the capacity of the storage capacitor is decreased by the storage capacity controllers 10 and 20. It is shown.

As shown in FIG. 11, the pixel circuit of the embodiment of the present invention increases the capacity of the storage capacitor as ⓐ by the storage capacity adjusting units 10 and 20 to drive the display device in daytime viewing mode and adjust the storage capacity. The display device can be driven in night viewing mode by reducing the capacity of the storage capacitor as indicated by the units 10 and 20. In other words, it can be driven with dual gamma in day viewing mode and night viewing mode.

In addition, as shown in FIGS. 12 and 13, the pixel circuit of the embodiment of the present invention can drive the data voltage range to be about 40% wider in the case of night viewing mode gamma compared to the daytime viewing mode gamma, so night viewing mode is possible. In this mode, deep and clear image quality is possible for low-gradation expressions.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

10, 20: Storage capacity control unit
100: display panel 110: data driver
120: Gate driver 130: Timing controller
101: subpixel 102: data line
104: Gate line DT: Driving transistor
T1, T2: switching transistors T3, T3_1~T3_n: selection transistors
Cst: storage capacitor OLED: light emitting element
C1~Cn: Regulating capacitor

Claims (19)

light emitting device;
A driving transistor connected to the light emitting device to control a current flowing through the light emitting device; and
A storage capacity control unit that adjusts the capacity of a storage capacitor between the gate electrode and the source electrode of the driving transistor by a data transfer rate control signal,
The storage capacity adjusting unit is a pixel circuit comprised of a plurality of selection transistors and a plurality of control capacitors. According to claim 1,
The storage capacity control unit is a pixel circuit consisting of one selection transistor and one control capacitor. delete light emitting device;
A driving transistor connected to the light emitting device to control a current flowing through the light emitting device; and
a storage capacitor connected between the gate electrode and the source electrode of the driving transistor; and
A storage capacitance control unit that adjusts the capacitance of a storage capacitor between the gate electrode and the source electrode of the driving transistor using a data transfer rate control signal,
The storage capacity adjusting unit is a pixel circuit comprised of a plurality of selection transistors and a plurality of control capacitors. According to claim 4,
The storage capacity control unit is a pixel circuit consisting of one selection transistor and one control capacitor. delete light emitting device;
A driving transistor having a first electrode connected to a high-potential voltage supply line and a second electrode connected to an anode of the light-emitting device to control a current flowing in the light-emitting device;
a first switching transistor controlled by a scan signal to supply a data voltage to the gate electrode of the driving transistor;
a second switching transistor controlled by a scan signal to connect a second electrode of the driving transistor and a reference voltage supply line;
A storage capacity adjuster connected between the gate electrode of the driving transistor and the second electrode of the driving transistor to adjust the storage capacitance between the gate electrode of the driving transistor and the second electrode by a data transfer rate control signal,
The storage capacity adjusting unit is a pixel circuit including a plurality of selection transistors and a plurality of control capacitors. According to claim 7,
The storage capacity adjusting unit includes a selection transistor and an adjustment capacitor connected in series between a gate electrode of the driving transistor and a second electrode of the driving transistor, and the selection transistor is controlled by the data transfer rate control signal. A pixel circuit. According to claim 7,
A pixel circuit in which a data rate control signal line supplying the data rate control signal is disposed parallel to a gate line supplying the scan signal. According to claim 7,
A pixel circuit in which a data rate control signal line supplying the data rate control signal is disposed parallel to a data line supplying the data voltage. According to claim 7,
The storage capacity control unit includes one control capacitor and one selection transistor connected in series to form a pair, and each pair is connected in parallel between the gate electrode of the driving transistor and the second electrode of the driving transistor, and the plurality of Pixel circuit where the select transistors are controlled by different data rate control signals. According to claim 11,
A pixel circuit wherein the plurality of adjustment capacitors each have the same capacity or different capacities. According to claim 11,
A pixel circuit wherein a plurality of data transfer rate control signal lines supplying a plurality of data transfer rate control signals that control the plurality of selection transistors are arranged parallel to a gate line supplying the scan signal. According to claim 11,
A pixel circuit in which a plurality of data transfer rate control signal lines supplying a plurality of data transfer rate control signals that control the plurality of selection transistors are arranged parallel to a data line supplying the data voltage. According to claim 7,
A pixel circuit further comprising a storage capacitor disposed between the gate electrode of the driving transistor and the second electrode of the driving transistor and connected in parallel with the storage capacity adjustment unit. A display panel including a plurality of subpixels; and
A display panel driving circuit that writes pixel data of an input image to the sub-pixels and outputs a data transfer rate control signal,
Each of the subpixels includes a pixel circuit,
The pixel circuit is,
light emitting device;
A driving transistor having a first electrode connected to a high-potential voltage supply line and a second electrode connected to an anode of the light-emitting device to control a current flowing in the light-emitting device; and
A storage capacity adjuster that adjusts the capacity of a storage capacitor between the gate electrode and the second electrode of the driving transistor according to the data transfer rate control signal,
The storage capacity adjusting unit is an electroluminescence display device including a plurality of selection transistors and a plurality of control capacitors. According to claim 16,
The storage capacity adjusting unit includes a selection transistor and an adjustment capacitor connected in series between the gate electrode of the driving transistor and the second electrode of the driving transistor, and the selection transistor is controlled by the data transfer rate control signal. . According to claim 16,
The storage capacity control unit includes one control capacitor and one selection transistor connected in series to form a pair, and each pair is connected in parallel between the gate electrode of the driving transistor and the second electrode of the driving transistor, and the plurality of An electroluminescent display device in which the selection transistors are controlled by different data rate control signals. According to claim 16,
The electroluminescent display device further includes a storage capacitor disposed between the gate electrode of the driving transistor and the second electrode of the driving transistor and connected in parallel with the storage capacity adjustment unit.