KR20190052822A - Electroluminescent Display Device - Google Patents

Abstract

According to the present invention, each pixel placed in an n-th horizontal pixel line (n is a natural number) in an electroluminescent display device comprises: a driving element in which a gate electrode is connected to a node N1 and a first electrode and a second electrode are connected to a node N2 and a node N3, respectively, and which generates driving currents according to gate-source voltages; a capacitor Cb of which one side electrode is connected to the node N1; a switch element ST2 which is connected between the other electrode of the capacitor Cb and a data line; a switch element ST3 which is connected between the node N2 and a first power line; and a light emitting element which is connected between the node N2 and an input end of a low level potential power voltage, and emits light according to the driving currents. While the switch element ST2 turns on, the switch element ST3 turns on. The present invention provides an electroluminescent display device which changes a compensating circuit applied in each pixel to improve data transmission rates, and enhances accuracy of threshold voltage compensation and uniformity of an image quality.

Description

[0001] Electroluminescent Display Device [0002]

The present invention relates to an electroluminescent display device.

An electroluminescent display device is classified into an inorganic light emitting display device and an organic light emitting display device depending on the material of the light emitting layer. Among them, an active matrix type organic light emitting display device includes an organic light emitting diode (OLED) that emits light by itself, has a high response speed, There is an advantage of a large viewing angle.

The organic light emitting display device arranges pixels each including an OLED in a matrix form and adjusts the brightness of the pixels according to the gradation of the image data. Each of the pixels includes a driving TFT (Thin Film Transistor) for controlling the driving current flowing in the OLED according to the gate-source voltage, and at least one switch TFT for programming the gate-to-source voltage of the driving TFT, The display gradation (luminance) is adjusted by the amount of light emitted by the OLED.

In order to realize a uniform image quality without luminance and color difference between pixels, the driving characteristic of a pixel equal to the threshold voltage of the driving TFT must be the same in all pixels. However, there may be variations in driving characteristics between pixels due to process variations. In addition, the deterioration progress speed between the pixels may be different according to the driving time of the display device, so that the difference in driving characteristics between the pixels may be large. Such a driving characteristic deviation can change the amount of driving current flowing to the OLED, resulting in non-uniformity of image quality among the pixels.

Accordingly, an internal compensation circuit for compensating a driving characteristic difference between pixels is applied to the OLED display in order to improve image quality and lifetime of the display device. The internal compensation circuit can be applied within the pixel. The organic light emitting display uses a compensation circuit in the pixel to sample the gate-source voltage of the driving TFT which changes according to the threshold voltage of the driving TFT and compensates the threshold voltage change of the driving TFT with the sampled voltage.

However, the conventional electroluminescent display device to which the compensation circuit is applied in the pixel has the following problems.

First, in the conventional electroluminescent display device, when the data voltage is written to the gate electrode of the driving TFT, the potential of the source electrode of the driving TFT is changed and the data transmission rate may be lowered. The data transfer rate represents the ratio of the amount of change of the data voltage to the amount of change of the gate-source voltage of the driving TFT. When the data transfer rate is low, the output voltage range of the source driver that outputs the data voltage must be widened, so that the power consumption can be increased.

Second, the conventional electroluminescent display device has a storage capacitor and an additional capacitor connected in parallel to the source electrode of the driving TFT to increase the data transmission rate. The additional capacitor is connected between the source electrode of the driving TFT and the high potential power supply voltage to minimize the source potential change of the driving TFT when the data voltage is written to the gate electrode of the driving TFT. Additional capacitors may have pixel-to-pixel variations depending on process conditions. In such a pixel structure, the gate-source voltage and the driving current amount of the driving TFT can be sensitively changed according to the deviation of the additional capacitor, and it is difficult to obtain uniformity of image quality.

Third, since the conventional electroluminescent display device stores the threshold voltage of the driving TFT in the sampling period in the source electrode of the driving TFT, when the driving TFT is turned on in the data writing period subsequent to the sampling period, The threshold voltage loss of the driving TFT is inevitable and the accuracy of compensation is reduced.

Accordingly, the present invention provides an electroluminescent display device capable of improving the data transmission rate and improving the accuracy of threshold voltage compensation and image quality uniformity by changing a compensation circuit applied to each pixel.

An electroluminescent display device according to the present invention includes a display panel to which a plurality of pixels are connected to a data line to which a data voltage is supplied, a first power source line to which a reference voltage is supplied, and a second power source line to which a high- In each of the pixels arranged in the nth horizontal pixel line (n is a natural number) of the pixels, the gate electrode is connected to the node N1, the first electrode and the second electrode are connected to the node N2 and the node N3, A driving device for generating a driving current according to a voltage between sources; A capacitor Cb having one electrode connected to the node N1; A switch element ST2 connected between the other electrode of the capacitor Cb and the data line; A switch element ST3 connected between the node N2 and the first power supply line; And a light emitting element which is connected between the node N2 and an input terminal of a low potential power supply voltage and emits light in accordance with the driving current, and the switch element ST3 is turned on while the switching element ST2 is turned on.

In each pixel disposed in the nth horizontal pixel line, while the data voltage is reflected to the potential of the node N1 by the turn-on of the switch element ST2, the potential of the node N2 is turned on To the reference voltage.

Each pixel disposed in the nth horizontal pixel line includes a switch element ST1 connected between the node N1 and the node N3; A capacitor Cst connected between the node N1 and the node N2; And a switch element ET connected between the second power supply line and the node N3.

One frame period includes a sampling period for sampling a threshold voltage of the driving element; A data writing period in which the data voltage is reflected to the potential of the node N1 after the sampling period; And a light emitting period for causing the light emitting element to emit light in accordance with the driving current in which the threshold voltage is compensated following the data writing period.

During the sampling period, the threshold voltage of the driving device is sampled and stored in the node N1.

The switch element ST1 is switched according to the n-1 scan signal 1, and the switch element ST2 is switched according to the n-th scan signal 1 having a slower on period than the n-1 scan signal 1, The element ST3 is switched according to the nth scan signal 2 overlapping the ON period with the nth scan signal 1 and the nth scan signal 1, and the switch element ET is switched between the nth scan signal 2 and the ON period Lt; / RTI > is switched in accordance with the opposite n-th emission signal.

The nth scan signal 1 is input to the on level during the sampling period and is input to the off level during the data write period and the light emission period, The n-th scan signal is input at an ON level during the sampling period and the data writing period and is input at an OFF level during the light emitting period, The nth emission signal is input at an off level during the sampling period and the data write period and is input to the on level during the light emission period.

The switch element ST1 is switched according to the (n-1) th scan signal, and the switch element ST2 and the switch element ST3 are switched according to the n-th scan signal having a slower on period than the (n-1) The switch element ET is switched according to the n-th emission signal and the n-th emission signal whose phase is opposite to that of the n-th scan signal.

The on period of the n-th scan signal is partially overlapped with the on period of the (n-1) th scan signal.

And the nth scan signal is input to the on level during the sampling period and the off period during the data write period and the light emission period, And the nth emission signal is input at an off level during the sampling period and the data write period and is input to the on level during the light emission period.

The capacitance of the capacitor Cb is larger than the capacitance of the capacitor Cst.

The capacitance of the capacitor Cb is 2 to 6 times larger than the capacitance of the capacitor Cst.

During the data write period, an initialization voltage is applied to the data line before the data voltage.

According to the electroluminescence display device of the present invention, the compensation circuit applied to each pixel can be changed to improve the data transmission rate and improve the accuracy of the threshold voltage compensation and the image quality uniformity.

The effects according to the present specification are not limited by the contents exemplified above, and a more various effects are included in the specification.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention.
2 is a view illustrating a pixel array of an electroluminescent display device according to an embodiment of the present invention.
3 is a diagram showing one equivalent circuit of the pixel shown in Fig.
4 is a waveform diagram showing driving signals input to the pixel of FIG.
5A is an equivalent circuit diagram showing the operation of a pixel during the sampling period of FIG.
5B is an equivalent circuit diagram showing the operation of the pixel during the data write period of FIG.
5C is an equivalent circuit diagram showing the operation of the pixel during the light emission period of FIG.
6 is a graph showing potentials and gate-source voltages of specific nodes of a pixel corresponding to the sampling period and the data writing period of FIG.
7 is a simulation result in which the driving current deviation according to the threshold voltage change according to the present invention is compared with the prior art.
FIG. 8 is a simulation result in which the driving current deviation according to the capacitor Cb deviation according to the present invention is compared with the conventional technique.
FIGS. 9 and 10 are simulation results showing the data transfer rate and the change in gate-source voltage according to Cb / Cst.
11 is a view showing a pixel array of an electroluminescent display device according to another embodiment of the present invention.
12 is a diagram showing one equivalent circuit of the pixel shown in Fig.
13 is a waveform diagram showing driving signals input to the pixel of FIG.
14A is an equivalent circuit diagram showing the operation of a pixel during the sampling period of FIG.
14B is an equivalent circuit diagram showing the operation of the pixel during the data write period of FIG.
14C is an equivalent circuit diagram showing the operation of the pixel during the light emission period of FIG.

Brief Description of the Drawings The advantages and features of the present disclosure, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that the description is not limited to the embodiments disclosed herein but is to be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, To fully inform the category of the specification. The scope of the present disclosure is defined only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description of the present invention, a detailed description of known related arts will be omitted when it is determined that the gist of the present specification may be unnecessarily obscured. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical concept of the present specification.

Like reference numerals refer to like elements throughout the specification.

It is to be understood that each of the features of the various embodiments of the present disclosure may be combined or combined with each other, partially or wholly, and technically various interlocking and driving are possible, and that the embodiments may be practiced independently of each other, It is possible.

In this specification, the pixel circuit formed on the substrate of the display panel can be realized by the TFT of the N type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, but the technical idea of the present invention is not limited thereto. A TFT is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers begin to flow from the source. The drain is an electrode in which the carrier exits from the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an N-type TFT (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an N-type TFT, the direction of the current flows from the drain to the source because electrons flow from the source to the drain. On the other hand, in the case of the P-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a P-type TFT, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. Therefore, in the description of the embodiments, one of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. The component names used in the following description are selected in consideration of easiness of specification, and may be different from the parts names of actual products. In the following embodiments, an electric field display device will be described mainly with respect to an organic light emitting display device including an organic light emitting material. However, the technical idea of the present invention is not limited to the organic light emitting display, but can be applied to an inorganic light emitting display device including an inorganic light emitting material.

1 is an electroluminescent display according to an embodiment of the present invention.

1, an electroluminescent display device according to the present invention includes a display panel 10 having pixels PXL, display panel driving circuits 12 and 13 for driving signal lines connected to the pixels PXL, And a timing controller 11 for controlling the display panel drive circuits 12 and 13. [

The display panel drive circuits 12 and 13 write the input image data (DATA) to the pixels PXL of the display panel 10. [ The display panel driving circuits 12 and 13 include a source driver 12 for driving the data lines 14 connected to the pixels PXL and a gate driver 15 for driving the gate lines 15 connected to the pixels PXL. And a driver 13.

The display panel 10 may include an active area AA having a pixel array and a non-display area outside the active area AA. In the active area AA, a plurality of data lines 14 and a plurality of gate lines 15 are crossed, and the pixels PXL are arranged in a matrix form. The pixels PXL may include an OLED. The OLED, which is a self-luminous element, includes an anode electrode, a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a power source voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons. As a result, the light emitting layer (EML) Thereby generating visible light.

Each of the pixels PXL may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel. The red pixel, the green pixel, the blue pixel, and the white pixel may constitute one unit pixel for color implementation. The color implemented in the unit pixel may be determined according to the emission ratio of the red pixel, the green pixel, the blue pixel, and the white pixel. On the other hand, a white pixel in a unit pixel can be omitted.

Each of the pixels PXL includes a driving element, a light emitting element, and an internal compensation circuit. The internal compensation circuit may be implemented with a plurality of switch elements and a plurality of capacitors. Each of the pixels PXL may be configured as shown in FIG. 3 or 12 so as to improve the data transmission rate, be insensitive to the capacitor deviation, and sufficiently compensate the threshold voltage of the driving device.

In the case of the pixel PXL shown in FIG. 3 or 12, since the source electrode potential of the driving element is fixed to the reference voltage while the data voltage is written to the gate electrode of the driving element, the data transfer rate can be improved. The data transfer rate represents the ratio of the amount of change of the data voltage to the amount of change of the gate-source voltage of the driving element. If the data transmission rate is improved, the output voltage range of the source driver 12 for outputting the data voltage need not be widened, which is effective for reducing power consumption.

In the case of the pixel PXL as shown in Fig. 3 or 12, it has a capacitor connecting structure which prevents the gate-source voltage and the driving current amount of the driving TFT from being sensitively affected by the deviation of the capacitor Cb.

In the case of the pixel PXL shown in FIG. 3 or 12, since the threshold voltage of the driving element is stored in the gate electrode of the driving element in the sampling period, when the driving element is turned on in the data writing period subsequent to the sampling period, The threshold voltage distortion of the driving element can be suppressed even if the source potential of the driving transistor is changed.

The timing controller 11 receives digital data (DATA) of an input image from the host system and a timing signal synchronized with the digital data (DATA). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. The host system may be any one of a TV system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The timing controller 11 multiplies the input frame frequency by i (i is a positive integer larger than 0) times and controls the operation timing of the display panel driving circuits 12 and 13 at the frame frequency of the input frame frequency x i Hz have. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the PAL (Phase-Alternating Line) system.

The timing controller 11 generates a data timing control signal DDC for controlling the operation timing of the source driver 12 based on the timing signals Vsync, Hsync and DE received from the host system, And generates a gate timing control signal GDC for controlling the operation timing.

The data timing control signal DDC includes a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the sampling start timing of the source driver 12. [ The source sampling clock is a clock for shifting the data sampling timing. If the signal transfer interface between the timing controller 11 and the source driver 12 is a mini LVDS (Low Voltage Differential Signaling) interface, the source start pulse and the source sampling clock may be omitted.

The gate timing control signal GDC includes a gate start pulse, a gate shift clock, a gate output enable signal, and the like. In the case of the GIP circuit, the gate output enable signal (Gate Output Enable) may be omitted. The gate start pulse is generated at the beginning of the frame period every frame period and is input to the shift register of each gate driver 13. [ The gate start pulse is a signal for outputting the scan signals SC (1) to SC (4) and the emission signals EM1 (1) to EM1 (4), EM2 (1) Controls the start timing. The gate shift clock is input to the shift register of the gate driver 13 to control the shift timing of the gate signal.

The source driver 12 converts the input video data DATA received from the timing controller 11 every frame into a data voltage Vdata and supplies the data voltage Vdata to the data lines 14 . The source driver 12 outputs the data voltage Vdata using a digital to analog converter that converts the input image data DATA to a gamma compensation voltage.

A multiplexer (not shown) may be further disposed between the source driver 12 and the data lines 14 of the display panel 10. [ The multiplexer can reduce the number of output channels of the source driver 12 to the number of data lines by distributing the data voltages output through one output channel from the source driver 12 to the plurality of data lines. The multiplexer can be omitted depending on the resolution and usage of the display device.

The source driver 12 may further include a power generator. The power generation unit generates an initialization voltage and supplies the generated initialization voltage to the data line 14 to generate a reference voltage Vref and supply it to the reference power supply line 16 to generate a high potential power supply voltage EVDD, 17). The power generation section may further generate the low potential power supply voltage EVSS. The power generator may be electrically connected to the source driver 12 through a conductive film or the like after being mounted outside the source driver 12. The reference voltage Vref can be set within a voltage range sufficiently lower than the operating point voltage of the OLED so that unnecessary emission of the OLED is prevented during the sampling period and the data writing period.

The gate driver 13 may include a scan driver for generating a scan signal and an emission driver for generating an emission signal. The scan driver and the emission driver can be variously modified depending on the pixel structure.

The scan driver may have a plurality of stages and may output scan signals sequentially shifted in on-duration to the gate lines under the control of the timing controller 11. The scan driver may be implemented as a shift register and may be connected to the gate lines through a plurality of output nodes.

The emission driving unit has a plurality of stages and can output emission signals to the gate lines under the control of the timing controller 11 in which the ON periods are sequentially shifted. The emission driver may be implemented as a shift register and may be connected to the gate lines through a plurality of output nodes.

The gate driver 13 may be formed directly on the non-display region of the display panel 10 together with the pixel array in a gate-driver In Panel (GIP) process, but is not limited thereto. The gate driver 13 may be manufactured in an IC type and then bonded to the display panel 10 through a conductive film.

2 is a view illustrating a pixel array of an electroluminescent display device according to an embodiment of the present invention.

Referring to FIG. 2, a plurality of horizontal pixel lines HL1 to HL4 are provided in a pixel array of the active area AA. Horizontal pixel lines HL1 to HL4 are horizontally adjacent to the horizontal pixel lines L1 to L4, A plurality of pixels PXL connected in common to the pixels 15a, 15b and 15c are arranged. Here, each of the horizontal pixel lines L1 to L4 is not a physical signal line but a pixel group of one line which is implemented by horizontally neighboring pixels PXL. The pixel array may include a reference power supply line 16 for supplying a reference voltage Vref to the pixels PXL and a high potential power supply line 17 for supplying a high potential power supply voltage EVDD to the pixels PXL have. Further, the pixels PXL may be connected to the low potential power supply voltage EVSS.

Each of the gate lines 15 included in the active area AA includes a first gate line 15a to which the first scan signal SC1 is supplied, a second gate line 15b to which the second scan signal SC2 is supplied, And a third gate line 15c to which the emission signal EM is supplied. (N), SC2 (n), SC2 (n), and SC2 (n) are assigned to each pixel PXL arranged in the nth horizontal pixel line L 1) th scan signal 1 (SC1 (n-1)) assigned to the (n-1) th horizontal pixel line L (n-1) in addition to the nth emission signal EM Can be supplied.

1 scan signal 1 (SC1 (n-1)) and the nth scan signal 1 (SC1 (n)) to the three scan signals applied to the pixels PXL of the nth horizontal pixel line Ln, And the nth scan signal 2 (SC2 (n)), the two gate drivers can drive the pixels PXL of the nth horizontal pixel line Ln, so that the configuration of the gate driver 13 can be simplified There is an advantage to be able to. In this case, since the n-th scan signal SC1 (n) and the n-1 scan signal SC1 (n-1) are gate signals successively output from a single gate driver, May be different.

3 is an equivalent circuit of the pixel shown in Fig.

3, a pixel PXL according to an embodiment of the present invention includes an OLED, a plurality of thin film transistors (ST1 to ST3, DT, ET), and a plurality of capacitors Cst and Cb do. The TFTs (ST1 to ST3, DT, ET) can be implemented as an NMOS type LTPS TFT, and fast response characteristics can be ensured through this. However, the technical idea of the present specification is not limited thereto. For example, at least one TFT among the switch TFTs (ST1 to ST3, ET) may be implemented as an NMOS type oxide TFT having good off-current characteristics.

Hereinafter, a connection configuration of one pixel PXL arranged on the nth horizontal pixel line will be described in detail.

The OLED is a light emitting element that emits light in accordance with a driving current flowing in the driving TFT DT. The anode electrode of the OLED is connected to the node N2, and the cathode electrode of the OLED is connected to the input terminal of the low potential power supply voltage (EVSS). An organic compound layer is provided between the anode electrode and the cathode electrode.

The driving TFT DT is a driving element for adjusting a driving current applied to the OLED according to a gate-source voltage. The driving TFT DT includes a gate electrode connected to the node N1, a first electrode (source electrode) connected to the node N2, and a second electrode (drain electrode) connected to the node N3.

The first switch TFT ST1 is a switch element connected between the node N1 and the node N3 and operated according to the (n-1) th scan signal 1 (SC1 (n-1)). The first switch TFT (ST1) is turned on during the sampling period (1) of Fig. 4 to diode-connect the drive TFT (DT). The threshold voltage of the driving TFT DT is sampled by the diode connection of the driving TFT DT and stored in the node N1. The gate electrode of the first switch TFT ST1 is connected to the (n-1) th first gate line 15a (n-1) to which the n-1 scan signal 1 (SC1 The first electrode of the first switch TFT (ST1) is connected to the node N3, and the second electrode of the first switch TFT (ST1) is connected to the node N1.

The first capacitor Cst is connected between the node N1 and the node N2. The first capacitor Cst maintains the gate-source voltage of the driving TFT DT during the light emission period (3) in Fig.

One electrode of the second capacitor Cb is connected to the node N1 and the other electrode of the second capacitor Cb is connected to the second switch TFT ST2. The second capacitor Cb reflects the initial voltage Vin and the data voltage Vdata applied through the second switch TFT ST2 to the potential of the node N1 during the data writing period (2) in Fig.

The second switch TFT ST2 is a switch element connected between the data line 14 and the other electrode of the second capacitor Cb and operated in accordance with the n-th scan signal SC1 (n). The second switch TFT ST2 is turned on during the data write period (2) of Fig. 4 to apply the initialization voltage Vin and the data voltage Vdata to the other electrode of the second capacitor Cb. The gate electrode of the second switch TFT ST2 is connected to the nth first gate line 15a (n) to which the nth scan signal 1 (SC1 (n)) is applied and the gate electrode of the first switch TFT One electrode is connected to the data line 14 and the second electrode of the first switch TFT ST1 is connected to the other electrode of the second capacitor Cb.

The third switch TFT ST3 is a switch element connected between the reference power supply line 16 and the node N2 and operated in accordance with the nth scan signal 2 (SC2 (n)). The third switch TFT (ST3) is turned on during the sampling period (1) and the data write period (2) in Fig. 4 to apply the reference voltage (Vref) to the node N2. The gate electrode of the third switch TFT ST3 is connected to the nth second gate line 15b (n) to which the nth scan signal 2 (SC2 (n)) is applied, and the gate of the third switch TFT ST3 One electrode is connected to the reference power supply line 16, and the second electrode of the third switch TFT (ST3) is connected to the node N2.

The fourth switch TFT ET is a switch element connected between the high potential power supply line 17 and the node N3 and operated in accordance with the nth emission signal EM (n). The fourth switch TFT ET is turned off during the sampling period (1) and the data writing period (2) in FIG. 4 to block the high potential power supply voltage EVDD applied to the node N3, ) To apply a high potential power supply voltage (EVDD) to the node N3. The gate electrode of the fourth switch TFT ET is connected to the nth third gate line 15c (n) to which the nth emission signal EM (n) is applied, One electrode is connected to the high potential power supply line 17, and the second electrode of the fourth switch TFT ET is connected to the node N3.

The nth emission signal EM (n) for controlling the operation of the fourth switch TFT ET may be continuously input at the ON level during the light emission period (3) in FIG. 4, And may be input at an off level for a predetermined time. Thus, the nth emission signal EM (n) can switch ON / OFF of the fourth switch TFT ET at a predetermined PWM (Pulse Width Modulation) duty ratio. The pixels PXL are repeatedly turned on and off with a duty ratio of about 50% within a duty ratio range of about 20% to 90% by the nth emission signal EM (n) during the light emission period (3) The flicker and the afterimage can be minimized. The technical idea of the present invention is not limited to a specific duty ratio.

On the other hand, the fourth switch TFT (ET) may be omitted. In this case, the high-potential power supply voltage EVDD can be supplied at two levels. Is supplied at the off level during the sampling period (1) and the data write period (2) in FIG. 4, and can be supplied at the on level during the light emission period (3) in FIG.

4 is a waveform diagram showing driving signals input to the pixel of FIG. 5A, 5B and 5C are equivalent circuit diagrams showing the operation of the pixels during the sampling period, the data writing period, and the light emitting period, respectively, in FIG. 6 is a graph showing potentials and gate-source voltages of specific nodes of a pixel corresponding to the sampling period and the data writing period of FIG.

4, one frame period for driving each pixel PXL disposed on the nth horizontal pixel line Ln is divided into a sampling period ①, a data writing period ② following the sampling period ➀, , And a light emitting period (3) following the data writing period (2).

Referring to FIG. 4, the n-th scan signal SC1 (n) has a slower on-duration than the n-1 scan signal SC1 (n-1). The nth scan signal 2 (SC2 (n)) is overlapped with the nth scan signal 1 (SC1 (n-1)) and the nth scan signal 1 (SC1 (n)). The n-th emission signal EM (n) is opposite in phase to the n-th scan signal 2 (SC2 (n)).

Referring to FIG. 4, the n-1 scan signal 1 (SC1 (n-1)) and the nth scan signal 2 (SC2 (n) The nth scan signal 1 (SC1 (n)) and the nth emission signal EM (n) are inputted at the off level (OFF). The sampling period (1) is for sampling the threshold voltage of the driving TFT DT.

Referring to FIG. 5A, the first switch TFT ST1 is turned on in response to the n-1 scan signal 1 (SC1 (n-1)) of the on level (ON) during the sampling period The third switch TFT (ST3) is turned on in response to the n-th scan signal 2 (SC2 (n)) of the first switch TFT (ON).

During the sampling period (1), the first switch TFT (ST1) is turned on, so that the gate electrode and the drain electrode of the drive TFT DT are shorted to each other, and the drive TFT DT operates as a diode. That is, the gate electrode and the drain electrode of the driving TFT DT are short-circuited, and the driving TFT DT is diode-connected. At this time, if the reference voltage Vref is applied to the node N2 by turning on the third switch TFT ST3, the voltage of the node N1 and the node N3 becomes "Vref + Vth" by the drive TFT DT operating as a diode, . Here, " Vth " is the threshold voltage of the driving TFT DT. 6, the potential of the node N1 becomes "Vref + Vth", the potential of the node N2 becomes "Vref", and the gate-source voltage Vgs of the drive TFT DT becomes " Becomes the threshold voltage Vth of the driving TFT DT. The threshold voltage Vth of the driving TFT DT is stored in the node N1.

On the other hand, the second switch TFT (n) is turned on in response to the n-th scan signal 1 (SC1 (n)) of the off level (OFF) so that the threshold voltage Vth of the drive TFT DT can be accurately sampled during the sampling period The fourth switch TFT ET is turned off in response to the n-th emission signal EM (n) of OFF level (OFF).

4, the nth scan signal 1 (SC1 (n)) and the nth scan signal 2 (SC2 (n)) are inputted to the ON level (ON) in the data writing period 1 scan signal 1 (SC1 (n-1)) and the nth emission signal EM (n) are input at OFF level (OFF). The data writing period (2) is for reflecting the data voltage (Vdata) to the potential of the node N1.

5B, the second switch TFT ST2 is turned on and the on-level (ON) is turned on in response to the n-th scan signal 1 (SC1 (n)) of the on level (ON) The third switch TFT (ST3) maintains the on state in response to the nth scan signal 2 (SC2 (n)). The first switch TFT ST1 is turned off in response to the n-1 scan signal 1 (SC1 (n-1)) of the OFF level (OFF) during the data writing period (2) The fourth switch TFT ET maintains the OFF state in response to the nth emission signal EM (n)

The initializing voltage Vin is applied to the data line 14 for a predetermined period of time XX before the data voltage Vdata in the data writing period ② and the initializing voltage Vin is applied to the other side of the data line 14 and the second capacitor Cb Thereby resetting the electrode potential. The reason for performing the reset operation is to minimize errors in threshold voltage compensation and gradation representation.

The initialization voltage Vin and the data voltage Vdata are successively applied to the other electrode of the second capacitor Cb by the turn-on of the second switch TFT ST2 during the data writing period (2). When the data voltage Vdata is applied, the potential of the other electrode of the second capacitor Cb becomes "C '(Vdata-Vin)". Here, C 'is "CB / (CB + CST)". CB is the capacitance of the second capacitor Cb, and CST is the capacitance of the first capacitor Cst.

At this time, since the node N1 is coupled to the second capacitor Cb in a floating state by the turn-off of the first switch TFT (ST1), the potential of the node N1 becomes "Vref + Vth + C Vdata-Vin) ".

The third switch TFT (ST3) remains on even during the data writing period (2). Therefore, in spite of the potential change of the node N1 during the data writing period (2), the potential of the node N2 is fixed to " Vref " The source electrode potential of the driving TFT DT is fixed to the reference voltage Vref while the data voltage Vdata is written to the gate electrode of the driving TFT DT so that the data transmission rate can be improved. The gate-source voltage Vgs of the driving TFT DT during the data writing period (2) is programmed to be "Vth + C '(Vdata-Vin)" as shown in FIG. 6 and the programmed gate- Vgs are stored in the first capacitor Cst.

Referring to FIG. 4, in the light emission period (3), the n-1 scan signal 1 (SC1 (n-1)), the nth scan signal 1 (SC1 ) Is input to the off level (OFF), and the nth emission signal EM (n) is input to the ON level (ON). The light emitting period (3) is for causing the OLED to emit light in accordance with the driving current flowing in the driving TFT DT.

Referring to FIG. 5C, the fourth switch TFT ET is turned on in response to the n-th emission signal EM (n) of the on level ON during the light emission period (3) The first to third switch TFTs ST1 to ST3 are turned off in response to the scan signals SC1 (n-1), SC1 (n), and SC2 (n).

During the light emission period (3), the high-potential power supply voltage EVDD is applied to the node N3 by the turn-on of the fourth switch TFT (ET). During the light emission period (3), the gate-source voltage Vgs of the driving TFT DT is maintained at "Vth + C" (Vdata-Vin) by the first capacitor Cst. Therefore, a driving current proportional to the square of the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs, that is, "C '(Vdata-Vin)" is applied to the driving TFT DT during the light emission period Flows. The driving current Ioled flowing through the OLED during the light emission period (3) is a function irrespective of the threshold voltage (Vth) of the driving TFT (DT) as shown in Equation (1). Thus, the influence of the change in the threshold voltage Vth on the drive current Ioled is eliminated.

[Equation 1]

Here, K is a constant value determined by the mobility of the driving TFT DT, the channel ratio, the parasitic capacitance, and the like.

7 is a simulation result in which the driving current deviation according to the threshold voltage change according to the present invention is compared with the prior art.

As described above, in the present invention, the threshold voltage of the driving device in the sampling period is not stored in the source electrode connected to the node N2 of the driving device, but is stored in the gate electrode connected to the node N1. Therefore, the present invention can suppress the threshold voltage distortion of the driving element even when the source potential of the driving element is changed when the driving element is turned on in the data writing period, and can accurately compensate the threshold voltage. In other words, according to the present invention, the accuracy of the threshold voltage compensation is improved, and the driving current deviation according to the threshold voltage change is drastically reduced as compared with the prior art as shown in FIG.

FIG. 8 is a simulation result in which the driving current deviation according to the capacitor Cb deviation according to the present invention is compared with the conventional technique.

As described above, the present invention has a capacitor connecting structure that prevents the gate-source voltage and the driving current amount of the driving TFT from being sensitively affected by the process variation of the second capacitor Cb. The change amount? Vgs of the gate-source voltage of the drive TFT in accordance with the process variation of the second capacitor Cb is "CB / (CB + CST) * Vdata". Here, CB is the capacitance of the second capacitor Cb, and CST is the capacitance of the first capacitor Cst. Since the CB is included in both the denominator and the molecule in the equation of the change amount of the gate-source voltage (? Vgs), the change amount? Vgs of the gate-source voltage and the drive current variation amount? Compared to the previous year.

FIGS. 9 and 10 are simulation results showing the data transfer rate and the change in gate-source voltage according to Cb / Cst.

9 and 10, the data transfer rate and the gate-source voltage Vgs of the driving TFT are changed according to the ratio between the first and second capacitors Cst and Cb, Cb / Cst. In order to improve the data transfer rate, it is desirable to design the capacitance of the second capacitor Cb to be larger than that of the first capacitor Cst. However, it is difficult to design the capacitance of the second capacitor Cb too large in consideration of the aperture ratio of the pixel. According to the experiment, it is preferable that the capacity of the second capacitor Cb is designed to be 2 to 6 times larger than the capacity of the first capacitor Cst. In this case, the data transmission rate could be improved without significantly lowering the pixel aperture ratio.

11 is a view showing a pixel array of an electroluminescent display device according to another embodiment of the present invention.

Referring to FIG. 11, a plurality of horizontal pixel lines HL1 to HL4 are provided in a pixel array of the active area AA, horizontally neighboring pixels of the horizontal pixel lines L1 to L4, A plurality of pixels PXL connected in common to the pixels 15a and 15b are disposed. The pixel array may include a reference power supply line 16 for supplying a reference voltage Vref to the pixels PXL and a high potential power supply line 17 for supplying a high potential power supply voltage EVDD to the pixels PXL have. Further, the pixels PXL may be connected to the low potential power supply voltage EVSS.

Each of the gate lines 15 included in the active area AA includes a first gate line 15a to which a scan signal SC is supplied and a second gate line 15b to which an emission signal EM is supplied do. Each of the pixels PXL disposed in the nth horizontal pixel line L (n) is supplied with an nth scan signal SC (n) and an nth emission signal SC (n) 1 scan signal SC (n-1) allocated to the (n-1) th horizontal pixel line L (n-1) other than the scan signal EM (n).

If the ON period of the n-th scan signal SC (n) and the ON period of the (n-1) th scan signal SC (n-1) are partially overlapped, the scan signals applied to the pixels PXL Can be reduced to two. The two scan signals applied to the pixels PXL of the nth horizontal pixel line Ln are divided into an n-1 scan signal SC (n-1) and an nth scan signal SC (n) It is possible to drive the pixels PXL of the nth horizontal pixel line Ln with one gate driving unit, which is advantageous in that the configuration of the gate driver 13 can be simplified. In this case, since the (n-1) th scan signal SC (n-1) and the n th scan signal SC (n) are gate signals successively output from a single gate driver, can be different.

12 is a diagram showing one equivalent circuit of the pixel shown in Fig.

12, the pixel PXL according to another embodiment of the present invention has the same structure as the pixel PXL of FIG. 3 except that the second and third switch TFTs ST2 and ST3 are connected to the same n-th scan signal SC (n)) and that the gate electrode of the fourth switch TFT ET is connected to the n-th second gate line 15b (n), and the remainder is substantially the same as the pixel PXL of Fig. 3 Do.

The second switch TFT ST2 is a switch element connected between the data line 14 and the other electrode of the second capacitor Cb and operated in accordance with the nth scan signal SC (n). The second switch TFT ST2 is turned on during the sampling period (1) and the data write period (2) in FIG. 13 to apply the initialization voltage Vin and the data voltage Vdata to the other electrode of the second capacitor Cb do. The gate electrode of the second switch TFT ST2 is connected to the nth first gate line 15a (n) to which the nth scan signal SC (n) is applied, and the first switch TFT (ST1) The electrode is connected to the data line 14 and the second electrode of the first switch TFT ST1 is connected to the other electrode of the second capacitor Cb.

The third switch TFT ST3 is a switch element connected between the reference power supply line 16 and the node N2 and operated in accordance with the n-th scan signal SC (n). The third switch TFT (ST3) is turned on during the sampling period (1) and the data writing period (2) in FIG. 13 and applies the reference voltage Vref to the node N2. The gate electrode of the third switch TFT ST3 is connected to the nth first gate line 15a (n) to which the nth scan signal SC (n) is applied, and the gate electrode of the third switch TFT (ST3) The electrode is connected to the reference power supply line 16, and the second electrode of the third switch TFT (ST3) is connected to the node N2.

The fourth switch TFT ET is a switch element connected between the high potential power supply line 17 and the node N3 and operated in accordance with the nth emission signal EM (n). The fourth switch TFT ET is turned off during the sampling period (1) and the data writing period (2) in FIG. 4 to block the high potential power supply voltage EVDD applied to the node N3, ) To apply a high potential power supply voltage (EVDD) to the node N3. The gate electrode of the fourth switch TFT ET is connected to the nth second gate line 15b (n) to which the nth emission signal EM (n) is applied, One electrode is connected to the high potential power supply line 17, and the second electrode of the fourth switch TFT ET is connected to the node N3.

13 is a waveform diagram showing driving signals input to the pixel of FIG. 14A, 14B and 14C are equivalent circuit diagrams showing the operation of the pixels during the sampling period, the data writing period, and the light emitting period in FIG. 13, respectively.

13, one frame period for driving each pixel PXL disposed on the nth horizontal pixel line Ln is a data writing period (2) following the sampling period (1), the sampling period (1) , And a light emitting period (3) following the data writing period (2).

Referring to FIG. 13, the n-th scan signal SC (n) has a slower on-period phase than the n-1-th scan signal SC (n-1). The ON period of the nth scan signal SC (n) is partially overlapped with the ON period of the (n-1) th scan signal SC (n-1). The nth emission signal EM (n) is opposite in phase to the nth scan signal SC (n) and the ON period.

13, the n-1 scan signal SC (n-1) and the nth scan signal SC (n) are input to the on level (ON) in the sampling period (1) The emission signal EM (n) is input to the off level (OFF). The sampling period (1) is for sampling the threshold voltage of the driving TFT DT.

14A, the first switch TFT ST1 is turned on in response to the n-1th scan signal SC (n-1) of the ON level ON during the sampling period (1) The second and third switch TFTs ST2 and ST3 are turned on in response to the n-th scan signal SC (n).

During the sampling period (1), the first switch TFT (ST1) is turned on, so that the gate electrode and the drain electrode of the drive TFT DT are shorted to each other, and the drive TFT DT operates as a diode. That is, the gate electrode and the drain electrode of the driving TFT DT are short-circuited, and the driving TFT DT is diode-connected. At this time, if the reference voltage Vref is applied to the node N2 by turning on the third switch TFT ST3, the voltage of the node N1 and the node N3 becomes "Vref + Vth" by the drive TFT DT operating as a diode, . Here, " Vth " is the threshold voltage of the driving TFT DT. 6, the potential of the node N1 becomes "Vref + Vth", the potential of the node N2 becomes "Vref", and the gate-source voltage Vgs of the drive TFT DT becomes " Becomes the threshold voltage Vth of the driving TFT DT. The threshold voltage Vth of the driving TFT DT is stored in the node N1.

On the other hand, the data voltage to be written to the (n-1) th horizontal pixel line Ln-1 is applied to the other electrode of the second capacitor Cb by the turn-on of the second switch TFT ST2 during the sampling period . The fourth switch TFT ET is turned on in response to the off-level nth emission signal EM (n) so that the threshold voltage Vth of the driving TFT DT can be accurately sampled during the sampling period (1) Is turned off.

13, the n-th scan signal SC (n) is input to the ON level (ON) in the data write period (2) n emission signal EM (n) is input at off-level (OFF). The data writing period (2) is for reflecting the data voltage (Vdata) to the potential of the node N1.

14B, the second and third switch TFTs ST2 and ST3 are turned on in response to the n-th scan signal SC (n) of the on level (ON) during the data writing period (2) do. The first switch TFT ST1 is turned off in response to the n-1th scan signal SC (n-1) of the off level (OFF) during the data writing period (2) The fourth switch TFT ET maintains the OFF state in response to the nth emission signal EM (n).

The initializing voltage Vin is applied to the data line 14 for a predetermined period of time XX before the data voltage Vdata in the data writing period ② and the initializing voltage Vin is applied to the other side of the data line 14 and the second capacitor Cb Thereby resetting the electrode potential. The reason for performing the reset operation is to minimize errors in threshold voltage compensation and gradation representation.

The initialization voltage Vin and the data voltage Vdata are successively applied to the other electrode of the second capacitor Cb by the turn-on of the second switch TFT ST2 during the data writing period (2). When the data voltage Vdata is applied, the other electrode potential of the second capacitor Cb becomes " Vdata-Vin ". At this time, since the node N1 is coupled to the second capacitor Cb in a floating state by the turn-off of the first switch TFT (ST1), the potential of the node N1 becomes "Vref + Vth + Vdata-Vin &Quot;

The third switch TFT (ST3) remains on even during the data writing period (2). Therefore, in spite of the potential change of the node N1 during the data writing period (2), the potential of the node N2 is fixed to " Vref " The source electrode potential of the driving TFT DT is fixed to the reference voltage Vref while the data voltage Vdata is written to the gate electrode of the driving TFT DT so that the data transmission rate can be improved. During the data writing period (2), the gate-source voltage Vgs of the driving TFT DT is programmed to "Vth + Vdata-Vin" as shown in FIG. 6 and the programmed gate- 1 < / RTI > capacitor Cst.

13, the n-1th scan signal SC (n-1) and the nth scan signal SC (n) are input at OFF level in the light emission period (3) The emission signal EM (n) is input to the ON level (ON). The light emitting period (3) is for causing the OLED to emit light in accordance with the driving current flowing in the driving TFT DT.

Referring to FIG. 14C, the fourth switch TFT ET is turned on in response to the n-th emission signal EM (n) of the ON level ON during the light emission period (3) The first to third switch TFTs ST1 to ST3 are turned off in response to the scan signals SC (n-1) and SC (n).

During the light emission period (3), the high-potential power supply voltage EVDD is applied to the node N3 by the turn-on of the fourth switch TFT (ET). During the light emission period (3), the gate-source voltage Vgs of the driving TFT DT maintains "Vth + Vdata-Vin" by the first capacitor Cst. Therefore, during the light emission period (3), a driving current proportional to the square of "Vdata-Vin" flows to the driving TFT DT by subtracting the threshold voltage Vth from the gate-source voltage Vgs. The driving current Ioled flowing through the OLED during the light emission period (3) becomes a function irrespective of the threshold voltage (Vth) of the driving TFT (DT) as shown in the above-mentioned equation (1). Thus, the influence of the change in the threshold voltage Vth on the drive current Ioled is eliminated.

As described above, according to the electroluminescence display device of the present invention, the compensation circuit applied to each pixel can be changed to improve the data transmission rate and improve the accuracy of the threshold voltage compensation and the image quality uniformity.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present specification should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source driver 13: Gate driver

Claims (13)

A display panel having a plurality of pixels connected to a data line to which a data voltage is supplied, a first power supply line to which a reference voltage is supplied, and a second power supply line to which a high potential supply voltage is supplied,
Each of the pixels arranged in the nth horizontal pixel line (n is a natural number)
A driving element having a gate electrode connected to the node N1, a first electrode and a second electrode respectively connected to the node N2 and the node N3, and generating a driving current according to a gate-source voltage;
A capacitor Cb having one electrode connected to the node N1;
A switch element ST2 connected between the other electrode of the capacitor Cb and the data line;
A switch element ST3 connected between the node N2 and the first power supply line; And
And a light emitting element connected between the node N2 and an input terminal of a low potential power supply voltage and emitting light according to the driving current,
And the switch element (ST3) is turned on while the switch element (ST2) is turned on. The method according to claim 1,
The potential of the node N2 is fixed to the reference voltage by the turn-on of the switch element ST3 while the data voltage is reflected to the potential of the node N1 by turning on the switch element ST2. The method according to claim 1,
Each of the pixels arranged in the nth horizontal pixel line,
A switch element ST1 connected between the node N1 and the node N3;
A capacitor Cst connected between the node N1 and the node N2; And
And a switch element (ET) connected between the second power line and the node (N3). The method of claim 3,
In one frame period,
A sampling period for sampling a threshold voltage of the driving device;
A data writing period in which the data voltage is reflected to the potential of the node N1 after the sampling period; And
And a light emitting period for causing the light emitting element to emit light in accordance with the driving current in which the threshold voltage is compensated after the data writing period. 5. The method of claim 4,
And a threshold voltage of the driving device is sampled and stored in the node N1 during the sampling period. 5. The method of claim 4,
The switch element ST1 is switched according to the (n-1) th scan signal 1,
The switch element ST2 is switched according to the n-th scan signal 1 whose phase is late in the on period compared to the n-1 scan signal 1,
The switch element ST3 is switched according to the n-th scan signal 2 and the n-th scan signal 2 which are overlapped with the n-1 scan signal 1 and the n-th scan signal 1,
Wherein the switch element (ET) is switched according to an n-th emission signal whose phase is opposite to that of the n-th scan signal (2). The method according to claim 6,
The n-1 scan signal (1) is input at an on level during the sampling period and is input at an off level during the data write period and the light emission period,
The n-th scan signal 1 is input to the off-level during the sampling period, is input to the on-level during the data writing period, is input to the off-
The nth scan signal (2) is input at the ON level during the sampling period and the data write period and is input at the OFF level during the light emission period,
Wherein the nth emission signal is input at an off level during the sampling period and the data write period and is input at an on level during the light emission period. 5. The method of claim 4,
The switch element ST1 is switched according to the (n-1) th scan signal,
The switch element ST2 and the switch element ST3 are switched according to the n-th scan signal whose on-period is slower than the (n-1) th scan signal,
Wherein the switch element (ET) is switched according to an n-th emission signal whose phase is opposite to that of the n-th scan signal. 9. The method of claim 8,
And the on period of the n-th scan signal is partially overlapped with the on period of the (n-1) th scan signal. 10. The method of claim 9,
Wherein the nth scan signal is input at an on level during the sampling period and is input at an off level during the data write period and the light emission period,
Wherein the nth scan signal is input at an ON level during the sampling period and the data write period and is input at an OFF level during the light emission period,
Wherein the nth emission signal is input at an off level during the sampling period and the data write period and is input at an on level during the light emission period. The method according to claim 1,
And the capacitance of the capacitor Cb is larger than the capacitance of the capacitor Cst. 12. The method of claim 11,
And the capacitance of the capacitor Cb is two to six times larger than the capacitance of the capacitor Cst. 5. The method of claim 4,
And an initializing voltage is applied to the data line before the data voltage during the data writing period.

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