KR20190002949A - Electroluminescent Display Device - Google Patents

Abstract

The present invention relates to an electroluminescent display device. According to the present invention, a plurality of pixels (PXL) are provided with a display panel (10) connected to a data line (14) to which a data voltage (Vdata) is supplied and a first power line (17) to which a high-level power voltage (EVDD) is supplied. Each pixel (PXL) disposed in an n^th horizontal pixel line (Ln) comprises a driving TFT (DT) in which a gate electrode, a source electrode, and a drain electrode are respectively connected to a node (N2), the first power line (17), and a node (N3); a first switch TFT (T1) switched according to an n^th scan signal (SC(n)), a second switch TFT (T2) switched according to the n^th scan signal (SC(n)), a third switch TFT (T3) switched according to an n^th emission signal (EM(n)), an organic light emitting diode connected between a node (N4) and a low potential power voltage (EVSS), and a storage capacitor (Cst) connected between the node N1 and the node N2.

Description

[0001] Electroluminescent Display Device [0002]

The present invention relates to an electroluminescent display device.

An electroluminescent display device is classified into an inorganic light emitting display device and an organic light emitting display device depending on the material of the light emitting layer. Among them, an active matrix type organic light emitting display device includes an organic light emitting diode (OLED) that emits light by itself, has a high response speed, There is an advantage of a large viewing angle.

The organic light emitting display device arranges pixels each including an OLED in a matrix form and adjusts the brightness of the pixels according to the gradation of the image data. Each of the pixels includes a driving TFT (Thin Film Transistor) for controlling the driving current flowing in the OLED according to the gate-source voltage, and at least one switch TFT for programming the gate-to-source voltage of the driving TFT, The display gradation (luminance) is adjusted by the amount of light emitted by the OLED.

In order to realize a uniform image quality without luminance and color difference between pixels, the driving characteristic of a pixel equal to the threshold voltage (Vth) of the driving TFT must be the same in all the pixels. However, there may be variations in driving characteristics between pixels due to various causes including process variations. In addition, the deterioration progress speed between the pixels may be different according to the driving time of the display device, so that the difference in driving characteristics between the pixels may be large. Therefore, the amount of driving current flowing to the OLED varies depending on the driving characteristic deviation between the pixels, thereby causing unevenness in image quality.

Accordingly, an internal compensation circuit for compensating a driving characteristic difference between pixels is applied to the OLED display in order to improve image quality and lifetime of the display device. The internal compensation circuit can be applied within the pixel. The organic light emitting display uses a compensating circuit in a pixel to sample the gate-source voltage of the driving TFT which varies depending on the electrical characteristics of the driving TFT, and compensates the data voltage with the sampled voltage.

The drive current of the OLED in the internal compensation circuit can be influenced by the high potential supply voltage (hereinafter referred to as " EVDD ") of the pixel. In this case, if the EVDD differs according to the position of the pixel in the panel due to the voltage drop of the EVDD (IR drop), the driving current of the OLED differs from the required current of the pixel, and uniform image quality can not be obtained. In order to reduce the voltage drop of the EVDD, it is possible to consider increasing the line width of the EVDD wiring. However, since the pixel area of the high-resolution panel is small, it is difficult to design the reinforcement for increasing the line width.

Currently, OLED display devices are being developed with high resolution, large area, and high brightness trend. Therefore, the width of EVDD wiring is inevitably reduced and the EVDD wiring becomes long. Therefore, there is a limit to improve the EVDD voltage drop by the EVDD resistance reduction method have.

On the other hand, the internal compensation circuit provided in each pixel requires a plurality of switch TFTs in order to increase the accuracy of compensation. The gate electrodes of these switch TFTs are connected to the gate driver through gate lines. The gate driver generates a gate signal for controlling the switching operation of the switch TFTs and supplies the gate signal to the gate lines. The larger the number of switch TFTs, the more complicated the configuration of the gate driver.

Accordingly, it is an object of the present invention to provide an electroluminescent display device capable of real-time compensation of a change in driving characteristics of a pixel regardless of an EVDD voltage drop.

It is another object of the present invention to provide an electroluminescent display device which realizes a real time compensation of a driving characteristic change of a pixel regardless of an EVDD voltage drop, and simplifies the configuration of a gate driver.

To achieve the above object, an electroluminescent display device according to the present invention includes a plurality of pixels PXL, a data line 14 to which a data voltage Vdata is supplied, and a data line 14 to which a high potential power supply voltage EVDD is supplied. And a display panel (10) connected to the power line (17). Each pixel PXL disposed in the nth horizontal pixel line Ln is connected to the driving TFT DT connected to the gate electrode, the source electrode, and the drain electrode at the node N2, the first power source line 17 and the node N3, ; A first switch TFT (T1) connected between the node N2 and the node N3 and switched in accordance with the n-th scan signal SC (n); A second switch TFT (T2) connected between the data line (14) and a node (N1) and switched according to the nth scan signal (SC (n)); A third switch TFT (T3) connected between the node N3 and the node N4 and switched in accordance with the nth emission signal EM (n); An organic light emitting diode connected between the node N4 and a low potential power supply voltage (EVSS); And a storage capacitor Cst connected between the node N1 and the node N2. Here, in the compensation period B for sampling the threshold voltage Vth of the driving TFT DT, the first and second switch TFTs T1 and T2 are turned on by the nth scan signal SC ( n), and the third switch TFT T3 is turned off according to the nth emission signal EM (n) at the off level.

Since the OLED current of a pixel is not affected by EVDD, the present invention can realize a uniform image quality on the entire screen without a low resistance design of the EVDD wiring, and realize a high resolution and large-screen electroluminescent display device.

Further, since the present invention drives a pixel using a front-end gate signal, the structure of the gate driver can be simplified, and a narrow bezel can be easily implemented.

Further, the present invention can sufficiently cope with a source driver having a small data voltage range in terms of the structure of a pixel, which is advantageous in power consumption.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention.
2 is a view showing an OLED structure included in each pixel of an OLED display.
3 is a view showing a pixel array of an OLED display according to an embodiment of the present invention.
FIG. 4 is a view showing an example of a gate driver for driving the pixel array of FIG. 3. FIG.
5 is a diagram showing one equivalent circuit of the pixel shown in Fig.
FIG. 6 is a waveform diagram showing driving signals input to the pixel of FIG. 5 and the potential changes of the specific pixel nodes according to the driving signals.
7A is an equivalent circuit diagram of a pixel corresponding to the initialization period of FIG.
7B is an equivalent circuit diagram of a pixel corresponding to the compensation period of FIG.
7C is an equivalent circuit diagram of a pixel corresponding to the light emission period of FIG.
8 is a graph showing a result of simulating the OLED driving current change according to EVDD with respect to the pixel as shown in FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or wholly and technically various interlocking and driving are possible and that the embodiments may be practiced independently of each other, It is possible.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The component names used in the following description are selected in consideration of easiness of specification, and may be different from the parts names of actual products. In the embodiments of the present invention, an organic light emitting display is mainly described.

1 is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention. 2 is a view showing an OLED structure included in each pixel of an OLED display. 3 is a view showing a pixel array of an OLED display according to an embodiment of the present invention. FIG. 4 is a view showing an example of a gate driver for driving the pixel array of FIG. 3. Referring to FIG.

1 to 4, an OLED display according to an exemplary embodiment of the present invention includes a display panel 10 having pixels PXL, a display panel driving circuit 12 for driving signal lines connected to the pixels PXL, , 13), and a timing controller (11) for controlling the display panel drive circuits (12, 13).

The display panel drive circuits 12 and 13 write the input image data (DATA) to the pixels PXL of the display panel 10. [ The display panel driving circuits 12 and 13 include a source driver 12 for driving the data lines 14 connected to the pixels PXL and a gate driver 15 for driving the gate lines 15 connected to the pixels PXL. And a driver 13.

In the display panel 10, a plurality of data lines 14 and a plurality of gate lines 15 are crossed, and the pixels PXL are arranged in a matrix form. The pixels PXL include the OLED as shown in Fig. The OLED, which is a self-luminous element, includes an anode electrode, a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a power source voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons. As a result, the light emitting layer (EML) Thereby generating visible light.

The pixel array of the display panel 10 includes a plurality of horizontal pixel lines HL1 to HL4 as shown in FIG. 3, horizontally neighboring gate lines A plurality of pixels PXL connected in common to the pixels 15a and 15b are arranged. Here, each of the horizontal pixel lines L1 to L4 is not a physical signal line but a pixel block of one line amount which is implemented by horizontally neighboring pixels PXL. The pixel array includes a first power supply line 17 for supplying a high potential supply voltage EVDD to the pixels PXL and a second power supply line 16 for supplying the initialization voltage Vinit to the pixels PXL . Further, the pixels PXL may be connected to the low potential power supply voltage EVSS.

Each of the gate lines 15 includes a first gate line 15a to which a scan signal SC is supplied and a second gate line 15b to which an emission signal EM is supplied. Each of the pixels PXL disposed in the nth horizontal pixel line L (n) is supplied with an nth scan signal SC (n) and an nth emission signal SC (n) 1 scan signal SC (n-1) allocated to the (n-1) th horizontal pixel line L (n-1) other than the scan signal EM (n).

Each of the pixels PXL may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel for various color implementations. The red pixel, the green pixel, the blue pixel, and the white pixel may constitute one unit pixel. The color implemented in the unit pixel may be determined according to the emission ratio of the red pixel, the green pixel, the blue pixel, and the white pixel. Each of the pixels PXL includes one data line 14, one first gate line 15a, one second gate line 15b, a first power source line 17, a second power source line 16, Can be connected. Each of the pixels PXL may be further connected to the first gate line 15a disposed in the front-end horizontal pixel line.

The source driver 12 converts the input video data DATA received from the timing controller 11 every frame into a data voltage Vdata and supplies the data voltage Vdata to the data lines 14 . The source driver 12 outputs the data voltage Vdata using a digital to analog converter that converts the input image data DATA to a gamma compensation voltage.

A multiplexer (not shown) may be further disposed between the source driver 12 and the data lines 14 of the display panel 10. [ The multiplexer can reduce the number of output channels of the source driver 12 to the number of data lines by distributing the data voltages output through one output channel from the source driver 12 to the plurality of data lines. The multiplexer can be omitted depending on the resolution and usage of the display device.

The source driver 12 generates the initialization voltage Vinit and supplies it to the second power supply line 16 to generate and supply the high potential supply voltage EVDD to the first power supply line 17. [ To this end, the source driver 12 may further include a power generator (not shown). The power generation section may further generate the low potential power supply voltage EVSS. The power generator may be electrically connected to the source driver via a conductive film or the like after being mounted outside the source driver 12. The initialization voltage Vinit may be selected to be equal to or lower than the low potential power supply voltage EVSS so that unnecessary light emission of the OLED is prevented during the initialization period.

The gate driver 13 includes a first gate driver 13A and a second gate driver 13B as shown in FIG.

The first gate driver 13A has first stages GSTG1 to GSTGn as many as the horizontal pixel lines L1 to Ln and generates scan signals SC (1) to SC (n) under the control of the timing controller 11 ) To select the horizontal pixel lines L1 to Ln to which the data voltage Vdata is to be charged. The first gate driver 13A is implemented as a shift register and supplies the scan signals SC (1) to SC (n) through the first output nodes to the first gate lines 15a (1) to 15a (n)).

The second gate driver 13B has second stages ESTG1 to ESTGn as many as the horizontal pixel lines L1 to Ln and outputs the emission signals EM (1) to EM (1) under the control of the timing controller 11. [ n) to control the emission timing of the horizontal pixel lines L1 to Ln to which the data voltage Vdata is charged. The second gate driver 13B includes a shift register and an inverter and outputs the emission signals EM (1) to EM (n) through the second output nodes to the second gate lines 15b (1) to 15b n)).

In Fig. 4, GDUM, EDUM, G-MNT, and E-MNT mean a dummy stage. L Dummy indicates a dummy pixel line. And, VGH and VGL applied to the stages indicate driving power, VGH indicates a gate high voltage, and VGL indicates a gate low voltage. The dummy stage and the dummy pixel line may be optionally included or excluded. The pixel of the dummy pixel line is similar to the pixel PXL of the horizontal pixel line, but can be configured not to emit light. That is, the dummy pixel line may be configured not to include at least the OLED, or configured to not receive the data voltage, or may be configured not to receive the scan signal and the emission signal.

Two output nodes including any one of the first output nodes and the second output nodes of the gate driver 13 may be connected to each horizontal pixel line L1 to Ln. In particular, each of the first output nodes may be connected in common to two neighboring horizontal pixel lines so that the configuration of the gate driver 13 is simplified. The pixels PXL of the respective horizontal pixel lines L1 to Ln need three gate signals having different ON timings. For example, the pixels PXL of the nth horizontal pixel line Ln require two scan signals and one emission signal. Here, the two scan signals are composed of the n-1 scan signal SC (n-1) and the nth scan signal SC (n), and one emission signal is converted into the nth emission signal EM n), it is possible to drive the pixels PXL of the nth horizontal pixel line Ln with two stages, which is advantageous in that the configuration of the gate driver 13 can be simplified. In this case, the n-th scan signal SC (n) and the (n-1) th scan signal SC (n-1) have the same pulse width and different phases.

The gate driver 13 may be formed directly on the substrate of the display panel 10 together with the pixel array in a gate-driver In Panel (GIP) process, but is not limited thereto. The gate driver 13 may be manufactured in an IC type and then bonded to the display panel 10 through a conductive film.

The timing controller 11 receives digital data (DATA) of an input image from a host system (not shown) and a timing signal synchronized with the digital data (DATA). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. The host system may be any one of a TV system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The timing controller 11 multiplies the input frame frequency by i times to control the operation timing of the display panel driving circuits 12 and 13 at a frame frequency of the input frame frequency * i (i is a positive integer larger than 0) Hz have. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the PAL (Phase-Alternating Line) system.

The timing controller 11 generates a data timing control signal DDC for controlling the operation timing of the source driver 12 based on the timing signals Vsync, Hsync and DE received from the host system, And generates a gate timing control signal GDC for controlling the operation timing.

The data timing control signal DDC includes a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the sampling start timing of the source driver 12. [ The source sampling clock is a clock for shifting the data sampling timing. If the signal transfer interface between the timing controller 11 and the source driver 12 is a mini LVDS (Low Voltage Differential Signaling) interface, the source start pulse and the source sampling clock may be omitted.

The gate timing control signal GDC includes a gate start pulse, a gate shift clock, an emission shift clock, a gate output enable signal, and the like . In the case of the GIP circuit, the gate output enable signal (Gate Output Enable) may be omitted. The gate start pulse is generated at the beginning of the frame period every frame period and is input to the shift register of each gate driver 13. [ The gate start pulse controls the start timing at which the scan signals SC (1) to SC (n) and the emission signals EM (1) to EM (n) are output every frame period. The gate shift clock is input to the shift register of the gate driver 13 to control the shift timing of the shift register. The emission-shift clock is input to the inverter of the gate driver 13 to control the shift timing of the inverter.

5 is a diagram showing one equivalent circuit of the pixel shown in Fig.

Referring to FIG. 5, the pixel PXL of the present invention includes an OLED, a plurality of thin film transistors (ST1 to ST6, DT), and a storage capacitor Cst. The TFTs (ST1 to ST6, DT) can be implemented as a PMOS type LTPS TFT, and the desired response characteristic can be secured through this. However, the technical idea of the present invention is not limited thereto. For example, at least one TFT among the switch TFTs ST1 to ST6 may be implemented as an NMOS type oxide TFT having good off-current characteristics, and the remaining TFTs may be implemented as a PMOS type LTPS TFT having good response characteristics.

Hereinafter, a connection configuration of one pixel PXL arranged on the nth horizontal pixel line will be described in detail.

The OLED emits light with an amount of current adjusted in accordance with the gate-source voltage of the driving TFT DT. The anode electrode of the OLED is connected to the node N4, and the cathode electrode of the OLED is connected to the low potential power supply voltage EVSS. An organic compound layer is provided between the anode electrode and the cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). ≪ / RTI >

The driving TFT DT is a driving element for adjusting the current flowing in the OLED according to the gate-source voltage Vgs. The driving TFT DT includes a gate electrode connected to the node N2, a source electrode connected to the first power supply line 17, and a drain electrode connected to the node N3.

The first switch TFT (ST1) is connected between the node N2 and the node N3 and is switched according to the n-th scan signal SC (n). The gate electrode of the first switch TFT ST1 is connected to the nth first gate line 15a (n) to which the nth scan signal SC (n) is applied, and the source electrode of the first switch TFT (ST1) Is connected to the node N3, and the drain electrode of the first switch TFT (ST1) is connected to the node N2.

The second switch TFT T2 is connected between the data line 14 and the node N1 and is switched in accordance with the n-th scan signal SC (n). The gate electrode of the second switch TFT ST2 is connected to the nth first gate line 15a (n) to which the nth scan signal SC (n) is applied, and the source electrode of the second switch TFT ST2 Is connected to the data line 14, and the drain electrode of the second switch TFT (ST2) is connected to the node N1.

The third switch TFT T3 is connected between the node N3 and the node N4 and is switched in accordance with the nth emission signal EM (n). The gate electrode of the third switch TFT T3 is connected to the nth second gate line 15b (n) to which the nth emission signal EM (n) is applied, and the source of the third switch TFT T3 The electrode is connected to the node N3, and the drain electrode of the third switch TFT (T3) is connected to the node N4.

The fourth switch TFT T4 is connected between the node N1 and the second power supply line 16 and is switched in accordance with the nth emission signal EM (n). The gate electrode of the fourth switch TFT T4 is connected to the nth second gate line 15b (n) to which the nth emission signal EM (n) is applied, and the source of the fourth switch TFT T4 The electrode is connected to the node N1, and the drain electrode of the third switch TFT (T3) is connected to the second power supply line 16. [

The fifth switch TFT T5 is connected between the node N2 and the second power supply line 16 and is switched in accordance with the (n-1) th scan signal SC (n-1). The gate electrode of the fifth switch TFT T5 is connected to the (n-1) th first gate line 15a (n-1) to which the (n-1) th scan signal SC The source electrode of the switch TFT (ST5) is connected to the node N2, and the drain electrode of the fifth switch TFT (ST5) is connected to the second power supply line (16).

The sixth switch TFT T6 is connected between the node N4 and the second power supply line 16 and is switched in accordance with the (n-1) th scan signal SC (n-1). The gate electrode of the sixth switch TFT T6 is connected to the (n-1) th first gate line 15a (n-1) to which the (n-1) The source electrode of the switch TFT (ST6) is connected to the node N4, and the drain electrode of the sixth switch TFT (ST6) is connected to the second power supply line (16).

The storage capacitor Cst is connected between the node N1 and the node N2.

FIG. 6 is a waveform diagram showing driving signals input to the pixel of FIG. 5 and the potential changes of the specific pixel nodes according to the driving signals. 7A is an equivalent circuit diagram of a pixel corresponding to the initialization period of FIG. 7B is an equivalent circuit diagram of a pixel corresponding to the compensation period of FIG. 7C is an equivalent circuit diagram of a pixel corresponding to the light emission period of FIG.

6, each pixel PXL disposed on the nth horizontal pixel line Ln is divided into an initializing period A, a compensation period B subsequent to the initializing period A, B) and the light emission period (C).

Referring to FIG. 6, in the initialization period A, the n-1 scan signal SC (n-1) is input to the ON level and the nth scan signal SC (n) The emission signal EM (n) is input to the off level (OFF).

7A, the fifth switch TFT T5 and the sixth switch TFT T6 are turned on in response to the n-1 scan signal SC (n-1) of the ON level ON during the initialization period A, Is turned on. The initializing voltage Vinit is applied to the node N2 by turning on the fifth switch TFT T5 and the initializing voltage Vinit is applied to the node N4 by turning on the sixth switch TFT T6. The initialization voltage Vinit is a voltage lower than the high potential power supply voltage EVDD and a voltage equal to or lower than the low potential power supply voltage EVSS or the low potential power supply voltage EVSS. Since the gate-source voltage Vgs of the driving TFT DT, that is, "EVDD-Vinit" during the initialization period A is larger than the threshold voltage Vth of the driving TFT DT, Condition. Therefore, during the initialization period A, the node N3 is supplied with the high potential power supply voltage EVDD. On the other hand, since the initialization voltage Vinit applied to the node N2 during the initialization period A is lower than the operating point voltage of the OLED, the OLED does not emit light.

7A, the first switch TFT T1 and the second switch TFT T2 are turned off in response to the n-th scan signal SC (n) of OFF level (OFF) during the setup period (A) . During the initialization period A, the node N1 maintains the initialization voltage Vinit charged in the light emission period of the previous frame. In addition, the third switch TFT T3 and the fourth switch TFT T4 are turned off in response to the n-th emission signal EM (n) of OFF level (OFF) during the initialization period (A).

As a result, the potentials of the nodes N1, N2, and N4 become the initializing voltage (Vinit) and the potential of the node N3 becomes the high potential power supply voltage (EVDD) during the initialization period (A)

Referring to Fig. 7B, the first switch TFT T1 and the second switch TFT T2 are turned on in response to the n-th scan signal SC (n) of the on level ON during the compensation period B . The gate electrode and the drain electrode of the drive TFT DT are short-circuited by the turn-on of the first switch TFT (T1), and the drive TFT DT is diode-connected. The threshold voltage Vth of the driving TFT DT is sampled by the diode connection of the driving TFT DT and stored in the node N2 and the node N3. The data voltage Vdata applied to the data line 14 by the turn-on of the second switch TFT T2 is applied to the node N1.

7B, the third switch TFT T3 and the fourth switch TFT T4 are turned off in response to the n-th emission signal EM (n) of OFF level (OFF) during the compensation period (B) do. Then, the fifth switch TFT T5 and the sixth switch TFT T6 are turned off in response to the n-1th scan signal SC (n-1) of off level (OFF) during the compensation period (B) .

As a result, the potential of the node N1 becomes the data voltage (Vdata) during the compensation period (B), the potentials of the nodes N2 and N3 become "EVDD-Vth ", and the potential of the node N4 becomes the initialization voltage Vinit).

7C, when the third switch TFT T3 and the fourth switch TFT T4 are turned on in response to the n-th emission signal EM (n) of the ON level ON during the light emission period C, do. The first switch TFT T1 and the second switch TFT T2 are turned off in response to the n-th scan signal SC (n) of OFF level (OFF) during the light emission period (C). The fifth switch TFT T5 and the sixth switch TFT T6 are turned off in response to the (n-1) th scan signal SC (n-1) of off level (OFF) during the light emission period C .

The initialization voltage Vinit is applied to the node N1 by the turn-on of the fourth switch TFT T4 during the light emission period C and the potential of the node N1 is initialized from the data voltage Vdata in the immediately preceding compensation period B And is lowered to a voltage (Vinit).

During the light emission period C, the node N2 floats and is coupled to the node N1 through the storage capacitor Cst. Therefore, during the light emission period C, the potential change "Vdata-Vinit" of the node N1 is reflected to the node N2. As a result, the potential of the node N2 becomes lower by "Vdata-Vinit" than the "EVDD-Vth" of the immediately preceding compensation period B during the light emission period C. In other words, the potential of the node N2 during the light emission period C becomes "EVDD-Vth-Vdata + Vinit" as shown in Table 1. On the other hand, during the light emission period C, the potentials of the nodes N3 and N4 become "EVDD-Vth"

Thus, the Vgs voltage of the driving TFT DT for determining the driving current amount of the OLED is set. At this time, the driving current Ioled as shown in the following Equation 1 flows in the OLED.

Here, K is a constant value determined by the mobility of the driving TFT DT, the channel ratio, the parasitic capacitance, and the like, and Vth is the threshold voltage of the driving TFT DT.

The driving current Ioled of the OLED is not influenced by not only the threshold voltage Vth of the driving TFT DT but also the high potential power supply voltage EVDD. Since the driving current Ioled of the OLED is not influenced by the high potential power supply voltage EVDD, the embodiment of the present invention can be applied to the first power supply line 17 without designing a low resistance of the first power supply line 17, it is possible to uniformize the brightness and hue of the pixels on the entire screen without forming them in the form of a mesh. Thus, the present invention is very advantageous for realizing a uniform image quality in a high-resolution panel having a small pixel size. Further, the present invention is effective in providing a large-sized panel having improved luminance and image quality.

A B C N1 Vinit Vdata Vinit N2 Vinit EVDD-Vth EVDD-Vth-Vdata + Vinit N3 EVDD EVDD-Vth EVDD-Vth N4 Vinit Vinit EVDD-Vth

FIG. 8 is a graph showing a result of simulating the OLED driving current change according to the high-potential power supply voltage EVDD with respect to the pixel shown in FIG.

The simulation results in FIG. 8 show current changes when the EVDD-EVSS is set to 7.5V and the high-potential power supply voltage EVDD is changed by 0.1V and 0.2V based on the OLED driving current 50nA. Referring to FIG. 8, it can be seen that the OLED driving current Ioled is negligible to 1 to 2% of the 50 nA even when the high-potential power supply voltage EVDD is reduced by 0.1 V and 0.2 V, respectively.

As described above, since the OLED current of a pixel is not affected by EVDD, a uniform image quality can be realized in the entire screen without a low-resistance design of the EVDD wiring, and a high-resolution and large-area electroluminescent display device can be realized.

Further, since the present invention drives a pixel using a front-end gate signal, the structure of the gate driver can be simplified, and a narrow bezel can be easily implemented.

Further, the present invention can sufficiently cope with a source driver having a small data voltage range in terms of the structure of a pixel, which is advantageous in power consumption. Specifically, the pixel structure proposed in the present invention is implemented in proportion to the driving current of the OLED (Vdata - Vinit) 2. When the data voltage (Vdata) is regarded as a variable, it has a form of a quadratic function graph having an initialization voltage (Vinit) as an x-intercept. Therefore, if the absolute value of the initialization voltage Vinit can be reduced, the range of the data voltage Vdata for the entire gradation period (for example, 0 gradation to 255 gradation on an 8-bit basis) can be reduced. The smaller the range of the data voltage (Vdata), the lower the power consumption consumed by the source driver.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source driver 13: Gate driver

Claims (10)

The display panel 10 has a plurality of pixels PXL connected to the data line 14 to which the data voltage Vdata is supplied and the first power supply line 17 to which the high potential power supply voltage EVDD is supplied,
Each pixel PXL arranged in the nth horizontal pixel line Ln is connected to the n-
A driver TFT (DT) having a gate electrode, a source electrode, and a drain electrode connected to the node N2, the first power supply line (17), and the node N3;
A first switch TFT (T1) connected between the node N2 and the node N3 and switched in accordance with the n-th scan signal SC (n);
A second switch TFT (T2) connected between the data line (14) and a node (N1) and switched according to the nth scan signal (SC (n));
A third switch TFT (T3) connected between the node N3 and the node N4 and switched in accordance with the nth emission signal EM (n);
An organic light emitting diode connected between the node N4 and a low potential power supply voltage (EVSS); And
And a storage capacitor (Cst) connected between the node (N1) and the node (N2)
The first and second switch TFTs T1 and T2 are turned on during the compensation period B for sampling the threshold voltage Vth of the drive TFT DT. , And the third switch TFT (T3) is turned off in accordance with the nth emission signal EM (n) at the off level. The method according to claim 1,
1) th scan signal SC (n-1) neighboring the nth horizontal pixel line Ln and having a phase earlier than the nth scan signal SC (n) is supplied to the display panel 10 The (n-1) th horizontal pixel line Ln to be input is arranged,
The nth horizontal pixel line Ln is further connected to a second power line 16 to which an initialization voltage Vinit is supplied,
Each pixel PXL arranged in the nth horizontal pixel line Ln is connected to the n-
A fourth switch TFT (T4) connected between the node N1 and the second power supply line (16) and switched according to the nth emission signal EM (n);
A fifth switch TFT T5 which is connected between the node N2 and the second power supply line 16 and is switched in accordance with the (n-1) th scan signal SC (n-1); And
And a sixth switch TFT (T6) connected between the node N4 and the second power supply line (16) and being switched in accordance with the (n-1) th scan signal SC (n-1) Device. 3. The method of claim 2,
In the compensation period,
, The fourth switch TFT (T4) is turned off in accordance with the nth emission signal EM (n) at the off level, and the fifth and sixth switch TFTs (T5, T6) -1 scan signal SC (n-1). 3. The method of claim 2,
In the initialization period (A) for initializing the node N2 and the node N4 prior to the compensation period (B)
The first and second switch TFTs Tl and T2 are turned off according to the nth scan signal SC (n) at an off level, and the third and fourth switch TFTs T3 and T4 are turned off Th scan signal SC (n-1) of the on level, and the fifth and sixth switch TFTs T5 and T6 are turned off according to the n-th emission signal EM (n) ) According to the second embodiment of the present invention. 3. The method of claim 2,
In the light emission period (C) for causing the organic light emitting diode to emit light following the compensation period (B)
The first and second switch TFTs Tl and T2 are turned off according to the n-th scan signal SC (n) at an off level, and the third and fourth switch TFTs T3 and T4 are turned off Th scan signal SC (n-1) of the off level, and the fifth and sixth switch TFTs T5 and T6 are turned on according to the n-th emission signal EM (n) ) Is turned off. 6. The method of claim 5,
The current flowing in the organic light emitting diode in the light emitting period is,
And is independent of a change in threshold voltage of the driving TFT (DT) and a change in the high-potential power supply voltage (EVDD). 6. The method of claim 5,
The current flowing in the organic light emitting diode in the light emitting period is,
(Vdata) and the initialization voltage (Vinit). 3. The method of claim 2,
Wherein the nth scan signal SC (n) and the nth scan signal SC (n-1) have the same pulse width. 3. The method of claim 2,
Further comprising a gate driver for outputting a plurality of scan signals through a plurality of first output nodes and outputting a plurality of emission signals through a plurality of second output nodes,
Wherein two output nodes including any one of the first output nodes and the second output nodes are connected to each horizontal pixel line. 10. The method of claim 9,
And each of the first output nodes is commonly connected to two neighboring horizontal pixel lines.

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