KR101474024B1 - Organic light emitting diode display device - Google Patents

Abstract

The present invention relates to an organic light emitting diode (OLED) display, and more particularly, A first switch element that turns on / off according to the voltage of the second scan line to switch a current path between the first node and the data line; A storage capacitor connected between the first node and the second node; A second switch element that turns on / off according to the voltage of the third scan line to switch the current path between the reference voltage source and the first node; A third switch element that turns on / off according to a voltage of the second scan line to switch a current path between the second node and a drain electrode of the driving element; A fourth switch element that turns on / off according to the voltage of the third scan line to switch the current path between the drain electrode of the driving element and the third node; An organic light emitting diode (OLED) element connected between the third node and a low potential power source; A fifth switch element that turns on / off according to the voltage of the first scan line to switch the current path between any one of the reference voltage source, the low potential power source voltage source, the first scan line, and the third node; And supplying a first scan pulse to the first scan line during a first period to a fourth period, supplying a second scan pulse to the second scan line during a third period, And a scan driving circuit for supplying the scan signal to the third scan line.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display.

Various flat panel displays (FPDs) have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes (CRTs). Such a flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) And a light emitting device (Electroluminescence Device).

The electroluminescent device is divided into an inorganic electroluminescent device and an organic light emitting diode (OLED) according to the material of the light emitting layer, and is a self-luminous device which emits itself, has a high response speed and a large luminous efficiency, luminance and viewing angle have.

The organic light emitting diode display device can be driven by driving methods such as voltage driving, voltage compensation, current driving, digital driving, and external compensation, and in recent years, voltage compensation driving methods have been selected the most. The voltage compensation driving method initializes the driving element before storing the threshold voltage of the driving element that supplies the current to the organic light emitting diode element OLED. The ground voltage (GND) is mainly used as the initializing voltage of the driving device. At this time, a current flows instantaneously to the organic light emitting diode OLED connected to the driving device, and the contrast ratio is lowered. The contrast ratio can be increased by adjusting the initialization time appropriately, but it is difficult to adjust the initialization time. In this case, the initialization of the driving element becomes incomplete, and the display image may be delayed. Uniform compensation can not be obtained.

Accordingly, an object of the present invention is to provide an organic light emitting diode display device capable of increasing the contrast ratio, stabilizing the initialization of the driving device while reducing the initialization time of the driving device, and extending the service life.

According to an aspect of the present invention, there is provided an organic light emitting diode display device including: a driving device to which a high-potential power supply voltage is supplied; A first switch element that turns on / off according to the voltage of the second scan line to switch a current path between the first node and the data line; A storage capacitor connected between the first node and the second node; A second switch element that turns on / off according to the voltage of the third scan line to switch the current path between the reference voltage source and the first node; A third switch element that turns on / off according to a voltage of the second scan line to switch a current path between the second node and a drain electrode of the driving element; A fourth switch element that turns on / off according to the voltage of the third scan line to switch the current path between the drain electrode of the driving element and the third node; An organic light emitting diode (OLED) element connected between the third node and a low potential power source; A fifth switch element that turns on / off according to the voltage of the first scan line to switch the current path between any one of the reference voltage source, the low potential power source voltage source, the first scan line, and the third node; And supplying a first scan pulse to the first scan line during a first period to a fourth period, supplying a second scan pulse to the second scan line during a third period, And a scan driving circuit for supplying the scan signal to the third scan line.

According to another aspect of the present invention, there is provided an organic light emitting diode display device including: a driving device to which a high potential power supply voltage is supplied; A first switch element that turns on / off according to the voltage of the first scan line to switch a current path between the first node and the data line; A storage capacitor connected between the first node and the second node; A second switch element that turns on / off according to the voltage of the second scan line to switch the current path between the reference voltage source and the first node; A third switch element that turns on / off according to a voltage of the first scan line to switch a current path between the second node and a drain electrode of the driving element; A fourth switch element that turns on / off according to the voltage of the second scan line to switch the current path between the drain electrode of the driving element and the third node; An organic light emitting diode (OLED) element connected between the third node and a low potential power source; And a fifth switch element for switching the current path between the reference voltage source, the low potential power supply voltage source, and the first scan line and the current path between the third node and the third node by turning on / off according to the voltage of the first scan line. ; And a scan driver circuit for supplying a first scan pulse to the first scan line and supplying a second scan pulse to the second scan line to initialize the first to third nodes.

According to another aspect of the present invention, there is provided an organic light emitting diode display device including: a driving device to which a high potential power supply voltage is supplied; A first switch element for turning on / off according to the voltage of the second scan line (N is a positive integer) second scan line to switch the current path between the first node and the data line; A boost capacitor connected between the first node and the second node; A storage capacitor connected between the second node and a high potential source for generating the high potential power supply voltage; A second switch element that turns on / off according to the voltage of the (N-1) th scan line and switches the current path between the reference voltage source and the first node; A third switch element for turning on / off according to a voltage of the (N-1) th scan line and switching a current path between the second node and a drain electrode of the driving element; A fourth switch element that turns on / off according to the voltage of the third scan line to switch the current path between the drain electrode of the driving element and the third node; An organic light emitting diode (OLED) element connected between the third node and a low potential power source; A fifth switch element that turns on / off according to the voltage of the first scan line to switch the current path between any one of the reference voltage source, the low potential power source voltage source, and the first scan line, and the third node; And supplies a first scan pulse to the first scan line during the first to third periods, and supplies an (N-1) th second scan pulse to the (N-1) th scan line during the second and third periods Wherein the scan driver supplies a light emission control pulse to the third scan line during a third period and supplies an Nth second scan pulse to the Nth scan line during a fourth period after initializing the first to third nodes during the first and second periods, Th scan line to the first scan line.

The organic light emitting diode display device according to the embodiment of the present invention may be applied to any one of a first voltage source, a low potential power source, and a first scan line, and a fifth switch element for switching a current path between a third node, It is possible to increase the contrast ratio by lowering the anode voltage of the organic light emitting diode simultaneously with the initialization of the three nodes, stabilize the initialization of the driving device while extending the lifetime of the organic light emitting diode device while reducing the initialization time of the driving device.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to Figs. 1 to 17, focusing on a touch sensor.

1 to 5, an organic light emitting diode display device according to a first embodiment of the present invention includes a plurality of light emitting cells 11 arranged in a matrix in the form of m × n (where m and n are positive integers) A data driver 13 for supplying a data voltage to the data lines D1 to Dm; a first scan driver for sequentially supplying a first scan pulse to the first scan lines S1 to Sn; A second scan driver 16 for sequentially supplying a second scan pulse to the scan driver 14 and the second scan lines R11 to Rn and a second scan driver 16 for applying a light emission control pulse to the third scan lines E1 to En A third scan driver 15 for sequentially supplying the scan signals, and a timing controller 12 for controlling the drivers 13 to 16.

The light emitting cells 11 are formed in the pixel regions defined by the intersections of the data lines D1 to Dm and the scan lines S1 to Sn and R1 to Rn and E1 to En. A high potential power supply voltage VDD EL, a low potential power supply voltage or ground voltage GND and a reference voltage Vref are commonly supplied to the light emitting cells 11 of the display panel 10 as shown in FIGS. do. The reference voltage Vref is a voltage lower than the threshold voltage of the organic light emitting diode OLED so that the difference between the reference voltage Vref and the low potential power supply voltage or the ground voltage GND may be lower than the threshold voltage of the organic light emitting diode OLED. Respectively. The reference voltage Vref may be set to a negative voltage so as to apply a reverse bias to the organic light emitting diode OLED at the time of initialization of the driving element connected to the organic light emitting diode OLED. In this case, since the reverse bias is periodically applied to the organic light emitting diode device OLED, deterioration of the organic light emitting diode device OLED can be reduced and the lifetime can be extended.

Each of the light emitting cells 11 includes an organic light emitting diode OLED, five TFTs T1 to T5, a driving device DTFT and a storage capacitor Cstg as shown in FIGS.

The data driver 13 converts the digital video data RGB into analog data voltages DATA and supplies them to the data lines D1 to Dm. The data driver 13 supplies the data voltage Data to the data lines D1 to Dm during the third period (3) as shown in FIG.

3, the first scan driver 14 generates a first scan pulse SCAN having a low logic voltage during the first to fourth periods (1 to 4), and generates a first scan pulse SCAN using a shift register, ) To the first scan lines (S1 to Sn) sequentially. The second scan driver 16 generates a second scan pulse SRO1 having a low logic voltage during the second and third periods (2, 3) as shown in FIG. 3, and generates a second scan pulse SRO1 ) To the second scan lines (R1 to Rn) sequentially. The third scan driver 15 generates a light emission control pulse EM1 generated with high logic during the second and third periods (2, 3) as shown in FIG. 3, and uses the shift register to generate the light emission control pulse EM1 ) To the third scan lines (E1 to En) sequentially. The light emission control pulse EM1 is generated in the reverse phase of the second scan pulse SRO1.

The timing controller 12 supplies the digital video data RGB to the data driver 13 and supplies the data driver 13 and the first to third scan drivers 14 to 16 (CS, CG1 to CG3) for controlling the operation timing of the timing control signal CS.

FIG. 2 is a circuit diagram showing the first embodiment of the light emitting cells 11 shown in FIG. 1 in detail. FIG. 3 is a waveform diagram showing a driving signal waveform applied to the light emitting cells 11 shown in FIG.

2 and 3, the light emitting cells 11 include first to fifth TFTs T1 to T5, a storage capacitor Cstg, and a light emitting diode (OLED). The first to fifth TFTs T1 to T5 and the driving TFT DTFT are implemented as a p-type MOS TFT (Metal Oxide Semiconductor TFT).

The first TFT T1 is a switch TFT which supplies the data voltage DATA to the first node N1 in response to the second scan pulse SRO1. The first TFT T1 is turned on during the second and third periods (2 and 3) during which the second scan pulse SR01 is applied to turn on the data lines D1 to Dm and the first node RTI ID = 0.0 > N1. ≪ / RTI > The drain electrode of the first TFT T1 is connected to the first node N1, and the source electrode thereof is connected to the data lines D1 to Dm. The gate electrode of the first TFT T1 is connected to the second scan lines R1 to Rn.

The second TFT T2 blocks the current path between the first node N1 and the reference voltage Vref during the third period (3) in response to the emission control pulse EM and the third scan line E1 to En Is turned on during the first and fourth periods (1, 4) for maintaining the low logic voltage to supply the reference voltage Vref to the first node N1. A reference voltage Vref is supplied to the drain electrode of the second TFT T2, and the source electrode thereof is connected to the first node N1. And the gate electrode of the second TFT T2 is connected to the third scan lines E1 to En.

The third TFT T3 supplies the voltage of the second node N2 to the source electrode of the fourth TFT T4 during the second and third periods (2, 3) in response to the second scan pulse SRO1 . The source electrode of the third TFT T3 is connected to the second node N2 and the drain electrode thereof is connected to the source electrode of the fourth TFT T4 and the drain electrode of the driving element DTFT. And the gate electrode of the third TFT T3 is connected to the second scan lines R1 to Rn.

The fourth TFT T4 is turned on during the second and third periods (2, 3) in response to the light emission control pulse EM and the driving TFT DTFT, the third TFT T3, and the organic light emitting diode OLED The current path is blocked and the voltage of the third scan lines E1 to En is turned on for the first period (1) before and the fourth period (4) during which the low logic voltage is maintained, Thereby forming a current path between the TFT T3 and the organic light emitting diode OLED. The drain electrode of the fourth TFT T4 is connected to the anode electrode of the organic light emitting diode device OLED and the source electrode thereof is connected to the driving TFT DTFT and the drain electrodes of the third TFT T3. And the gate electrode of the fourth TFT T4 is connected to the third scan lines E1 to En.

The fifth TFT T5 is turned on during the first through fourth periods (1 through 4) in response to the first scan pulse SCAN to generate a current path between the third node N3 and the reference voltage source Vref . The pulse width of the first scan pulse SCAN is wider than the pulse width of the second scan pulse SRO1. The rising time of the first scan pulse SCAN is faster than the rising time of the second scan pulse SRO1 by a first period (1), and the falling time of the first scan pulse SCAN is a second scan It is later than the polling time of the pulse SRO1. The drain electrode of the fifth TFT T5 is connected to the third node N3, and the source electrode thereof is connected to the reference voltage source Vref. The gate electrode of the fifth TFT T5 is connected to the first scan lines S1 to Sn.

The driving element DTFT supplies a current from the high potential power source voltage source VDD EL to the organic light emitting diode element OLED and controls the current to the gate-source voltage. The drain electrode of the driving element DTFT is connected to the drain electrode of the third TFT T3 and the source electrode of the fourth TFT T4, and the source electrode thereof is connected to the high potential power source voltage source VDD EL. The gate electrode of the driving element DTFT is connected to the second node N2.

The storage capacitor Cstg is connected between the first node N1 and the second node N2 to maintain the gate voltage of the driving element DTFT.

A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). The organic light emitting diode OLED emits light for a fourth period (4) during which the voltage of the third scan lines E1 to En maintains the low logic voltage according to the current supplied under the control of the driving device DTFT. The anode electrode of the organic light emitting diode OLED is connected to the third node N3, and the cathode electrode thereof is connected to the low potential voltage source or the ground voltage source GND.

Hereinafter, the operation of the light emitting cell 11 will be described in detail.

During the first period (1), the fifth TFT T5 is turned on in response to the first scan pulse SCAN, and as a result, the voltage of the third node N3 is initialized to the reference voltage Vref. During the first period (1), the voltage of the third node N3 is discharged to the reference voltage source Vref. At this time, since the voltage difference between the reference voltage Vref and the ground voltage GND is equal to or lower than the threshold voltage of the organic light emitting diode OLED or a reverse bias is applied to the organic light emitting diode OLED, Does not flow. During the first period (1), a high logic voltage is applied to the second scan lines (R 1 to Rn) and a low logic voltage is applied to the third scan lines (E 1 to En). Thus, during the first period (1), the second and fourth TFTs (T2, T4) are turned on while the first and third TFTs (T1, T3) are turned off.

During the second period (2), the first and third TFTs T1 and T3 are turned on in response to the second scan pulse SR01 of the low logic voltage. The emission control pulse EM1 changing from the low logic voltage to the high logic voltage is applied to the gate electrodes of the second and fourth TFTs T2 and T4 during the second period (2). As a result, the first and second nodes N1 and N2 are initialized to the reference voltage Vref. At this time, since the fifth TFT T5 maintains the On state, the third node N3 maintains the reference voltage Vref. The organic light emitting diode OLED maintains the non-emission state during the second period (2) because the anode voltage is low as the reference voltage Vref.

During the third period (3), the threshold voltage of the driving element DTFT is stored in the storage capacitor Cstg. During the third period (3 & cirf), the second and fourth TFTs T2 and T4 are kept off and the third node N3 is maintained at the reference voltage Vref.

During the fourth period (4), the second and fourth TFTs T2 and T4 are turned on because the voltages of the third scan lines E1 to En are inverted to a low logic voltage, while the first and third And the fifth TFTs (T1, T3, T5) are turned off. Accordingly, the organic light emitting diode OLED emits light for about one frame period from the fourth period (4).

The light emitting cells 11 are driven while repeating the first to fourth periods (1 to 4) to compensate the threshold voltage of the driving element DTFT and the high-potential power supply voltage VDD EL.

In FIG. 2, the first period (1) may be omitted. In this case, the first scan pulse SCAN and the second scan pulse SRO1 are synchronized and can be simultaneously inverted to the low logic voltage during the second period (2). During the second period (2), the second and third nodes N2 and N3 are initialized to the reference voltage Vref.

As described above, according to the present invention, since the third node N3 can be kept below the threshold voltage of the organic light emitting diode OLED during the initialization times (①, ②), the organic light emitting diode OLED, The contrast ratio can be increased. It is necessary to design the channel ratio (W / L) of the fifth TFT T5 to be appropriately large in order to effectively perform initialization.

4 is a circuit diagram showing the second embodiment of the light emitting cells 11 in detail. The driving signal waveform applied to the light emitting cells 11 of Fig. 4 is substantially the same as that of Fig. In this embodiment, substantially the same constituent elements as those of the above-described embodiment are denoted by the same reference numerals, and a detailed description thereof will be omitted.

Referring to FIGS. 3 and 4, the light emitting cells 11 include first through fifth TFTs T1 through T51, a storage capacitor Cstg, and a light emitting diode OLED. The first to fifth TFTs T1 to T51 and the driving device DTFT are implemented as a p-type MOS TFT. The first to fourth TFTs T1 to T4 are substantially the same as the above-described embodiments.

The fifth TFT T51 is turned on during the first to fourth periods (1 to 4) in response to the first scan pulse SCAN to generate a current path between the third node N3 and the ground voltage source GND . The drain electrode of the fifth TFT (T51) is connected to the third node (N3), and the source electrode thereof is connected to the ground voltage source (GND). The gate electrode of the fifth TFT T51 is connected to the first scan lines S1 to Sn.

The circuit operation of this embodiment is substantially the same as the embodiment of Fig. 2 described above. However, the second embodiment of FIG. 4 applies the ground voltage GND to the third node N3 during the initialization time (1, 2) instead of the reference voltage Vref.

5 is a circuit diagram showing the third embodiment of the light emitting cells 11 in detail. The driving signal waveform applied to the light emitting cells 11 of Fig. 5 is substantially the same as that of Fig. In this embodiment, substantially the same constituent elements as those of the above-described embodiment are denoted by the same reference numerals, and a detailed description thereof will be omitted.

3 and 5, the light emitting cells 11 include first to fifth TFTs T1 to T52, a storage capacitor Cstg, and a light emitting diode (OLED). The first to fifth TFTs T1 to T52 and the driving device DTFT are implemented as p-type MOS TFTs. The first to fourth TFTs T1 to T4 are substantially the same as the above-described embodiments.

The fifth TFT T52 is turned on during the first to fourth periods (1 to 4) in response to the first scan pulse SCAN and is turned on between the third node N3 and the first scan lines S1 to Sn Thereby forming a current path. A low logic voltage is applied to the first scan lines S1 to Sn during the first to fourth periods (1 to 4). This row logic voltage is a negative voltage. The drain electrode of the fifth TFT T52 is connected to the third node N3, and the source electrode and the gate electrode thereof are connected to the first scan lines S1 to Sn.

The third embodiment applies a reverse bias to the organic light emitting diode OLED during the initialization times (1, 2), and controls the organic light emitting diode OLED to be in a non-light emitting state during the initialization times (1, And the lifetime of the organic light emitting diode (OLED) can be prolonged.

6 and 7 show an organic light emitting diode display device according to a second embodiment of the present invention. 8 is a waveform diagram illustrating a driving signal waveform applied to the light emitting cells of the organic light emitting diode display according to the second embodiment of the present invention.

Referring to FIG. 6, the organic light emitting diode display according to the second embodiment of the present invention includes a display panel 60 in which m × n light emitting cells 61 are arranged in a matrix, A first scan driver 64 for sequentially supplying a scan pulse SCAN to the first scan lines R1 to Rn and a second scan driver 62 for sequentially supplying scan pulses to the first scan lines R1 to Rn, A second scan driver 65 for sequentially supplying the emission control pulses EM1 to the scan electrodes E1 to En and a timing controller 62 for controlling the drivers 63 to 65. [

The light emitting cells 61 are formed in the pixel regions defined by the intersections of the data lines D1 to Dm and the scan lines S1 to Sn and R1 to Rn. A high potential power supply voltage VDD EL, a low potential power supply voltage or a ground voltage GND and a reference voltage Vref are commonly supplied to the light emitting cells 61 of the display panel 60 as shown in FIG. The reference voltage Vref is a voltage lower than the threshold voltage of the organic light emitting diode OLED so that the difference between the reference voltage Vref and the low potential power supply voltage or the ground voltage GND may be lower than the threshold voltage of the organic light emitting diode OLED. Respectively. The reference voltage Vref may be set to a negative voltage so as to apply a reverse bias to the organic light emitting diode OLED at the time of initialization of the driving element connected to the organic light emitting diode OLED. In this case, since the reverse bias is periodically applied to the organic light emitting diode device OLED, deterioration of the organic light emitting diode device OLED can be reduced and the lifetime can be extended.

Each of the light emitting cells 61 includes an organic light emitting diode OLED, five TFTs T1 to T4 and T53, a driving device DTFT and a storage capacitor Cstg as shown in FIG.

The data driver 63 converts the digital video data RGB into an analog data voltage DATA and supplies the data to the data lines D1 to Dm. The data driver 63 supplies the data voltage Data to the data lines D1 to Dm during the second period (2) as shown in FIG.

8, the first scan driver 64 changes from the high logic voltage to the low logic voltage during the first period (1) and maintains the low logic voltage during the second period (2), and during the third period (3) A second scan pulse SRP1 inverted to a high logic voltage is generated and the second scan pulse SRP1 is sequentially supplied to the first scan lines R1 to Rn using a shift register. The second scan driver 65 generates the emission control pulse EM1 generated in the opposite phase of the second scan pulse SRP1 as shown in FIG. 8, and uses the shift register to apply the emission control pulse EM1 to the second And sequentially supplies them to the scan lines E1 to En.

The timing controller 62 supplies the digital video data RGB to the data driver 63 and controls the operation timings of the data driver 63 and the scan drivers 64 and 65 using a vertical / And generates timing control signals (CS, CG1, CG2) for controlling them.

7 and 8, the light emitting cells 61 include first to fifth TFTs T1 to T4 and T53, a storage capacitor Cstg, and a light emitting diode (OLED). The first to fifth TFTs T1 to T4 and T53 and the driving device DTFT are implemented as a p-type MOS TFT.

The first TFT T1 is a switch TFT which supplies the data voltage DATA to the first node N1 in response to the second scan pulse SRO1. The first TFT T1 is turned on during the first and second periods (1, 2) during which the first scan pulse SR01 is applied to turn on the current between the data lines D1 to Dm and the first node N1 Thereby forming a path. The drain electrode of the first TFT T1 is connected to the first node N1, and the source electrode thereof is connected to the data lines D1 to Dm. The gate electrode of the first TFT T1 is connected to the first scan lines R1 to Rn.

The second TFT T2 blocks the current path between the first node N1 and the reference voltage Vref during the first and second periods (1, 2) in response to the emission control pulse EM1, The reference voltage Vref is supplied to the first node N1 while the voltage of the lines E1 to En is kept turned on during the third period (3) before the first period (1) do. A reference voltage Vref is supplied to the source electrode of the second TFT T2, and the drain electrode thereof is connected to the first node N1. And the gate electrode of the second TFT T2 is connected to the second scan lines E1 to En.

The third TFT T3 supplies the voltage of the second node N2 to the source electrode of the fourth TFT T4 during the first and second periods (1, 2) in response to the scan pulse SRO1. The source electrode of the third TFT T3 is connected to the second node N2 and the drain electrode thereof is connected to the source electrode of the fourth TFT T4 and the drain electrode of the driving element DTFT. The gate electrode of the third TFT T3 is connected to the first scan lines R1 to Rn.

The fourth TFT T4 is turned on during the first and second periods (1, 2) in response to the light emission control pulse EM and between the driving TFT DTFT and the third TFT T3 and the organic light emitting diode OLED The first and second scan lines E1 to En are turned on during the first period (1) and the third period (4) during which the voltage of the second scan line (E1 to En) 3 TFT (T3) and the organic light emitting diode element OLED. The drain electrode of the fourth TFT T4 is connected to the anode electrode of the organic light emitting diode device OLED and the source electrode thereof is connected to the driving TFT DTFT and the drain electrodes of the third TFT T3. And the gate electrode of the fourth TFT T4 is connected to the second scan lines E1 to En.

The fifth TFT T53 is turned on during the first and second periods (1, 2) in response to the scan pulse SRO1 to form a current path between the third node N3 and the reference voltage source Vref . The drain electrode of the fifth TFT T53 is connected to the third node N3, and the source electrode thereof is connected to the reference voltage source Vref. The gate electrode of the fifth TFT T53 is connected to the first scan lines R1 to Rn.

The driving element DTFT supplies a current from the high potential power source voltage source VDD EL to the organic light emitting diode element OLED and controls the current to the gate-source voltage. The drain electrode of the driving element DTFT is connected to the drain electrode of the third TFT T3 and the source electrode of the fourth TFT T4, and the source electrode thereof is connected to the high potential power source voltage source VDD EL. The gate electrode of the driving element DTFT is connected to the second node N2.

The storage capacitor Cstg is connected between the first node N1 and the second node N2 to maintain the gate voltage of the driving element DTFT.

A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL). The organic light emitting diode OLED emits light for a third period (3) during which the voltage of the second scan lines E1 to En maintains the low logic voltage according to the current supplied under the control of the driving device DTFT. The anode electrode of the organic light emitting diode OLED is connected to the third node N3, and the cathode electrode thereof is connected to the low potential voltage source or the ground voltage source GND.

The operation of the light emitting cell 61 will be described in detail as follows.

During the first period (1), the first, third and fifth TFTs T1, T3 and T53 are turned on in response to the scan pulse SR01 so that the second and third nodes N2 and N3 Is initialized to the reference voltage Vref. At this time, since the voltage difference between the reference voltage Vref and the ground voltage GND is equal to or lower than the threshold voltage of the organic light emitting diode OLED or a reverse bias is applied to the organic light emitting diode OLED, Does not flow. During the first period (1), the voltages of the second scan lines E1 to En are inverted from the low logic voltage to the high logic voltage. Therefore, the second and fourth TFTs T2 and T4 are turned on during the first period (1).

During the second period (2), the threshold voltage of the driving element DTFT is stored in the storage capacitor Cstg. During the second period (2), the second and fourth TFTs T4 maintain the off state and the third node N3 maintains the reference voltage Vref.

During the third period (3), the second and fourth TFTs T2 and T4 are turned on because the voltages of the second scan lines E1 to En are inverted to a low logic voltage, while the first and third And the fifth TFTs (T1, T3, T53) are turned off. Therefore, the organic light emitting diode OLED emits light for about one frame period from the third period (3).

The light emitting cells 61 are driven by repeating the first to third periods (1 to 3) while compensating for the threshold voltage of the driving element DTFT and the high potential power supply voltage VDD EL.

As described above, according to the present invention, since the third node N3 can be kept below the threshold voltage of the organic light emitting diode OLED during the initialization time period (1), the organic light emitting diode OLED The contrast ratio can be increased by controlling the light emitting state. It is necessary to design the channel ratio (W / L) of the fifth TFT T5 to be appropriately large in order to effectively perform initialization.

9, 10 and 12 show an organic light emitting diode display device according to a third embodiment of the present invention. 11 is a waveform diagram showing driving signal waveforms applied to the light emitting cells of the organic light emitting diode display device according to the third embodiment of the present invention.

9, the organic light emitting diode display device according to the third embodiment of the present invention includes a display panel 90 in which m × n light emitting cells 91 are arranged in a matrix, A first scan driver 94 for sequentially supplying a first scan pulse SCAN to the first scan lines S1 to Sn, a second scan driver 94 for sequentially supplying a first scan pulse SCAN to the first scan lines S1 to Sn, A second scan driver 96 for sequentially supplying a second scan pulse SELN-1 and SELN to the first scan lines SEL1 to SELn and a second scan driver 96 for sequentially supplying a second scan pulse SELN- And a timing controller 92 for controlling the driving units 93 to 96. The third scan driver 95 supplies the scan signals to the second scan driver 95 in sequence.

The light emitting cells 91 are formed in the pixel regions defined by the intersections of the data lines D1 to Dm and the scan lines S1 to Sn and SEL1 to SELn and E1 to En. A high potential power supply voltage VDD EL, a low potential power supply voltage or a ground voltage GND and a reference voltage Vref are commonly supplied to the light emitting cells 91 of the display panel 90 as shown in FIG. The reference voltage Vref is a voltage lower than the threshold voltage of the organic light emitting diode OLED so that the difference between the reference voltage Vref and the low potential power supply voltage or the ground voltage GND may be lower than the threshold voltage of the organic light emitting diode OLED. Respectively. The reference voltage Vref may be set to a negative voltage so as to apply a reverse bias to the organic light emitting diode OLED at the time of initialization of the driving element connected to the organic light emitting diode OLED. In this case, since the reverse bias is periodically applied to the organic light emitting diode device OLED, deterioration of the organic light emitting diode device OLED can be reduced and the lifetime can be extended.

Each of the light emitting cells 91 includes an organic light emitting diode OLED, five TFTs T1 to T4 and T54, a driving device DTFT, a storage capacitor Cstg, and a boost capacitor Cboost).

The data driver 93 converts the digital video data RGB into an analog data voltage DATA and supplies the data to the data lines D1 to Dm. The data driver 93 synchronizes with the second scan pulse SELN for selecting the light emitting cells 91 of N (N is a positive integer equal to or less than n) The data voltage Data N is supplied to the data lines D1 to Dm.

11, the first scan driver 94 generates a first scan pulse SCAN having a low logic voltage during the first to third periods (? To?), And uses the shift register to apply the first scan pulse SCAN) to the first scan lines (S1 to Sn) sequentially. The second scan driver 96 generates the second scan pulse SELN-1, SELN having a low logic voltage during the second and third periods (2, 3) as shown in FIG. 11, And sequentially supplies the second scan pulses SELN-1 and SELN to the second scan lines SEL1 to SELn. The third scan driver 95 generates a light emission control pulse EM having a high logic voltage during the second and third periods (2, 3) as shown in FIG. 11, and outputs the light emission control pulse EM using a shift register. To the third scan lines E1 to En in sequence.

The timing controller 92 supplies the digital video data RGB to the data driver 93 and controls the operation timing of the data driver 93 and the scan drivers 94 to 96 using a vertical / (CS, CG1 to CG3) for controlling the timing control signals CS, CG1 to CG3.

10 is a circuit diagram showing details of the first embodiment of the light emitting cells 91 shown in FIG.

10 and 11, the light emitting cells 91 include first to fifth TFTs T1 to T4 and T54, a storage capacitor Cstg, a boost capacitor Cboost, and a light emitting diode OLED do. The first to fifth TFTs T1 to T4 and T54 and the driving device DTFT are implemented as a p-type MOS TFT.

The first TFT T1 supplies the data voltage DATA to the first node N1 during the fourth period (4) in response to the Nth second scan pulse SELN. The drain electrode of the first TFT T1 is connected to the first node N1, and the source electrode thereof is connected to the data lines D1 to Dm. The gate electrode of the first TFT T1 is connected to the Nth second scan line SELN.

The second TFT T2 supplies the reference voltage Vref to the first node N1 during the second and third periods (2, 3) in response to the (N-1) th second scan pulse SELN-1 . The drain electrode of the second TFT T2 is connected to the first node N1, and the source electrode thereof is connected to the reference voltage source Vref. And the gate electrode of the second TFT T2 is connected to the (N-1) th scan line SELN-1.

The third TFT T3 applies the voltage of the second node N2 to the fourth TFT T4 during the second and third periods (2, 3) in response to the (N-1) th second scan pulse SELN- To the source electrode of the transistor. The source electrode of the third TFT T3 is connected to the second node N2 and the drain electrode thereof is connected to the source electrode of the fourth TFT T4 and the drain electrode of the driving element DTFT. And the gate electrode of the third TFT T3 is connected to the (N-1) th scan line SELN-1.

The fourth TFT T4 blocks the current path between the driving element DTFT and the third TFT T3 and the organic light emitting diode OLED during the third period (3) in response to the emission control pulse EM The voltages of the third scan lines E1 to En are turned on during the first, second and fourth periods (1, 2, and 4) during which the voltage of the third scan lines E1 to En maintains the low logic voltage, ), And the organic light emitting diode device OLED. The drain electrode of the fourth TFT T4 is connected to the anode electrode of the organic light emitting diode device OLED and the source electrode thereof is connected to the driving TFT DTFT and the drain electrodes of the third TFT T3. And the gate electrode of the fourth TFT T4 is connected to the third scan lines E1 to En.

The fifth TFT T54 is turned on during the first to third periods (? To?) In response to the first scan pulse SCAN to generate a current path between the third node N3 and the ground voltage source GND . The drain electrode of the fifth TFT (T54) is connected to the third node (N3), and the source electrode thereof is connected to the ground voltage source (GND). A gate electrode of the fifth TFT (T54) is connected to the first scan lines (S1 to Sn).

The driving element DTFT supplies a current from the high potential power source voltage source VDD EL to the organic light emitting diode element OLED and controls the current to the gate-source voltage. The drain electrode of the driving element DTFT is connected to the drain electrode of the third TFT T3 and the source electrode of the fourth TFT T4, and the source electrode thereof is connected to the high potential power source voltage source VDD EL. The gate electrode of the driving element DTFT is connected to the second node N2.

The boost capacitor Cboost is connected between the first node N1 and the second node N2 to store the data voltage DATAN applied to the first node N1 during the fourth period Boost by voltage. The first node N1 and the second node N2 are coupled through a boost capacitor Cboost.

The storage capacitor Cstg is connected between the second node N1 and the high potential power source VDD EL to maintain the gate-source voltage of the driving element DTFT.

A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL). The organic light emitting diode OLED emits light for a fourth period (4) during which the voltage of the second scan lines E1 to En maintains the low logic voltage according to the current supplied under the control of the driving device DTFT. The anode electrode of the organic light emitting diode OLED is connected to the third node N3, and the cathode electrode thereof is connected to the low potential voltage source or the ground voltage source GND.

Hereinafter, the operation of the light emitting cell 91 will be described in detail.

During the first period (1), the fifth TFT (T54) is turned on in response to the first scan pulse (SCAN). During the first period (1), the fourth TFT T4 maintains the on state according to the row logic voltage of the third scan lines E1 to En. During the first period (1), the first to third TFTs (T1 to T3) maintain the off state. The first first period (1) corresponds to the initialization preparation period.

During the second period (2), the (N-1) -th second scan pulse SELN-1 is generated as a low logic voltage, and as a result, the second and third TFTs T2 and T3 during the second period And the fourth and fifth TFTs T4 and T54 remain on. During the second period (2), the first TFT (T1) remains off. Therefore, the first, second and third nodes N1 to N3 are initialized to the reference voltage Vref. At this time, the second node N2 is initialized by coupling with the first node N1 to which the reference voltage Vref is applied. Since the voltage difference between the voltage of the third node N3 and the ground voltage GND is lower than the threshold voltage of the organic light emitting diode OLED or the reverse bias is applied to the organic light emitting diode OLED during the second period (2) No current flows through both ends of the diode (OLED).

During the third period (3), the emission control pulse EM of the high logic voltage is generated. During the third period (3), the fourth TFT T4 is turned off in response to the emission control pulse EM of the high logic voltage. During the third period (3), the second, third and fifth TFTs (T2, T3, T54) maintain the on state and the first TFT (T1) maintains the off state. Therefore, the gate-source voltage of the driving element DTFT is stored in the storage capacitor Cst and the boost capacitor Cboost so that the threshold voltage of the driving element DTFT is sampled.

The voltages of the (N-1) th scan line SELN-1 and the scan line SCAN are inverted to the low logic voltage during the fourth period (4) Inverted to the sub-logic voltage. During the fourth period (4), the fourth TFT (T4) is turned on while the second, third and fifth TFTs (T1, T3, T54) are turned off. The Nth second scan pulse SELN is generated after the (N-1) th scan pulse SELN-1 in the fourth period (4). The first TFT T1 is turned on in response to the Nth scan pulse SELN generated after the (N-1) th scan pulse SELN-1 and supplies the data voltage DATAN to the first node N1. Accordingly, the organic light emitting diode OLED emits light for about one frame period from the fourth period (4).

The light emitting cells 91 are driven by repeating the first to fourth periods (1 to 4) while compensating for the threshold voltage of the driving element DTFT and the high-potential power supply voltage VDD EL.

As described above, according to the present invention, since the third node N3 can be kept below the threshold voltage of the organic light emitting diode OLED during the initialization times (①, ②), the organic light emitting diode OLED, The contrast ratio can be increased. It is necessary to design the channel ratio (W / L) of the fifth TFT T5 to be appropriately large in order to effectively perform initialization.

12 is a detailed circuit diagram of a second embodiment of the light emitting cells 91 shown in FIG. In the light emitting cell of FIG. 12, substantially the same constituent elements as those of the above-described embodiment are denoted by the same reference numerals, and a detailed description thereof will be omitted.

11 and 12, the light emitting cells 91 include first to fifth TFTs T1 to T4 and T55, a driving device DTFT, a storage capacitor Cstg, a boost capacitor Cboost, And a diode (OLED). The first to fifth TFTs T1 to T4 and T55 and the driving device DTFT are implemented as a p-type MOS TFT.

The fifth TFT T55 turns on during the first to third periods (1 to 3) in response to the first scan pulse SCAN and is turned on between the third node N3 and the first scan lines S1 to Sn Thereby forming a current path. A low logic voltage is applied to the first scan lines S1 to Sn during the first to third periods (1 to 3). This row logic voltage is a negative voltage. The drain electrode of the fifth TFT (T56) is connected to the third node (N3), and the source electrode and the gate electrode thereof are connected to the first scan line (S1 to Sn).

Since the light emitting cell 91 of FIG. 12 applies a reverse bias to the organic light emitting diode OLED during the initialization times (1, 2), the organic light emitting diode OLED is controlled to be in a non- The contrast ratio can be increased and the lifetime of the organic light emitting diode (OLED) can be extended.

13, 14 and 16 show an organic light emitting diode display device according to a fourth embodiment of the present invention. FIGS. 15 and 17 are waveform charts showing driving signal waveforms applied to the light emitting cells of the organic light emitting diode display device according to the third embodiment of the present invention. 13 to 17, a part of the switch TFTs of the light emitting cells 131 is implemented as a p-type MOS TFT using a CMOS (Complementary Metal Oxide Semiconductor) process, and a part of the switch TFTs Are implemented as n-type MOS TFTs.

13, the organic light emitting diode display device according to the fourth embodiment of the present invention includes a display panel 130 in which m × n light emitting cells 131 are arranged in a matrix form, A first scan driver 134 for sequentially supplying a first scan pulse SCAN to the first scan lines S1 to Sn, a second scan driver 134 for sequentially applying a first scan pulse SCAN to the first scan lines S1 to Sn, A second scan driver 136 for sequentially supplying a second scan pulse SR01 to the scan lines R1 to Rn and a second scan driver 136 for sequentially supplying an emission control pulse EM1 to the third scan lines E1 to En, And a timing controller 132 for controlling the driving units 133-136.

The light emitting cells 131 are formed in the pixel regions defined by the intersections of the data lines D1 to Dm and the scan lines S1 to Sn and R1 to Rn and E1 to En. A high potential power supply voltage VDD EL, a low potential power supply voltage or ground voltage GND and a reference voltage Vref are commonly supplied to the light emitting cells 131 of the display panel 130 as shown in FIGS. 14 and 16 do. The reference voltage Vref is a voltage lower than the threshold voltage of the organic light emitting diode OLED so that the difference between the reference voltage Vref and the low potential power supply voltage or the ground voltage GND may be lower than the threshold voltage of the organic light emitting diode OLED. Respectively. The reference voltage Vref may be set to a negative voltage so as to apply a reverse bias to the organic light emitting diode OLED at the time of initialization of the driving element connected to the organic light emitting diode OLED. In this case, since the reverse bias is periodically applied to the organic light emitting diode device OLED, deterioration of the organic light emitting diode device OLED can be reduced and the lifetime can be extended.

Each of the light emitting cells 131 includes an organic light emitting diode OLED, five TFTs T1 to T4, T56 and T57, a driving device DTFT and a storage capacitor Cstg .

The data driver 133 converts the digital video data RGB into an analog data voltage DATA and supplies the analog data voltage DATA to the data lines D1 to Dm. The data driver 133 supplies the data voltage Data N to the data lines D1 to Dm during the third period (3) in FIG. 15 in synchronization with the second scan pulse SR01.

15 and 17, the first scan driver 134 generates a first scan pulse SCAN during the first to third periods (1 to 3), and uses the shift register to apply the first scan pulse SCAN ) To the first scan lines (S1 to Sn) sequentially. The second scan driver 136 generates the second scan pulse SRO1 during the second and third periods (2, 3) as shown in FIGS. 15 and 17, and uses the shift register to generate the second scan pulse SRO1 ) To the second scan lines (R1 to Rn) sequentially. The third scan driver 135 generates the emission control pulse EM during the third period (3 & cir &) as shown in FIGS. 15 and 17, and uses the shift register to apply the emission control pulse EM to the third scan lines (E1 to En).

The timing controller 132 supplies the digital video data RGB to the data driver 133 and controls the operation timing of the data driver 133 and the scan drivers 134 to 136 using a vertical / (CS, CG1 to CG3) for controlling the timing control signals CS, CG1 to CG3.

FIG. 14 is a circuit diagram showing the first embodiment of the light emitting cells 131 shown in FIG. 13 in detail.

14 and 15, the light emitting cells 131 include first to fifth TFTs T1 to T4 and T56, a driving device DTFT, a storage capacitor Cstg, and a light emitting diode OLED do. The first, third and fifth TFTs T1, T3 and T56 are implemented as n-type MOS TFTs and the second and fourth TFTs T2 and T4 and the driving element DTFT are implemented as p- .

The first TFT T1 supplies the data voltage DATA to the first node N1 during the second and third periods (2, 3) in response to the second scan pulse SOR1. The source electrode of the first TFT T1 is connected to the first node N1, and the drain electrode thereof is connected to the data lines D1 to Dm. The gate electrode of the first TFT T1 is connected to the second scan lines R1 to Rn.

The second TFT T2 supplies the reference voltage Vref to the first node N1 during the second and third periods (2, 3) in response to the second scan pulse SOR1. The source electrode of the second TFT T2 is connected to the first node N1, and the drain electrode thereof is connected to the reference voltage source Vref. And the gate electrode of the second TFT T2 is connected to the second scan lines R1 to Rn.

The third TFT T3 supplies the voltage of the second node N2 to the source electrode of the fourth TFT T4 during the second and third periods (2, 3) in response to the second scan pulse SOR1 . The drain electrode of the third TFT T3 is connected to the second node N2 and its source electrode is connected to the source electrode of the fourth TFT T4 and the drain electrode of the driving element DTFT. And the gate electrode of the third TFT T3 is connected to the second scan lines R1 to Rn.

The fourth TFT T4 is turned on during the second and third periods (2, 3) in response to the light emission control pulse EM and the driving TFT DTFT, the third TFT T3, and the organic light emitting diode OLED Second, and fourth periods (1, 2, and 4) during which the current path is blocked and the voltages of the third scan lines E1 to En hold the low logic voltage to turn off the driving elements DTFT and Thereby forming a current path between the third TFT T3 and the organic light emitting diode OLED. The drain electrode of the fourth TFT T4 is connected to the anode electrode of the organic light emitting diode device OLED and the source electrode thereof is connected to the driving TFT DTFT and the drain electrodes of the third TFT T3. And the gate electrode of the fourth TFT T4 is connected to the third scan lines E1 to En.

The fifth TFT T56 is turned on during the first to third periods (1 to 3) in response to the first scan pulse SCAN to generate a current path between the third node N3 and the reference voltage source Vref . The source electrode of the fifth TFT (T56) is connected to the third node (N3), and the drain electrode thereof is connected to the reference voltage source (Vref). A gate electrode of the fifth TFT (T54) is connected to the first scan lines (S1 to Sn).

The driving element DTFT supplies a current from the high potential power source voltage source VDD EL to the organic light emitting diode element OLED and controls the current to the gate-source voltage. The drain electrode of the driving element DTFT is connected to the source electrodes of the third and fourth TFTs T3 and T4, and the source electrode thereof is connected to the high potential power source voltage source VDD EL. The gate electrode of the driving element DTFT is connected to the second node N2.

The storage capacitor Cstg is connected between the first node N1 and the second node N1 to maintain the gate-source voltage of the driving element DTFT.

A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL). The organic light emitting diode OLED emits light for a fourth period (4) during which the voltage of the second scan lines E1 to En maintains the low logic voltage according to the current supplied under the control of the driving device DTFT. The anode electrode of the organic light emitting diode OLED is connected to the third node N3, and the cathode electrode thereof is connected to the low potential voltage source or the ground voltage source GND.

Hereinafter, the operation of the light emitting cell 131 will be described in detail.

During the first period (1), the fifth TFT (T56) is turned on in response to the first scan pulse (SCAN), and as a result, the voltage of the third node (N3) is initialized to the reference voltage (Vref). During the first period (1), the voltage of the third node N3 is discharged to the reference voltage source Vref. At this time, since the voltage difference between the reference voltage Vref and the ground voltage GND is equal to or lower than the threshold voltage of the organic light emitting diode OLED or a reverse bias is applied to the organic light emitting diode OLED, Does not flow. During the first period (1), a low logic voltage is applied to the second and third scan lines (R1 to Rn, E1 to En). Thus, during the first period (1), the second and fourth TFTs (T2, T4) are turned on while the first and third TFTs (T1, T3) are turned off.

During the second period (2), the second scan pulse SR01 having a high logic voltage is applied to the gate electrodes of the first to third TFTs T1 to T3. As a result, the first and third TFTs T1 and T3 are turned on and the second TFT T2 is turned off. The fourth and fifth TFTs T4 and T5 maintain the ON state. During the second period (2), the second and third nodes N2 and N3 are initialized to the reference voltage Vref. At this time, since the fifth TFT (T56) maintains the on state, the third node (N3) maintains the reference voltage (Vref). The organic light emitting diode OLED maintains the non-emission state during the second period (2) because the anode voltage is low as the reference voltage Vref.

During the third period (3), the threshold voltage of the driving element DTFT is stored in the storage capacitor Cstg. During the third period (3), the second and fourth TFTs (T2, T4) maintain the off state and the third node (N3) maintains the reference voltage (Vref).

During the fourth period (4), the second and fourth TFTs (T2, T4) are turned on since the voltages of the second and third scan lines (R1 to Rn, E1 to En) On the other hand, the first, third and fifth TFTs T1, T3 and T5 are turned off. Accordingly, the organic light emitting diode OLED emits light for about one frame period from the fourth period (4).

The light emitting cells 131 are driven by repeating the first to fourth periods (1 to 4) while compensating for the threshold voltage of the driving element DTFT and the high potential power supply voltage VDD EL.

As described above, according to the present invention, since the third node N3 can be kept below the threshold voltage of the organic light emitting diode OLED during the initialization times (①, ②), the organic light emitting diode OLED, The contrast ratio can be increased. It is necessary to design the channel ratio (W / L) of the fifth TFT T5 to be appropriately large in order to effectively perform initialization.

FIG. 16 is a circuit diagram showing the second embodiment of the light emitting cells 131 shown in FIG. 13 in detail.

16 and 17, the light emitting cells 131 include first to fifth TFTs T1 to T4 and T56, a driving device DTFT, a storage capacitor Cstg, and a light emitting diode OLED do. The first, third and fifth TFTs T1, T3 and T57 are implemented as p-type MOS TFTs and the second and fourth TFTs T2 and T4 and the driving element DTFT are implemented as an n-type MOS TFT .

The first TFT T1 supplies the data voltage DATA to the first node N1 during the second and third periods (2, 3) in response to the second scan pulse SOR1. The source electrode of the first TFT T1 is connected to the first node N1, and the drain electrode thereof is connected to the data lines D1 to Dm. The gate electrode of the first TFT T1 is connected to the second scan lines R1 to Rn.

The second TFT T2 supplies the reference voltage Vref to the first node N1 during the second and third periods (2, 3) in response to the second scan pulse SOR1. The source electrode of the second TFT T2 is connected to the first node N1, and the drain electrode thereof is connected to the reference voltage source Vref. And the gate electrode of the second TFT T2 is connected to the second scan lines R1 to Rn.

The third TFT T3 supplies the voltage of the second node N2 to the source electrode of the fourth TFT T4 during the second and third periods (2, 3) in response to the second scan pulse SOR1 . The drain electrode of the third TFT T3 is connected to the second node N2 and its source electrode is connected to the source electrode of the fourth TFT T4 and the drain electrode of the driving element DTFT. And the gate electrode of the third TFT T3 is connected to the second scan lines R1 to Rn.

The fourth TFT T4 is turned on during the second and third periods (2, 3) in response to the light emission control pulse EM and the driving TFT DTFT, the third TFT T3, and the organic light emitting diode OLED Second, and fourth periods (1, 2, and 4) during which the current path is blocked and the voltages of the third scan lines E1 to En hold the low logic voltage to turn off the driving elements DTFT and Thereby forming a current path between the third TFT T3 and the organic light emitting diode OLED. The drain electrode of the fourth TFT T4 is connected to the anode electrode of the organic light emitting diode OLED and the source electrode thereof is connected to the drain electrode of the driving TFT DTFT and the source electrode of the third TFT T3. And the gate electrode of the fourth TFT T4 is connected to the third scan lines E1 to En.

The fifth TFT T57 is turned on during the first to third periods (1 to 3) in response to the first scan pulse SCAN to generate a current path between the third node N3 and the reference voltage source Vref . The source electrode of the fifth TFT (T57) is connected to the third node (N3), and the source electrode thereof is connected to the reference voltage source (Vref). A gate electrode of the fifth TFT (T54) is connected to the first scan lines (S1 to Sn).

The driving element DTFT supplies a current from the high potential power source voltage source VDD EL to the organic light emitting diode element OLED and controls the current to the gate-source voltage. The drain electrode of the driving element DTFT is connected to the source electrodes of the third and fourth TFTs T3 and T4, and the source electrode thereof is connected to the high potential power source voltage source VDD EL. The gate electrode of the driving element DTFT is connected to the second node N2.

The storage capacitor Cstg is connected between the first node N1 and the second node N1 to maintain the gate-source voltage of the driving element DTFT.

A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL). The organic light emitting diode OLED emits light for a fourth period (4) during which the voltage of the second scan lines E1 to En maintains the low logic voltage according to the current supplied under the control of the driving device DTFT. The anode electrode of the organic light emitting diode OLED is connected to the third node N3, and the cathode electrode thereof is connected to the low potential voltage source or the ground voltage source GND.

The operation of the light emitting cell 131 is substantially the same as that of FIG. 14 and FIG. 15 described above, so a detailed description thereof will be omitted.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

1 is a block diagram showing an organic light emitting diode display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing the first embodiment of the light emitting cell shown in FIG. 1 in detail.

FIG. 3 is a waveform diagram showing driving signal waveforms of the light emitting cells shown in FIG. 2, FIG. 4, and FIG.

FIG. 4 is a circuit diagram showing a second embodiment of the light emitting cell shown in FIG. 1 in detail.

FIG. 5 is a circuit diagram showing a third embodiment of the light emitting cell shown in FIG. 1 in detail.

6 is a block diagram showing an organic light emitting diode display device according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing the light emitting cell shown in FIG. 6 in detail.

8 is a waveform diagram showing a drive signal waveform applied to the light emitting cell shown in FIG.

9 is a block diagram showing an organic light emitting diode display device according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram showing the first embodiment of the light emitting cell shown in FIG. 9 in detail.

FIG. 11 is a waveform diagram showing driving signal waveforms of the light emitting cells shown in FIGS. 10 and 12. FIG.

FIG. 12 is a circuit diagram showing the second embodiment of the light emitting cell shown in FIG. 10 in detail.

13 shows an organic light emitting diode display device according to a fourth embodiment of the present invention.

FIG. 14 is a circuit diagram showing the first embodiment of the light emitting cell shown in FIG. 13 in detail.

15 is a waveform diagram showing a driving signal waveform of the light emitting cell shown in FIG.

FIG. 16 is a circuit diagram showing a second embodiment of the light emitting cell shown in FIG. 13 in detail.

17 is a waveform diagram showing a driving signal waveform of the light emitting cell shown in FIG.

Description of the Related Art

10, 60, 90, 130: display panel

11, 61, 91, 131: light emitting cells

12, 62, 92, 132: timing controller

13, 63, 93, 133:

14 to 16, 64, 65, 94 to 96, and 134 to 136:

T1 to T5, T51 to T57, DTFT: TFT

Cstg, Cboost: storage capacitor

OLED: Light emitting diode

Claims (8)

A driving element to which a high potential power supply voltage is supplied; A first switch element that turns on / off according to the voltage of the second scan line to switch a current path between the first node and the data line; A storage capacitor connected between the first node and a second node to which a gate of the driving element is connected; A second switch element that turns on / off according to the voltage of the third scan line to switch the current path between the reference voltage source and the first node; A third switch element that turns on / off according to a voltage of the second scan line to switch a current path between the second node and a drain electrode of the driving element; A fourth switch element that turns on / off according to the voltage of the third scan line to switch the current path between the drain electrode of the driving element and the third node; An organic light emitting diode (OLED) element connected between the third node and a low potential power source; A fifth switch element that turns on / off according to the voltage of the first scan line to switch the current path between any one of the reference voltage source, the low potential power source voltage source, the first scan line, and the third node; And Supplying a first scan pulse to the first scan line during a first period to a fourth period, supplying a second scan pulse to the second scan line during a third period, and supplying an emission control pulse to the second scan line during the third period, 3 scan lines, During the first period, the fifth TFT is turned on in response to the first scan pulse to initialize the voltage of the third node, Wherein during the second period, the first and third TFTs are turned on in response to the second scan pulse to initialize the first and second nodes. The method according to claim 1, Wherein a difference between a reference voltage generated from the reference voltage source and a low potential power supply voltage from the low potential power supply voltage source is less than a threshold voltage of the organic light emitting diode device. The method according to claim 1, Wherein a pulse width of the first scan pulse is equal to or longer than the first to third periods, And the emission control pulse is a reverse phase of the second scan pulse. A driving element to which a high potential power supply voltage is supplied; A first switch element that turns on / off according to the voltage of the first scan line to switch a current path between the first node and the data line; A storage capacitor connected between the first node and a second node to which a gate of the driving element is connected; A second switch element that turns on / off according to the voltage of the second scan line to switch the current path between the reference voltage source and the first node; A third switch element that turns on / off according to a voltage of the first scan line to switch a current path between the second node and a drain electrode of the driving element; A fourth switch element that turns on / off according to the voltage of the second scan line to switch the current path between the drain electrode of the driving element and the third node; An organic light emitting diode (OLED) element connected between the third node and a low potential power source; And a fifth switch element for switching the current path between the reference voltage source, the low potential power supply voltage source, and the first scan line and the current path between the third node and the third node by turning on / off according to the voltage of the first scan line. ; And And a scan driver circuit for supplying a first scan pulse to the first scan line and supplying a second scan pulse to the second scan line to initialize the first to third nodes, Device. 5. The method of claim 4, Wherein a difference between a reference voltage generated from the reference voltage source and a low potential power supply voltage from the low potential power supply voltage source is less than a threshold voltage of the organic light emitting diode device. 5. The method of claim 4, And the second scan pulse is a reverse phase of the first scan pulse. A driving element to which a high potential power supply voltage is supplied; A first switch element for turning on / off according to the voltage of the second scan line (N is a positive integer) second scan line to switch the current path between the first node and the data line; A boost capacitor connected between the first node and a second node coupled to a gate of the driving element; A storage capacitor connected between the second node and a high potential source for generating the high potential power supply voltage; A second switch element that turns on / off according to the voltage of the (N-1) th scan line and switches the current path between the reference voltage source and the first node; A third switch element for turning on / off according to a voltage of the (N-1) th scan line and switching a current path between the second node and a drain electrode of the driving element; A fourth switch element that turns on / off according to the voltage of the third scan line to switch the current path between the drain electrode of the driving element and the third node; An organic light emitting diode (OLED) element connected between the third node and a low potential power source; A fifth switch element that turns on / off according to the voltage of the first scan line to switch the current path between any one of the reference voltage source, the low potential power source voltage source, and the first scan line, and the third node; And Supplying a first scan pulse to the first scan line during the first to third periods and supplying an (N-1) th second scan pulse during the second and third periods to the (N-1) The first to third nodes are initialized during the first and second periods, the emission control pulse is supplied to the third scan line during the third period, and the Nth second scan pulse is applied to the Nth And a scan driving circuit for supplying the scan signal to the second scan line. 8. The method of claim 7, Wherein a difference between a reference voltage generated from the reference voltage source and a low potential power supply voltage from the low potential power supply voltage source is less than a threshold voltage of the organic light emitting diode device.

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