KR20080048831A - Organic light emitting diode display and driving method thereof - Google Patents

Abstract

An OLED display device is provided to obtain the uniform image quality on a whole display by minimizing effects due to threshold and source voltages of a driving TFT(Thin Film Transistor). An OLED(Organic Light Emitting Diode) display device includes high and low voltage level voltage sources(VDD,VSS), an OLED element(OLED), first and second capacitors(C1,C2), first and second switch elements(PT1,PT3), and a driving element(PT2). The high and low voltage level voltage sources generate high and low source voltages, respectively. The OLED element is illuminated by a current flowing between the high and low voltage level voltage sources. The first and second capacitors are connected between a first node and the high source voltage, and between first and second nodes, respectively. The first switch element supplies a data voltage to the first node in response to a scan pulse(SCAN) during a first period and blocks the data voltage during a second period. The second switch element blocks one of the high and low source voltages in response to a source voltage blocking pulse during the first period and supplies the blocked source voltage to the second node(B). The driving element supplies currents to the OLED element according to voltages of the first and second nodes.

Description

Organic light emitting diode display device {ORGANIC LIGHT EMITTING DIODE DISPLAY AND DRIVING METHOD THEREOF}

1 is a view schematically showing a structure of an organic light emitting diode display device.

2 is an equivalent circuit diagram of one pixel in an organic light emitting diode display device of an active matrix type.

3 is a block diagram illustrating an organic light emitting diode display device according to an exemplary embodiment of the present invention.

4 is a circuit diagram showing in detail a first embodiment of the pixel shown in FIG.

5 and 6 are waveform diagrams showing driving waveforms of pixels according to the first embodiment of the present invention;

FIG. 7 is a circuit diagram showing details of a second embodiment of the pixel shown in FIG. 3; FIG.

8 is a waveform diagram showing driving waveforms of a pixel according to a second embodiment of the present invention;

9 is a circuit diagram showing details of a third embodiment of the pixel shown in FIG. 3;

10 is a waveform diagram showing driving waveforms of a pixel according to a third embodiment of the present invention;

FIG. 11 is a circuit diagram showing details of a fourth embodiment of the pixel shown in FIG. 3;

Fig. 12 is a waveform diagram showing driving waveforms of a pixel 24 according to the fourth embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

20: display panel 21: timing controller

22: data driver 23: gate driver

24 pixels

PT1 to PT3, NT1 to NT3: thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display device, and more particularly, to an organic light emitting diode display device capable of obtaining uniform image quality over the entire display surface by minimizing the influence of the threshold voltage and the power supply voltage of the driving device.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (FEDs), plasma display panels (hereinafter referred to as "PDPs") and electric fields. Light emitting devices; and the like.

PDP is attracting attention as a display device that is light and small and is most advantageous for large screen because of its simple structure and manufacturing process. However, PDP has low luminous efficiency, low luminance and high power consumption. TFT LCDs with thin film transistors (hereinafter referred to as "TFTs") as switching devices are the most widely used flat panel display devices. However, TFT LCDs have a narrow viewing angle and low response speed because they are non-light emitting devices. In contrast, the electroluminescent device is classified into an inorganic electroluminescent device and an organic light emitting diode device according to the material of the light emitting layer. The electroluminescent device is a self-light emitting device that emits light, and has a high response speed and high luminous efficiency, luminance, and viewing angle.

The organic light emitting diode device includes organic compound layers HIL, HTL, EML, ETL, and EIL formed between the anode electrode and the cathode electrode as shown in FIG.

The organic compound layer includes a hole injection layer, a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). It includes.

When a driving voltage is applied to the anode electrode and the cathode electrode, holes supplied through the hole transport layer (HTL) and electrons passing through the electron injection layer (EIL) and the electron transport layer (ETL) are injected into the emission layer (EML) to form excitons. As a result, the light emitting layer EML emits visible light. Thus, an image or an image is displayed by the visible light generated from the emission layer EML.

Such an organic light emitting diode device is divided into a passive matrix type or an active matrix type display element using a TFT as a switching element. The passive matrix method selects light emitting cells according to currents applied to the anode and cathode electrodes which are orthogonal to each other, whereas the active matrix method selects light emitting cells by selectively turning on the active TFTs and selects a storage capacitor. Light emission of the light emitting cell is maintained at a voltage maintained in the (Storgage Capacitor).

2 is a circuit diagram equivalently showing one pixel in an active matrix type organic light emitting diode display.

Referring to FIG. 2, a pixel of an active matrix type organic light emitting diode display device includes an organic light emitting diode device OLED, a data line DL and a gate line GL that cross each other, a switch TFT T1, and a driving TFT T2. ), And a storage capacitor Cst. The switch TFT T1 and the driving TFT T2 are implemented with a P-type MOS-FET.

The switch TFT T1 is turned on in response to the gate low voltage (or the scan voltage) from the gate line GL to conduct a current path between its source electrode and the drain electrode, and the voltage of the gate line GL. It remains off when the gate high voltage is higher than its threshold voltage (Vth). During the on-time period of the switch TFT T1, the data voltage from the data line DL is applied to the gate electrode and the storage capacitor Cst of the driving TFT T2 via the source electrode and the drain electrode of the switch TFT T1. Is approved. On the contrary, the current path between the source electrode and the drain electrode of the switch TFT T1 is opened during the off time period of the switch TFT T1 so that the data voltage is not applied to the driving TFT T2 and the storage capacitor Cst.

The source electrode of the driving TFT T2 is connected to one electrode of the high potential power supply voltage source VDD and the storage capacitor Cst, and the drain electrode is connected to the anode electrode of the organic light emitting diode element OLED. The gate electrode of the driving TFT T2 is connected to the drain electrode of the switch TFT T1. The driving TFT T2 adjusts the current between the source electrode and the drain electrode according to the gate voltage supplied to the gate electrode, that is, the data voltage, and emits the organic light emitting diode OLED with brightness corresponding to the data voltage.

The storage capacitor Cst stores the difference voltage between the data voltage and the high potential power voltage VDD to maintain a constant voltage applied to the gate electrode of the driving TFT T2 for one frame period.

The organic light emitting diode OLED has the structure as shown in FIG. 1 and includes an anode electrode connected to the drain electrode of the driving TFT T2 and a cathode electrode connected to the base voltage source.

The brightness of the pixel as shown in FIG. 2 is proportional to the current flowing through the organic light emitting diode OLED, and the current is controlled by the gate voltage of the driving TFT T2.

At this time, the current I _OLED of the organic light emitting diode OLED flowing through the driving TFT T2 is expressed by Equation 1 below.

Here, 'Vth' is the threshold voltage of the driving TFT (T2), 'k' is a constant value that is a function of the mobility and parasitic capacitance of the driving TFT (T2), and 'L' is the channel length of the second TFT (PT2). , 'W' means the channel width of the driving TFT (T2), respectively.

As shown in Equation 1, the current I _OLED of the organic light emitting diode _OLED changes according to the threshold voltage Vth or mobility of the driving TFT T2. Therefore, in order to make the image quality of the display image uniform in the organic light emitting diode display device, uniform electrical characteristics of the driving TFT (T2) are required on the entire display surface, but there are problems in that streaks and the like appear in the display image due to unevenness of the polysilicon thin film. have.

The current I _OLED of the organic light emitting diode OLED is also affected by the high potential power supply voltage VDD. However, since a resistance exists in the power line VL, a deviation of the high potential power voltage VDD occurs according to the pixel position on the display surface, which makes it difficult to make the image quality uniform throughout the display surface.

In order to compensate for the threshold voltage unevenness of the driving TFT (T2) in the organic light emitting diode device, a plurality of TFTs are additionally added to each pixel, and a capacitor or the like which stores the threshold voltage of the driving TFT is added to detect the threshold voltage of the driving TFT. Later, a scheme for compensating the threshold voltage of the driving TFT detected in the data voltage has been developed. However, this scheme has other problems that significantly reduce the aperture ratio of the pixel and make the panel more difficult due to many additional elements.

Accordingly, an object of the present invention is to provide an organic light emitting diode display device capable of achieving uniform image quality over the entire display surface by minimizing the influence of the threshold voltage and the power supply voltage of the driving TFT. To provide.

Another object of the present invention is to provide an organic light emitting diode display device which minimizes the decrease in the aperture ratio.

In order to achieve the above object, the organic light emitting diode display device according to an embodiment of the present invention includes a high potential power supply voltage source for generating a high potential power supply voltage; A low potential power voltage source for generating a low potential power voltage; An organic light emitting diode device emitting light by a current flowing between the high potential power voltage source and the low potential power voltage source; A first capacitor connected between a first node and the high potential power voltage source; A second capacitor connected between the first node and a second; A first switch element configured to supply a data voltage to the first node in response to a scan pulse during a first period and to block the data voltage during the second period; A second switch element which cuts off any one of the high potential power voltage and the low potential power voltage in response to a power interruption pulse during the first period, and supplies the blocked power supply voltage to the second node during the second period; ; And a driving device for supplying current to the organic light emitting diode device according to the voltages of the first and second nodes.

The scan pulse and the power cutoff pulse are in phase with each other.

The scan pulse is generated at a low potential voltage during the first period and the power cutoff pulse is generated at a high potential voltage during the first period.

The drive element and the switch element include a p-type MOS-FET having a semiconductor layer formed of any one of amorphous silicon and polysilicon.

The first switch element comprises a gate electrode supplied with the scan pulse, a source electrode supplied with the data voltage, and a drain electrode connected to the first node; The second switch element comprises a gate electrode supplied with the power interruption pulse, a source electrode supplied with the high potential power voltage, and a drain electrode connected to the second node; The driving device includes a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to an anode electrode of the organic light emitting diode device.

The current I _OLED flowing through the organic light emitting diode device during the second period is as follows.

Here, 'Vth' is a threshold voltage of the driving device, 'k' is a constant value that is a function of mobility and parasitic capacitance of the driving device, 'L' is the channel length of the driving device, and 'W' is the driving. The channel width of the device, 'VDD' means the high potential power supply voltage, 'C1' means the capacitance of the first capacitor, 'C2' means the capacitance of the second capacitor, respectively.

The scan pulse is generated at a high potential voltage during the first period and the power cutoff pulse is generated at a low potential voltage during the first period.

The drive element and the switch element include an n-type MOS-FET having a semiconductor layer containing any one of amorphous silicon and polysilicon.

The first switch element comprises a gate electrode supplied with the scan pulse, a drain electrode supplied with the data voltage, and a source electrode connected to the first node; The second switch element comprises a gate electrode supplied with the power interruption pulse, a source electrode supplied with the low potential power supply voltage, and a drain electrode connected to the second node; The driving device includes a gate electrode connected to the first node, a drain electrode connected to the second node, and a source electrode connected to a cathode electrode of the organic light emitting diode device.

An organic light emitting diode display device according to claim 1, wherein the current I _OLED flowing through the organic light emitting diode device during the second period is as follows.

Here, 'Vth' is a threshold voltage of the driving device, 'k' is a constant value that is a function of mobility and parasitic capacitance of the driving device, 'L' is the channel length of the driving device, and 'W' is the driving. The channel width of the device, 'VSS' means the low potential power supply voltage, 'C1' means the capacitance of the first capacitor, 'C2' means the capacitance of the second capacitor, respectively.

An organic light emitting diode display device according to another embodiment of the present invention includes a high potential power supply voltage source for generating a high potential power supply voltage; A low potential power voltage source for generating a low potential power voltage; An organic light emitting diode device emitting light by a current flowing between the high potential power voltage source and the low potential power voltage source; A first capacitor connected between a first node and the high potential power voltage source; A second capacitor connected between the first node and a second; A first switch element configured to supply a data voltage to the first node in response to a power cut & scan pulse and to block the data voltage during the second period; Interrupting any one of the high potential power voltage and the low potential power voltage in response to the power cut & scan pulse during the first period, and supplying the blocked power voltage to the second node during the second period. 2 switch elements; And a driving device for supplying current to the organic light emitting diode device according to the voltages of the first and second nodes.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 12.

Referring to FIG. 3, the organic light emitting diode display according to the first exemplary embodiment of the present invention includes a display panel 20 in which m × n pixels 24 are formed, and m data lines D1 to Dm. The data driving unit 22 for supplying the data voltage to the power supply and the power cutoff pulses VSW are sequentially supplied to the n power control lines VSW1 to VSWn and the scan pulses to the n scan lines SCAN1 to SCANn. And a scan driver 23 for sequentially supplying the SCAN, and a timing controller 21 for controlling the operation timing of the drivers 22 and 23.

In the display panel 20, the pixels 24 are disposed in pixel areas defined by intersections of the power control lines VSW1 to VSWn and the scan lines SCAN1 to SCANn and the m data lines D1 to Dm. Is formed. In the display panel 20, power supply wirings for supplying the high potential power voltage VDD and the low potential power voltage VSS to the pixels 24 are formed.

The data driver 22 converts the digital video data RGB from the timing controller 21 into an analog gamma compensation voltage. The data driver 22 supplies the analog gamma compensation voltage as the data voltage to the data lines D1 to Dm in response to the control signal DDC from the timing controller 21. The data voltage is supplied to the data lines D1 to Dm in synchronization with the power cut-off pulse VSW and the scan pulse SCAN.

The scan driver 23 sequentially supplies the power cutoff pulses VSW to the power control lines VSW1 to VSWn in response to the control signal SDC from the timing controller 21, and the power cutoff pulses. The scan pulse SCAN is sequentially supplied to the scan lines SCAN1 to SCANn as shown in FIG. The power cutoff pulse VSW indicates the time to cut off the high potential power voltage supplied to the pixels 24 of the selected line, and the scan pulse SCAN indicates the supply time of the data voltage supplied to the pixels of the selected line. Instruct.

The timing controller 21 supplies digital video data RGB to the data driver 22 and controls the operation timing of the scan driver 23 and the data driver 22 using the vertical / horizontal synchronization signal and the clock signal. Generate control signals (DDC, SDC).

Each of the pixels 24 includes an organic light emitting diode (OLED), three TFTs, and two capacitors as shown in FIGS. 4, 7, 9, and 11.

4 is a circuit diagram illustrating a first embodiment of the pixel 24 in detail, and FIGS. 5 and 6 are waveform diagrams showing driving waveforms of the pixel 24 according to the first embodiment of the present invention.

4 to 6, the pixel 24 includes the organic light emitting diode OLED, the first capacitor C1 and the first node formed between the high potential power voltage source VDD and the first node A. A first capacitor C2 formed between A) and the second node B and a first path forming a current path between the data lines D1 to Dm and the first node A in response to the scan pulse SCAN. High potential in response to the TFT (PT1), the second TFT (PT2) for adjusting the current of the organic light emitting diode (OLED) according to the voltages of the first and second nodes (A, B), and the power-off pulse (VSW). A third TFT PT3 is provided to block the power supply voltage VDD. The first to third TFTs PT1 to PT3 are p-type MOS-FETs having a semiconductor layer of amorphous or polysilicon.

The organic light emitting diode OLED has an structure in which an anode electrode is connected to the drain electrode of the second TFT PT2 and a cathode electrode is connected to the low potential power supply voltage source VSS.

The first capacitor C1 charges the difference voltage between the high potential power voltage VDD and the voltage charged in the first node A. The first capacitor C1 is connected to the second capacitor C2 via the first node A. The first capacitor C1 is combined with the second capacitor C2 and the threshold voltage of the second TFT PT2 and the high potential power voltage VDD at the current flowing through the organic light emitting diode device OLED during the light emitting period EP. To reduce the impact of

The second capacitor C2 is connected between the first node A and the second node B to detect the threshold voltage of the second TFT PT2 during the programming period PP and also during the light emitting period EP. The gate-source voltage of the second TFT PT2 is kept constant to make the light emitting amount of the organic light emitting diode OLED constant, and is combined with the first capacitor C1 as described above to form the organic light emitting diode element ( In the current flowing through the OLED, the threshold voltage of the second TFT PT2 and the high potential power supply voltage VDD are reduced.

The first TFT PT1 is turned on during the programming period in response to the scan pulse SCAN from the scan lines SCAN1 to SCANn to provide a current path between the data lines D1 to Dm and the first node A. FIG. Is formed to supply the data voltage to the first node (A). The gate electrode of this first TFT PT1 is connected to the scan lines SCAN1 to SCANn, and the source electrode is connected to the data lines D1 to Dm. The drain electrode of the first TFT PT1 is connected to the first node A. FIG.

The second TFT PT2 is a driving TFT and supplies current to the organic light emitting diode OLED according to the voltages of the first and second nodes A and B during the light emitting period EP. The gate electrode of this second TFT PT2 is connected to the first node A, and the source electrode is connected to the second node B. The drain electrode of the second TFT PT2 is connected to the anode electrode of the organic light emitting diode element OLED.

The third TFT PT3 is turned off during the programming period PP in response to the power cut-off pulses VSW from the power control lines VSW1 to VSWn, so that the high potential power voltage source VDD and the second node B are turned off. The current path between the circuits is blocked and turned on during the light emitting period EP to supply the high potential power voltage VDD to the second node B. The gate electrode of this third TFT PT3 is connected to the power supply control lines VSW1 to VSWn, and the source electrode is connected to the high potential power supply voltage source VDD. The drain electrode of the third TFT PT3 is connected to the second node B.

The current of the organic light emitting diode element in each of the pixels 24 is minimized by the influence of the threshold voltage and the power supply voltage of the second TFT PT2 which is the driving TFT. Operation of these pixels 24 will be described step by step.

During the programming period PP, the scan pulse SCAN is generated at a low potential voltage and at the same time, the power cut-off pulse VSW is generated at a high potential voltage. The first TFT PT1 is turned on in response to the scan pulse SCAN to supply the data voltage to the first node A, and the third TFT PT3 is turned on in response to the power cut-off pulse VSW. Off to cut off the high potential supply voltage (VDD). The organic light emitting diode OLED, in which the high potential power voltage VDD is cut off, operates as a resistive load and absorbs the current of the second node B through the second TFT PT2. This current discharges the parasitic capacitors of the second capacitor C2 and the organic light emitting diode element OLED to reduce the voltage across the organic light emitting diode element OLED. At this time, since the data voltage Vdata is applied to the gate electrode of the second TFT PT2, the voltage of the second node B is discharged and the voltage of the second node B becomes the data voltage + second TFT PT2. When the threshold voltage (Vth) is reached, the discharge current of the second node B becomes '0' and programming is completed. When programming is completed, the voltage V _A of the first node _A and the voltage V _B of the second node _B are represented by Equations 2 and 3 below.

During the light emitting period EP, the high potential voltage is supplied to the scan lines SCAN1 to SCANn and the low potential voltage is supplied to the power supply control lines VSW1 to VSWn. During the light emitting period, the first TFT PT1 is turned off, and at the same time, the third TFT PT3 is turned on to supply the high potential power voltage VDD to the second node B. Therefore, the voltage V _B of the second node B rises to the high potential power voltage VDD. The voltage V _A of the first node A is bootstraped by the voltage of the second capacitor C2. Equations 4 and 5 below represent the voltage V _A of the first node _A and the voltage V _B of the second node B during the light emitting period EP.

During the light emitting period EP, the second TFT PT2 operates in the saturation region to supply the current I _OLED to the organic light emitting diode OLED, and the current I _OLED is represented by Equation 6 below. .

만큼 감소된다. 데이터전압(Vdata)의 감소양은 데이터 구동부(22)에서 그 감소양만큼 데이터전압(Vdata)을 높임으로써 보상될 수 있다. As shown in Equation 6, the current I _OLED flowing in the organic light emitting diode OLED during the light emission period EP is the high potential power voltage VDD, the threshold voltage Vth of the second TFT PT2 and the data voltage. Is affected by (Vdata), the voltages (VDD, Vth, Vdata)

Is reduced by. The reduction amount of the data voltage Vdata may be compensated for by increasing the data voltage Vdata by the reduction amount in the data driver 22.

만큼 감소시켜 고전위 전원전압(VDD)과 제2 TFT(PT2)의 문턱전압(Vth)의 변화로 인한 화질저하를 줄일 수 있다. According to the present invention, the high potential power voltage VDD and the threshold voltage Vth of the second TFT PT2 affecting the current I _OLED of the organic light emitting diode device OLED are represented by Equation 6 below.

As a result, the image quality deterioration due to the change of the high potential power voltage VDD and the threshold voltage Vth of the second TFT PT2 can be reduced.

FIG. 7 is a circuit diagram showing a second embodiment of the pixel 24 in detail, and FIG. 8 is a waveform diagram showing driving waveforms of the pixel 24 according to the second embodiment of the present invention.

7 and 8, the pixel 24 includes a first capacitor C1 and a first node formed between the organic light emitting diode device OLED, the high potential power voltage source VDD, and the first node A. The first and third TFTs NT1 and PT3 and the first and second nodes simultaneously controlled by the second capacitor C2 formed between A) and the second node B, the power cut & scan pulses VSW & SCAN. A second TFT (PT2) for adjusting the current of the organic light emitting diode (OLED) in accordance with the voltage of A, B). The first TFT NT1 is an n-type MOS-FET having an amorphous or polysilicon semiconductor layer, and the second and third TFTs PT2 and PT3 are a p-type MOS-FET having an amorphous or polysilicon semiconductor layer. admit.

In the present invention, TFTs having different channel characteristics are formed in one pixel by using a complementary metal oxide semiconductor (CMOS) process to form the pixel as shown in FIG. 7.

Since the first and second capacitors C1 and C2 and the organic light emitting diode OLED are substantially the same as those of the above-described embodiment, a detailed description thereof will be omitted.

The power cut & scan pulses VSW & SCAN serve as the power cut pulse VSW and the scan pulse SCAN described in the first embodiment.

In the pixel array of the display panel 20 to which the pixel 24 as shown in FIG. 7 is applied, signal wirings formed in the horizontal direction are reduced to 1/2 compared to the above-described first embodiment, and required for the gate driver 23. The number of circuits is reduced to 1/2. Therefore, the organic light emitting diode display device according to the second embodiment of the present invention can increase the aperture ratio and lower the driving circuit cost compared to the first embodiment.

The first TFT NT1 is turned on during the programming period in response to the power-off & scan pulses VSW & SCAN from the power-off lines VSW1 to VSWn, so that the data lines D1 to Dm and the first node A are turned on. A current path therebetween is formed to supply a data voltage to the first node A. The gate electrode of this first TFT NT1 is connected to the power cutoff lines VSW1 to VSWn, and the drain electrode is connected to the data lines D1 to Dm. The source electrode of the first TFT NT1 is connected to the first node A. As shown in FIG.

The second TFT PT2 is a driving TFT and supplies current to the organic light emitting diode OLED according to the voltages of the first and second nodes A and B during the light emitting period EP. The gate electrode of this second TFT PT2 is connected to the first node A, and the source electrode is connected to the second node B. The drain electrode of the second TFT PT2 is connected to the anode electrode of the organic light emitting diode element OLED.

만큼 감소시켜 고전위 전원전압(VDD)과 제2 TFT(PT2)의 문턱전압(Vth)의 변화로 인한 화질저하를 줄일 수 있다. The third TFT PT3 is turned off during the programming period PP in response to the power cut & scan pulse VSW & SCAN from the power control lines VSW1 to VSWn, so that the high potential power voltage source VDD and the second node are turned off. The current path between (B) is interrupted and turned on during the light emitting period EP to supply the high potential power voltage VDD to the second node B. The gate electrode of this third TFT PT3 is connected to the power supply control lines VSW1 to VSWn, and the source electrode is connected to the high potential power supply voltage source VDD. The drain electrode of the third TFT PT3 is connected to the second node B. In this embodiment, the high potential power voltage VDD and the threshold voltage Vth of the second TFT PT2 affecting the current I _OLED of the organic light emitting diode device OLED are represented by Equation 5 below.

As a result, the image quality deterioration due to the change of the high potential power voltage VDD and the threshold voltage Vth of the second TFT PT2 can be reduced.

FIG. 9 is a circuit diagram showing a third embodiment of the pixel 24 in detail, and FIG. 10 is a waveform diagram showing driving waveforms of the pixel 24 according to the third embodiment of the present invention.

9 and 10, the pixel 24 includes a first capacitor C1 and a first node formed between the organic light emitting diode device OLED, the high potential power voltage source VDD, and the first node A. A second capacitor C2 formed between A) and the second node B, and a current path formed between the data lines D1 to Dm and the first node A in response to the scan pulse / SCAN. In response to the first TFT (NT1), the second TFT (NT2) for adjusting the current of the organic light emitting diode (OLED) according to the voltages of the first and second nodes (A, B), and the power-off pulse (/ VSW). A third TFT NT3 for blocking the low potential power voltage VSS is provided. The first to third TFTs NT1 to NT3 are n-type MOS-FETs having a semiconductor layer of amorphous or polysilicon.

The power-off pulse (/ VSW) and the scan pulse (/ SCAN) of this embodiment are formed by n-type MOS-FETs, so that the power-off pulse (VSW) and the scan pulse (SCAN) of the first embodiment described above are different from each other. It occurs in reverse phase.

In the organic light emitting diode OLED, a cathode electrode is connected to the drain electrode of the second TFT NT2, and an anode electrode is connected to the high potential power voltage source VDD, and has a structure as shown in FIG.

The first capacitor C1 charges the difference voltage between the high potential power voltage VDD and the voltage charged in the first node A. The first capacitor C1 is connected to the second capacitor C2 via the first node A. The first capacitor C1 is combined with the second capacitor C2 and the threshold voltage of the second TFT NT2 and the high potential power voltage VDD at the current flowing through the organic light emitting diode device OLED during the light emitting period EP. To reduce the impact of

The second capacitor C2 is connected between the first node A and the second node B to detect the threshold voltage of the second TFT NT2 during the programming period PP and also during the emission period EP. The gate-source voltage of the second TFT NT2 is kept constant so that the amount of light emitted by the organic light emitting diode OLED is constant, and as described above, the organic light emitting diode element is combined with the first capacitor C1. In the current flowing through the OLED, the threshold voltage of the second TFT NT2 and the high potential power voltage VDD are reduced.

The first TFT NT1 is turned on during the programming period in response to the scan pulse / SCAN from the scan lines SCAN1 to SCANn, so that the current between the data lines D1 to Dm and the first node A is turned on. A path is formed to supply a data voltage to the first node A. The gate electrode of this first TFT NT1 is connected to the scan lines SCAN1 to SCANn, and the drain electrode is connected to the data lines D1 to Dm. The source electrode of the first TFT NT1 is connected to the first node A. As shown in FIG.

The second TFT NT2 is a driving TFT and supplies current to the organic light emitting diode OLED according to the voltages of the first and second nodes A and B during the light emitting period EP. The gate electrode of this second TFT PT2 is connected to the first node A, and the source electrode is connected to the second node B. The drain electrode of the second TFT NT2 is connected to the cathode electrode of the organic light emitting diode element OLED.

The third TFT NT3 is turned off during the programming period PP in response to the power cut-off pulses / VSW from the power control lines VSW1 to VSWn, so that the low potential power voltage source VSS and the second node ( The current path between B) is blocked and turned on during the light emitting period EP to supply the low potential power voltage VDD to the second node B. The gate electrode of this third TFT NT3 is connected to the power supply control lines VSW1 to VSWn, and the source electrode is connected to the low potential power supply voltage source VSS. The drain electrode of the third TFT NT3 is connected to the second node B.

The current of the organic light emitting diode element in each of the pixels 24 is minimized by the influence of the threshold voltage and the power supply voltage of the second TFT NT2 which is the driving TFT. Operation of these pixels 24 will be described step by step.

During the programming period PP, the scan pulse / SCAN is generated at the high potential voltage and at the same time, the power cut-off pulse / VSW is generated at the low potential voltage. The first TFT NT1 is turned on in response to the scan pulse / SCAN to supply the data voltage to the first node A, and the third TFT NT3 in response to the power cut-off pulse / VSW. It is turned off to cut off the low potential supply voltage (VSS). The organic light emitting diode OLED in which the low potential power voltage VSS is cut off operates as a resistive load and absorbs the current of the second node B through the second TFT NT2. This current discharges the parasitic capacitors of the second capacitor C2 and the organic light emitting diode element OLED to reduce the voltage across the organic light emitting diode element OLED. At this time, since the data voltage Vdata is applied to the gate electrode of the second TFT NT2, the voltage of the second node B is discharged and the voltage of the second node B becomes the data voltage + the second TFT NT2. When the threshold voltage (Vth) is reached, the discharge current of the second node B becomes '0' and programming is completed.

During the light emitting period EP, the low potential voltage is supplied to the scan lines SCAN1 to SCANn and the high potential voltage is supplied to the power supply control lines VSW1 to VSWn. During the light emitting period, the first TFT NT1 is turned off, and at the same time, the third TFT NT3 is turned on to supply the low potential power supply voltage VSS to the second node B. Therefore, the voltage V _B of the second node B drops to the low potential power supply voltage VSS. The voltage V _A of the first node A is bootstraped by the voltage of the second capacitor C2.

During the light emitting period EP, the second TFT NT2 operates in a saturation region to supply a current I _OLED to the organic light emitting diode OLED, and the current I _OLED is represented by Equation 7 below. .

만큼 감소된다. 데이터전압(Vdata)의 감소양은 데이터 구동부(22)에서 그 감소양만큼 데이터전압(Vdata)을 높임으로써 보상될 수 있다. As shown in Equation 7, the current I _OLED flowing in the organic light emitting diode OLED during the light emitting period EP is the low potential power voltage VSS, the threshold voltage Vth of the second TFT NT2 and the data voltage. Affected by (Vdata), the voltages (VSS, Vth, Vdata)

Is reduced by. The reduction amount of the data voltage Vdata may be compensated for by increasing the data voltage Vdata by the reduction amount in the data driver 22.

만큼 감소시켜 저전위 전원전압(VSS)과 제2 TFT(NT2)의 문턱전압(Vth)으로 인한 화질저하를 줄일 수 있다. According to the present invention, the variation of the low potential power supply voltage VSS and the threshold voltage Vth of the second TFT NT2 affecting the current I _OLED of the organic light emitting diode device OLED is represented by Equation 7 below.

As a result, the image quality degradation due to the low potential power voltage VSS and the threshold voltage Vth of the second TFT NT2 can be reduced.

FIG. 11 is a circuit diagram illustrating a fourth embodiment of the pixel 24 in detail, and FIG. 12 is a waveform diagram showing driving waveforms of the pixel 24 according to the fourth embodiment of the present invention.

11 and 12, the pixel 24 includes a first capacitor C1 and a first node formed between the organic light emitting diode device OLED, the high potential power voltage source VDD, and the first node A. In response to the second capacitor C2 and the power cut & scan pulse / VSW & SCAN formed between A) and the second node B, a current path between the data lines D1 to Dm and the first node A is applied. The first TFT PT1 to be formed, the second TFT NT2 to adjust the current of the organic light emitting diode OLED according to the voltages of the first and second nodes A and B, and the power cut & scan pulse (/ And a third TFT NT3 for blocking the low potential power supply voltage VSS in response to VSW & SCAN. The first TFT PT1 is a p-type MOS-FET having a semiconductor layer of amorphous or polysilicon. The second and third TFTs NT2 and NT3 are n-type MOS-FETs having a semiconductor layer of amorphous or polysilicon.

The present invention forms TFTs having different channel characteristics in one pixel by using a complementary metal oxide semiconductor (CMOS) process to form the pixel 24 as shown in FIG.

Since the first and second capacitors C1 and C2 and the organic light emitting diode OLED are substantially the same as those of the above-described embodiment, a detailed description thereof will be omitted.

The signal lines formed in the horizontal direction in the pixel array of the display panel 20 to which the pixel 24 as shown in FIG. 11 is applied are reduced to 1/2 compared to the above-described third embodiment, and required for the gate driver 23. The number of circuits is reduced to 1/2. Therefore, the organic light emitting diode display device according to the fourth embodiment of the present invention can increase the aperture ratio and lower the driving circuit cost compared to the third embodiment.

The power cut & scan pulse / VSW & SCAN serves as the power cut pulse / VSW and the scan pulse / SCAN described in the above-described third embodiment.

The first TFT PT1 is turned on during the programming period in response to the power-off & scan pulse / VSW & SCAN from the scan lines SCAN1 to SCANn, so that the data lines D1 to Dm and the first node A are turned on. A current path therebetween is formed to supply a data voltage to the first node (A). The gate electrode of this first TFT NT1 is connected to the scan lines SCAN1 to SCANn, and the source electrode is connected to the data lines D1 to Dm. The drain electrode of the first TFT PT1 is connected to the first node A. FIG.

The second TFT NT2 is a driving TFT and supplies current to the organic light emitting diode OLED according to the voltages of the first and second nodes A and B during the light emitting period EP. The gate electrode of this second TFT PT2 is connected to the first node A, and the source electrode is connected to the second node B. The drain electrode of the second TFT NT2 is connected to the cathode electrode of the organic light emitting diode element OLED.

The third TFT NT3 is turned off during the programming period PP in response to the power cut & scan pulse / VSW & SCAN from the scan lines SCAN1 to SCANn, so that the low potential power voltage source VSS and the second node are turned off. The current path between (B) is blocked and turned on during the light emitting period EP to supply the low potential power voltage VDD to the second node B. The gate electrode of this third TFT NT3 is connected to the scan lines SCAN1 to SCANn, and the source electrode is connected to the low potential power supply voltage source VSS. The drain electrode of the third TFT PT3 is connected to the second node n2.

만큼 감소시켜 저전위 전원전압(VSS)과 제2 TFT(NT2)의 문턱전압(Vth)으로 인한 화질저하를 줄일 수 있다. In the fourth embodiment of the present invention, the low potential power supply voltage VSS and the threshold voltage Vth of the second TFT NT2 affecting the current I _OLED of the organic light emitting diode device OLED are represented by together

As a result, the image quality degradation due to the low potential power voltage VSS and the threshold voltage Vth of the second TFT NT2 can be reduced.

As described above, the organic light emitting diode display device according to the present invention minimizes the influence of the threshold voltage and the power supply voltage of the driving TFT to obtain a uniform image quality over the entire display surface, and the number of TFTs and capacitors required for each pixel. It is possible to minimize the decrease in the aperture ratio by reducing the increase.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (19)

A high potential power voltage source generating a high potential power voltage; A low potential power voltage source for generating a low potential power voltage; An organic light emitting diode device emitting light by a current flowing between the high potential power voltage source and the low potential power voltage source; A first capacitor connected between a first node and the high potential power voltage source; A second capacitor connected between the first node and a second; A first switch element configured to supply a data voltage to the first node in response to a scan pulse during a first period and to block the data voltage during the second period; A second switch which cuts any one of the high potential power voltage and the low potential power voltage in response to a power interruption pulse during the first period, and supplies the blocked power supply voltage to the second node again during the second period; device; And And a driving device for supplying current to the organic light emitting diode device according to the voltages of the first and second nodes. The method of claim 1, And the scan pulse and the power cut-off pulse are out of phase with each other. The method of claim 2, And the scan pulse is generated at a low potential voltage during the first period and the power cut-off pulse is generated at a high potential voltage during the first period. The method of claim 3, wherein And the driving device and the switch device include a p-type MOS-FET having a semiconductor layer formed of any one of amorphous silicon and polysilicon. The method of claim 4, wherein The first switch element comprises a gate electrode supplied with the scan pulse, a source electrode supplied with the data voltage, and a drain electrode connected to the first node; The second switch element comprises a gate electrode supplied with the power interruption pulse, a source electrode supplied with the high potential power voltage, and a drain electrode connected to the second node; The driving device includes a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to an anode electrode of the organic light emitting diode device. . The method of claim 5, wherein An organic light emitting diode display device according to claim 1, wherein the current I _OLED flowing through the organic light emitting diode device during the second period is as follows.

Here, 'Vth' is a threshold voltage of the driving device, 'k' is a constant value that is a function of mobility and parasitic capacitance of the driving device, 'L' is the channel length of the driving device, and 'W' is the driving. The channel width of the device, 'VDD' means the high potential power supply voltage, 'C1' means the capacitance of the first capacitor, 'C2' means the capacitance of the second capacitor, respectively. The method of claim 2, And the scan pulse is generated at a high potential voltage during the first period and the power cut-off pulse is generated at a low potential voltage during the first period. The method of claim 7, wherein And the driving device and the switch device include an n-type MOS-FET having a semiconductor layer including any one of amorphous silicon and polysilicon. The method of claim 8, The first switch element comprises a gate electrode supplied with the scan pulse, a drain electrode supplied with the data voltage, and a source electrode connected to the first node; The second switch element comprises a gate electrode supplied with the power interruption pulse, a source electrode supplied with the low potential power supply voltage, and a drain electrode connected to the second node; The driving device includes a gate electrode connected to the first node, a drain electrode connected to the second node, and a source electrode connected to a cathode electrode of the organic light emitting diode device. . The method of claim 9, An organic light emitting diode display device according to claim 1, wherein the current I _OLED flowing through the organic light emitting diode device during the second period is as follows.

Here, 'Vth' is a threshold voltage of the driving device, 'k' is a constant value that is a function of mobility and parasitic capacitance of the driving device, 'L' is the channel length of the driving device, and 'W' is the driving. The channel width of the device, 'VSS' means the low potential power supply voltage, 'C1' means the capacitance of the first capacitor, 'C2' means the capacitance of the second capacitor, respectively. A high potential power voltage source generating a high potential power voltage; A low potential power voltage source for generating a low potential power voltage; An organic light emitting diode device emitting light by a current flowing between the high potential power voltage source and the low potential power voltage source; A first capacitor connected between a first node and the high potential power voltage source; A second capacitor connected between the first node and a second; A first switch element configured to supply a data voltage to the first node in response to a power cut & scan pulse and to block the data voltage during the second period; Interrupting any one of the high potential power voltage and the low potential power voltage in response to the power cut & scan pulse during the first period, and supplying the blocked power voltage to the second node during the second period. 2 switch elements; And And a driving device for supplying current to the organic light emitting diode device according to the voltages of the first and second nodes. The method of claim 11, And the power cut & scan pulse is generated at a high potential voltage during the first period. The method of claim 12, The drive element and the second switch element include a p-type MOS-FET having a semiconductor layer formed of any one of amorphous silicon and polysilicon; And the first switch element comprises an n-type MOS-FET having a semiconductor layer formed of any one of the amorphous silicon and the polysilicon. The method of claim 13, The first switch element comprises a gate electrode supplied with the power cut & scan pulse, a drain electrode supplied with the data voltage, and a source electrode connected to the first node; The second switch element includes a gate electrode to which the power cut & scan pulse is supplied, a source electrode to which the high potential power voltage is supplied, and a drain electrode connected to the second node; The driving device includes a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to an anode electrode of the organic light emitting diode device. . The method of claim 14, An organic light emitting diode display device according to claim 1, wherein the current I _OLED flowing through the organic light emitting diode device during the second period is as follows.

Here, 'Vth' is a threshold voltage of the driving device, 'k' is a constant value that is a function of mobility and parasitic capacitance of the driving device, 'L' is the channel length of the driving device, and 'W' is the driving. The channel width of the device, 'VDD' means the high potential power supply voltage, 'C1' means the capacitance of the first capacitor, 'C2' means the capacitance of the second capacitor, respectively. The method of claim 11, And the power cut & scan pulse is generated at a low potential voltage during the first period. The method of claim 16, The first switch element comprises a p-type MOS-FET having a semiconductor layer formed of any one of amorphous silicon and polysilicon; And the driving device and the second switch device include an n-type MOS-FET having a semiconductor layer formed of any one of the amorphous silicon and the polysilicon. The method of claim 17, The first switch element includes a gate electrode to which the power cut & scan pulse is supplied, a source electrode to which the data voltage is supplied, and a drain electrode connected to the first node; The second switch element includes a gate electrode to which the power cut & scan pulse is supplied, a source electrode to which the low potential power voltage is supplied, and a drain electrode connected to the second node; The driving device includes a gate electrode connected to the first node, a drain electrode connected to the second node, and a source electrode connected to a cathode electrode of the organic light emitting diode device. . The method of claim 18, An organic light emitting diode display device according to claim 1, wherein the current I _OLED flowing through the organic light emitting diode device during the second period is as follows.

Here, 'Vth' is a threshold voltage of the driving device, 'k' is a constant value that is a function of mobility and parasitic capacitance of the driving device, 'L' is the channel length of the driving device, and 'W' is the driving. The channel width of the device, 'VSS' means the low potential power supply voltage, 'C1' means the capacitance of the first capacitor, 'C2' means the capacitance of the second capacitor, respectively.

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