KR20070071524A - Method and apparatus for driving organic light diode display - Google Patents

Abstract

A method and an apparatus for driving an OLED(Organic Light Emitting Diode) display device are provided to recover characteristic of a TFT by compensating for the threshold voltage variation of the TFT. Reset and data voltages(Vrst,Vdata) are supplied to a data line(DL). First and second logical voltages are supplied through first and second scan lines(Sl,Sll), which are formed to cross with the data line. A reset pulse(RST) is supplied through a reset line(RL), which is formed to cross with the data line. Plural pixels are arranged in a matrix from. An OLED element(OLED) and a storage capacitor are formed on the each pixel. A first TFT(T1) supplies reset and data voltages from the data lines to a first node(n1). A second TFT(T2) controls current flow in the OLED element. A compensating circuit(41) stores the reset voltage of the first node in the storage capacitor, compensates for the data voltage as much as a threshold voltage of the second TFT, supplies the compensated data voltage to a second node(n2), and stores the compensated data voltage in the storage capacitor. A recovery circuit(42) supplies the second logical voltage to the second node.

Description

TECHNICAL AND APPARATUS FOR DRIVING ORGANIC LIGHT DIODE DISPLAY}

1 is a view schematically showing a structure of a conventional organic light emitting diode display device.

Fig. 2 is a circuit diagram equivalently showing one pixel in a conventional active matrix organic light emitting diode display element.

3 is a graph illustrating an example of threshold voltage variation of the driving thin film transistor illustrated in FIG. 2.

4 is a block diagram illustrating an organic light emitting diode display device according to an exemplary embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of one pixel illustrated in FIG. 4. FIG.

FIG. 6 is a waveform diagram illustrating a drive signal supplied to the pixel illustrated in FIG. 5. FIG.

FIG. 7 is a circuit diagram for describing an operation of the pixel illustrated in FIG. 5 during a period P1 of FIG. 6.

FIG. 8 is a circuit diagram for describing an operation of the pixel illustrated in FIG. 5 during a P2 period of FIG. 6.

9 is a graph for explaining the recovery principle of the threshold voltage characteristics of the thin film transistor by the recovery circuit shown in FIG.

10 is a waveform diagram showing a reset pulse according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

30: display panel 31: timing controller

32: data driver 33: gate driver

34: reset driver 41: compensation circuit

42: recovery circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display device, and more particularly, to a method and apparatus for driving an organic light emitting diode display device which compensates a threshold voltage variation of a thin film transistor and restores the characteristics of the thin film transistor to its original state.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (FED) plasma display panels (hereinafter referred to as "PDPs") and electroluminescence. Electroluminescence Device and the like.

Among them, PDP is attracting attention as the most favorable display device for light and small size and large screen because of its simple structure and manufacturing process, but it has the disadvantages of low luminous efficiency, low luminance and high power consumption. Active matrix LCDs with thin film transistors (hereinafter referred to as "TFTs") as switching devices are difficult to screen due to the use of semiconductor processes, but demand is increasing as they are mainly used as display devices in notebook computers. In contrast, the electroluminescent device is classified into an inorganic electroluminescent device and an organic light emitting diode device according to the material of the light emitting layer. The electroluminescent device is a self-light emitting device that emits light, and has a high response speed and high luminous efficiency, luminance, and viewing angle.

As the organic light emitting diode device, as shown in FIG. 1, an anode electrode made of a transparent conductive material is formed on a glass substrate, and an organic compound layer and a cathode electrode made of a conductive metal are stacked. The organic compound layer includes a hole injection layer, a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. do.

When a driving voltage is applied to the anode electrode and the cathode electrode, holes in the hole injection layer and electrons in the electron injection layer proceed toward the light emitting layer to excite the light emitting layer, thereby causing the light emitting layer to emit visible light. Thus, an image or an image is displayed by the visible light generated from the light emitting layer.

Such an organic light emitting diode device is divided into a passive matrix method and an active matrix method using a thin film transistor (hereinafter, referred to as a TFT) as a switching device. The passive matrix method selects the light emitting cells according to the current applied to the electrodes by orthogonal to the anode electrode and the cathode electrode, whereas the active matrix method selects the light emitting cells by turning on the TFT, and a storage capacitor. The light emission of the light emitting cell is maintained at a voltage maintained at.

2 is an equivalent circuit diagram of one pixel in an organic light emitting diode display device of an active matrix type.

Referring to FIG. 2, an organic light emitting diode display device of an active matrix type includes an organic light emitting diode (OLED), an intersecting data line DL and a gate line GL, a switch TFT (SW_TFT), and a driving TFT (DRV_TFT). , And a storage capacitor Cst.

The switch TFT SW_TFT is turned on in response to the gate high voltage (or scan voltage) from the gate line GL to conduct a current path between its source terminal and the drain terminal, and the voltage on the gate line GL. When the gate low voltage is less than its own threshold voltage (Vth) is maintained off. During the on-time period of the switch TFT SW_TFT, the data voltage from the data line DL is applied to the gate terminal of the driving TFT DRV_TFT via the source terminal and the drain terminal of the switch TFT SW_TFT. On the contrary, during the off time period of the switch TFT SW_TFT, the current path between the source terminal and the drain terminal of the switch TFT SW_TFT is opened so that the data voltage VDL is not applied to the driving TFT DRV_TFT.

The driving TFT DRV_TFT adjusts an amount of current between the source terminal and the drain terminal according to the data voltage supplied to its gate terminal to emit the organic light emitting diode OLED with brightness corresponding to the data voltage.

The storage capacitor Cst stores the difference voltage between the data voltage and the low potential common voltage VSS to maintain a constant voltage applied to the gate terminal of the driving TFT DRV_TFT for one frame period.

The organic light emitting diode OLED has a structure as shown in FIG. 1 and includes a cathode terminal connected to the drain terminal of the driving TFT DRV_TFT and a cathode terminal supplied with a high potential driving voltage VDD. The organic light emitting diode OLED emits light by the current from the driving TFT DRV_TFT.

However, an active matrix organic light emitting diode display device has a problem in that image quality deteriorates due to a change in the threshold voltage of the driving TFT DRV_TFT. In particular, when the semiconductor layers of the TFTs are made of amorphous silicon, gate voltages of the same polarity are repeatedly applied as the driving time elapses, and as the time passes, the threshold voltage fluctuation due to the cumulative stress becomes severe. Such amorphous silicon type TFTs are more affected by threshold voltage variations than polysilicon type TFTs.

3 shows an example of variation in threshold voltage due to cumulative stress in an amorphous silicon type TFT.

Referring to FIG. 3, in the case of an amorphous silicon type TFT, which is an N-type MOS-FET, when a gate voltage is applied to the gate electrode with a positive voltage for a long time, the threshold voltage is moved in the direction of the arrow, and as a result, the threshold voltage moves to the initial state at the same gate voltage. As compared with time, the current flowing through the organic light emitting diode OLED becomes smaller.

Accordingly, an object of the present invention is to provide a method and apparatus for driving an organic light emitting diode display device which compensates for a threshold voltage variation of a TFT and recovers the characteristics of the TFT to its original state.

In order to achieve the above object, a method of driving an organic light emitting diode display device according to the present invention comprises the steps of supplying a reset voltage to the data line; Supplying the reset voltage to a storage capacitor to initialize the storage capacitor; Supplying a scan pulse of a first logic voltage to the first scan line to turn on the first transistor; Supplying a data voltage to the data line; Compensating the data voltage supplied through the first thin film transistor by the threshold voltage of the second thin film transistor to generate a compensation data voltage and storing the compensated data voltage in the storage capacitor; Supplying a second logic voltage to the first scan line and supplying a reset pulse to a reset line; And supplying the second logic voltage to the gate electrode of the second thin film transistor in response to the reset pulse.

In the driving method, when the scan pulse of the first logic voltage is supplied to the first scan line, the second thin film transistor is turned off by supplying the scan pulse of the second logic voltage to a second scan line to turn off the organic light emitting diode device. Opening the current path of the further comprises.

An apparatus for driving an organic light emitting diode display device according to the present invention includes: a data line to which a reset voltage and a data voltage are supplied; A first scan line crossing the data line and having a first scan pulse and a second logic voltage of a first logic voltage; A reset line crossing the data line and supplied with a reset pulse; A plurality of pixels arranged in a matrix form; An organic light emitting diode element formed in each of the pixels; A storage capacitor formed in each of the pixels; A first thin film transistor supplying a reset voltage and a data voltage from the data line to a first node in response to the first scan pulse in the pixel; A second thin film transistor for controlling a current flowing through the organic light emitting diode device in response to a voltage of a second node in the pixel; After storing the reset voltage of the first node in the storage capacitor, the data voltage is compensated by the threshold voltage of the second thin film transistor to generate a compensation data voltage, and the compensation data voltage is supplied to the second node to store the storage voltage. A compensation circuit for storing the compensation data voltage in a capacitor; And a recovery circuit for supplying the voltage of the second node to the second logic voltage from the first scan line in response to the reset pulse.

Each of the compensation circuit and the recovery circuit is disposed in the pixel.

The driving device is configured to supply a second scan pulse of a second logic voltage and supply the second logic voltage to the first scan line while a first scan pulse of the first logic voltage is supplied to the first scan line. A second scan line to which the first logic voltage is supplied during the second scan line; A sixth thin film transistor for opening a current path between the organic light emitting diode device and a third node in response to a second logic voltage from the second scan line; The second thin film transistor controls the current between the third node and the low potential driving voltage source in response to the voltage of the second node.

The compensation circuit includes a third thin film transistor having a gate electrode and a source electrode connected to the first node, and a drain electrode connected to the second node; A fourth thin film transistor includes a drain electrode connected to the first node and a gate electrode and a source electrode connected to the second node.

The recovery circuit includes a fifth thin film transistor having a gate electrode connected to the reset line, a source electrode connected to the first scan line, and a drain electrode connected to the second node.

The organic light emitting diode device is connected between a high potential driving voltage source and a source electrode of the sixth thin film transistor.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 11.

4 to 6, a driving device of an organic light emitting diode display device according to an exemplary embodiment of the present invention includes a display panel 30 in which m × n pixels are formed, and data on data lines DL1 to DLm. A data driver 32 for supplying a voltage and a scan driver 33 for sequentially supplying a pair of anti-phase scan pulses to the first and second scan lines SI1 to SIn and SII1 to SIIn; And a reset driver 34 for supplying the reset pulse to the reset lines RL1 to RLn, and a timing controller 31 for controlling the drivers 32, 33, and 34.

The display panel 30 includes n first and second scan lines SI1 through SIn and SII1 through SIIn, and n first and second scan lines SI1 through SIn and SII1 through pixel, respectively. M data lines DL1 through DLm and m reset lines RL1 through RLn intersecting with SIIn are formed. Each pixel of the display panel 30 is supplied with a high potential driving voltage VDD and a low potential driving voltage VSS.

The data driver 32 controls the storage capacitor Cst of each pixel 35 before the organic light emitting diode OLED of each pixel 35 emits light in response to the control signal DDC from the timing controller 31. After supplying the reset voltage Vrst for initialization to the data lines DL1 to DLm, the digital video data RGB from the timing controller 31 is converted into an analog gamma compensation voltage lower than the reset voltage Vrst. The analog gamma compensation voltage is supplied to the data lines DL1 to DLm of the display panel 30 as the data voltage Vdata.

The scan driver 33 sequentially supplies the first scan pulse SP1 having a high logic voltage to the first scan lines SI1 to SIn in response to the control signal SDC from the timing controller 31. The second scan pulse SP2 having a low logic voltage generated out of phase with the first scan pulse SP1 is sequentially supplied to the first scan lines SI1 to SIn to be synchronized with the first scan pulse SP1. .

The first and second scan pulses SP1 and SP2 have a period P1 during which the storage capacitor Cst of each pixel 35 is initialized, and a period P2 during which a data voltage whose threshold voltage is compensated is stored in the storage capacitor Cst. Occurs during.

The reset driver 34 simultaneously supplies the reset pulses to the reset lines RL1 to RLn immediately after the conventional scanning of the frame after all the horizontal scanning lines have been scanned. For example, scan pulses and data are applied to about 90% of one frame period, and the reset driver 34 supplies reset pulses to the reset lines RL1 to RLn within the remaining 10% of the one frame period. On the other hand, the reset lines RL to RLn are commonly connected at the output terminal of the reset driver 34.

The timing controller 31 supplies the digital video data RGB to the data driver 32, and scan scan unit 33, data driver 32, and reset driver 34 by using a vertical / horizontal synchronization signal and a clock signal. Generates control signals DDC, GDC, RDC to control the operation timing of the signal.

Each of the pixels formed in the display panel 32 includes an organic light emitting diode (OLED), a storage capacitor (Cst), a first TFT (T1), a second TFT (T2), and a sixth TFT (T6) as shown in FIG. 4. And a compensation circuit 41 and a recovery circuit 42.

The organic light emitting diode OLED has a structure as shown in FIG. 1 in each pixel. The organic light emitting diode OLED emits light by flowing a current corresponding to the data voltage stored in the storage capacitor Cst during the light emitting period during which the second and sixth TFTs T2 and T6 are kept in an on state.

The storage capacitor Cst is initialized to the reset voltage Vrst before the light emitting period of the organic light emitting diode OLED by the compensation circuit 41 and then compensates for the data voltage compensated by the threshold voltage of the second TFT T2. To charge.

The first TFT T1 is a switch TFT and transmits the data voltage from the data line DL to the first node n1 in response to the first scan pulse of the high logic voltage supplied from the first scan line SI. Supply. The gate electrode of this first TFT T1 is connected to the first scan line SI and the source electrode is connected to the data line DL. The drain electrode of the first TFT T1 is connected to the first node n1.

The second TFT T2 serves as a driving TFT to flow the current between the source electrode and the drain electrode as much as the data voltage stored in the storage capacitor Cst to allow the current to flow through the organic light emitting diode OLED. Drive. The gate electrode of this second TFT T2 is connected to the second node n2, and the source electrode is connected to the third node n3. The drain electrode of the second TFT T2 is connected to a low potential common voltage source that generates a low potential driving voltage VSS or a base voltage.

The sixth TFT T6 is a switch TFT and is turned off during the periods P1 and P2 when the second scan pulse SP2 having a low logic voltage is supplied to the second scan line SII, so that the current of the organic light emitting diode OLED is changed. The path is blocked and is maintained in the other light emitting period to form a current path of the organic light emitting diode device OLED. The gate electrode of the sixth TFT T6 is connected to the second scan line SII, and the source electrode is connected to the high potential driving voltage VDD. The drain electrode of the sixth TFT T6 is connected to the source electrode of the second TFT T2 via the third node n3.

The compensation circuit 41 initializes the storage capacitor Cst in response to the voltage of the first node n1 and generates a data voltage (hereinafter referred to as a "compensation data voltage") for compensating the threshold of the second TFT. The compensation data voltage is stored in the storage capacitor Cst.

Each of the compensation circuits 41 serves as a diode and has third and fourth TFTs T3 and T4 having substantially the same or similar semiconductor characteristics as the second TFT T2.

As shown in FIG. 7, the third TFT T3 is turned on when the voltage of the first node n1 is higher than the voltage of the second node n2 by more than its threshold voltage so as to reset the voltage from the data line DL. Vrst is stored in the storage capacitor Cst. When the third TFT T3 is turned on, the current i flows from the first node n1 toward the second node n2. The gate electrode and the source electrode of this third TFT T3 are connected to the first node n1 and the drain electrode is connected to the second node n2.

As shown in FIG. 8, the fourth TFT T4 is turned on when the voltage of the second node n2 is higher than its own threshold voltage than the voltage of the first node n1 to reset the voltage of the storage capacitor Cst. The voltage Vrst is lowered from the data voltage Vdata to the threshold voltage of the fourth TFT T4. When the fourth TFT T4 is turned on, the current i flows from the second node n2 toward the first node n1. The gate electrode and the source electrode of this fourth TFT T4 are connected to the second node n2 and the drain electrode is connected to the first node n1.

The compensation operation of the compensation circuit 41 will be described step by step in conjunction with FIGS. 5 to 8.

During the period P1 of FIG. 6, the first scan pulse SP1 having the high logic voltage higher than the threshold voltage of the TFT is supplied to the first scan line SI and the gate low voltage lower than the threshold voltage of the TFT is applied. 2 scan pulses SP2 are supplied to the second scan line SII. Then, the fourth and sixth TFTs T4 and T6 are turned off while the first and third TFTs T1 and T3 are turned on so that the reset voltage Vrst from the data line DL is shown in FIG. 7. It is stored in the storage capacitor (Cst) as shown.

Subsequently, during the period P2 of FIG. 6, the first scan pulse SP1 maintains a high logic voltage and the second scan pulse SP2 maintains a low logic voltage. During this P2 period, the sixth TFTs T4 and T6 remain in the off state, and the first TFT T1 remains in the on state. As shown in FIG. 8, the third TFT T3 is turned off while the fourth TFT T4 is turned on. Therefore, during the P2 period, the voltage of the storage capacitor Cst is lowered from the reset voltage Vrst by (data voltage Vdata + threshold voltage of the fourth TFT). As a result, the data capacitor having the compensation of the threshold voltage of the second TFT T2 is stored in the storage capacitor Cst. This compensation principle can be clearly seen in Equation 1 below.

Where I _T2 is the current flowing between the source and drain electrodes of the second TFT (T2), k is a constant, Vdata is the data voltage, V _thT4 is the threshold voltage of the fourth TFT (T4), and V _thT2 is the second TFT ( Means the threshold voltage of T2).

As described above, the second and fourth TFTs T2 and T4 are arranged in close proximity so that the semiconductor characteristics and the threshold voltages are substantially the same. Accordingly, as can be seen from Equation 1, the threshold voltage of the fourth TFT T4 varies by the threshold voltage of the second TFT T2, and the storage capacitor Cst supplies the gate voltage of the second TFT T2. ) Stores the (data voltage Vdata + threshold voltage of the fourth TFT), so that the threshold voltage of the fourth TFT T4 is compensated.

Following the P2 period, when the voltage of the first scan line SI changes to a low logic voltage and the voltage of the second scan line SI changes to a high logic voltage, the sixth TFT T6 is turned on and the second TFT is turned on. The on state is maintained by the compensated data voltage of (T2). Therefore, following the P2 period, the organic light emitting diode OLED emits light by flowing a current corresponding to the gradation of the original data.

As a result, the compensation circuit 41 compensates the data voltage by the threshold voltage shift of the second TFT T4 in FIG. 3 so that the current flowing in the second TFT 2 matches the gray level of the original data. Allow current to flow through.

The recovery circuit 42 supplies the low logic voltage to the second node n2 in response to the reset pulse RST of the high logic voltage to reset the threshold voltage of the second TFT T2 as shown by the arrow in FIG. 9. To recover. For this purpose, the recovery circuit 42 includes a fifth TFT T5. The gate electrode of the fifth TFT T5 is connected to the reset line RL and the source electrode is connected to the first scan line SI. The drain electrode of the fifth TFT T5 is connected to the second node n2. The recovery principle of the threshold voltage characteristic of the second TFT T2 of the driving TFT characteristic recurring circuit 42 is as follows.

When the second TFT T2 is implemented with an N-type MOS-FET and its gate voltage is continuously supplied with a positive voltage above the threshold voltage, the threshold voltage is shifted toward a higher voltage as shown by the arrow of FIG. 3. That is, in the second TFT T2, the threshold voltage is shifted by positive stress. The recovery circuit 42 supplies a low logic voltage lower than a threshold voltage of the second TFT to the second node n2 connected to the gate electrode of the second TFT T2 during the vis scan period, that is, to remove the negative bias voltage. The threshold voltage characteristic of the second TFT T2 is restored as shown in FIG. 9 by applying it to the gate electrode of the second TFT T2 so that the gate-source voltage of the second TFT T2 becomes a negative value.

10 and 11 are waveform diagrams illustrating driving waveforms of an organic light emitting diode display device according to example embodiments. As shown in FIG. 10, the reset pulse RST is sequentially supplied to the reset lines RL1 to RLn after the scan pulses SP1 and SP2 as shown in FIG. 10. Also, as shown in FIG. 11, the reset pulse RST includes all reset lines at the end of one frame period immediately after the scan pulses SP1 and SP2 are supplied to all of the scan lines SI1 to SIn and SII1 to SIIn. It is supplied simultaneously to (RL1 to RLn).

On the other hand, the organic light emitting diode display device according to the present invention has been described based on the N-type MOS-FET in the embodiment, but may be applied to the P-type MOS-FET. If the switches in the pixels are implemented with a P-type MOS-FET, the polarities of the data, scan pulses, and reset pulses are reversed from the above-described embodiment. In addition, the TFTs of the organic light emitting diode display according to the present invention include a semiconductor layer of amorphous silicon or polysilicon.

As described above, the method and apparatus for driving an organic light emitting diode display according to the present invention configure a compensation circuit in each pixel to compensate for the threshold voltage variation of the driving TFT, and also configure a recovery circuit in each pixel. The stress accumulated in the driving TFT can be restored to its original state.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

A data line, a first scan line and a reset line crossing the data line, a plurality of pixels arranged in a matrix form, an organic light emitting diode element and a storage capacitor formed in each of the pixels, and formed in the pixel to form the first scan line A method of driving an organic light emitting diode display device comprising: a first thin film transistor controlled in accordance with a voltage of a second thin film transistor and a second thin film transistor formed in the pixel to control a current of the organic light emitting diode device. Supplying a reset voltage to the data line; Supplying the reset voltage to the storage capacitor to initialize the storage capacitor; Supplying a scan pulse of a first logic voltage to the first scan line to turn on the first transistor; Supplying a data voltage to the data line; Compensating the data voltage supplied through the first thin film transistor by the threshold voltage of the second thin film transistor to generate a compensation data voltage and storing the compensated data voltage in the storage capacitor; Supplying a second logic voltage to the first scan line and supplying a reset pulse to the reset line; And supplying the second logic voltage to the gate electrode of the second thin film transistor in response to the reset pulse. The method of claim 1, The organic light emitting diode display device includes a second scan line and a sixth thin film transistor controlled according to a voltage of the second scan line; When the scan pulse of the first logic voltage is supplied to the first scan line, the scan pulse of the second logic voltage is supplied to the second scan line to turn off the sixth thin film transistor to turn off the sixth thin film transistor of the organic light emitting diode device. A method of driving an organic light emitting diode display device, the method comprising: opening a current path. A data line to which a reset voltage and a data voltage are supplied; A first scan line crossing the data line and having a first scan pulse and a second logic voltage of a first logic voltage; A reset line crossing the data line and supplied with a reset pulse; A plurality of pixels arranged in a matrix form; An organic light emitting diode element formed in each of the pixels; A storage capacitor formed in each of the pixels; A first thin film transistor supplying a reset voltage and a data voltage from the data line to a first node in response to the first scan pulse in the pixel; A second thin film transistor for controlling a current flowing through the organic light emitting diode device in response to a voltage of a second node in the pixel; After the reset voltage of the first node is stored in the storage capacitor, the data voltage is compensated by the threshold voltage of the second thin film transistor and the compensation data voltage is supplied to the second node to provide the compensation data voltage to the storage capacitor. A compensation circuit for storing; And a recovery circuit configured to supply the voltage of the second node to the second node in response to the reset pulse to the second node. Drive. The method of claim 3, wherein And each of the compensation circuit and the recovery circuit is disposed in the pixel. The method of claim 3, wherein While the first scan pulse of the first logic voltage is supplied to the first scan line, the second scan pulse of the second logic voltage is supplied and the second logic voltage is supplied to the first scan line. A second scan line to which a logic voltage is supplied; And a sixth thin film transistor which opens a current path between the organic light emitting diode element and a third node in response to a second logic voltage from the second scan line. And the second thin film transistor controls the current between the third node and the low potential driving voltage source in response to the voltage of the second node. The method of claim 5, The compensation circuit, A third thin film transistor having a gate electrode and a source electrode connected to the first node, and a drain electrode connected to the second node; And a fourth thin film transistor having a drain electrode connected to the first node and a gate electrode and a source electrode connected to the second node. The method according to claim 3 or 6, wherein The recovery circuit, And a fifth thin film transistor having a gate electrode connected to the reset line, a source electrode connected to the first scan line, and a drain electrode connected to the second node. The method of claim 5, The organic light emitting diode device, And a high potential driving voltage source and a source electrode of the sixth thin film transistor.

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