KR102650560B1 - Electroluminescent Display Device - Google Patents

Abstract

The present invention relates to an electroluminescent display, wherein the pixel circuit of the display device includes a driving transistor for driving an electroluminescent diode, a first switch transistor for supplying a first voltage to the gate of the driving transistor in response to a first scan signal, and a first switch transistor for supplying a first voltage to the gate of the driving transistor in response to a first scan signal. 2 A second switch transistor for supplying a second voltage to the gate of the driving transistor in response to the scan signal, a third switch transistor for supplying the second voltage to the drain of the driving transistor in response to the second scan signal, in response to the light emission control signal a fourth switch transistor that supplies a high potential driving voltage to the source of the driving transistor, a first capacitor connected between a first node connected to the gate of the driving transistor and a second node connected to the source of the driving transistor, and a second voltage or high voltage. A second capacitor is provided between the power wiring to which the above driving voltage is applied and the second node.

Description

Electroluminescent Display Device

The present invention relates to electroluminescence display devices.

Electroluminescent displays are roughly divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. Among these, the active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness and It has the advantage of a large viewing angle.

OLED, a self-luminous device, includes an anode and a cathode, and an organic compound layer formed between them. The organic compound layer includes a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an EMission Layer (EML), an Electron Transport Layer (ETL), and an Electron Injection Layer. EIL), etc. When the power voltage is applied to the anode and cathode, holes from the hole transport layer (HTL) and electrons from the electron transport layer (ETL) are moved to the light emitting layer (EML) to form excitons, and these excitons form the light emitting layer (EML). This produces visible light.

The organic light emitting display device arranges pixels including OLED and thin film transistor (hereinafter referred to as “TFT”) in a matrix form and adjusts the luminance of the image implemented in the pixels according to the gradation of the image data. . The TFT can be composed of a driving TFT that adjusts the amount of current of the OLED according to data and a switch TFT that switches the current path of the pixel circuit. The driving TFT controls the driving current flowing through the OLED according to the voltage applied between its gate electrode and source electrode (hereinafter referred to as “gate-source voltage”). The amount of light emitted and brightness of OLED are determined depending on the driving current.

The driving characteristics of pixels, such as the threshold voltage (Vth) of the driving TFT and the electron mobility (μ) of the driving TFT, are the same for all pixels, enabling uniform image quality without differences in luminance and color between pixels. However, there may be differences in driving characteristics between pixels due to various causes, including process deviations. Additionally, the rate of deterioration between pixels may vary depending on the driving time of the display device, which may increase the difference in driving characteristics between pixels. Therefore, the amount of driving current flowing to the OLED changes depending on the driving characteristic deviation between pixels, resulting in pixel non-uniformity.

Accordingly, in order to improve the image quality and lifespan of electroluminescent displays, compensation circuits to compensate for differences in driving characteristics between pixels are being applied to organic light emitting displays. The compensation circuit may use an internal compensation method or an external compensation method. The internal compensation method uses a compensation circuit within the pixel to sample the voltage between the gate and source of the driving TFT, which changes depending on the electrical characteristics of the driving TFT, and compensates for the data voltage with the sampled voltage. The external compensation method uses a sensing circuit connected to the pixel to sense the voltage of the pixel, which changes according to the electrical characteristics of the driving TFTs, and modulates the pixel data (digital data) of the input image in the external compensation circuit based on the sensed voltage.

In the internal compensation circuit, the luminance of the OLED may be affected by the high-potential driving voltage (Voltage Drain Drain: hereinafter referred to as “VDD”) of the pixel. In this case, if VDD is different depending on the position of the pixel in the screen due to the voltage drop (IR drop) of VDD, the current of the OLED differs from the required current of the pixel, making it impossible to obtain uniform image quality. In order to reduce the voltage drop of VDD, the line width of the VDD wiring can be increased, but in high-resolution panels, the width of the VDD wiring is inevitably reduced and the VDD wiring becomes longer, so in the case of high-resolution, large-screen panels, VDD resistance is reduced by reducing the VDD resistance. There are limits to improving voltage drop.

In an internal compensation circuit, during an initialization operation to initialize a pixel, VDD and a reference voltage (hereinafter referred to as “Vref”) are shorted and current may flow. This short current increases power consumption and accelerates TFT deterioration of the pixel.

According to the trend of high-resolution and high-speed driving of electroluminescence displays, existing compensation methods cannot sufficiently compensate for differences in driving characteristics between pixels. For example, as the resolution increases and the driving frequency increases, 1 horizontal period for writing data to pixels of 1 line in the display panel decreases, so the threshold voltage sampling period of the driving TFT allocated within 1 horizontal period decreases. There is no choice but to do so. If the time required to sample the threshold voltage of the driving TFT is insufficient, the threshold voltage sampling value of the driving voltage becomes inaccurate, resulting in differences in driving characteristics between pixels on the screen. Differences in driving characteristics between pixels cause spots to appear on the screen due to differences in luminance even if data of the same gray level is written to all pixels.

The present invention provides an electroluminescent display device that can compensate for changes in pixel driving characteristics in real time.

The electroluminescence display device of the present invention includes a display panel on which a plurality of pixels including subpixels are arranged. The pixel circuit of each of the subpixels includes a driving transistor that is connected to the anode of the electroluminescent diode to drive the electroluminescent diode, a first switch transistor that supplies a first voltage to the gate of the driving transistor in response to the first scan signal, and a second switch transistor. A second switch transistor for supplying a second voltage to the gate of the driving transistor in response to the scan signal, a third switch transistor for supplying the second voltage to the drain of the driving transistor in response to the second scan signal, in response to the light emission control signal A fourth switch transistor for supplying a high potential driving voltage to the source of the driving transistor, a first capacitor connected between a first node connected to the gate of the driving transistor and a second node connected to the source of the driving transistor, and a second voltage or high potential. It has a second capacitor connected between the power wiring to which the driving voltage is applied and the second node. By applying a low-potential power supply voltage to the cathode of the electroluminescent diode, uniform image quality can be achieved across the entire screen without a low-resistance design of the VDD wiring, and power consumption can be reduced because VDD and Vref are not short-circuited.

The electroluminescent display device of the present invention includes a display panel on which a plurality of pixels including subpixels are arranged, and each pixel circuit of the subpixels includes a driving transistor that is connected to the anode of the electroluminescent diode and drives the electroluminescent diode. , in response to the n-1 (n is a positive integer) scan signal, a reference voltage that is higher than the low-potential power supply voltage and lower than the high-potential driving voltage is applied to the gate and drain of the driving transistor, and then applied to the n-th scan signal. A switch circuit that supplies a data voltage to the gate of the driving transistor in response and then supplies a high-potential driving voltage to the source of the driving transistor in response to the light emission control signal, a first node connected to the gate of the driving transistor and the source of the driving transistor. A first capacitor connected between connected second nodes, a power wiring to which a reference voltage or a high-potential driving voltage is applied, and a second capacitor connected between the second nodes, and a low-potential power supply voltage applied to the cathode of the electroluminescent diode. By being applied, uniform image quality can be achieved across the entire screen without the low-resistance design of the VDD wiring, and power consumption can be reduced because VDD and Vref are not short-circuited.

The electroluminescent display device of the present invention includes a display panel on which a plurality of pixels including subpixels are arranged, and each pixel circuit of the subpixels includes a driving transistor that is connected to the anode of the electroluminescent diode and drives the electroluminescent diode. , a first switch transistor for supplying a data voltage to the gate of the driving transistor in response to the nth (n is a positive integer) scan signal, higher than the low-potential power supply voltage and higher than the high-potential driving voltage in response to the n-1th scan signal. A second switch transistor for supplying a low reference voltage to the gate of the driving transistor, a third switch transistor for supplying a reference voltage to the drain of the driving transistor in response to the n-1th scan signal, and a high potential in response to the light emission control signal. a fourth switch transistor that supplies driving voltage to the drain of the driving transistor, a fifth switch transistor that forms a current path between the source of the driving transistor and the anode of the electroluminescent diode in response to the light emission control signal, and a fourth switch transistor connected to the gate of the driving transistor. A first capacitor connected between node 1 and a second node connected to the source of the driving transistor, a power wiring to which a reference voltage or a high potential driving voltage is applied, and a second capacitor connected between the second node, and an electroluminescent diode. By applying a low-potential power supply voltage to the cathode, uniform image quality can be achieved across the screen without a low-resistance design of the VDD wiring, and power consumption can be reduced because VDD and Vref are not short-circuited.

In the present invention, since the OLED current of the pixel is not affected by VDD, uniform image quality can be realized across the entire screen without a low-resistance design of the VDD wiring, and a high-resolution and large-screen electroluminescent display device can be implemented.

In the present invention, since VDD and Vref are not shorted within the pixel, reliability can be improved by reducing power consumption and reducing pixel deterioration.

In the present invention, the data voltage range can be set according to the ratio of the capacitor size within the pixel, so detailed grayscale expression is possible.

The present invention can shorten the time for the anode of the OLED to float after the emission control signal is inverted to the gate-off voltage, thereby improving the display quality of the electroluminescence display device.

The present invention turns on/off the emission control signal (EM) at a predetermined pulse width modulation (PWM) duty ratio during the emission driving period to prevent flicker and afterimages. You can improve image quality by minimizing it. Also, since the Vsg (or Vgs) of the driving TFT can be stored in the capacitor C1 during the off period of the emission control signal EM in the emission driving period, stable duty driving is possible.

The internal compensation circuit of the present invention can control the sampling period of the driving TFT to be sufficiently long by adjusting the pulse width of the scan signal. Accordingly, the electroluminescent display device of the present invention can stably secure compensation for differences in pixel driving characteristics in high-resolution and large-screen displays.

The internal compensation circuit of the present invention has a simple circuit configuration and allows for a compact layout, making it possible to implement a high-resolution display device with a small unit pixel size and high PPI (Pixels per Inch).

The present invention can prevent a decrease in contrast ratio when displaying black and white grayscale levels by initializing the anode voltage of the OLED with the data voltage (Vdata) during the initialization and sampling period (Tis).

In the present invention, by configuring a capacitor between the first node and the EM signal line, the brightness of the pixel can be increased in white grayscale, thereby increasing the contrast ratio, which has an advantageous effect in implementing HDR (High Dynamic Range).

In the present invention, by configuring a capacitor between the first node and the EM signal line, Vsg of the driving TFT can be increased, and thus the brightness of the pixel can be improved.

The present invention is configured to drive two scan lines in a display panel by connecting them to one output terminal from the scan driver, so that two EM signal lines in the display panel can be driven by connecting them to one output terminal from the EM driver. Therefore, a narrow bezel can be implemented by reducing the number of output terminals for each of the scan driver and EM driver.

1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention.
Figure 2 is a circuit diagram showing a pixel circuit according to the first embodiment of the present invention.
FIG. 3 is a waveform diagram showing the operation of the pixel circuit shown in FIG. 2.
FIGS. 4 to 7 are diagrams showing step-by-step the operation of the pixel circuit shown in FIG. 3.
Figure 8 is a waveform diagram showing an example of an EM signal being modulated with a PWM of 50% or less during the pixel's light emission driving period.
Figure 9 is a diagram showing an example of expanding the pulse width of a scan signal applied to a pixel circuit.
FIG. 10 is a circuit diagram showing an example in which a fifth switch TFT is added to the pixel circuit shown in FIG. 2.
11 to 15 are diagrams showing a pixel circuit and a driving method thereof according to a second embodiment of the present invention.
16 to 18 are circuit diagrams showing an example in which a third capacitor is connected to a pixel circuit.
Figures 19 and 20 are waveform diagrams showing the change in Vsg of the driving TFT depending on the presence or absence of the third capacitor.
Figures 21 to 23 are circuit diagrams showing examples in which the connection relationship between the second and third switch TFTs of the pixel circuit is changed.
Figure 24 is a diagram showing a pixel circuit and its driving method according to a third embodiment of the present invention.
Figure 25 is a diagram showing a pixel circuit and its driving method according to a fourth embodiment of the present invention.
Figure 26 is a circuit diagram schematically showing one stage that outputs a gate pulse from the shift register of the gate driver.
FIG. 27 is a waveform diagram showing the operation of the stage shown in FIG. 1.
Figure 28 is a diagram showing stages connected dependently in the shift register of the gate driver.
FIG. 29 is a diagram showing the connection relationship between the output terminal of the scan driver that outputs the scan signal shown in FIG. 3 and the screen display unit.
FIG. 30 is a diagram showing the connection relationship between the output terminal of the scan driver that outputs the scan signal shown in FIG. 9 and the screen display unit.
FIG. 31 is a diagram showing the connection relationship between the output terminal of the EM driver that outputs the EM signal shown in FIGS. 3 and 9 and the screen display unit.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

First, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be partially or fully combined or combined with each other, and various technical interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

In the present invention, the gate driver may be formed directly on the substrate of the display panel. The transistors that make up the pixel circuit and the gate driver may be implemented as a TFT with an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. A TFT (or transistor) is a three-terminal device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the TFT, carriers begin to flow from the source. The drain is the electrode through which carriers go out of the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type TFT (or n-type transistor, NMOS), the carrier is an electron, so the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in an n-type TFT, the direction of current flows from the drain to the source. In the case of a p-type TFT (or p-type transistor, PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage to allow holes to flow from the source to the drain. In a p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. In the following embodiments, the source and drain of the TFT will be referred to as the first electrode and the second electrode. In the present invention, the present invention is not limited by the source and drain of the TFT.

The transistors constituting the pixel circuit and gate driver of the present invention may include one or more of Oxide TFT, a-Si TFT, and Low Temperature Poly Silicon (LTPS) TFT.

Hereinafter, Gate On Voltage is the voltage of the gate signal at which the TFT can be turned on. Gate Off Voltage is the voltage at which the TFT can be turned off. In PMOS, the gate-on voltage is the gate low voltage (VGL), and the gate-off voltage is the gate high voltage (VGH). In NMOS, the gate-on voltage is VGH and the gate-off voltage is VGL.

Each pixel circuit of the present invention includes an electroluminescent diode driven by Vsg or Vgs of the driving TFT. As an example of an electroluminescent diode, an organic light emitting diode is illustrated in the following examples, but the present invention is not limited thereto.

The following embodiments will be described focusing on the organic light emitting display device. However, embodiments of the present invention are not limited to organic light emitting display devices and may also be applied to inorganic light emitting display devices including inorganic light emitting materials. For example, it can be applied to quantum dot display devices.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted or explained briefly.

Referring to FIG. 1, an electroluminescent display device according to an embodiment of the present invention includes a display panel 100, a data driver 102, a gate driver 108, and a timing controller 110. The gate driver 108 includes a scan driver 103 and an EM driver 104.

In the display panel 100, a plurality of data lines 11 and a plurality of gate lines 12a, 12b, and 12c may intersect, and pixels are arranged. The screen display unit (AA) of the display panel 100 displays data of an input image on a pixel array. The display panel 100 includes power wires commonly connected to neighboring pixels. The power wires include a VDD wire that supplies a high-potential driving voltage (VDD) to the pixels, and a Vref wire that supplies a reference voltage (Vref) lower than VDD to the pixels.

The gate lines 12a, 12b, and 12c are connected to a plurality of scan lines 12a, 12b to which scan signals (SCAN(n-1), SCAN(n)) are supplied, and an emission control signal (hereinafter referred to as “EM signal”). ”) includes a plurality of EM signal lines 12c supplied.

Each pixel is divided into red sub-pixel, green sub-pixel and blue sub-pixel to implement color. Each of the pixels may further include a white subpixel. Each of the subpixels includes a pixel circuit as shown in FIGS. 2 to 25.

The 1 frame period is a scan period in which data is addressed to the pixels in each of the display lines connected to the pixels and data of the input image is written to each pixel, and after the scan period, the pixels repeatedly turn on and off according to the EM signal. It is divided into a light emission driving period (Tem). As shown in FIG. 3, the scan period is divided into an initialization and sampling period (Tis) and a pixel driving voltage setting period (Tw). The scan period may further include a holding period (Th), but the holding period (Th) may be minimized or omitted. During the scan period, initialization of the pixel circuit, threshold voltage compensation and data voltage charging of the driving TFT, and light emission operation of the pixel are performed. Since the scan period during which data is addressed to pixels is only approximately one horizontal period, most of one frame period is the light emission drive period. The pixels charge their data voltage during the scan period. In addition, the pixels do not receive additional data voltage during the light emission driving period (Tem) after the scan period, and repeatedly turn on and off according to the EM signal, displaying data with the same luminance for one frame period with the data voltage charged during the scan period. do.

Referring to FIG. 1, the data driver 102 converts the data of the input image received from the timing controller 110 into a gamma compensation voltage under the control of the timing controller 110 to generate a data voltage (Vdata), and the data Voltage is output to data lines (11). Then, the data voltage is supplied to the pixels through the data lines 11.

1 to 3, the scan driver 103 sequentially transmits scan signals (SCAN(n-1), SCAN(n)) to the scan lines 12a and 12b under the control of the timing controller 110. supply. The n-1th scan signal applied to the n-1th display line (n is a positive integer) is synchronized to the n-1th data voltage. The nth scan signal applied to the nth display line is synchronized to the nth data voltage (Vdata(n)). At this time, the n-1th display line is connected to the n-1th subpixels, and the nth display line is connected to the n-1th subpixels. Since the n-1th scan signal (SCAN(n-1)) and the nth scan signal (SCAN(n)) are applied to the nth display line, two scan lines are output from one output terminal in the scan driver 103. By sharing, the number of output terminals of the scan driver 103 can be reduced. Accordingly, when the number of output terminals of the scan driver 103 is reduced, the circuit area occupied by the gate driver 108 is reduced, so the size of the bezel area BZ, which is a non-display area, may be reduced as the circuit area is reduced.

The EM driver 104 generates an EM signal (EM(n)) under the control of the timing controller 110. The EM driver 104 sequentially supplies the EM signal EM(n) to the EM signal lines 12c. As shown in Figure 3, the off-level pulse of the EM signal (EM(n)) is the n-1th and nth scan signals (SCAN(n-1), SCAN(n)), and the n+1th scan. It is synchronized with the on-level pulse of the signal and overlaps with the on-level pulses of the n-1th, nth, and n+1th scan signals. The voltage of the on-level pulse is generated as the gate-on voltage, and the voltage of the off-level pulse is generated as the gate-off voltage. The timing controller 110 receives digital video data of an input image and a timing signal synchronized with the digital video data from the host system. The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (CLK), and a data enable signal (DE). The host system may be any one of a television (TV) system, set-top box, navigation system, DVD player, Blu-ray player, personal computer (PC), home theater system, and mobile information device.

Additionally, the timing controller 110 provides a data timing control signal for controlling the operation timing of the data driver 102 and a gate timing control for controlling the operation timing of the gate driver 108 based on the timing signal received from the host system. Generates signals, etc. The gate timing control signal includes a start pulse, shift clock, etc. The start pulse may define a start timing that causes the first output to be generated from each of the shift registers of the scan driver 103 and the EM driver 104. The shift register begins to operate when the start pulse is input and generates the first output signal at the first clock timing. The shift clock controls the output shift timing of the shift register.

2 and 3 are equivalent circuit diagrams and waveform diagrams showing an example of a pixel circuit. The pixel circuit 20 shown in FIG. 2 exemplifies an n-th pixel circuit that is disposed on the n-th display line of the screen display unit AA and generates a current corresponding to the n-th data voltage.

Referring to FIGS. 2 and 3 , each of the pixel circuits 20 includes an OLED, a plurality of TFTs (DT, T1 to T4), first and second capacitors (C1, C2), etc. This embodiment is an example in which TFTs are implemented with PMOS transistors. Hereinafter, it will be described with reference to FIG. 1.

This pixel circuit 20 includes an internal compensation circuit that automatically detects the threshold voltage of the driving TFT. Since the occupied area of the switch TFTs (T2 to T4) and capacitors (C1, C2) required for the internal compensation circuit is not large, the present invention enables the construction of a compact layout of the pixel circuit, resulting in a small unit pixel size. A high-resolution display device with high PPI (Pixels per Inch) can be implemented.

Pixel power sources such as a high-potential driving voltage (VDD), a low-potential power supply voltage (VSS), and a reference voltage (Vref) are applied to the n-th pixel circuit 20. VDD, VSS, and Vref may be direct current voltages of VDD = 7V~8V, VSS = 0V, and Vref = 1V, but are not limited thereto. Then, pixel driving signals such as the n-1th scan signal (SCAN(n-1)), the nth scan signal (SCAN(n)), and the data voltage (Vdata) are applied to the nth pixel circuit.

Scan signals (SCAN(n-1), SCAN(n)) are supplied to the scan lines 12a and 12b by the scan driver 103. The EM signal (EM(n)) is supplied to the EM signal line 12c by the EM driver 104. Vdata may be a voltage between 0V and 5V from the data driver 102, but is not limited to this. The scan signals (SCAN(n-1), SCAN(n)) are generated with a pulse width of one horizontal period (1H) and swing between VGH and VGL. In this embodiment, since the TFTs (DT, T1 to T4) are PMOS transistors, the gate on voltage is VGL and the gate off voltage is VGH. VGH and VGL may be VGH = 10V and VGL = -6V, but are not limited thereto.

Referring to FIG. 3, the n-1th scan signal (SCAN(n-1)) followed by the nth scan signal (SCAN(n)) synchronized with the nth data voltage (Vdata(n)) is transmitted to the nth pixel circuit. is supplied to. The driving method of the pixel circuit 20 can be divided into an initialization and sampling period (Tis), a pixel driving voltage setting period (Tw), and a light emission driving period (Tem). The on-level pulse of the n-1th scan signal (SCAN(n-1)) is input to the nth pixel circuit during the initialization and sampling period (Tis), and the gate-off voltage is applied during the remaining period other than the initialization and sampling period (Tis). is maintained. The on-level pulse of the nth scan signal (SCAN(n)) is input to the nth pixel circuit 20 during the pixel driving voltage setting period (Tw), and the gate is turned off during the remaining period other than the pixel driving voltage setting period (Tw). maintained at voltage. The off-level pulse of the EM signal (EM(n)) is generated as a gate-off voltage for approximately 3 horizontal periods overlapping with the n-1th and nth scan signals. The voltage of the EM signal (EM(n)) is inverted between the gate-on voltage and the gate-off voltage at a preset duty ratio of the PWM during the light emission driving period (Tem) to switch the current of the OLED.

OLED emits light with an amount of current that is adjusted in the driving TFT (DT) according to the data voltage (Vdata), expressing luminance corresponding to the data grayscale of the input image. VDD = 7V to 8V, VSS = 0V, Vref = 1V, and Vdata = 0V to 5V may be applied to the pixel circuit 20 as shown in FIGS. 2 and 3. The lower the data voltage (Vdata), the greater the voltage (Vsg) between the source and gate of the driving TFT (DT), increasing the luminance of the pixel. And, as Vsg of the driving TFT (DT) increases, the current of the OLED increases and the amount of light emitted from the OLED increases. Accordingly, in the pixel circuit 20 as shown in FIGS. 2 and 3, the lower the data voltage (Vdata), the higher the luminance of the pixel, and the higher the data voltage (Vdata), the lower the luminance of the pixel.

The current path of the OLED is switched by the fourth switch TFT (T4) controlled according to the EM signal (EM(n)). OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, an emission layer (EML) and at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Referring to FIG. 2, the anode of the OLED is connected to the drain of the driving TFT (DT) via the third node (DTD), and the cathode is connected to the VSS electrode to which VSS is applied.

The driving TFT (DT) is a driving element that regulates the current (Ioled) flowing through the OLED according to the voltage (Vsg) between the source and gate. The driving TFT (DT) includes a gate connected to the first node (DTG), a source connected to the second node (DTS), and a drain connected to the third node (DTD).

The first capacitor C1 is connected between the first node (DTG) and the second node (DTS). The second capacitor C2 includes a first electrode that receives a voltage from the VDD wire 13 or the Vref wire 14, and a second electrode connected to the second node DTS.

The switch circuit of this pixel circuit 20 uses the first to fourth switch TFTs (T1 to T4) to provide a reference voltage in response to the on-level pulse of the n-1th scan signal (SCAN(n-1)). After applying (Vref) to the gate and drain of the driving TFT (DT), the data voltage (Vdata(n)) is applied to the driving TFT (DT) in response to the on-level pulse of the nth scan signal (SCAN(n)). Supply to the gate. And, the switch circuit supplies a high-potential driving voltage (VDD) higher than the reference voltage (Vref) to the source of the driving TFT (DT) in response to the gate-on voltage after the off-level pulse of the EM signal (EM(n)). .

The first switch TFT (T1) is a switch element that supplies the first voltage to the first node (DTG) in response to the nth scan signal (SCAN(n)). The first voltage is a data voltage (Vdata(n)) that is synchronized with the nth scan signal (SCAN(n)). The first switch TFT (T1) includes a gate connected to the first scan line 12a, a drain connected to the data line 11, and a source connected to the first node (DTG). The nth scan signal SCAN(n) is supplied to the nth pixel circuit 20 through the first scan line 12a. The nth scan signal SCAN(n) is supplied to the nth pixel circuit 20 as a gate-on voltage during the pixel driving voltage setting period Tw.

The second switch TFT (T2) is a switch element that supplies a second voltage to the first node (DTG) in response to the n-1th scan signal (SCAN(n-1)). The second voltage is a reference voltage (Vref) that is higher than VSS and lower than VDD. The on-level pulse of the n-1th scan signal (SCAN(n-1)) precedes the on-level pulse of the nth scan signal. The second switch TFT (T2) includes a gate connected to the second scan line 12b, a source connected to the Vref line 14, and a drain connected to the first node (DTG). The n-1th scan signal (SCAN(n-1)) is supplied to the nth pixel circuit 20 through the second scan line 12b. At the same time, the n-1th scan signal (SCAN(n-1)) is synchronized with the n-1th data voltage and disposed on the n-1th display line of the screen display unit AA (n-1th pixel circuit 20). ) can be supplied. The n-1th scan signal (SCAN(n-1)) is supplied to the nth pixel circuit 20 as a gate-on voltage during the initialization and sampling period Tis.

The third switch TFT (T3) is a switch element that supplies the reference voltage (Vref) to the third node (DTD) in response to the n-1th scan signal (SCAN(n-1)). The third switch TFT (T3) includes a gate connected to the second scan line 12b, a source connected to the Vref line 14, and a drain connected to the third node DTD.

The fourth switch TFT (T4) is a switch element that switches the current flowing through the OLED in response to the EM signal (EM(n)). The fourth switch TFT (T4) includes a gate connected to the EM signal line 12c, a source connected to the VDD wire 13, and a drain connected to the second node (DTS). The EM signal EM(n) is supplied to the nth pixel circuit 20 through the EM signal line 12c.

The operation of this pixel circuit 20 will be explained with reference to FIGS. 4 to 7.

As shown in FIG. 4, during the light emission driving period (Tem) preceding the initialization and sampling period (Tis), the EM signal (EM(n)) is generated as a gate-on voltage to turn on the fourth switch TFT (T4). do. At this time, the fourth switch TFT (T4) and the driving TFT (DT) are turned on, and the first to third switch TFTs (T1, T2, T3) are maintained in the off state so that a current (Ioled) is supplied to the OLED. flows and the second node (DTS) is set to VDD.

Referring to FIG. 5, when the initialization and sampling period (Tis) starts, the voltage of the n-1th scan signal (SCAN(n-1)) is inverted to the gate-on voltage, and the EM signal (EM(n)) is gate-on voltage. Inverted to off voltage. During the initialization and sampling period Tis, the nth scan signal SCAN(n) maintains the gate-off voltage. During the initialization and sampling period Tis, the second and third switch TFTs T2 and T3 are turned on in response to the on-level pulse of the n-1 scan signal SCAN(n-1), so that the switch TFT The reference voltage Vref is applied to the first and third nodes DTG and DTD through the nodes T2 and T3. Accordingly, the voltages of the first and third nodes (DTG and DTD) are initialized to Vref during the initialization and sampling period (Tis). During the initialization and sampling period (Tis), a voltage of Vref + |Vth| is applied to the second node (DTS), so Vth is stored in the first capacitor (C1). Vth is the threshold voltage of the driving TFT (DT). Accordingly, the threshold voltage (Vth) of the driving TFT (DT) is sensed during the initialization and sampling period (Tis).

Since the fourth switch TFT (T4) is turned off during the initialization and sampling period (Tis), VDD and Vref are not shorted within the pixel circuit 20. Accordingly, problems such as increased power consumption, pixel deterioration, and reduced reliability due to short circuit between VDD and Vref in the pixel circuit 20 can be minimized.

During the initialization and sampling period Tis, when VDD is applied to one electrode of the second capacitor C2, the voltage of the second capacitor C2 is am. When Vref is applied to one electrode of the second capacitor (C2), the voltage of the second capacitor (C2) is am.

Following the initialization and sampling period (Tis), the pixel circuit 20 operates in the pixel driving voltage setting period (Tw). When the pixel driving voltage setting period (Tw) begins, as shown in FIG. 6, the nth scan signal (SCAN(n)) is inverted to the gate-on voltage, and the n-1th scan signal (SCAN(n-1)) is inverted to the gate-on voltage. ) is inverted to the gate-off voltage. During the pixel driving voltage setting period Tw, the EM signal EM(n) is maintained at the gate-off voltage. During the pixel driving voltage setting period (Tw), that is, during one horizontal period (1H), the first switch TFT (T1) is turned on in response to the on-level pulse of the nth scan signal (SCAN(n)) to generate the data voltage. (Vdata) is applied to the first node (DTG). During the pixel driving voltage setting period (Tw), the remaining TFTs (T2 to T4, DT) other than the first switch TFT (T1) are turned off. During the pixel driving voltage setting period Tw, the voltage of the first node DTG is charged to the data voltage Vdata. During the pixel driving voltage setting period (Tw), due to coupling through the capacitor (C1), the voltage of the second node (DTS) changes to

During the pixel driving voltage setting period (Tw), when VDD is applied to one electrode of the second capacitor (C2), the voltage of the second capacitor (C2) is am. When Vref is applied to one electrode of the second capacitor (C2), the voltage of the second capacitor (C2) is am.

Following the pixel driving voltage setting period (Tw), the nth scan signal (SCAN(n)) is inverted to the gate-off voltage during the sustain period (Th), and the n-1th scan signal (SCAN(n-1)) and The voltage of the EM signal (EM(n)) is maintained at the previous level. During the sustain period Th, the voltages of the first and second nodes DTG and DTS may change by a kickback voltage generated when the nth scan signal SCAN(n) changes to the gate-off voltage.

After the sustain period (Th), when the light emission drive period (Tem) begins, as shown in Figure 7, the scan signals (SCAN(n-1), SCAN(n)) are maintained at the gate-off voltage and the EM signal (EM (n)) is inverted to the gate-on voltage. At this time, the voltage of the second node (DTS) changes to VDD, so that the gate voltage of the first node (DTG), that is, the driving TFT (DT) becomes Vdata+VDD- The Vsg voltage of the driving TFT (DT), which changes and determines the current amount of the OLED, is set. At this time, a current (Ioled) flows through the OLED as shown in Equation 1 below.

Here, K is a constant value determined by the mobility, channel ratio, parasitic capacitance, etc. of the driving TFT (DT), and Vth is the threshold voltage of the driving TFT (DT).

As can be seen from Equation 1, in the present invention, the current of the OLED is not affected by VDD. If uneven image quality occurs due to a voltage drop in the VDD wiring, the resistance of the VDD wiring can be reduced by configuring the VDD wiring in a mesh form. However, in the case of a high-resolution display panel, the area corresponding to the pixel becomes small, and the width of the VDD wire must be reduced, so there is a limit to reducing the resistance of the VDD wire. Also, when the display panel has a large screen, the power supply path to the inside of the screen display unit (AA) becomes longer, so the resistance of the VDD wiring increases. Therefore, in the embodiment of the present invention, since the current of the OLED is not affected by VDD, the luminance and color of the pixels are uniform throughout the screen without designing a low-resistance VDD wiring or configuring a VDD wiring in the form of a mesh. can do. As a result, the present invention can implement uniform image quality in a high-resolution panel with a small pixel size. Additionally, the present invention has the effect of providing a large screen panel with improved luminance and image quality. Additionally, since the embodiment of the present invention can compensate for the voltage drop of the VDD wiring, there is an effect of eliminating the need to configure the VDD wiring in a mesh form.

During the light emission driving period (Tem), the voltage of the first node (DTG) is And since the voltage of the second node (DTS) is VDD, the voltage of the first capacitor (C1) storing the difference voltage between the first node (DTG) and the second node (DTS) is am. During the light emission driving period Tem, when VDD is applied to one electrode of the second capacitor C2, the voltage of the second capacitor C2 is am. When Vref is applied to one electrode of the second capacitor (C2), the voltage of the second capacitor (C2) is am.

As can be seen in FIGS. 2 to 7, the time at which the anode of the OLED floats during the off period of the emission control signal EM(n) in the pixel circuit 20, that is, the emission drive period Tem and Since the time between pixel driving voltage setting periods (Tw) can be controlled to be very small, display quality can be improved by minimizing the phenomenon of increasing luminance of black grayscale or decreasing contrast ratio. Black grayscale pixel data has the lowest grayscale value, for example, 00000000 ₍₂₎ . The luminance of a pixel in a black grayscale may be the lowest luminance. Accordingly, the time for the anode of the OLED to float after the emission control signal EM(n) is inverted to the gate-off voltage can be shortened, and thus the display quality of the electroluminescent display device can be improved.

In equation 1, is the gain of the data voltage (Vdata). This gain can be appropriately selected in consideration of the voltage range of the drive IC in which the data driver circuit is integrated, the power consumption of the data driver 102, the gray level expression ability, etc. The larger C2 is, the closer the gain is to “1”, and the smaller C2 is, the closer the gain is to 0. C1 is a capacitor that stores Vsg (or Vgs) of the driving TFT (DT). As the capacitance value of C1 increases, it has the ability to maintain a stable voltage, but the gain value decreases. As the gain becomes smaller, the data voltage range of the data driver 102 increases, and as the data voltage range increases, the power consumption of the data driver 102 may increase. As the gain becomes smaller, the data voltage range of the data driver 102 increases, enabling detailed grayscale expression. Therefore, since the data voltage range of the data driver 102 can be adjusted according to the capacitor ratio within the pixel, detailed grayscale expression is possible. Here, the capacitor ratio may be the ratio of the capacitance values of the first capacitor C1 and the second capacitor C2. FIG. 8 shows an EM signal modulated with a PWM of 50% or less during the light emission driving period (Tem) of the pixel. This is a waveform diagram showing an example.

In FIG. 8 , SCAN1(1) and EM(1) are the first scan signal and the first EM signal applied to pixels arranged in the first row of the display panel 100. SCAN1(2) and EM(2) are a second scan signal and a second EM signal applied to pixels arranged in the second row of the display panel 100. After data is addressed to the pixel during the scan period, switching the EM signal (EM) to a duty ratio of 50% or less during the light emission driving period (Tem) can reduce flicker and afterimage, thereby improving image quality. In addition, Vsg of the driving TFT (DT) can be stored in the first capacitor (C1) during the off period of the EM signal (EM) in the emission driving period (Tem), thereby providing stable duty driving without the need to write additional data to the pixel. This is possible.

The first and second switch TFTs T1 and T2 are vulnerable to leakage current because their off period is long. Considering this, the first and second switch TFTs T1 and T2 may be transistors with a dual gate structure with a small leakage current, as shown in FIGS. 2 to 7. If these first and second switch TFTs T1 and T2 are implemented as transistors with very small leakage current, for example, oxide TFTs, a single gate structure may be possible.

FIG. 9 is a diagram showing an example of expanding the pulse width of a scan signal applied to the pixel circuit 20.

Referring to FIG. 9, the pixel circuit 20 is substantially the same as the pixel circuit 20 shown in FIGS. 2 to 7, except that the pulse widths of the scan signals SCAN1 and SCAN2 are set differently. In this embodiment, the pulse width of the second scan signal SCAN2, which defines the initialization and sampling period Tis, is set to be different from the pulse width of the first scan signal SCAN1 synchronized to the data voltage Vdata. For example, in Figure 9, the pulse width of the second scan signal SCAN2 is set to be larger than the pulse width of the first scan signal SCAN1, but the present invention is not limited to this. The pulse width of the second scan signal SCAN2 can be adjusted considering resolution and panel characteristics.

In this embodiment, the OLED, driving TFT (DT), capacitors (C1, C2), and fourth switch TFT (T4) are substantially the same as the above-described embodiment, so detailed description thereof is omitted.

The first switch TFT (T1) is a switch element that supplies the data voltage (Vdata(n)) to the first node (DTG) in response to the first scan signal (SCAN1). The first switch TFT (T1) includes a gate connected to the first scan line to which the first scan signal (SCAN1) is applied, a drain connected to the data line 11, and a source connected to the first node (DTG). The first scan signal SCAN1 is generated as a gate-on voltage during the pixel driving voltage setting period (Tw) and is maintained as a gate-off voltage for the remaining frame period other than the pixel driving voltage setting period (Tw).

The second switch TFT (T2) is a switch element that supplies the reference voltage (Vref) to the first node (DTG) in response to the second scan signal (SCAN2). The second switch TFT (T2) includes a gate connected to the second scan line to which the second scan signal (SCAN2) is applied, a source connected to the Vref wire 14, and a drain connected to the first node (DTG). The second scan signal (SCAN2) is generated as a gate-on voltage during the initialization and sampling period (Tis) preceding the pixel driving voltage setting period (Tw) and maintained as a gate-off voltage during the remaining frame period other than the initialization and sampling period (Tis). do.

The third switch TFT (T3) is a switch element that supplies the reference voltage (Vref) to the third node (DTD) in response to the second scan signal (SCAN2). The third switch TFT (T3) includes a gate connected to the second scan line to which the second scan signal (SCAN2) is applied, a source connected to the Vref line, and a drain connected to the third node (DTD).

As the resolution of the display panel increases, one horizontal period (1H) becomes shorter, so one horizontal period (1H) is insufficient time to sense the threshold voltage (Vth) of the driving TFT (DT). In this case, by lengthening the pulse width of the second scan signal (SCAN2) independent of the data voltage (Vdata), sufficient sensing time of the driving TFT (DT) can be secured. Therefore, there is an effect of securing sufficient compensation time for a display panel with high resolution.

FIG. 10 is a circuit diagram showing an example in which a fifth switch TFT is added to the pixel circuit 20 shown in FIG. 2. In this embodiment, the same reference numerals are given to the same components as those in the above-described embodiment, and detailed description thereof is omitted.

Referring to FIG. 10, the pixel circuit 30 includes a fifth switch TFT (T5) disposed between the third node (DTD) and the anode of the OLED. In this embodiment, the OLED, driving TFT (DT), capacitors (C1, C2), and switch TFTs (T1 to T4) are the same as the above-described embodiment.

The fifth switch TFT (T5) blocks the current path between the driving TFT (DT) and the OLED during the initialization and sampling period (Tis) to prevent the OLED from emitting unwanted light. When the OLED emits light during the initialization and sampling period (Tis), the luminance of the black grayscale may increase and the contrast ratio may decrease. In particular, when the host system requires a high reference voltage (Vref), during the initialization and sampling period (Tis), when the nodes (DTG, DTS, DTD) of the pixel circuit 20 are initialized, the anode voltage of the OLED is The higher the current flows to the OLED, the OLED can emit light. That is, in order to prevent the OLED from emitting light in a period other than the light emission driving period (Tem), the fifth switch TFT (T5) responds to the EM signal (EM(n)) and displays the OLED during the initialization and sampling period (Tis). Block the current path connected to and connect the current path between the OLED and the driving TFT (DT) during the light emission driving period (Tem).

The fifth switch TFT (T5) is turned on/off simultaneously with the fourth switch TFT (T4) in response to the EM signal (EM(n)). The fifth switch TFT (T5) includes a gate connected to the EM signal line 12c to which the EM signal EM(n) is applied, a source connected to the third node DTD, and a drain connected to the anode of the OLED.

Depending on the host system, pixels can be driven using a positive gamma correction method in which the higher the data voltage (Vdata), the higher the luminance of the pixel. In this case, positive gamma correction is performed by changing the data voltage application path and the reference voltage application path and increasing the reference voltage in the pixel circuit, as shown in FIGS. 11 to 15, without changing the above-described pixel circuits 20 and 30. method can be implemented.

11 to 15 are diagrams showing the pixel circuit 40 and its driving method according to the second embodiment of the present invention. The pixel circuit 40 of FIGS. 11 to 15 shows an example in which the data voltage application path and the reference voltage application path in the pixel circuit 20 shown in FIGS. 2 to 7 are swapped. Although omitted from the drawing, an example in which the data voltage application path and the reference voltage application path are interchanged in the pixel circuit 30 shown in FIG. 10 is also possible.

Referring to FIG. 11, each of the pixel circuits 40 includes an OLED, a plurality of TFTs (DT, T11, T12, T13, T4), first and second capacitors C1, C2, etc.

Pixel power sources such as a high-potential driving voltage (VDD), a low-potential power supply voltage (VSS), and a reference voltage (Vref) are applied to the n-th pixel circuit 40. VDD, VSS, and Vref may be direct current voltages of VDD = 7V to 8V, VSS = 0V, and Vref = 4V to 5V, but are not limited to this. Then, pixel driving signals such as the nth scan signal (SCAN(n)), the n+1th scan signal (SCAN(n+1)), and the data voltage (Vdata) are applied to the nth pixel circuit 40.

Scan signals (SCAN(n), SCAN(n+1)) are supplied to the scan lines 12a and 12d by the scan driver 103. The EM signal (EM(n)) is supplied to the EM signal line 12c by the EM driver 104. The data voltage Vdata may be generated from the data driver 102 at a voltage between 0V and 5V, but is not limited to this. The scan signal (SCAN(n+1)), SCAN(n)) is generated with a pulse width of one horizontal period (1H) and swings between VGH and VGL. In this embodiment, since the TFTs (DT, T1 to T4) are PMOS transistors, the gate-on voltage is VGL and the gate-off voltage is VGH. VGH and VGL may be VGH = 10V and VGL = -6V, but are not limited thereto.

The driving of the pixel circuit 40 shown in FIG. 11 may be divided into an initialization and sampling period (Tis), a pixel driving voltage setting period (Tw), and a light emission driving period (Tem). A maintenance period (Th) may exist between the pixel driving voltage setting period (Tw) and the light emission driving period (Tem), but may be omitted. The on-level pulse of the nth scan signal (SCAN(n)) is input to the nth pixel circuit 40 during the initialization and sampling period (Tis), and is used as a gate-off voltage during the remaining period other than the initialization and sampling period (Tis). maintain. The on-level pulse of the n+1th scan signal (SCAN(n+1)) is input to the nth pixel circuit 40 during the pixel driving voltage setting period (Tw), and is maintained as the gate-off voltage for the remaining period. do. The off-level pulse of the EM signal (EM(n)) is generated as a gate-off voltage for approximately 3 horizontal periods overlapping with the nth and n+1th scan signals (SCAN(n), SCAN(n+1)). The voltage of the EM signal (EM(n)) is inverted between the gate-on voltage and the gate-off voltage at a preset duty ratio of the PWM during the light emission driving period (Tem) to switch the current of the OLED.

OLED emits light with an amount of current that is adjusted in the driving TFT (DT) according to the data voltage (Vdata) to express luminance corresponding to the data grayscale of the input image. In the pixel circuit 40 as shown in FIGS. 11 to 15, VDD = 7V to 8V, VSS = 0V, Vref = 4V to 5V, and Vdata = 0V to 5V may be applied. The higher the data voltage (Vdata), the greater the voltage (Vsg) between the source and gate of the driving TFT (DT), increasing the luminance of the pixel. When the Vsg of the driving TFT (DT) increases, the current of the OLED increases and the amount of light emitted from the OLED increases. Accordingly, in the pixel circuit 40 shown in FIGS. 11 to 15, the higher the data voltage Vdata, the higher the luminance of the pixel, and the lower the data voltage Vdata, the lower the luminance of the pixel.

Compared to the pixel circuits 20 and 30 described in the first embodiment described above, the pixel circuit 40 shown in FIGS. 11 to 15 has a switch TFT to which a data voltage is applied and a switch TFT to which a reference voltage is applied. Except for the changes, they have substantially the same circuit structure. In this pixel circuit 40, components that are substantially the same as those in the above-described embodiment will be given the same reference numerals and detailed description thereof will be omitted. The connection relationship between the OLED, the driving TFT, the fourth switch TFT (T4), and the capacitors C1 and C2 in the pixel circuit 40 is substantially the same as the above-described embodiment.

The first switch TFT (T11) is a switch element that supplies the first voltage to the first node (DTG) in response to the n+1th scan signal (SCAN(n+1)). The first voltage is a reference voltage (Vref) that is higher than VSS and lower than VDD. The on level pulse of the n+1th scan signal (SCAN(n+1)) is later than the on level pulse of the nth scan signal (SCAN(n)). The first switch TFT (T11) includes a gate connected to the second scan line 12d, a source connected to the Vref line 14, and a drain connected to the first node (DTG). The n+1th scan signal (SCAN(n+1)) is generated as a gate-on voltage during the pixel driving voltage setting period Tw and is supplied to the nth pixel circuit 40 through the second scan line 12d.

The second switch TFT (T12) is a switch element that supplies a second voltage to the first node (DTG) in response to the nth scan signal (SCAN(n)) synchronized with the data voltage (Vdata). The second voltage is the data voltage (Vdata). The second switch TFT (T12) includes a gate connected to the first scan line 12a, a source connected to the data line 11, and a drain connected to the first node (DTG). The nth scan signal SCAN(n) is generated as a gate-on voltage during the initialization and sampling period Tis and is supplied to the nth pixel circuit 40 through the first scan line 12a.

The third switch TFT (T13) is a switch element that supplies the data voltage (Vdata) to the third node (DTD) in response to the nth scan signal (SCAN(n)) synchronized with the data voltage (Vdata). The third switch TFT (T13) includes a gate connected to the first scan line 12a, a source connected to the data line 11, and a drain connected to the third node DTD.

The driving method of the pixel circuit 40 shown in FIG. 11 will be described in conjunction with FIGS. 12 to 15.

As shown in FIG. 12, during the light emission driving period (Tem) preceding the initialization and sampling period (Tis), the EM signal (EM(n)) is generated as a gate-on voltage to turn on the fourth switch TFT (T4). do. At this time, the fourth switch TFT (T4) and the driving TFT (DT) are turned on, and the first to third switch TFTs (T11, T12, and T13) remain in the off state so that a current (Ioled) flows to the OLED. The second node (DTS) is set to VDD.

Referring to FIG. 13, during the initialization and sampling period Tis, the voltage of the nth scan signal SCAN(n) is inverted to the gate-on voltage, and the EM signal EM(n) is inverted to the gate-off voltage. During the initialization and sampling period Tis, the n+1th scan signal SCAN(n+1) maintains the gate-off voltage. During the initialization and sampling period Tis, that is, during one horizontal period 1H, the second and third switch TFTs T12 and T13 receive an nth scan signal SCAN( n)) is turned on in response to the on level pulse, and the data voltage Vdata(n) is supplied to the first and third nodes DTG and DTD through the second and third switch TFTs T12 and T13. ) is approved. Accordingly, during the initialization and sampling period Tis, the voltages of the first and third nodes DTG and DTD are initialized to the data voltage Vdata(n). During the initialization and sampling period (Tis), a voltage of Vdtata + |Vth| is applied to the second node (DTS), so Vth is stored in the first capacitor (C1). Vth is the threshold voltage of the driving TFT (DT). Accordingly, the threshold voltage (Vth) of the driving TFT (DT) is sensed during the initialization and sampling period (Tis).

Since the fourth switch TFT (T4) is turned off during the initialization and sampling period (Tis), VDD and Vref are not shorted within the pixel circuit 40. Accordingly, problems such as increased power consumption, pixel deterioration, and reduced reliability due to short circuit between VDD and Vref in the pixel circuit 40 can be minimized.

During the initialization and sampling period Tis, when VDD is applied to one electrode of the second capacitor C2, the voltage of the second capacitor C2 is am. When Vref is applied to one electrode of the second capacitor (C2), the voltage of the second capacitor (C2) is am.

Following the initialization and sampling period (Tis), the pixel circuit 40 operates in the pixel driving voltage setting period (Tw). When the pixel driving voltage setting period (Tw) starts, the n+1th scan signal (SCAN(n+1)) is inverted to the gate-on voltage, as shown in FIG. 14, and the nth scan signal (SCAN(n)) is inverted to the gate-on voltage. ) is inverted to the gate-off voltage. During the pixel driving voltage setting period Tw, the EM signal EM(n) is maintained at the gate-off voltage. During the pixel driving voltage setting period (Tw), the first switch TFT (T11) is turned on in response to the on level pulse of the n+1 scan signal (SCAN(n+1)) to control the reference voltage (Vref). 1 Applies to node (DTG). During the pixel driving voltage setting period (Tw), the second to fourth switch TFTs and driving TFTs (T12, T13, T4, and DT), which are the remaining TFTs other than the first switch TFT (T11), are turned off. During the pixel driving voltage setting period Tw, the voltage of the first node DTG is charged to the reference voltage Vref. During the pixel driving voltage setting period (Tw), due to coupling through the capacitor (C1), the voltage of the second node (DTS) changes to

During the pixel driving voltage setting period (Tw), when VDD is applied to one electrode of the second capacitor (C2), the voltage of the second capacitor (C2) is am. When Vref is applied to one electrode of the second capacitor (C2), the voltage of the second capacitor (C2) is am.

Following the pixel driving voltage setting period (Tw), the n+1th scan signal (SCAN(n+1)) is inverted to the gate-off voltage during the sustain period (Th), and the nth scan signal (SCAN(n)) and The voltage of the EM signal (EM(n)) is maintained at the previous level. During the maintenance period (Th), the voltages of the first and second nodes (DTG, DTS) are increased by the kickback voltage generated when the n+1th scan signal (SCAN(n+1)) changes to the gate-off voltage. It can change.

After the sustain period (Th), when the light emission drive period (Tem) begins, as shown in FIG. 15, the scan signals (SCAN(n), SCAN(n+1)) are maintained at the gate-off voltage and the EM signal (EM (n)) is inverted to the gate-on voltage. At this time, the voltage of the second node (DTS) changes to VDD, and the gate voltage of the first node (DTG), that is, the driving TFT (DT), changes to VDD. The Vsg voltage of the driving TFT (DT), which determines the amount of current of the OLED, is set. At this time, a current (Ioled) flows through the OLED as shown in Equation 2 below.

Here, K is a constant value determined by the mobility, channel ratio, parasitic capacitance, etc. of the driving TFT (DT), and Vth is the threshold voltage of the driving TFT (DT).

As can be seen from Equation 2, in the present invention, the current of the OLED is not affected by VDD. If uneven image quality occurs due to a voltage drop in the VDD wiring, the resistance of the VDD wiring can be reduced by configuring the VDD wiring in a mesh form. However, in the case of a high-resolution display panel, the area corresponding to the pixel becomes small, and the width of the VDD wire must be reduced, so there is a limit to reducing the resistance of the VDD wire. Also, when the display panel has a large screen, the power supply path to the inside of the screen display unit (AA) becomes longer, so the resistance of the VDD wiring increases. Therefore, in the embodiment of the present invention, since the current of the OLED is not affected by VDD, the luminance and color of the pixels are uniform throughout the screen without designing a low-resistance VDD wiring or configuring a VDD wiring in the form of a mesh. can do. As a result, the present invention can implement uniform image quality in a high-resolution panel with a small pixel size. Additionally, the present invention has the effect of providing a large screen panel with improved luminance and image quality. Additionally, since the embodiment of the present invention can compensate for the voltage drop of the VDD wiring, there is an effect of eliminating the need to configure the VDD wiring in a mesh form.

As can be seen from Equation 2, the pixel circuit 40 shown in FIGS. 11 to 15 is driven by a positive gamma driving method in which the higher the data voltage Vdata, the higher the luminance of the pixel.

The pixel circuit 40 shown in FIGS. 11 to 15 is initialized with a data voltage (Vdata) that varies depending on gray level. The data voltage (Vdata) of the black grayscale is a low voltage, for example, 0V. When the anode voltage of the OLED is initialized with the data voltage (Vdata) of the black grayscale, the OLED cannot be turned on and the black grayscale luminance of the pixel cannot increase, so there is no need to worry about the problem of lowering the contrast ratio. When the anode voltage of the OLED is initialized with the data voltage (Vdata) of white grayscale, the OLED may turn on and the pixel may emit light, but in this case, the pixel emits white grayscale during the light emission driving period (Tem), resulting in a decrease in contrast ratio. There is no problem and the user does not notice the pixel emitting light during the initialization and sampling period (Tis). That is, by initializing the anode voltage of the OLED with the data voltage (Vdata) during the initialization and sampling period (Tis), it is possible to prevent contrast ratio deterioration when displaying black and white gradations. Black grayscale pixel data has the lowest grayscale value, for example, 00000000 ₍₂₎ , and white grayscale pixel data has the highest grayscale value, for example, 11111111 ₍₂₎ . The luminance of a pixel in a black grayscale is the lowest luminance, and the luminance of a pixel in a white grayscale is the highest luminance.

16 to 18 are circuit diagrams showing an example in which a third capacitor is connected to the pixel circuits 20, 30, and 40. FIG. 16 is an example in which the third capacitor C3 is added to the pixel circuit 20 shown in FIGS. 2 to 7, and FIG. 17 is an example in which the third capacitor C3 is added to the pixel circuit 30 shown in FIG. 10. This is an added example. And, FIG. 18 is an example in which a third capacitor C3 is added to the pixel circuit 40 shown in FIGS. 11 to 15. The third capacitor can be applied to all embodiments, not just the above-described embodiments. Components that are the same as those in the embodiments described above in FIGS. 16 to 18 will be assigned the same reference numerals and detailed description thereof will be omitted.

16 to 18, each of the pixel circuits 20-1, 30-1, and 40-1 further includes a third capacitor C3 connected between the first node DTG and the EM signal line 12c. Includes.

As described above, when the light emission driving period Tem begins, the voltage of the EM signal EM(n) is lowered to the gate-on voltage. At this time, since the first node (DTG) is coupled to the EM signal line 12c through the third capacitor C3, when the voltage of the EM signal (EM(n)) is lowered to the gate-on voltage, the first node (DTG) is coupled to the EM signal line 12c through the third capacitor C3. As the voltage of DTG decreases, Vsg of driving TFT (DT) increases. As a result, the luminance of the pixel can increase at the white gray level, thereby increasing the contrast ratio, which is advantageous for implementing High Dynamic Range (HDR). And, when the voltage of the EM signal line 12c changes to the gate-on voltage, the driving TFT (DT) is driven to a voltage greater than the voltage of the first capacitor C1 through coupling through the third capacitor C3. By increasing Vsg, the luminance of the pixel can be further increased.

FIG. 19 is a diagram showing Vsg of the driving TFT (DT) in the pixel circuit without the third capacitor C3. FIG. 20 is a diagram illustrating an example in which when the third capacitor C3 is added to the pixel circuit, the voltage of the first node (DTG) is lowered and the Vsg of the driving TFT (DT) increases by α. Vsg is , and α is am. Here, VEH is the gate-off voltage (or high level voltage) of the EM signal (EM(n)), and VEL is the gate-on voltage (or low level voltage) of the EM signal (EM(n)).

The connection structure of the second and third switch TFTs T2, T12, T3, and T13 in the pixel circuits 20, 30, and 40 may be changed as shown in FIGS. 21 to 23. The circuit operations and effects of FIGS. 21 to 23 are substantially the same as the above-described embodiments.

21 to 23 are circuit diagrams showing examples in which the connection structures of the second and third switch TFTs of the pixel circuits 20-2, 30-2, and 40-2 are changed. FIG. 21 is an example in which the connection structure of the second and third switch TFTs T2 and T3 in the pixel circuit 20 shown in FIGS. 2 to 7 is changed, and FIG. 22 is an example of the pixel circuit 30 shown in FIG. 10. ) is an example in which the connection structure of the second and third switch TFTs (T2, T3) is changed. And, FIG. 23 is an example in which the connection structure of the second and third switch TFTs T12 and T13 in the pixel circuit 40 shown in FIGS. 11 to 15 is changed. 21 to 23, the same reference numerals will be applied to the same components as those of the above-described embodiments, and detailed description thereof will be omitted.

21 to 23, the second switch TFT (T2, T12) has a gate connected to the scan lines (12b, 12a), a source connected to the third node (DTD), and a drain connected to the first node (DTG). Includes. The third switch TFT (T3) includes a gate connected to the scan line 12b, a source connected to the Vref line 14, and a drain connected to the third node DTD.

In the pixel circuits 20-2, 30-2, and 40-2 of FIGS. 21 to 23, between the first node (DTG) and the Vref line 14 or the first node (DTG) and the data line 11. Since the second and third switch TFTs (T2, T12, T3, and T13) exist on the current path, leakage current can be further reduced compared to an embodiment in which only the second switch TFT (T2) exists. The connection structure of the second and third switch TFTs (T2, T12, T3, and T13) may be selected depending on the panel structure or driving method of the display panel and is not limited to any one.

Figure 24 is a diagram showing the pixel circuit 50 and its driving method according to the third embodiment of the present invention. This embodiment is an example in which transistors in a pixel circuit are implemented with NMOS.

Referring to FIG. 24, each of the pixel circuits 50 includes an OLED, a plurality of TFTs (NDT, NT1 to NT5), first and second capacitors C1 and C2, etc.

The n-th pixel circuit 50 includes a high-potential driving voltage (VDD), a low-potential power supply voltage (VSS), a reference voltage (Vref), an n-1 scan signal (SCAN(n-1)), and an n-th scan signal ( SCAN(n)), data voltage (Vdata), etc. are provided. For example, VDD, VSS, and Vref may be direct current voltages of VDD = 7V~8V, VSS = 0V, and Vref = 1V, but are not limited thereto. Vdata may be generated from the data driver 102 at a voltage between 0V and 5V. The scan signals (SCAN(n-1), SCAN(n)) are generated with a pulse width of one horizontal period (1H) and swing between VGH and VGL. In this embodiment, since the TFTs (NDT, NT1 to NT4) are NMOS transistors, the gate on voltage is VGH and the gate off voltage is VGL. For example, VGH and VGL may be VGH = 10V and VGL = -6V, but are not limited thereto.

Following the n-1th scan signal (SCAN(n-1)), the nth scan signal (SCAN(n)) synchronized with the nth data voltage (Vdata(n)) is supplied to the nth pixel circuit 50. . The driving of the pixel circuit 50 may be divided into an initialization and sampling period (Tis), a pixel driving voltage setting period (Tw), and a light emission driving period (Tem). The n-1th scan signal (SCAN(n-1)) is input to the nth pixel circuit 50 during the initialization and sampling period (Tis), and is used as a gate-off voltage during the remaining period other than the initialization and sampling period (Tis). maintain. The nth scan signal (SCAN(n)) is input to the nth pixel circuit 50 during the pixel driving voltage setting period (Tw), and is maintained at the gate-off voltage for the remaining period other than the pixel driving voltage setting period (Tw). . The EM signal (EM(n)) is generated as a gate-off voltage for approximately 3 horizontal periods overlapping with the n-1st to nth scan signals, and the gate is turned on/off at a preset duty ratio of PWM during the light emission drive period (Tem). The current of the OLED is switched by repeating the voltage.

OLED emits light with an amount of current controlled by the driving TFT (NDT) according to the data voltage (Vdata), expressing luminance corresponding to the data grayscale of the input image. The current path of the OLED is switched by the fourth switch TFT (NT4) controlled according to the EM signal (EM(n)). It includes an organic compound layer formed between the anode and cathode of the OLED. The anode of the OLED is connected to the source of the driving TFT (NDT) via the second node (DTS) and the fifth switch TFT (NT5), and the cathode is connected to the VSS electrode to which VSS is applied.

The driving TFT (NDT) is a driving element that regulates the current (Ioled) flowing through the OLED according to the voltage (Vsg) between the source and gate. The driving TFT (NDT) includes a gate connected to the first node (DTG), a source connected to the second node (DTS), and a drain connected to the third node (DTD).

The first capacitor C1 is connected between the first node (DTG) and the second node (DTS). The second capacitor C2 includes a first electrode to which the VDD wire 13 or the Vref wire 14 is applied, and a second electrode connected to the second node DTS.

The switch circuit of this pixel circuit 50 drives the reference voltage (Vref) in response to the n-1th scan signal (SCAN(n-1)) using the first to fifth switch TFTs (NT1 to NT5). After being applied to the gate and drain of the TFT (NDT), the data voltage is supplied to the gate of the driving TFT (NDT) in response to the nth scan signal (SCAN(n)). Next, in response to the EM signal (EM(n)), a high-potential driving voltage (VDD) higher than the reference voltage (Vref) is supplied to the drain of the driving TFT (NDT), and at the same time, the source of the driving TFT (NDT) and the OLED Forms a current path between the anodes.

The first switch TFT (NT1) is a switch element that supplies the data voltage (Vdata(n)) to the first node (DTG) in response to the nth scan signal (SCAN(n)) or the first scan signal (SCAN1). . The first switch TFT (NT1) includes a gate connected to the first scan line, a drain connected to the data line 11, and a source connected to the first node (DTG). The nth scan signal SCAN(n) or the first scan signal SCAN1 is supplied to the nth pixel circuit 50 through the first scan line 12a.

The second switch TFT (NT2) is a switch element that supplies a reference voltage (Vref) to the first node (DTG) in response to the n-1th scan signal (SCAN(n-1)) or the second scan signal (SCAN2) am. As shown in FIG. 9, the second scan signal SCAN2 may be set to be longer than the pulse width of the first scan signal SCAN1 at high resolution. The second switch TFT (NT2) includes a gate connected to the second scan line, a source connected to the Vref line, and a drain connected to the first node (DTG).

The third switch TFT (NT3) is a switch element that supplies a reference voltage (Vref) to the third node (DTD) in response to the n-1th scan signal (SCAN(n-1)) or the second scan signal (SCAN2). am. The third switch TFT (NT3) includes a gate connected to the second scan line, a source connected to the Vref line, and a drain connected to the third node (DTD).

The fourth switch TFT (NT4) is a switch element that switches the current path between the VDD wire and the third node (DTD) in response to the EM signal (EM(n)). The fourth switch TFT NT4 includes a gate connected to the third EM signal line 12c to which the EM signal EM(n) is applied, a drain connected to the VDD wire, and a source connected to the third node DTD. .

The fifth switch TFT (NT5) is a switch element that switches the current flowing through the OLED in response to the EM signal (EM(n)). The fifth switch TFT (NT5) includes a gate connected to the third EM signal line 12c to which the EM signal (EM(n)) is applied, a drain connected to the second node (DTS), and a source connected to the anode of the OLED. . The fifth switch TFT (NT5) blocks the current of the OLED so that the OLED does not emit light during the initialization and sampling period (Tis), thereby preventing an increase in the luminance of the black grayscale and improving the contrast ratio. And, in the above-described embodiment of FIGS. 2 to 9, the fourth switch TFT (T4) can perform the functions of the fourth and fifth TFTs (NT4 and NT5) of this embodiment.

Figure 25 is a diagram showing the pixel circuit 60 and its driving method according to the fourth embodiment of the present invention. This embodiment is a pixel circuit in which some of the switch TFTs (T1, T2, T3, and T4) in the pixel circuit 20 of FIGS. 2 to 7 are changed to NMOS.

The electroluminescence display device of the present invention can drive pixels at a low speed by lowering the frame rate to reduce power consumption in still images. In this case, because the data update cycle is long, flicker may occur if leakage current occurs in the pixel. If switch TFTs (NT1, NT2, NT3, NT4) with long off periods are manufactured with n-type oxide transistors (NMOS oxide TFTs) with small off current, flicker and power consumption can be reduced during low-speed operation. In particular, if the first switch TFT (NT1), the second switch TFT (NT2), and the third switch TFT (NT3) connected to the gate of the driving TFT (DT), which can generate a lot of leakage current, are implemented as oxide TFTs, the dual gate Even if it is not implemented as a transistor structure, the off-current can be lowered. Considering the efficiency and power consumption of OLED, the driving TFT (DT) may be a p-type low-temperature polysilicon transistor (PMOS LTPS TFT) with high mobility.

24 and 25, the third capacitor C3 is connected between the first node connected to the gate of the driving TFT (NDT, DT) and the third EM signal line 12c to which the emission control signal is applied. can be connected, and the connection relationship between the second and third switch TFTs (NT2 and NT3) can be applied to the embodiments shown in FIGS. 21 to 23.

26 to 28 are diagrams for explaining the shift register of the gate driver 108.

26 to 28, each of the scan driver 103 and the EM driver 104 of the gate driver 108 is a shift register that sequentially shifts the output in response to a gate timing control signal from the timing controller 110. Includes.

The shift register of the gate driver 108 includes a number of dependently connected stages (ST(1) to ST(n+3)) and shifts the output voltage in accordance with the shift clock timing. The shift register receives the start pulse (VST) or the carry signal received from the previous stage (ST(1) to ST(n+3)) as a start pulse and generates an output signal when the clock is input. The output signal of the scan driver 103 is a scan signal, and the output signal of the EM driver 104 is an EM signal.

Each of the stages of the shift register (ST(1) to ST(n+3)) charges the output terminal (Vout(n)) in response to the Q node voltage, rising the voltage of the output signal to the gate-on voltage (VGL). A pull-up transistor (Tu), a pull-down transistor (Td) that discharges the output terminal (Vout(n)) to the gate-off voltage (VGH) in response to the QB node voltage, and a Q node and a switch circuit 120 that charges and discharges the QB node.

The pull-up transistor (Tu) is connected to the gate-on voltage (VGL) of the shift clock (CLK(n)) when the shift clock (CLK(n)) is input to the drain while the Q node is pre-charged by VGL. Charge the output terminal until With the Q node charged to VGL and floating, the shift clock (CLK(n)) is input to the pull-up transistor (Tu). When the VGL of the shift clock (CLK(n)) is input to the drain of the pull-up transistor (Tu), bootstrapping occurs through the parasitic capacitance between the drain and gate of the pull-up transistor (Tu), and the Q node The voltage of increases by approximately 2VGL. At this time, the pull-up transistor Tu is turned on by the voltage 2VGL of the Q node, and the voltage at the output terminal is charged up to VGL of the shift clock CLK(n). The pull-down transistor (Td) supplies the gate-off voltage (VGH) to the output terminal when the QB voltage is charged by VGL and adjusts the output voltage (Vout(n)) to VGH. The voltage (Vgout(n)) of the output signal is supplied to the scan line or EM signal line and is also supplied as a carry signal (CRY(n) to CRY(n+4)) to the previous stage and the next stage.

The switch circuit 120 charges the Q node in response to a start pulse (VST) input through the VST terminal or a carry signal (CRY(n) to CRY(n+4)) received from the previous stage, and RST (reset ) discharges the Q node in response to a signal received through the terminal or VNEXT terminal. A reset signal is applied to the RST terminal to simultaneously initialize the Q nodes of all stages (ST(1) to ST(n+3)). The carry signal generated from the next stage is applied to the VNEXT terminal. The switch circuit 120 can charge and discharge the QB node as opposed to the Q node using an inverter.

The start pulse (VST) is applied to the first stage (ST(1)) of the shift register. A start pulse may be applied to one or more stages. The shift clock (CLK(n)) may be a 2-phase clock to an 8-phase clock, but is not limited thereto.

FIG. 29 is a diagram showing the connection relationship between the output terminal of the scan driver that outputs the scan signals (SCAN(n-1), SCAN(n)) shown in FIG. 3 and the screen display unit. In Fig. 29, reference numerals “LINE1”, “LINE2”, and “LINE3” indicate display lines.

Since the scan signals (SCAN(n-1), SCAN(n)) are shifted with the same pulse width and constant phase difference, they can be output from one shift register without changing the gate timing control signal.

The display lines are respectively connected to subpixels 105 to 107 in the screen display portion AA of the display panel 100. The initialization and sampling period (Tis) of the nth display line overlaps with the pixel driving voltage setting period (Tw) of the n-1th display line. As a result, the n-2th scan signal and the n-1th scan signal are applied to the subpixels 105 to 107 of the n-1th display line, and the n-th scan signal is applied to the subpixels 105 to 107 of the nth display line. Since the n-1th scan signal and the nth scan signal are applied, two scan lines are shared for one output terminal in the scan driver 103, thereby reducing the number of output terminals of the scan driver 103. Therefore, during the initialization and sampling period (Tis), the n-1th scan signal is input to the n-1th display line and the nth display line, and during the pixel driving voltage setting period (Tw), the nth scan signal is input to the nth display line. is entered into As a result, one output terminal of the scan driver 103 is connected to the subpixels 105 to 107 arranged in two neighboring display lines among the display lines. Accordingly, in the display panel 100, two scan signal lines can be connected to one output terminal in the scan driver 103, so a narrow bezel can be implemented by reducing the size of the scan driver 103.

FIG. 30 is a diagram showing the connection relationship between the output terminal of the scan driver that outputs the scan signals (SCAN1 and SCAN2) shown in FIG. 9 and the screen display unit.

Referring to FIG. 30, in a high-resolution display device, the threshold voltage sensing time of the driving TFT may be insufficient. In this case, as shown in FIG. 9, the pulse of the second scan signal (SCAN2) defining the initialization and sampling period (Tis) By increasing the width, sufficient sensing time can be secured. Since the second scan signal SCAN2 is generated independently of the data voltage, the pulse width of the second scan signal SCAN2 may be expanded. In order to generate the second scan signal SCAN2, the width of the shift clock in the gate timing control signal must be longer than the shift clock for generating the first scan signal SCAN1. The first scan signal SCAN1 and the second scan signal SCAN2 may be output using the two scan drivers 103A and 103B in the bezel area BZ. The scan drivers 103A and 103B share a start pulse (VST) and are independently input shift clocks. The first scan driver 103A outputs a first scan signal SCAN1 and sequentially shifts the output first scan signal SCAN1. The second scan driver 103B outputs a second scan signal SCAN2 and sequentially shifts the output second scan signal SCAN2.

FIG. 31 is a diagram showing the connection relationship between the output terminal of the EM driver that outputs the EM signal shown in FIGS. 3 and 9 and the screen display unit.

Since the pulse width of the EM signal (EM(n)) in FIGS. 3 and 9 is set to approximately 3 horizontal periods, it can be shared by the two display lines (LINE1 to LINE#) of the screen display unit (AA). As a result, one output terminal of the EM driver 104 may be connected to the subpixels 105 to 107 arranged in two neighboring display lines (LINE1 to LINE#) among the display lines. Since the size of the EM driver 104 can be reduced, the bezel area can be made smaller as the size of the EM driver 104 is reduced. In the display panel 100, two EM signal lines can be connected to one output terminal in the EM driver 104, so a narrow bezel can be implemented by reducing the size of the EM driver 104.

An electroluminescent display device according to an embodiment of the present specification can be described as follows.

An electroluminescent display device according to an embodiment of the present specification includes a display panel on which a plurality of pixels including subpixels are arranged. The pixel circuit of each of the subpixels includes a driving transistor that is connected to the anode of the electroluminescent diode to drive the electroluminescent diode, a first switch transistor that supplies a first voltage to the gate of the driving transistor in response to the first scan signal, and a second switch transistor. A second switch transistor for supplying a second voltage to the gate of the driving transistor in response to the scan signal, a third switch transistor for supplying the second voltage to the drain of the driving transistor in response to the second scan signal, in response to the light emission control signal A fourth switch transistor for supplying a high potential driving voltage to the source of the driving transistor, a first capacitor connected between a first node connected to the gate of the driving transistor and a second node connected to the source of the driving transistor, and a second voltage or high potential. It has a second capacitor connected between the power wiring to which the driving voltage is applied and the second node. By applying a low-potential power supply voltage to the cathode of the electroluminescent diode, uniform image quality can be achieved across the entire screen without a low-resistance design of the VDD wiring, and power consumption can be reduced because VDD and Vref are not short-circuited.

The first voltage may be a data voltage synchronized with the first scan signal, and the second voltage may be a reference voltage that is higher than the low-potential power supply voltage and lower than the high-potential driving voltage. In this embodiment, the first scan signal is the nth scan signal, and the second scan signal is the n-1th scan signal preceding the first scan signal.

The first voltage may be a reference voltage that is higher than the low-potential power supply voltage and lower than the high-potential driving voltage, and the second voltage may be a data voltage synchronized with the first scan signal. In this embodiment, the first scan signal is the n+1th scan signal, and the second scan signal is the nth scan signal preceding the first scan signal.

The electroluminescent display device further includes display lines connected to subpixels, and the scan period during which the pixel circuit is initialized, the threshold voltage of the driving transistor is compensated, and the pixel circuit is charged with the data voltage is n-1 (n is a positive number). integer) includes a first period in which the scan signal is input to the n-1th display line and the nth display line, and a second period in which the nth scan signal is input to the nth display line. The second switch transistor and the third switch transistor are turned on according to the gate-on voltage of the n-1th scan signal during the first period, and following the first period, the second switch transistor is turned on according to the gate-on voltage of the nth scan signal during the second period. Accordingly, the first switch transistor is turned on, the fourth switch transistor is turned on according to the gate-on voltage of the light emission control signal after the first to third switch transistors are turned off, and the fourth switch transistor is turned on according to the gate-on voltage of the light emission control signal. And the off state may be maintained during the off period of the light emission control signal that overlaps the second period.

The first switch transistor and the second switch transistor may include a transistor with a dual gate structure.

The second scan signal is applied to the n-1 (n is a positive integer) subpixels and is synchronized to the n-1th data voltage, and the first scan signal is applied to the nth subpixels and synchronized to the nth data voltage. They are synchronized, and the first scan signal can be supplied to the pixel circuit following the second scan signal.

The pulse width of the second scan signal may be wider than the pulse width of the first scan signal.

Each of the first to fourth switch transistors and driving transistors may include p-type transistors.

The electroluminescent display device further includes a scan driver that outputs a second scan signal and a first scan signal, an EM driver that outputs an emission control signal, and display lines connected to the subpixels, and the scan driver has one output terminal. may be connected to subpixels disposed on two neighboring display lines among the display lines.

One output terminal of the EM driver may be connected to subpixels disposed on two adjacent display lines among the display lines.

The electroluminescent display device further includes a first scan driver that outputs a second scan signal, a second scan driver that outputs a first scan signal, an EM driver that outputs an emission control signal, and display lines connected to subpixels. In addition, the first scan driver and the second scan driver share a start pulse and can receive shift clocks with different widths.

One output terminal of the EM driver may be connected to subpixels disposed on two adjacent display lines among the display lines.

The electroluminescent display device may further include a third capacitor connected between the first node and the signal line to which the emission control signal is applied.

An electroluminescent display device according to an embodiment of the present specification includes a display panel on which a plurality of pixels including subpixels are arranged, and a pixel circuit of each subpixel is connected to the anode of an electroluminescent diode to generate an electroluminescent diode. After applying a reference voltage that is higher than the low-potential power supply voltage and lower than the high-potential driving voltage to the gate and drain of the driving transistor in response to the n-1th (n is a positive integer) scan signal, A switch circuit that supplies a data voltage to the gate of the driving transistor in response to the nth scan signal and then supplies a high-potential driving voltage to the source of the driving transistor in response to the light emission control signal, a first node connected to the gate of the driving transistor, and A first capacitor connected between a second node connected to the source of the driving transistor, a power wiring to which a reference voltage or a high potential driving voltage is applied, and a second capacitor connected between the second node, and connected to the cathode of the electroluminescent diode. By applying a low-potential power supply voltage, uniform image quality can be achieved across the screen without a low-resistance VDD wiring design, and power consumption can be reduced because VDD and Vref are not short-circuited.

The switch circuit includes a first switch transistor for supplying a data voltage to the gate of the driving transistor in response to the n-th scan signal, a second switch transistor for supplying a reference voltage to the gate of the driving transistor in response to the n-1th scan signal, A third switch transistor for supplying a reference voltage to the drain of the driving transistor in response to an n-1 scan signal, and a fourth switch transistor for supplying a high potential driving voltage to the drain of the driving transistor in response to an emission control signal. You can.

An electroluminescent display device according to an embodiment of the present specification includes a display panel on which a plurality of pixels including subpixels are arranged, and a pixel circuit of each subpixel is connected to the anode of an electroluminescent diode to generate an electroluminescent diode. A driving transistor for driving, a first switch transistor for supplying a data voltage to the gate of the driving transistor in response to the nth (n is a positive integer) scan signal, and a low potential higher than the power supply voltage in response to the n-1th scan signal. A second switch transistor for supplying a reference voltage lower than the high potential driving voltage to the gate of the driving transistor, a third switch transistor for supplying a reference voltage to the drain of the driving transistor in response to the n-1th scan signal, and a light emission control signal a fourth switch transistor that supplies a high-potential driving voltage to the drain of the driving transistor in response to a light emission control signal, a fifth switch transistor that forms a current path between the source of the driving transistor and the anode of the electroluminescent diode in response to the light emission control signal, and a driving transistor. A first capacitor connected between a first node connected to the gate of and a second node connected to the source of the driving transistor, and a power wiring to which a reference voltage or high potential driving voltage is applied, and a second capacitor connected between the second node. And, by applying a low-potential power supply voltage to the cathode of the electroluminescent diode, uniform image quality can be realized across the entire screen without a low-resistance design of the VDD wiring, and power consumption can be reduced because VDD and Vref are not short-circuited.

The electroluminescent display device further includes display lines connected to subpixels, and the scan period during which the pixel circuit is initialized, the threshold voltage of the driving transistor is compensated, and the pixel circuit is charged with the data voltage is determined by the n-1th scan signal being the nth scan signal. It includes a first period in which the -1 display line and the nth display line are input, and a second period in which the nth scan signal is input to the nth display line. The second switch transistor and the third switch transistor are turned on according to the gate-on voltage of the n-1th scan signal during the first period, and following the first period, the second switch transistor is turned on according to the gate-on voltage of the nth scan signal during the second period. Accordingly, the first switch transistor is turned on, the fourth switch transistor is turned on according to the gate-on voltage of the light emission control signal after the first to third switch transistors are turned off, and the fourth switch transistor is turned on according to the gate-on voltage of the light emission control signal. And the off state may be maintained during the off period of the light emission control signal that overlaps the second period.

The first switch transistor and the second switch transistor may include a transistor with a dual gate structure.

The n-1th scan signal is applied to the n-1th subpixels and synchronized to the n-1th data voltage, and the nth scan signal is applied to the nth subpixels and synchronized to the nth data voltage. Following the -1 scan signal, an nth scan signal may be supplied to the pixel circuit.

The pulse width of the n-1th scan signal may be wider than the pulse width of the nth scan signal.

Each of the first to fifth switch transistors and driving transistors may include n-type transistors.

At least one of the first to fourth switch transistors may include an n-type oxide transistor, and the driving transistor may include p-type polysilicon transistors.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

100: display panel 102: data driver
103, 103A, 103B: scan driving unit 104: EM driving unit
108: Gate driver 110: Timing controller
AA: Screen display BZ: Bezel
DT, NDT: Driving TFT of pixel circuit
T1~T4, NT1~NT5: Switch TFT of pixel circuit
C1, C2: Capacitors in the pixel circuit
OLED: Organic light emitting diode in pixel circuit
LINE1~LINE#: Display lines in the screen display section

Claims (22)

It has a display panel on which a plurality of pixels including sub-pixels are arranged,
The pixel circuit of each of the subpixels is
a driving transistor connected to the anode of the electroluminescent diode to drive the electroluminescent diode;
a first switch transistor supplying a first voltage to the gate of the driving transistor in response to a first scan signal;
a second switch transistor supplying a second voltage to the gate of the driving transistor in response to a second scan signal;
a third switch transistor supplying the second voltage to the drain of the driving transistor in response to the second scan signal;
a fourth switch transistor that supplies a high-potential driving voltage to the source of the driving transistor in response to a light emission control signal;
a first capacitor connected between a first node connected to the gate of the driving transistor and a second node connected to the source of the driving transistor; and
A power wiring to which the second voltage or the high potential driving voltage is applied, and a second capacitor connected between the second node,
A low-potential power supply voltage is applied to the cathode of the electroluminescent diode,
The second scan signal is a scan signal preceding the first scan signal. According to claim 1,
The first voltage is a data voltage synchronized to the first scan signal,
The second voltage is a reference voltage that is higher than the low-potential power supply voltage and lower than the high-potential driving voltage,
The electroluminescent display device wherein the first scan signal is an nth (n is a positive integer) scan signal, and the second scan signal is an n-1th scan signal preceding the first scan signal. According to claim 1,
The first voltage is a reference voltage that is higher than the low-potential power supply voltage and lower than the high-potential driving voltage,
The second voltage is a data voltage synchronized to the first scan signal,
The first scan signal is an n+1 (n is a positive integer) scan signal, and the second scan signal is an nth scan signal preceding the first scan signal. According to claim 1,
further comprising display lines connected to the subpixels,
The scan period during which the pixel circuit is initialized, the threshold voltage of the driving transistor is compensated, and the pixel circuit is charged with a data voltage is,
A first period in which the second scan signal is input to the n-1 (n is a positive integer) display line and the nth display line and a second period in which the first scan signal is input to the nth display line; ,
The second switch transistor and the third switch transistor are turned on according to the gate-on voltage of the second scan signal during the first period,
Following the first period, the first switch transistor is turned on according to the gate-on voltage of the first scan signal during the second period,
The fourth switch transistor is turned on according to the gate-on voltage of the light emission control signal after the first to third switch transistors are turned off,
The fourth switch transistor maintains an off state during the off period of the light emission control signal that overlaps the first and second periods. According to claim 1,
The first switch transistor and the second switch transistor include a dual gate structure transistor. According to claim 1,
The second scan signal is applied to the n-1th (n is a positive integer) subpixels and is synchronized to the n-1th data voltage,
The first scan signal is applied to the n-th subpixels and is synchronized to the n-th data voltage,
An electroluminescence display device in which the first scan signal is supplied to the pixel circuit following the second scan signal. According to claim 1,
An electroluminescence display device in which the pulse width of the second scan signal is wider than the pulse width of the first scan signal. According to claim 1,
Each of the first to fourth switch transistors and the driving transistor includes p-type transistors. According to claim 6,
a scan driver outputting the second scan signal and the first scan signal;
an EM driver that outputs the light emission control signal; and
Further comprising display lines connected to the subpixels,
An electroluminescence display device in which one output terminal of the scan driver is connected to the subpixels disposed on two neighboring display lines. According to clause 9,
An electroluminescence display device in which one output terminal of the EM driver is connected to the subpixels disposed on two neighboring display lines. According to claim 7,
a first scan driver outputting the second scan signal;
a second scan driver outputting the first scan signal;
an EM driver that outputs the light emission control signal; and
Further comprising display lines connected to the subpixels,
The first scan driver and the second scan driver share a start pulse and are supplied with shift clocks having different widths. According to claim 11,
An electroluminescence display device in which one output terminal of the EM driver is connected to the subpixels disposed on two neighboring display lines. According to claim 1,
The electroluminescent display device further includes a third capacitor connected between the first node and a signal line to which the emission control signal is applied. According to claim 1,
At least one of the first to fourth switch transistors includes an n-type oxide transistor,
The driving transistor is an electroluminescent display device including p-type polysilicon transistors. It has a display panel on which a plurality of pixels including sub-pixels are arranged,
The pixel circuit of each of the subpixels is
a driving transistor connected to the anode of the electroluminescent diode to drive the electroluminescent diode;
After applying a reference voltage that is higher than the low-potential power supply voltage and lower than the high-potential driving voltage to the gate and drain of the driving transistor in response to the n-1 (n is a positive integer) scan signal, the n-th scan signal a switch circuit that supplies a data voltage to the gate of the driving transistor in response and then supplies the high potential driving voltage to the drain of the driving transistor in response to a light emission control signal;
a first capacitor connected between a first node connected to the gate of the driving transistor and a second node connected to the source of the driving transistor; and
A power wiring to which the reference voltage or the high-potential driving voltage is applied, and a second capacitor connected between the second node,
The low-potential power supply voltage is applied to the cathode of the electroluminescent diode,
The switch circuit is,
a first switch transistor supplying the data voltage to the gate of the driving transistor in response to the nth scan signal;
a second switch transistor supplying the reference voltage to the gate of the driving transistor in response to the n-1th scan signal; and
A third switch transistor supplies the reference voltage to the drain of the driving transistor in response to the n-1th scan signal,
The n-1th scan signal is a scan signal preceding the nth scan signal. According to claim 15,
The switch circuit is
An electroluminescent display device comprising a fourth switch transistor that supplies the high-potential driving voltage to the drain of the driving transistor in response to the emission control signal. It has a display panel on which a plurality of pixels including sub-pixels are arranged,
The pixel circuit of each of the subpixels is
a driving transistor connected to the anode of the electroluminescent diode to drive the electroluminescent diode;
a first switch transistor that supplies a data voltage to the gate of the driving transistor in response to an nth (n is a positive integer) scan signal;
a second switch transistor that supplies a reference voltage higher than a low-potential power supply voltage and lower than a high-potential driving voltage to the gate of the driving transistor in response to an n-1th scan signal;
a third switch transistor supplying the reference voltage to the drain of the driving transistor in response to the n-1th scan signal;
a fourth switch transistor that supplies the high-potential driving voltage to the drain of the driving transistor in response to a light emission control signal;
a fifth switch transistor forming a current path between the source of the driving transistor and the anode of the electroluminescent diode in response to the light emission control signal;
a first capacitor connected between a first node connected to the gate of the driving transistor and a second node connected to the source of the driving transistor; and
A power wiring to which the reference voltage or the high-potential driving voltage is applied, and a second capacitor connected between the second node,
The low-potential power supply voltage is applied to the cathode of the electroluminescent diode,
The n-1th scan signal is a scan signal preceding the nth scan signal. According to claim 17,
further comprising display lines connected to the subpixels,
The scan period during which the pixel circuit is initialized, the threshold voltage of the driving transistor is compensated, and the pixel circuit is charged with a data voltage is,
A first period in which the n-1th scan signal is input to the n-1th display line and the nth display line and a second period in which the nth scan signal is input to the nth display line,
The second switch transistor and the third switch transistor are turned on according to the gate-on voltage of the n-1th scan signal during the first period,
Following the first period, the first switch transistor is turned on according to the gate-on voltage of the nth scan signal during the second period,
The fourth switch transistor is turned on according to the gate-on voltage of the light emission control signal after the first to third switch transistors are turned off,
The fourth switch transistor maintains an off state during the off period of the light emission control signal that overlaps the first and second periods. According to claim 17,
The first switch transistor and the second switch transistor include a dual gate structure transistor. According to claim 17,
The n-1th scan signal is applied to the n-1th subpixels and is synchronized to the n-1th data voltage,
The nth scan signal is applied to the nth subpixels and is synchronized to the nth data voltage,
An electroluminescence display device in which the nth scan signal is supplied to the pixel circuit following the n-1th scan signal. According to claim 17,
An electroluminescence display device in which the pulse width of the n-1th scan signal is wider than the pulse width of the nth scan signal. According to claim 17,
Each of the first to fifth switch transistors and the driving transistor includes n-type transistors.