KR20190064267A - Electroluminescent display device - Google Patents

Abstract

According to an embodiment of the present invention, an electroluminescent display device includes a display panel including pixel lines. Among pixel lines, individual pixel circuits included in an n^th (n is a natural number) pixel line comprise respectively: a driving transistor of which a gate is connected to a second node, and which is connected between a first node and a third node; a first transistor which controls current flow between the second node and the third node in response to an n+1 scan signal; a second transistor which applies reference voltage to the first node in response to an n scan signal; a third transistor which applies high potential power voltage to the first node in response to an n emission signal; a fourth transistor which applies initialization voltage to a fourth node in response to an n-1 scan signal; and a fifth transistor which applies the high potential power voltage to the fourth node in response to the n emission signal; and a sixth transistor which applies the high potential power voltage to the fourth node in response to the n-1 scan signal; a seventh transistor which applies data voltage to the fourth node in response to the n+1 scan signal; a capacitor which is connected between the second node and the fourth node; and a light emitting element of which an anode is connected to the third node and a cathode is connected to wiring applied with low potential power voltage. Therefore, the electroluminescent display device can improve image quality thereof because a sub-pixel applied with reference voltage provides a light emitting element with driving current not influenced by high potential power voltage.

Description

ELECTROLUMINESCENT DISPLAY DEVICE [0002]

TECHNICAL FIELD The present invention relates to an electroluminescent display device, and more particularly, to an electroluminescent display device including a pixel circuit capable of voltage drop compensation.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, various types of display devices such as an electroluminescent display device, a liquid crystal display device, and a quantum dot display device are increasingly used.

In an electroluminescent display device, when a gate signal, a data signal, or the like is supplied to subpixels, a light emitting element of a selected subpixel emits light, thereby displaying an image. The light emitting device can be implemented based on an organic material or an inorganic material.

The electroluminescence display device displays an image based on light generated from the light emitting element in the subpixel so that it is necessary to improve the accuracy of the pixel circuit for controlling the light emission of the subpixel in order to improve the image quality of the image represented by the electroluminescence display device . For example, the accuracy of the pixel circuit can be improved by compensating for the time-varying characteristic (or temporal change) of the threshold voltage of the transistor included in the pixel circuit.

There are various methods for compensating time-varying characteristics of an electroluminescent display device. Some of the compensation methods do not consider the drop of the power supply voltage applied to the subpixels, resulting in image quality issues such as vertical brightness unevenness and cross-talk of the display panel.

Therefore, research is underway to design a pixel circuit in which the drop of the power supply voltage is compensated for the accurate image display of the electroluminescence display device.

Accordingly, the inventors of the present invention have recognized the above-mentioned problem and invented a display device for minimizing a voltage drop to a voltage-applied wiring.

A solution according to embodiments of the present invention is to provide a pixel circuit in which image quality problems such as vertical luminance unevenness and crosstalk of a display panel are improved by compensating for a voltage drop to a power supply voltage applied wiring and an electroluminescent display device including the pixel circuit will be.

SUMMARY OF THE INVENTION The present invention provides an electroluminescent display device capable of realizing a high-definition display device by disposing a part of transistors included in a subpixel in a non-display region.

The present invention provides a light emitting display device having a step of providing a reference voltage according to a driving method of a sub pixel so that a driving current applied to a light emitting device can be excluded from the influence of a voltage drop will be.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

In an electroluminescent display according to an embodiment of the present invention, an electroluminescent display includes a display panel including pixel lines. Each of the pixel circuits included in the n-th (n is a natural number) pixel line of the pixel lines includes a driving transistor connected to the second node and connected between the first node and the third node, A first transistor for conducting a current flow between a second node and a third node in response to a scan signal, a second transistor for applying a reference voltage to a first node in response to an n-th scan signal, A fourth transistor for applying an initialization voltage to the fourth node in response to the n-1 scan signal, a third transistor for applying a high voltage to the fourth node in response to the nth emission signal, A sixth transistor for applying a high potential power supply voltage to a fourth node in response to an (n-1) th scan signal, a fifth transistor for applying a data voltage to the fourth node in response to the (n + The seventh trans Stirrer, and the anode is connected to the second node and the capacitor, and a third node, the fourth node being coupled between a light emitting element is connected to the cathode wiring is applied with a low potential power supply voltage. Accordingly, the subpixel to which the reference voltage is applied can provide the light emitting element with a driving current that is not affected by the high-potential power supply voltage, thereby improving the image quality of the electroluminescence display device.

In an electroluminescent display according to an embodiment of the present invention, an electroluminescent display includes a display panel including pixel lines. Each of the pixel circuits included in the n-th (n is a natural number) pixel line of the pixel lines includes a driving transistor having a gate connected to the second node and connected between the first node and the third node, A first transistor for conducting a current flow between the second node and the third node in response to the scan signal, a second transistor for applying a reference voltage to the first node in response to an n-th scan signal, A fourth transistor for applying an initialization voltage to a fifth node in response to an n-th scan signal, a third transistor for applying a high-potential power supply voltage to the fourth node in response to the n-th emission signal, A sixth transistor for applying a high voltage to the fourth node in response to the (n-1) th scan signal, a seventh transistor for applying a data voltage to the fourth node in response to the n th scan signal, An nth transistor for supplying an initialization voltage to the second node in response to the (n-1) th scan signal, a ninth transistor for conducting a current flow between the third node and the fifth node in response to the nth emission signal, A capacitor connected between the second node and the fourth node, and a light emitting element having an anode connected to the fifth node and a cathode connected to a wiring to which a low potential power voltage is applied. Accordingly, the subpixel to which the reference voltage is applied can provide the light emitting element with a driving current that is not affected by the high-potential power supply voltage, thereby improving the image quality of the electroluminescence display device.

The details of other embodiments are included in the detailed description and drawings.

According to the embodiments of the present invention, it is possible to improve image quality problems such as vertical luminance unevenness and crosstalk of a display panel by implementing a pixel circuit capable of compensating time-varying characteristics in consideration of a voltage drop of a power supply voltage.

According to the embodiments of the present invention, some of the plurality of transistors driving the pixel circuit are disposed in the non-display area and are commonly used in the pixel circuit connected to the same pixel line, thereby improving the efficiency of the pixel circuit design And a high-resolution display device can be realized.

The scope of the claims is not limited by the matters described in the description of the specification, as the contents of the description in the problems, the solutions to the problems, and the effects described above do not specify the essential features of the claims.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention.
2 is a block diagram of signal lines input to the subpixels and subpixels shown in FIG.
3 is a circuit diagram of a subpixel according to the first embodiment of the present invention.
4A is a diagram illustrating driving in a setup period of a subpixel according to the first embodiment of the present invention.
4B is a waveform diagram showing the driving of FIG. 4A.
5A is a diagram illustrating driving of a subpixel in a sampling period according to the first embodiment of the present invention.
5B is a waveform diagram showing the driving of FIG. 5A.
6A is a diagram illustrating driving in a programming period of a subpixel according to the first embodiment of the present invention.
6B is a waveform diagram showing the driving of Fig. 6A.
7A is a diagram illustrating driving in a holding period of a subpixel according to the first embodiment of the present invention.
Fig. 7B is a waveform diagram showing the drive of Fig. 7A.
8A is a diagram illustrating driving in a light emission period of a subpixel according to the first embodiment of the present invention.
8B is a waveform diagram showing the drive of FIG. 8A.
9 is a circuit diagram of a subpixel according to the second embodiment of the present invention.
10A is a waveform diagram showing driving in a setup period of a subpixel according to the second embodiment of the present invention.
10B is a diagram showing the driving of FIG. 10A.
11A is a waveform diagram showing driving in a sampling period of a subpixel according to the second embodiment of the present invention.
11B is a circuit diagram showing the driving of Fig. 11A.
12A is a circuit diagram showing driving in a holding period of a subpixel according to the second embodiment of the present invention.
12B is a waveform diagram showing the driving of Fig. 12A.
13A is a circuit diagram showing driving in a light emission period of a subpixel according to the second embodiment of the present invention.
13B is a waveform diagram showing the driving of Fig. 13A.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if a temporal posterior relationship is described by 'after', 'after', 'after', 'before', etc., 'May not be contiguous unless it is used.

It is to be understood that each of the features of the various embodiments herein may be combined or combined with each other, partially or wholly, and technically various interlocking and driving are possible, and that the embodiments may be practiced independently of each other, It is possible.

The pixel circuit formed on the substrate of the display panel in this specification may be implemented as an n-type or p-type transistor. For example, the transistor may be implemented as a transistor of a metal oxide semiconductor field effect transistor (MOSFET) structure. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. For example, the flow of carriers in a transistor flows from a source to a drain. In the case of an n-type transistor, since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so as to flow from the source to the drain. In an n-type transistor, the direction of the current flows from the drain to the source because electrons flow from the source to the drain. In the case of a p-type transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. Since the holes of the p-type transistor flow from the source to the drain, current flows from the source to the drain. The source and the drain of the transistor are not fixed, and the source and drain of the transistor can be changed according to the applied voltage. Further, the source and the drain of the transistor may be referred to as a first electrode and a second electrode, respectively, or a second electrode and a first electrode, respectively.

In the following, the gate on voltage may be the voltage of the gate signal that the transistor may be turned on. The gate off voltage may be the voltage of the gate signal that the transistor may turn off. In a p-type transistor, the gate-on voltage may be a gate-low voltage or a logic low (VL), and a gate-off voltage may be a gate high voltage or a logic high voltage (VH). In an n-type transistor, the gate-on voltage may be a gate high voltage or a logic high voltage (VH), and the gate-off voltage may be a gate-low voltage or a logic low voltage (VL). In addition, the magnitude of the high-potential power supply voltage, the low-potential power supply voltage, the initialization voltage, the reference voltage, the data voltage, the gate high voltage, and the gate low voltage described below may be varied according to the brightness of the electroluminescence display device.

Hereinafter, an electroluminescent display according to an embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention.

1, an EL display device 100 includes an image processing unit 110, a timing control unit 120, a gate driving unit 130, a data driving unit 140, and a display panel 150.

The image processing unit 110 outputs driving signals for driving various devices in addition to image data supplied from the outside. The driving signal output from the image processing unit 110 may include a data enable signal, a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal.

The timing controller 120 receives a driving signal and the like in addition to the video data supplied from the video processor 110. The timing controller 120 includes a gate timing control signal GTC for controlling the operation timing of the gate driver 130 and a data timing control signal DTC for controlling the operation timing of the data driver 140, .

The gate driver 130 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120. The gate driver 130 outputs a gate signal through the gate lines GL1, ..., and GLp. The gate driver 130 may be formed in the form of an integrated circuit (IC) or a gate in panel (GIP) embedded in a display panel. The gate driver 130 may be disposed on the left side or the right side of the display panel 150, or may be disposed on either side. The gate driver 130 outputs the first scan signal to the p scan signal to the first scan line to the p scan line of the display panel, respectively.

The data driver 140 outputs the data voltage in response to the data timing control signal DTC supplied from the timing controller 120. The data driver 140 samples and latches the digital data signal DATA supplied from the timing controller 120 and converts the data signal into an analog data signal based on the gamma reference voltage. The data driver 140 outputs a data signal through the data lines DL1, ..., DLq. The data driver 140 may be formed on a display panel in the form of an integrated circuit (IC), or may be formed in the form of a chip on film (COF) on the display panel.

The power supply unit 180 outputs a high potential power supply voltage VDD and a low potential power supply voltage VSS. The high power supply voltage VDD and the low potential power supply voltage VSS output from the power supply unit 180 are supplied to the display panel 150. The high potential power supply voltage VDD is supplied to the display panel 150 through the high potential power supply line and the low potential power supply voltage VSS is supplied to the display panel 150 through the low potential power supply line. The voltage output from the power supply unit 180 may be used in the gate driver 130 or the data driver 140.

The display panel 150 displays an image corresponding to the gate signal and the data signal supplied from the gate driver 130 and the data driver 140 and the power supply voltage supplied from the power supplier 180.

The display panel 150 includes a display region in which the subpixels SP are formed and a non-display region in which various signal lines, pads, and the like are formed outside the display region. Since the display region is an area for displaying an image, the subpixels SP are located, and the non-display region is an area where no image is displayed, and therefore dummy subpixels are located or subpixels SP are not located.

The display area includes a plurality of sub-pixels (SP), and displays an image based on a gray level displayed by each sub-pixel (SP). Each sub-pixel SP is connected to a data line arranged along a column line and connected to a gate line arranged along a pixel line or a row line. The subpixels SP arranged on the same pixel line share the same gate line and are simultaneously supplied with the gate signal through the gate line. When the subpixels SP arranged in the first pixel line are defined as first subpixels and the subpixels SP arranged in the ppixel line are defined as pp subpixels, The pixels to the p sub-pixels are sequentially driven.

The subpixels SP of the display panel 150 are arranged in a matrix form to constitute a pixel array, but are not limited thereto. The subpixels SP may be arranged in various forms such as a pixel sharing shape, a stripe shape, and a diamond shape, in addition to a matrix shape.

The subpixels SP may include a red subpixel, a green subpixel, and a blue subpixel or may include a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP may have one or more different emission areas depending on the emission characteristics.

2 is a block diagram of signal lines input to the subpixels and subpixels shown in FIG.

One subpixel SP includes a gate line GL, a data line DL, a high potential power supply line VDDL, a low potential power supply line VSSL, an initialization voltage line ViniL and a reference voltage line VrefL. Lt; / RTI > The number of transistors and capacitors and the driving method of the sub-pixel SP are determined according to the configuration of the pixel circuit. In this case, the gate line GL may include a plurality of scan lines for transmitting a scan signal and a plurality of emission lines for transmitting an emission signal.

3 is a circuit diagram of a subpixel according to the first embodiment of the present invention.

The display panel 150 includes a display region for displaying an image based on the subpixels SP, a non-display region for displaying a signal line, a driving circuit, or the like and not displaying an image.

The electroluminescent display device 100 displays an image based on light generated from the light emitting device EL included in the sub-pixel SP. However, in the electroluminescent display device, it is necessary to compensate for the time-varying characteristics of the elements included in the subpixel SP and the voltage drop of the wiring to which the power supply voltage is applied due to the enlargement of the display panel.

Therefore, a pixel circuit for recognizing and improving a problem causing image quality problems such as vertical luminance unevenness and crosstalk in an electroluminescent display device according to an embodiment of the present invention will be described. The pixel circuit to be described below will be described by taking p-type transistors as an example, but the present invention is not limited thereto and n-type transistors are also applicable. The subpixel SP according to the first embodiment of the present invention is described by taking as an example a subpixel SP arranged in n (n is a natural number, 1? N? P) th pixel line.

The nth sub-pixel SP includes the first to seventh transistors T1 to T7, the driving transistor DT, the capacitor Cst, and the light emitting element EL. In the first embodiment of the present invention, the nth sub-pixel SP is implemented based on a total of eight transistors and one capacitor.

The driving transistor DT includes a source connected to the first node N1, a gate connected to the second node N2, and a drain connected to the third node N3. The driving transistor DT is turned on when a gate-on voltage is applied to the second node N2 to provide a constant current to the third node N3.

The first transistor T1 includes a gate connected to the (n-1) th scan line, a source connected to the second node, and a drain connected to the third node. The first transistor T1 is turned on in response to the gate-on voltage of the (n + 1) th scan signal Scan (n + 1) applied through the (n + 1) th scan line. When the first transistor T1 is turned on, the gate and drain of the driving transistor DT become conductive, so that the driving transistor DT becomes a diode connection state.

The second transistor T2 includes a gate connected to the nth scan line, a source connected to the reference voltage line, and a drain connected to the first node. The second transistor T2 is turned on in response to the gate-on voltage of the nth scan signal Scan (n) applied through the nth scan line. When the second transistor T2 is turned on, the reference voltage Vref is applied to the first node N1.

The third transistor T3 includes a gate connected to the nth emission line, a source connected to the high potential power line, and a drain connected to the first node. The third transistor T3 is turned on in response to the gate-on voltage of the nth emission signal EM (n) applied through the nth emission line. When the third transistor T3 is turned on, the high potential power supply voltage VDD is applied to the first node N1.

The light emitting device EL includes an anode connected to the third node N3 and a cathode to which a low potential power supply voltage VSS is applied. When the driving current generated through the driving transistor DT is applied to the anode of the light emitting element EL, the light emitting element EL emits light. For example, the low potential power supply voltage (VSS) is a voltage of -4V to -2.5V.

The fourth transistor T4 includes a gate connected to the (n-1) th scan line, a source connected to the fourth node N4, and a drain connected to the initialization line. The fourth transistor T4 is turned on in response to the gate-on voltage of the (n-1) th scan signal Scan (n-1) applied through the (n-1) th scan line. When the fourth transistor T4 is turned on, the anode of the light emitting device EL is initialized based on the initialization voltage.

The fifth transistor T5 includes a gate connected to the nth emission line, a source connected to the high potential power supply line, and a drain connected to the fourth node N4. The fifth transistor T5 is turned on in response to the gate-on voltage of the nth emission signal EM (n) applied through the nth emission line. When the fifth transistor T5 is turned on, the high potential power supply voltage VDD is applied to the fourth node N4.

The capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the fourth node N4.

The sixth transistor T6 includes a gate connected to the (n-1) th scan line, a source connected to the high potential power supply line, and a drain connected to the fourth node N4. The sixth transistor T6 is turned on in response to the gate-on voltage of the (n-1) th scan signal Scan (n-1) applied through the (n-1) th scan line. When the sixth transistor T6 is turned on, the high potential supply voltage VDD is applied to the fourth node N4.

The seventh transistor T7 includes a gate connected to the (n + 1) th scan line, a source connected to the data line, and a drain connected to the fourth node N4. The seventh transistor T7 is turned on in response to the gate-on voltage of the (n + 1) th scan signal Scan (n + 1) applied through the (n + 1) th scan line. When the seventh transistor T7 is turned on, the data voltage Vdata is applied to the fourth node N4.

Since the voltage applied to the gate of the driving transistor DT controls the turn-on state of the driving transistor DT, the transistor whose source or drain is connected to the gate of the driving transistor DT is turned off It can be configured to include two or more transistors connected in series. In this case, the two or more transistors are controlled by the same control signal. Therefore, the nth sub-pixel SP according to the first embodiment of the present invention can be formed by the first transistor T1 as a double gate type transistor.

The nth sub-pixel SP according to the first embodiment of the present invention operates in the order of an initialization period, a first holding period, a sampling period, a second holding period, and a light emitting period. The initialization period is a period for initializing the anode of the light emitting element EL. The first holding period is a period for applying the reference voltage Vref to the source of the driving transistor DT. The sampling period is a period for initializing the data voltage Vdata Is a period for writing to the node and sampling the threshold voltage of the driving transistor DT. The second holding period holds the data voltage Vdata at a specific node and the light emitting period is a period during which the light emitting device EL emits light using the driving current generated based on the data voltage Vdata.

The nth subpixel SP according to the first embodiment of the present invention is supplied with an initialization period INI, a first holding period HLD1 (n) during a period in which the gate- ), The sampling period (SAM), and the second holding period (HLD2), internal circuit based compensation is performed. The operation characteristics during these periods will be described as follows. The scan signal is supplied with a gate-on voltage during two horizontal periods (2H), and the emission signal is an example in which a gate-off voltage is applied during four horizontal periods (4H). An example is shown in which the initialization period INI, the first holding period HLD1, the sampling period SAM, and the second holding period HLD2 are each performed during one horizontal period (1H). In the following drawings, the driving of the pixel circuit as described above will be described.

4A is a diagram illustrating driving in a setup period of a subpixel according to the first embodiment of the present invention. 4B is a waveform diagram showing the driving of FIG. 4A.

1) th scan signal Scan (n-1) in the initialization period INI is a gate-on voltage and the nth scan signal Scan (n) and the (n + 1) ), And the nth emission signal EM (n) are gate-off voltages. For example, the gate-on voltage is -8V with a logic low voltage (VL) and the gate-off voltage is 8V with a logic high voltage (VH).

The fourth transistor T4 and the sixth transistor T6 are turned on by the gate-on voltage applied through the (n-1) th scan line. Since the initializing voltage Vini is applied to the fourth node N4 through the turned-on fourth transistor T4, the gate of the light emitting device EL is initialized to the initializing voltage Vini. The high-level power supply voltage VDD is applied to the fourth node N4 through the turned-on sixth transistor T6. In this case, the initialization voltage (Vini) is equal to or lower than the low potential power supply voltage (VSS). For example, the initialization voltage Vini is a voltage between -3V and -4V, and the data voltage Vdata is a voltage that varies with luminance between 0.3V and 6.3V.

During the initialization period INI, the anode of the light emitting device EL is initialized based on the initialization voltage Vini and the high potential power supply voltage VDD is applied to one electrode of the capacitor Cst.

5A is a diagram illustrating driving in a first holding period of a subpixel according to the first embodiment of the present invention. 5B is a waveform diagram showing the driving of FIG. 5A.

Scan signals Scan (n-1) and Scan n (n) are gate-on voltages in the first holding period HLD1, 1) and the nth emission signal EM (n) are gate-off voltages. The nth scan signal Scan (n-1) and the nth scan signal Scan (n) are overlapped with each other during the first holding period HLD1.

The fourth transistor T4 is turned on by the gate-on voltage applied through the (n-1) th scan line, and the second transistor T2 is turned on by the gate-on voltage applied through the nth scan line . The initialization voltage Vini applied to the anode of the light emitting device EL is maintained through the fourth transistor T4 turned on and the reference voltage Vref is applied to the first node N1 .

6A is a diagram illustrating driving of a subpixel in a sampling period according to the first embodiment of the present invention. 6B is a waveform diagram showing the driving of Fig. 6A.

1) th scan signal Scan (n-1) is a gate-on voltage and the nth scan signal Scan (n) and the (n + 1) ) And the nth emission signal EM (n) are gate-off voltages.

The second transistor T2 is turned on by the gate-on voltage applied through the nth scan line and the first transistor T1 is turned on by the gate-on voltage applied through the (n + 1) th scan line The driving transistor DT is in a diode connection state. The reference voltage Vref is applied to the source of the driving transistor DT through the turned on second transistor T2 and the gate and the drain of the driving transistor DT are connected to each other by the first transistor T1 turned on , The driving transistor DT is turned on. The voltage of the second node N2 connected to the gate of the driving transistor DT rises to the sum of the reference voltage Vref and the threshold voltage Vth of the driving transistor DT. Then, the data voltage Vdata is applied to the fourth node N4 by the seventh transistor T7 turned on by the gate-on voltage applied through the (n + 1) th scan line. The sum of the reference voltage Vref and the threshold voltage Vth of the driving transistor DT is applied to the first electrode of the capacitor Cst and the data voltage Vdata is applied to the second electrode thereof. ) Is charged with the difference (Vdata- (Vref + Vth)) between the voltage applied to the first electrode and the second applied voltage. In this case, the reference voltage Vref is higher than the low potential power supply voltage VSS and lower than the high potential power supply voltage VDD. In this case, the reference voltage Vref is higher than the low potential power supply voltage VSS and lower than the high potential power supply voltage VDD. For example, the reference voltage Vref may be 4V and the threshold voltage Vth may be -4V, but is not limited thereto.

On voltage is applied to both the n-th scan signal Scan (n) and the (n + 1) -th scan signal Scan (n + 1) during the sampling period (SAM) And applies the reference voltage Vref to the source of the driving transistor DT to apply the threshold voltage Vth of the driving transistor DT to the second node N2 It is possible to sample and sense the reference voltage Vref.

7A is a diagram illustrating driving in a second holding period of a subpixel according to the first embodiment of the present invention. Fig. 7B is a waveform diagram showing the drive of Fig. 7A.

1) th scan signal Scan (n + 1) in the second holding period HLD2 maintains the gate-on voltage and the nth scan signal Scan (n-1) Scan (n), and nth emission signal EM (n) are gate-off voltages.

The first transistor T1 and the seventh transistor T7 are turned on by the gate-on voltage applied through the (n + 1) th scan signal Scan (n + 1). Therefore, in the second holding period HLD2, the capacitor Cst charges and holds the data voltage Vdata based on the voltage difference between both ends.

8A is a diagram illustrating driving in a light emission period of a subpixel according to the first embodiment of the present invention. 8B is a waveform diagram showing the drive of FIG. 8A.

The nth emission signal EM (n) is the gate-on voltage in the emission period EMI and the nth scan signal Scan (n-1), the nth scan signal Scan (n) The (n + 1) th scan signal Scan (n + 1) is a gate-off voltage.

The third transistor T3 and the fifth transistor T5 are turned on by the gate-on voltage applied through the nth emission signal EM (n). The high level power supply voltage VDD is applied to the first node N1 through the turned on third transistor T3 and the high level power supply voltage VDD is supplied to the fourth node N1 through the turned- N4. The voltage of the fourth node N4 connected to the second electrode of the capacitor Cst is changed from the data voltage Vdata to the high potential power supply voltage VDD and the capacitor Cst is coupled by the coupling phenomenon of the capacitor Cst, The voltage of the first electrode of the fourth node N4 varies by the amount of voltage variation of the fourth node N4. Therefore, the voltage of the second node N2 connected to the first electrode of the capacitor Cst becomes Vref + Vth + (VDD-Vdata). In this case, since the high-potential power supply voltage VDD is applied to the source of the driving transistor DT, the driving transistor DT is turned on to apply the driving current to the anode of the light-emitting element EL. Therefore, the light emitting element EL emits light. For example, the high-potential power supply voltage (VDD) is 4.6V.

The nth subpixel SP according to the first embodiment of the present invention has a high potential power supply voltage VDD at the source and gate of the driving transistor DT so that the voltage drop of the high potential power supply voltage VDD can be taken into consideration, . Accordingly, the current of the compensated nth subpixel SP can be expressed by the following equation.

Vdata = K (Vgs - Vth) 2 = K (Vref + Vth + VDD - Vdata) - VDD - Vth}

Vgs is the voltage between the gate and the source of the driving transistor DT, Vth is the threshold voltage of the driving transistor DT, and VDD is the voltage of the high-potential power source (Vdd). In the above equation, Ioled is the current flowing through the light- Vref denotes a reference voltage applied through the reference voltage line VrefL, and Vdata denotes a data voltage applied through the data line DL.

As can be seen from the above equation, Ioled is determined by the difference between the reference voltage and the data voltage. According to the formula, the nth subpixel SP according to the first embodiment of the present invention has a high power supply voltage VDD applied to the gate and source of the driving transistor DT in the emission period EMI, It can be seen that the high-potential power-supply voltage drop can be compensated for by the reference voltage Vref applied to the source of the driving transistor DT in the scan driver SAM.

Therefore, by implementing a driver circuit that can compensate time-varying characteristics in consideration of the voltage drop of the high-potential power supply voltage, it is possible to improve image quality problems such as uneven luminance of the display panel and crosstalk.

Among the plurality of transistors constituting the nth subpixel SP according to the first embodiment of the present invention, the second transistor T2 and the third transistor T3 are disposed on one side of the non-display region to form the n < th > Pixels can be commonly used for q subpixels arranged in a pixel line. Alternatively, when the gate driver 130 is disposed on the left and right sides, the second transistor T2 and the third transistor T3 are arranged in the left and right non-display regions, respectively, and q / 2 sub- It can be used for public use. Accordingly, the number of transistors constituting the subpixel can be reduced to efficiently design subpixels, and a high-resolution display device can be realized. In this case, among the plurality of transistors constituting the nth subpixel SP, the remaining transistors except the second transistor T2 and the third transistor T3 are connected to the n-th pixel line A high-definition display device can be realized by disposing the second transistor T2 and the third transistor T3 in the non-display region.

9 is a circuit diagram of a subpixel according to the second embodiment of the present invention. FIG. 9 is a modified example in which two transistors are added to the pixel circuit of FIG. 3, so redundant explanations can be omitted or briefly explained.

The nth sub-pixel SP according to the second embodiment of the present invention includes the first to ninth transistors T1 to T9, the driving transistor DT, the capacitor Cst, and the light emitting element EL . In the second embodiment of the present invention, the nth sub-pixel SP is implemented based on a total of ten transistors and one capacitor.

The driving transistor DT includes a source connected to the first node N1, a gate connected to the second node N2, and a drain connected to the third node N3. The driving transistor DT is turned on when a gate-on voltage is applied to the second node N2 to provide a constant current to the third node N3.

The first transistor T1 includes a gate connected to the nth scan line, a source connected to the second node, and a drain connected to the third node. The first transistor T1 is turned on in response to the gate-on voltage of the nth scan signal Scan (n) applied through the nth scan line. When the first transistor T1 is turned on, the gate and drain of the driving transistor DT become conductive, so that the driving transistor DT becomes a diode connection state.

The second transistor T2 includes a gate connected to the nth scan line, a source connected to the reference voltage line, and a drain connected to the first node. The second transistor T2 is turned on in response to the gate-on voltage of the nth scan signal Scan (n) applied through the nth scan line. When the second transistor T2 is turned on, the reference voltage Vref is applied to the first node N1.

The third transistor T3 includes a gate connected to the nth emission line, a source connected to the high potential power line, and a drain connected to the first node. The third transistor T3 is turned on in response to the gate-on voltage of the nth emission signal EM (n) applied through the nth emission line. When the third transistor T3 is turned on, the high potential power supply voltage VDD is applied to the first node N1.

The fourth transistor T4 includes a gate connected to the nth scan line, a source connected to the fifth node N5, and a drain connected to the initialization line. In this case, the fifth node N5 is connected to the anode of the light emitting element EL. The fourth transistor T4 is turned on in response to the gate-on voltage of the nth scan signal Scan (n) applied through the nth scan line. When the fourth transistor T4 is turned on, the initialization voltage Vini is applied to the fifth node N5, so that the anode of the light emitting element EL is initialized.

The fifth transistor T5 includes a gate connected to the nth emission line, a source connected to the high potential power supply line, and a drain connected to the fourth node N4. The fifth transistor T5 is turned on in response to the gate-on voltage of the nth emission signal EM (n) applied through the nth emission line.

The sixth transistor T6 includes a gate connected to the (n-1) th scan line, a source connected to the high potential power supply line, and a drain connected to the fourth node N4. The sixth transistor T6 is turned on in response to the gate-on voltage of the (n-1) th scan signal Scan (n-1) applied through the (n-1) th scan line. When the sixth transistor T6 is turned on, the high potential supply voltage VDD is applied to the fourth node N4.

The capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the fourth node N4.

The seventh transistor T7 includes a gate connected to the nth scan line, a source connected to the data line, and a drain connected to the fourth node N4. The seventh transistor T7 is turned on in response to the gate-on voltage of the nth scan signal Scan (n) applied through the nth scan line. When the seventh transistor T7 is turned on, the data voltage Vdata is applied to the fourth node N4.

The eighth transistor T8 includes a gate connected to the (n-1) th scan line, a source connected to the second node N2, and a drain connected to the initialization line. The eighth transistor T8 is turned on in response to the gate-on voltage of the (n-1) th scan signal Scan (n-1) applied through the (n-1) th scan line. When the eighth transistor T8 is turned on, the initializing voltage Vini is applied to the second node N2.

The ninth transistor T9 includes a gate connected to the nth emission line, a source connected to the third node N3, and a drain connected to the fifth node N5. The ninth transistor T9 is turned on in response to the gate-on voltage of the nth emission signal EM (n) applied through the nth emission line. When the ninth transistor T9 is turned on, the third node N3 and the fifth node N5 are turned on.

The light emitting device EL includes an anode connected to the fifth node N5 and a cathode to which a low potential power supply voltage VSS is applied. When the ninth transistor T9 is turned on, the driving current generated through the driving transistor DT is applied to the anode of the light emitting device EL, so that the light emitting device EL emits light. For example, the low potential supply voltage VSS may be a voltage of -4V to -2.5V, but is not limited thereto.

Since the voltage applied to the gate of the driving transistor DT controls the turn-on state of the driving transistor DT, the transistor whose source or drain is connected to the gate of the driving transistor DT is turned off It can be configured to include two or more transistors connected in series. In this case, the two or more transistors are controlled by the same control signal. Therefore, the n-th sub-pixel SP according to the second embodiment of the present invention may be formed of a double gate type transistor in which the first transistor T1 and the eighth transistor T8 are formed.

The nth sub-pixel SP according to the second embodiment of the present invention operates in the order of an initialization period, a sampling period, a holding period, and a light emission period. The initialization period is a period for initializing the gate node of the driving transistor DT. The sampling period is a period for sampling the threshold voltage of the driving transistor DT and applying the data voltage Vdata through the data line, This is a period for preventing unnecessary light emission due to signal delay. The light emitting period is a period for causing the light emitting element EL to emit light through the driving current generated based on the data voltage Vdata.

The nth subpixel SP according to the second embodiment of the present invention is characterized by including an initialization period INI and a sampling period SAM for a period during which gate off voltage is applied to the nth emission signal EM As a result, internal circuit based compensation is achieved. The operation characteristics during these periods will be described as follows. The gate-on voltage is applied to the scan signal during one horizontal period (1H), and the gate-off voltage is applied during the three horizontal periods (3H) for the emission signal. An example is shown in which the initialization period INI, the sampling period SAM, and the holding period HLD are each performed during one horizontal period (1H). In the following drawings, the driving of the pixel circuit as described above will be described.

10A is a diagram illustrating driving in a setup period of a subpixel according to the second embodiment of the present invention. 10B is a waveform diagram showing the driving of FIG. 10A.

The nth scan signal Scan (n) and the nth emission signal EM (n) are the gate-on voltage, and the nth scan signal Scan (n) Off voltage. For example, the gate-on voltage may be -8V with a logic low voltage (VL) and the gate-off voltage may be 8V with a logic high voltage (VH), but is not limited thereto.

The sixth transistor T6 and the eighth transistor T8 are turned on by the gate-on voltage applied through the (n-1) th scan line. The high level power supply voltage VDD is applied to the fourth node N4 through the turned on sixth transistor T6 and the initializing voltage Vini is applied to the second node N2 through the turned on eighth transistor T8, The gate of the driving transistor DT is initialized to the initializing voltage Vini. In this case, the initialization voltage (Vini) is equal to or lower than the low potential power supply voltage (VSS). For example, the initialization voltage Vini is a voltage between -3V and -4V, and the data voltage Vdata is a voltage that varies with luminance between 0.3V and 6.3V.

During the initialization period INI, the gate of the driving transistor DT is initialized based on the initializing voltage Vini.

11A is a diagram illustrating driving in a sampling period of a subpixel according to the second embodiment of the present invention. Fig. 11B is a waveform diagram showing the driving of Fig. 11A.

The scan signal Scan (n) is a gate-on voltage in the sampling period SAM and the nth scan signal Scan (n-1) and the nth emission signal EM (n) Off voltage.

The first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on by the gate-on voltage applied through the nth scan line. The reference voltage Vref is applied to the source of the driving transistor DT through the turned on second transistor T2 and the gate and the drain of the driving transistor DT are connected to each other by the first transistor T1 turned on , The driving transistor DT is turned on in the diode connection state. The voltage of the second node N2 connected to the gate of the driving transistor DT rises to the sum of the reference voltage Vref and the threshold voltage Vth of the driving transistor DT. The data voltage Vdata is applied to the fourth node N4 through the turned-on seventh transistor T7. The sum of the reference voltage Vref and the threshold voltage Vth of the driving transistor DT is applied to the first electrode of the capacitor Cst and the data voltage Vdata is applied to the second electrode thereof. ) Is charged with the difference (Vdata- (Vref + Vth)) between the voltage applied to the first electrode and the second applied voltage. Then, the fourth transistor T4 is turned on to initialize the anode of the light emitting element EL to the initializing voltage Vini. For example, the reference voltage Vref may be 4V and the threshold voltage Vth may be -4V, but is not limited thereto.

A gate-on voltage is applied to the nth scan signal Scan (n) during the sampling period SAM to apply a data voltage Vdata to the fourth node N4 to hold one electrode of the capacitor Cst, The reference voltage Vref is applied to the source of the transistor DT and the second node N2 can sample the threshold voltage Vth of the driving transistor DT and sense the reference voltage Vref.

12A is a diagram illustrating driving in a holding period of a subpixel according to the second embodiment of the present invention. 12B is a waveform diagram showing the driving of Fig. 12A.

The nth scan signal Scan (n-1), the nth scan signal Scan (n), and the nth emission signal EM (n) in the holding period HLD are gate- The first to ninth transistors T1 to T9 are turned off.

The voltage of the gate of the driving transistor DT is slightly lowered by the parasitic capacitor of the first transistor T1 as the nth scan signal Scan (n) is switched from the gate-on voltage to the gate-off voltage in the holding period HLD Lt; / RTI > In this case, the driving transistor DT is in the turned off state.

For example, when the nth emission signal EM (n) is switched to the gate-on voltage at the moment when the nth scan signal Scan (n) becomes the gate-off voltage at the gate-on voltage, . This is because the nth scan signal Scan (n) is not ideally switched from a logic low voltage to a logic high voltage as shown in the drawing, but the time when the logic low voltage is switched to a logic high voltage by an RC delay Can be delayed. In this case, unwanted light emission may occur when the nth emission signal EM (n) is switched to the gate-on voltage. Therefore, the subpixel according to the second embodiment of the present invention includes a holding period (HLD), thereby preventing unnecessary light emission due to the delay of the scan signal.

13A is a diagram illustrating driving in a light emission period of a subpixel according to the second embodiment of the present invention. 13B is a waveform diagram showing the driving of Fig. 13A.

In the light emission period EMI, the nth emission signal EM (n) is a gate-on voltage.

The third transistor T3, the fifth transistor T5, and the ninth transistor T9 are turned on by the gate-on voltage applied through the nth emission signal EM (n). Accordingly, the voltage of the second node N2 becomes Vref + Vth + (Vdd-Vdata) due to the coupling of the capacitor Cst by applying the high potential power supply voltage VDD to the second electrode of the capacitor Cst And the high-potential power supply voltage VDD is applied to the source of the driving transistor DT, so that the driving transistor DT is turned on. Then, the ninth transistor T9 is turned on to conduct current flow between the third node N3 and the fifth node N5. Therefore, the driving current generated in the turned-on driving transistor DT is applied to the anode of the light emitting element EL through the ninth transistor T9 to emit the light emitting element. The ninth transistor T9 maintains a turn-off state in a period other than the light emission period (EMI), thereby suppressing light emission that may unnecessarily occur.

The current of the nth subpixel SP according to the second embodiment of the present invention can be expressed by the following equation.

Vdata = K (Vgs - Vth) 2 = K (Vref + Vth + VDD - Vdata) - VDD - Vth}

Vgs is the voltage between the gate and the source of the driving transistor DT, Vth is the threshold voltage of the driving transistor DT, and VDD is the voltage of the high-potential power source (Vdd). In the above equation, Ioled is the current flowing through the light- Vref denotes a reference voltage applied through the reference voltage line VrefL, and Vdata denotes a data voltage applied through the data line DL. For example, the high-potential power supply voltage is 4.6.

As can be seen from the above equation, Ioled is determined by the difference between the reference voltage and the data voltage. According to the formula, the nth subpixel SP according to the second embodiment of the present invention is driven by a reference voltage Vref applied to the source of the driving transistor DT during the sampling period (SAM) It can be seen that the high potential power supply drop can be compensated for by the high potential power supply voltage VDD applied to the gate and the source of the transistor DT.

Therefore, by implementing a driver circuit that can compensate time-varying characteristics in consideration of the voltage drop of the high-potential power supply voltage, it is possible to improve image quality problems such as uneven luminance of the display panel and crosstalk.

The nth sub-pixel SP according to the second embodiment of the present invention includes the eighth transistor T8 so that the gate of the driving transistor DT is initialized so that the luminance of the black screen of the display panel rises .

Among the plurality of transistors constituting the nth subpixel SP according to the second embodiment of the present invention, the second transistor T2 and the third transistor T3 are disposed at one side of the non-display region, Pixels can be commonly used for q subpixels arranged in a pixel line. Alternatively, when the gate driver 130 is disposed on the left and right sides, the second transistor T2 and the third transistor T3 are arranged in the left and right non-display regions, respectively, and q / 2 sub- It can be used for public use. Accordingly, the number of transistors constituting the subpixel can be reduced to efficiently design subpixels, and a high-resolution display device can be realized. In this case, among the plurality of transistors constituting the nth subpixel SP, the remaining transistors except the second transistor T2 and the third transistor T3 are connected to the n-th pixel line A high-definition display device can be realized by disposing the second transistor T2 and the third transistor T3 in the non-display region.

An electroluminescent display device according to an embodiment of the present invention can be described as follows.

In an electroluminescent display according to an embodiment of the present invention, an electroluminescent display includes a display panel including pixel lines. Each of the pixel circuits included in the n-th (n is a natural number) pixel line of the pixel lines includes a driving transistor connected to the second node and connected between the first node and the third node, A first transistor for conducting a current flow between a second node and a third node in response to a scan signal, a second transistor for applying a reference voltage to a first node in response to an n-th scan signal, A fourth transistor for applying an initialization voltage to the fourth node in response to the n-1 scan signal, a third transistor for applying a high voltage to the fourth node in response to the nth emission signal, A sixth transistor for applying a high potential power supply voltage to a fourth node in response to an (n-1) th scan signal, a fifth transistor for applying a data voltage to the fourth node in response to the (n + The seventh trans Stirrer, and the anode is connected to the second node and the capacitor, and a third node, the fourth node being coupled between a light emitting element is connected to the cathode wiring is applied with a low potential power supply voltage. Accordingly, the subpixel to which the reference voltage is applied can provide the light emitting element with a driving current that is not affected by the high-potential power supply voltage, thereby improving the image quality of the electroluminescence display device.

According to another aspect of the present invention, the reference voltage is higher than the low potential power supply voltage and lower than the high potential power supply voltage, the initialization voltage is equal to or lower than the low potential power supply voltage, And the period in which the nth scan signal is the gate-on voltage may overlap each other.

According to another aspect of the present invention, the gate-on voltage for the n-1 scan signal and the scan signal for the n-th scan period may be applied for two horizontal periods, and the gate-off voltage for the n-th emission signal may be applied during the four horizontal periods.

According to another aspect of the present invention, one frame for driving the pixel circuit includes an initialization period in which the gate-on voltage of the (n-1) th scan signal is input to the (n-1) th pixel line, A first holding period in which the gate-on voltage of the n-th scan signal is held in the (n-1) -th pixel line and the gate-on voltage of the n-th scan signal is input to the n-th pixel line, A second holding period in which the gate-on voltage of the (n + 1) -th scan signal is held in the (n + 1) -th pixel line, and the second holding period during which the light- And a light emitting period for emitting light. In the initialization period, the fourth transistor and the sixth transistor are turned on, the second transistor and the fourth transistor are turned on in the first holding period, and in the sampling period, the first transistor, the second transistor, The transistor is turned on, the first transistor and the seventh transistor are turned on in the second holding period, and the third transistor and the fifth transistor are turned on in the light emitting period.

According to another feature of the present disclosure, the first transistor may be a double gate type transistor.

In an electroluminescent display according to an embodiment of the present invention, an electroluminescent display includes a display panel including pixel lines. Each of the pixel circuits included in the n-th (n is a natural number) pixel line of the pixel lines includes a driving transistor having a gate connected to the second node and connected between the first node and the third node, A first transistor for conducting a current flow between the second node and the third node in response to the scan signal, a second transistor for applying a reference voltage to the first node in response to an n-th scan signal, A fourth transistor for applying an initialization voltage to a fifth node in response to an n-th scan signal, a third transistor for applying a high-potential power supply voltage to the fourth node in response to the n-th emission signal, A sixth transistor for applying a high voltage to the fourth node in response to the (n-1) th scan signal, a seventh transistor for applying a data voltage to the fourth node in response to the n th scan signal, An nth transistor for supplying an initialization voltage to the second node in response to the (n-1) th scan signal, a ninth transistor for conducting a current flow between the third node and the fifth node in response to the nth emission signal, A capacitor connected between the second node and the fourth node, and a light emitting element having an anode connected to the fifth node and a cathode connected to a wiring to which a low potential power voltage is applied. Accordingly, the subpixel to which the reference voltage is applied can provide the light emitting element with a driving current that is not affected by the high-potential power supply voltage, thereby improving the image quality of the electroluminescence display device.

According to another aspect of the present invention, one frame for driving the pixel circuit includes a reset period during which the gate-on voltage of the (n-1) th scan signal is input to the (n-1) th pixel line, a holding period during which the gate-off voltage of the (n-1) th scan signal and the nth scan signal is input to the n-th pixel line, and a gate- And a light emission period that is input to the light emission period. In the initialization period, the sixth transistor and the eighth transistor are turned on, and the first transistor, the second transistor, the fourth transistor, and the seventh transistor are turned on in the sampling period, The ninth transistor is turned off, and the third transistor, the fifth transistor, and the ninth transistor may be turned on in the light emitting period.

According to another feature of the present disclosure, in the initialization period, the sampling period, and the holding period, the nth emission signal may be a gate-off voltage.

According to another aspect of the present invention, the gate-on voltage may be applied to the (n-1) th scan signal and the (n) scan signal during one horizontal period, and the gate-off voltage may be applied to the nth emission signal during three horizontal periods.

According to another feature of the present disclosure, the first transistor and the eighth transistor may be double gate type transistors.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

GL1 to GLp: Gate lines
DL1 to DLq: Data lines
100: display device
110:
120:
130: Gate driver
140:
150: Display panel
180: Power supply

Claims (10)

And a display panel including pixel lines,
Each pixel circuit included in the n-th (n is a natural number) pixel line of the pixel lines,
A driving transistor having a gate connected to the second node and connected between the first node and the third node;
A first transistor for conducting a current flow between the second node and the third node in response to an (n + 1) th scan signal;
A second transistor for applying a reference voltage to the first node in response to an n-th scan signal;
A third transistor for applying a high potential power supply voltage to the first node in response to the nth emission signal;
A fourth transistor for applying an initialization voltage to a fourth node in response to the (n-1) th scan signal;
A fifth transistor for applying the high potential power supply voltage to the fourth node in response to the nth emission signal;
A sixth transistor for applying the high potential power supply voltage to a fourth node in response to the (n-1) th scan signal;
A seventh transistor for applying a data voltage to the fourth node in response to the (n + 1) th scan signal;
A capacitor coupled between the second node and the fourth node; And
And a light emitting element having a cathode connected to a wiring to which an anode is connected to the third node and a low potential power supply voltage is applied. The method according to claim 1,
Wherein the reference voltage is higher than the low potential power supply voltage and lower than the high potential power supply voltage,
The initialization voltage is equal to or lower than the low potential power supply voltage,
Wherein the nth scan signal is a gate-on voltage and the nth scan signal is a gate-on voltage. 3. The method of claim 2,
Wherein the gate-on voltage is applied to the (n-1) th scan signal and the (n) th scan signal during the 2 horizontal periods, and the gate-off voltage is applied to the nth emission signal during the 4 horizontal periods. The method according to claim 1,
1 frame for driving the pixel circuit is a reset period in which the gate-on voltage of the (n-1) th scan signal is input to the (n-1) th pixel line, the gate- On voltage of the n-th scan line is held in the n-th pixel line and the gate-on voltage of the n-th scan line is held in the n-th pixel line, A second holding period in which the gate-on voltage of the scan signal is input to the (n + 1) -th pixel line, the gate-on voltage of the (n + And a light emission period in which light is emitted,
The fourth transistor and the sixth transistor are turned on in the initialization period,
The second transistor and the fourth transistor are turned on in the first holding period,
The first transistor, the second transistor, and the seventh transistor are turned on in the sampling period,
The first transistor and the seventh transistor are turned on in the second holding period,
And the third transistor and the fifth transistor are turned on in the light emission period. The method according to claim 1,
Wherein the first transistor is a double gate type transistor. And a display panel including pixel lines,
Each pixel circuit included in the n-th (n is a natural number) pixel line of the pixel lines,
A driving transistor having a gate connected to the second node and connected between the first node and the third node;
A first transistor for conducting a current flow between the second node and the third node in response to an n-th scan signal;
A second transistor for applying a reference voltage to the first node in response to the n-th scan signal;
A third transistor for applying a high potential power supply voltage to the first node in response to the nth emission signal;
A fourth transistor for applying an initialization voltage to a fifth node in response to the nth scan signal;
A fifth transistor for applying the high potential power supply voltage to a fourth node in response to the nth emission signal;
A sixth transistor for applying the high potential power supply voltage to a fourth node in response to an (n-1) th scan signal;
A seventh transistor for applying a data voltage to the fourth node in response to the nth scan signal;
An eighth transistor for supplying an initialization voltage to the second node in response to the (n-1) th scan signal;
A ninth transistor for conducting a current flow between the third node and the fifth node in response to the nth emission signal;
A capacitor coupled between the second node and the fourth node; And
And a light emitting element having a cathode connected to a wiring to which the anode is connected to the fifth node and a low potential power supply voltage is applied. The method according to claim 6,
Wherein the first period for driving the pixel circuit is an initialization period in which the gate-on voltage of the (n-1) th scan signal is input to the (n-1) th pixel line, A holding period during which the gate-off voltage of the (n-1) th scan signal and the nth scan signal is input to the n-th pixel line, and a gate-on voltage of the n- The light emitting period including the light emitting period,
The sixth transistor and the eighth transistor are turned on in the initialization period,
The first transistor, the second transistor, the fourth transistor, and the seventh transistor are turned on in the sampling period,
The first transistor to the ninth transistor are turned off in the holding period,
And the third transistor, the fifth transistor, and the ninth transistor are turned on in the light emission period. 8. The method of claim 7,
Wherein the nth emission signal in the initialization period, the sampling period, and the holding period is a gate-off voltage. 9. The method of claim 8,
Wherein the gate-on voltage is applied to the (n-1) th scan signal and the (n) th scan signal during one horizontal period, and the gate-off voltage is applied to the n th emission signal during three horizontal periods. The method according to claim 6,
Wherein the first transistor and the eighth transistor are double gate transistors.

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