KR20230015037A - Display panel compensation circuit and display device including same - Google Patents

Abstract

The present invention relates to a display panel and a display device including the same, which can reduce the number of transistors in a compensation circuit (CC) in a pixel to have a large area, high resolution, narrow bezel, and low power performance. According to one embodiment of the present invention, the display panel comprises a first to a fourth switching element (T1-T4), a sixth to an eighth switching element (T6-T8), and a storage capacitor (Cst) for a compensation circuit (CC) compensating for a threshold voltage change of a driving element (DT) adjusting a current flowing through a light emitting element. Therefore, the present invention has the effect of securing a layout region by removing a switching element initializing the storage capacitor (Cst) in the compensation circuit in a pixel to reduce the number of switching elements.

Description

Display panel and display device including same {Display panel compensation circuit and display device including same}

The present invention relates to a display panel having a large area, high resolution, narrow bezel, and low power consumption, and a display device including the same.

An organic light emitting diode (OLED) display device, which is one of flat panel displays (FPDs), has characteristics of high luminance and low operating voltage.

Since this OLED display device is a self-luminous type that emits light by itself, the contrast ratio is large, it is possible to implement an ultra-thin display, and the response time is about several microseconds, so it is easy to implement moving pictures, and the viewing angle is not limited. It is stable even at low temperature, and it is easy to manufacture and design a driving circuit because it is driven with a low voltage of 5 to 15V DC.

In addition, since the manufacturing process of the OLED display device can be said to be all of deposition and encapsulation, the manufacturing process is very simple.

A plurality of thin film transistors such as a switching thin film transistor, a driving thin film transistor, and a sensing thin film transistor are formed in each pixel area of the OLED display device.

However, in the OLED display device, the number of thin film transistors in each sub-pixel may be greatly increased to compensate for driving power VDD and threshold power Vth. In the case of a display panel having an 8T1C structure, it can be driven in a 2-scan 1EM method in which an emission operation is performed after an initial operation for one horizontal (H) period, a sampling operation for one horizontal (H) period, and A thin film transistor for initializing the storage capacitor Cst may be further added.

Therefore, with the above-described structure, it is difficult to secure a layout area for design to apply high-resolution, narrow bezel gate driving circuit (AAGIP) in the display area for high-end IT OLED models, and MTO application. A problem exists.

Accordingly, the inventors of the present specification invented a display panel capable of securing a layout area for design by reducing the number of transistors in order to solve the above-described problem.

In addition, the inventors of the present specification invented a display device capable of compensating for a drop in driving power (VDD IR Drop) by changing the driving timing used in the 2Scan 1EM method as well as reducing the number of transistors in the OLED display device. .

The above objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned above can be understood by the following description and will be more clearly understood by the examples of the present invention. will be. It will also be readily apparent that the objects and advantages of the present invention may be realized by means of the instrumentalities and combinations indicated in the claims.

A display panel according to an embodiment of the present invention may be provided. The display panel includes first to fourth switching elements T1 to T4 and sixth to fourth switching elements T1 to T4 for a compensation circuit CC that compensates for a threshold voltage change of a driving element DT that controls a current flowing through a light emitting element. It consists of 8 switching elements T6 to T8 and a storage capacitor Cst, and drives the data power supply Vdata through the second switching element T2 and the driving power supply VDD through the third switching element T3. device, the reference power Vref through the eighth switching element T8 may be applied to the storage capacitor, and the initialization power Vini may be applied to the light emitting element through the sixth switching element T6.

In addition, a display device according to an embodiment of the present invention may be provided. The display device includes a display panel having the above structure, a scan driver for applying a scan signal to the display panel, a data driver for applying data signals, a power supply for providing various types of power, and a timing controller for controlling the scan driver and the data driver. can include

In addition, in the display panel according to an exemplary embodiment of the present invention, a plurality of scan lines SL1 to SLn disposed in each row and a plurality of data lines DL1 to DLn disposed in each column intersect, and sub-pixels are intersected at respective intersections. a display area in which they are arranged; at least one or more GIP units arranged in at least two or more columns; a light emitting element disposed in each of the sub-pixels; and a compensation circuit (CC) electrically connected to the light emitting element and compensating for a threshold voltage change of a driving element (DT) controlling a current flowing through the light emitting element, wherein the compensation circuit comprises first to fourth switching elements. (T1 to T4), sixth to eighth switching elements (T6 to T8), and a storage capacitor (Cst), and a data power supply (Vdata) through the second switching element (T2) and a third switching element (T3). ) is applied to the drive element, the reference power Vref is applied to the storage capacitor through the eighth switching element T8, and the initialization power supply Vini is applied through the sixth switching element T6. may be applied to the light emitting device.

According to an embodiment of the present invention, the number of switching elements is reduced by removing the switching element for initializing the storage capacitor (Cst) in the compensation circuit in each sub-pixel of the display panel having the 8T1C structure, thereby reducing the layout of the display panel. It has the effect of securing an area.

In addition, according to an embodiment of the present invention, by changing the driving timing used in the 2Scan 1EM scheme, a drop in driving power (VDD IR Drop) can be compensated for, and AAGIP can be easily applied.

In addition, according to an embodiment of the present invention, by deleting a floating section of the storage capacitor Cst, defects caused by shaking of the reference voltage can be prevented.

In addition, according to an embodiment of the present invention, the n-1th light emission from the nth light emission control signal EM(n) with respect to the light emission control signal EM applied to the third and seventh switching elements T3 and T7. Initial timing can be secured by changing to the control signal EM(n-1).

In addition, according to an embodiment of the present invention, in the 2Scan 1EM method, a sampling time of 8H or more can be secured without an increase in signal wiring.

In addition, according to an embodiment of the present invention, an 8T1C-based MTO can be applied and a high-resolution AAGIP display device can be implemented, and an oxide transistor (Oxide TR) can be used for the first switching element (T1). can

In addition, according to an embodiment of the present invention, a display panel having a large area, high resolution, narrow bezel, and low power consumption and a display device including the same may be provided.

Effects of the present specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

In addition to the effects described above, specific effects of the present invention will be described together while explaining specific details for carrying out the present invention.

1 is a configuration diagram schematically illustrating a configuration of a display device according to an exemplary embodiment of the present invention.
2 is a diagram illustrating a compensation circuit of a pixel PX according to an embodiment of the present invention.
FIG. 3 is a diagram showing timing of control signals driving the compensation circuit of FIG. 2 .
4 is a circuit diagram illustrating an initialization period operation of a compensation circuit in a display panel according to an exemplary embodiment of the present invention.
5 is a circuit diagram illustrating a sampling period operation of a compensation circuit in a display panel according to an exemplary embodiment of the present invention.
6 is a circuit diagram illustrating an operation of a light emitting period of a compensation circuit in a display panel according to an exemplary embodiment of the present invention.
7 and 8 are signal waveform diagrams illustrating signal input and output during an initialization period, a sampling period, and an emission period in a compensation circuit according to an embodiment of the present invention.
9 is a diagram illustrating a pixel compensation circuit for using MTO in a display panel according to another embodiment of the present invention.
FIG. 10 is a diagram illustrating timing of control signals for driving the pixel compensation circuit of FIG. 9 .
11 is a diagram showing the configuration of a display area of an AAGIP display panel according to another embodiment of the present invention.
FIG. 12 is a configuration diagram illustrating a display area and a bezel area of the display panel of FIG. 11 .
13 is a diagram illustrating an example in which a display panel according to another embodiment of the present invention further secures a bezel area by an AAGIP method.
14 is a diagram showing a scan circuit diagram for scan driving of a GIP unit according to another embodiment of the present invention.
15 is a diagram showing an example of arranging transistors and wires in an AAGIP according to another embodiment of the present invention.

For the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention can be implemented in various forms, and It should not be construed as limited to the described embodiments.

Since the present invention can have various changes and various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific form disclosed, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

The above objects, features and advantages will be described later in detail with reference to the accompanying drawings, and accordingly, those skilled in the art to which the present invention belongs will be able to easily implement the technical spirit of the present invention.

In describing the present invention, if it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

In addition, when a component is described as "connected", "coupled" or "connected" to another component, the components may be directly connected or connected to each other, but other components may be "interposed" between each component. ", or each component may be "connected", "coupled" or "connected" through other components. On the other hand, when an element is referred to as being “directly connected” or “directly connected” to another element, it should be understood that there are no intervening elements. Other expressions describing the relationship between elements, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", etc., should be interpreted similarly.

Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that the disclosed feature, number, step, operation, component, part, or combination thereof exists, but that one or more other features or numbers, It should be understood that the presence or addition of steps, operations, components, parts, or combinations thereof is not precluded.

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used in a meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless explicitly specifically defined.

Meanwhile, when a certain embodiment can be implemented differently, functions or operations specified in a specific block may occur in a different order from the order specified in the flowchart. For example, two successive blocks may actually be performed substantially concurrently, or the blocks may be performed backwards depending on the function or operation involved.

When an element or layer is referred to as “on” or “on” another element or layer, it includes both cases where another element or layer is intervening as well as directly on another element or layer. do. On the other hand, when an element is referred to as “directly on” or “directly on”, it indicates that no other element or layer is intervening.

The spatially relative terms "below, beneath", "lower", "above", "upper", etc., refer to one element or component as shown in the drawing. It can be used to easily describe the correlation between and other elements or components. Spatially relative terms should be understood as encompassing different orientations of elements in use or operation in addition to the orientations shown in the figures. For example, when flipping elements shown in the figures, elements described as “below” or “beneath” other elements may be placed “above” the other elements. Thus, the exemplary term “below” may include directions of both below and above.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present invention. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term.

Hereinafter, an organic light emitting diode display and a manufacturing method thereof according to an exemplary embodiment of the present invention will be described.

1 is a configuration diagram schematically illustrating a configuration of a display device according to an exemplary embodiment of the present invention, FIG. 2 is a diagram illustrating a compensation circuit of a pixel PX according to an exemplary embodiment of the present invention, and FIG. It is a diagram showing the timing of the control signal that drives the compensation circuit.

1 to 3 , the display device 100 according to an embodiment of the present invention includes a luminance controller 10, a display panel 20, a scan driver 30, a data driver 40, a light emitting controller ( 50), a power supply unit 60 and a timing control unit 70, and the like.

The luminance controller 10 provides one gamma set selected from among a plurality of gamma sets each including a plurality of gamma data to the data driver 40, and transmits dimming data corresponding to the selected gamma set to the light emitting controller 50. can be provided to

The display panel 20 may include an active area (AA) and a non-active area (NA).

In the display area AA, a plurality of scan lines (SL1 to SLn) disposed in each row and a plurality of data lines (DL1 to DLn) disposed in each column intersect, and each pixel is formed at each intersection. ; PX) can be defined. Each pixel PX may include at least one sub-pixel (R, G, B, etc.). Accordingly, sub-pixels may be disposed at each intersection.

For example, the display panel 20 is formed by crossing a plurality of scan lines SL1 to SLn and a plurality of data lines DL1 to DLn on an organic or plastic substrate, and the scan lines SL and the data lines Sub-pixels R, G, and B corresponding to red, green, and blue, respectively, may be defined at points where (DL) intersects. One pixel PX including one or more sub-pixels (R, G, B, W, etc.) may be referred to as a 'unit pixel'.

In this case, each of the sub-pixels may include an organic light emitting diode (OLED). A plurality of scan lines SL1 to SLn may be arranged in each row of a plurality of sub-pixels, and a plurality of data lines DL1 to DLn may be arranged in each column of a plurality of sub-pixels. Accordingly, in the plurality of sub-pixels, the light emitting diodes OLED may be arranged in rows and columns.

When the display panel 20 has, for example, a resolution of 2,160 3,840, 2,160 scan lines (SL) and 3,840 data lines (DL) may be provided, and these scan lines (SL) and data lines ( Sub-pixels G, G, and B may be disposed at points where DLs intersect.

Each of the wires SL and DL of the display panel 20 may be connected to the scan driver 30 and the data driver 40 formed outside the display panel 20 . Further, power voltage supply lines VDD, Vini, and VSS formed in a direction parallel to the data line DL may be further formed in the display panel 20 to be connected to the respective pixels PX.

Also, each pixel PX may include at least one organic light emitting diode (OLED), a storage capacitor Cst, switching thin film transistors T1, T2, T6, and T8, and a driving thin film transistor DT. Here, the organic light emitting diode (OLED) may include a first electrode (hole injection electrode), an organic compound layer, and a second electrode (electron injection electrode).

The organic compound layer may further include various organic layers for efficiently transferring hole or electron carriers to the light emitting layer in addition to the light emitting layer in which light is actually emitted. These organic layers may be a hole injection layer and a hole transport layer positioned between the first electrode and the light emitting layer, and an electron injection layer and electron transport layer positioned between the second electrode and the light emitting layer.

In addition, the switching and driving thin film transistors T1, T2, T6, T8, and TD are connected to the scan line SL, the control signal supply line EL, and the data line DL, and are input to the scan line SL. The switching thin film transistors (T1, T2, T6, T8) are conducted according to the gate voltage, and at the same time, the data voltage input to the data line (DL) is transmitted to the driving thin film transistor (TD). The storage capacitor Cst is connected between the thin film transistor and the power supply line, and is charged with the data voltage transmitted from the thin film transistor and maintained for one frame.

Also, the driving thin film transistor TD is connected to the power supply line and the storage capacitor Cst, and supplies a drain current corresponding to the gate-source voltage to the organic light emitting diode OLED. Accordingly, the organic light emitting diode (OLED) emits light by the drain current. Here, the driving thin film transistor (TD) includes a gate electrode, a source electrode, and a drain electrode, and an anode electrode of the organic light emitting diode (OLED) is connected to one electrode of the driving thin film transistor (TD).

The scan driver 30 may apply scan signals to the plurality of scan lines SL. For example, the scan driver 30 may sequentially apply a gate voltage to each pixel PX in units of horizontal lines in response to the gate control signal GCS. The scan driver 30 may be implemented as a shift register having a plurality of stages for sequentially outputting high-level gate voltages for each horizontal (H) period.

The data driver 40 may apply data signals to the plurality of data lines DL. For example, the data driver 40 receives an image signal of a digital waveform applied from the timing controller 70 and converts it into a data voltage in the form of an analog voltage having a grayscale value that can be processed by the pixel PX. A data voltage may be supplied to each pixel PX through the data line DL in response to the input data control signal DCS. Here, the data driver 40 may convert an image signal into a data voltage using a plurality of reference voltages supplied from a reference voltage supply unit (not shown).

In addition, the data driver 40 sets the low potential voltage VSS and the initialization voltage Vini in the low-speed driving mode to different values from the low potential voltage VSS and the initialization voltage Vini in the high-speed driving mode. It can be applied to the display panel 20 . For example, the data driver 40 may provide the low potential voltage VSS and the initialization voltage Vini, which have the same values, to the display panel 20 in the 60Hz driving mode. However, in the 90Hz driving mode, the data driver 40 displays a low potential voltage (VSS) and an initialization voltage (Vini) having different values from the low potential voltage (VSS) and the initialization voltage (Vini) in the 60Hz driving mode. It can be provided to the panel 20.

In addition, when the data driver 40 receives the selected gamma set from the luminance controller 10, the low potential voltage VSS corresponding to the selected gamma set based on the look-up table and The initialization voltage Vini may be provided to the display panel 20 .

The emission controller 50 may apply the emission control signal EM to a plurality of pixels.

The power supply unit 60 may provide a high potential voltage VDD, a low potential voltage VSS, a reference voltage Vref, and an initialization voltage Vini to each pixel.

The timing controller 70 may control the scan driver 30 and the data driver 40 . For example, the timing control unit 70 receives timing signals such as a video signal, a clock signal, and vertical and horizontal synchronization signals applied from the outside to generate a gate control signal (GCS) and a data control signal (DCS), It can be provided to the scan driving unit 30 and the data driving unit 40 .

Here, the horizontal synchronization signal represents the time taken to display one line of the screen, and the vertical synchronization signal represents the time taken to display the screen of one frame. In addition, the clock signal is a signal serving as a reference for generating control signals of the gate and each driver.

Meanwhile, the timing controller 70 is connected to an external system through a predetermined interface and can receive video-related signals and timing signals output therefrom at high speed without noise. As such an interface, a low voltage differential signal (LVDS) method or a transistor-transistor logic (TTL) interface method may be used.

In addition, the timing controller 70 according to an embodiment of the present specification may embed a microchip (not shown) equipped with a compensation model for generating a compensation value of a data voltage according to a current deviation of each pixel. A voltage compensation value may be applied to an image signal provided to the driving unit 40 so that the voltage compensation value may be reflected in a data voltage supplied by the data driving unit 40 thereafter.

The present invention may implement a bottom-emission type organic light emitting display device, but is not limited thereto, and a top-emission or dual-emission type organic light emitting display device as needed. may also be applied.

Referring to FIG. 2 , the display panel 20 according to an exemplary embodiment of the present invention may include a light emitting element OLED, a driving element DT, a storage capacitor Cst, and a compensation circuit.

The light emitting element OLED is, for example, an organic light emitting diode (OLED), and may include an anode electrode of the first electrode and a cathode electrode of the second electrode.

The driving element DT is, for example, a driving thin film transistor DT, is electrically connected to the light emitting element, and controls current flowing through the light emitting element.

One electrode of the storage capacitor Cst may be electrically connected to the driving element DT.

The compensation circuit may compensate for a change in the threshold voltage of the driving element DT. To this end, the compensation circuit may include first to fourth switching elements T1 to T4 and sixth to eighth switching elements T6 to T8.

The first to fourth switching elements T1 to T4, the sixth to eighth switching elements T6 to T8, and the driving element DT are TFTs having an N-type or P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. can be implemented Although the P-type TFT is exemplified in the following embodiments, the present invention is not limited thereto. A TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit from the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an N-type MOSFET (NMOS), since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in an N-type MOSFET, the direction of current flows from the drain to the source. In the case of a P-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. Since holes flow from the source to the drain side in the P-type TFT, current flows from the source to the drain side. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be changed depending on the applied voltage. In the following embodiments, the transistors constituting the GIP circuit and the pixel circuit are exemplified as P-type TFTs, but are not limited thereto. Therefore, the invention should not be limited by the sources and drains of TFTs in the following description.

In the compensation circuit, the first switching element T1 is connected between the gate electrode and the second electrode of the driving element DT, and the data power supply Vdata is connected to the first electrode of the driving element through the second switching element T2. The driving power VDD is applied to the driving element through the third switching element T3, the driving power VDD is applied to the storage capacitor Cst through the seventh switching element T7, and the reference power Vref may be applied to the storage capacitor Cst through the eighth switching element T8, and initialization power supply Vini may be applied to the light emitting element OLED through the sixth switching element T6.

In this case, each of the first to fourth switching elements T1 to T4 and the sixth to eighth switching elements T6 to T8 may be a thin film transistor.

In the first switching element T1, one of the first electrode and the second electrode is connected to the gate electrode of the driving element DT, the other is connected to the second electrode N3 of the driving element, and the gate electrode is It may be connected to the nth second scan line S2(n). Here, the first electrode may be a source electrode and the second electrode may be a drain electrode, but is not limited thereto and may be interchanged.

In the second switching element T2, one of the first electrode and the second electrode is connected to the data power supply Vdata, the other is connected to the first electrode N1 of the driving element, and the gate electrode has an n-th electrode. It can be connected to 1 scan wire (S1(n)). Here, the first electrode may be a source electrode and the second electrode may be a drain electrode, but is not limited thereto and may be interchanged.

In the third switching element T3, one of the first electrode and the second electrode is connected to the first electrode N1 of the driving element, the other is connected to the driving power line VDD, and the gate electrode is n- It may be connected to the first emission control line EM(n-1). Here, the first electrode may be a source electrode and the second electrode may be a drain electrode, but is not limited thereto and may be interchanged.

In the fourth switching element T4, one of the first electrode and the second electrode is connected to the first electrode N4 of the light emitting element OLED, and the other is connected to the second electrode N3 of the driving element DT. , and the gate electrode may be connected to the n-th emission control line EM(n). Here, the first electrode may be a source electrode and the second electrode may be a drain electrode, but is not limited thereto and may be interchanged.

In the sixth switching element T6, one of the first electrode and the second electrode is connected to the initialization power line Vini, the other is connected to the first electrode N4 of the light emitting element, and the gate electrode has an nth electrode. It may be connected to the second scan line S2(n). Here, the first electrode may be a source electrode and the second electrode may be a drain electrode, but is not limited thereto and may be interchanged.

In the seventh switching element T7, one of the first electrode and the second electrode is connected to the driving power line VDD, the other is connected to the first electrode of the storage capacitor Cst, and the gate electrode has n- It may be connected to the first emission control line EM(n-1). Here, the first electrode may be a source electrode and the second electrode may be a drain electrode, but is not limited thereto and may be interchanged.

In the eighth switching element T8, one of the first electrode and the second electrode is connected to the reference power line Vref, the other is connected to the first electrode of the storage capacitor, and the gate electrode is connected to the n-th second scan. It may be connected to the wire S2(n). Here, the first electrode may be a source electrode and the second electrode may be a drain electrode, but is not limited thereto and may be interchanged.

On the other hand, in the compensation circuit, for the first to fourth switching elements T1 to T4, the first switching element T1 is connected between the gate electrode and the second electrode of the driving element, and the first electrode and The second switching element T2 is connected between the data power line Vdata, the third switching element T3 is connected between the first electrode of the driving element and the driving power line VDD, and the first switching element T3 of the light emitting element A fourth switching element T4 may be connected between the electrode and the second electrode of the driving element.

In addition, in the compensation circuit, with respect to the sixth to eighth switching elements T6 to T8, the sixth switching element T6 is connected between the first electrode of the light emitting element and the initialization power line Vini, and the storage capacitor ( A seventh switching element T7 may be connected between Cst and the driving power line VDD, and an eighth switching element T8 may be connected between the storage capacitor Cst and the reference power line Vref.

The first switching element T1 is switched by the n-th second scan signal S2(n), the second switching element T2 is switched by the n-th first scan signal S1(n), The third switching element T3 is switched by the n-1th light emission control signal EM(n-1), and the fourth switching element T4 is switched by the nth light emission control signal EM(n). The sixth switching element T6 is switched by the n-th second scan signal S2(n), and the seventh switching element T7 generates the n-1th light emission control signal EM(n-1). , and the eighth switching element T8 can be switched by the n-th second scan signal S2(n).

Referring to FIG. 3 , the display panel 20 according to an exemplary embodiment of the present invention may be driven by dividing into an initialization period (Initial), a sampling period (Sampling), and an emission period (Emission).

Here, the sampling period (Sampling) may be referred to as a sensing and initialization period (Sensing & Initial), and may be referred to as a 'programming period' in some cases.

Also, the display panel 20 may have a driving timing of a holding period between the sampling period (Sampling) and the emission period (Emission).

In FIG. 3 , the initialization period (Initial) may be set equal to or shorter than one horizontal period (1H).

In FIG. 3 , the n-th first scan signal S1(n) may be a high signal in an initialization period, a low signal in a sampling period for 1H, and a high signal in an emission period.

The nth second scan signal S2(n) may be a low signal during an initialization period, a low signal during a 2H sampling period, and a high signal during an emission period.

The n−1 th light emission control signal EM(n−1) may be a high signal during the initialization period and the sampling period, and may be a high signal during the light emission period and the remaining periods.

The n-th emission control signal EM(n) may be a high signal during a part of the sampling period and a light emission period, and may be a low signal during the remaining period.

In FIG. 3 , the data voltage signal Vdata applied to the source electrode DRS of the driving element DT may be a low signal during the sampling period 1H and a high signal during the remaining period.

In FIG. 3 , the data voltage signal applied to the gate electrode DRG of the driving element DT is a low signal during the initialization period 1H, rises from a low signal to a (Vdata-Vth) signal during the sampling period, and It could be a high signal.

In FIG. 3 , the reference voltage signal Vref applied to the contact node STR of the storage capacitor Cst may be a low signal during an initialization period and a sampling period, and may be a high signal during an emission period.

4 is a circuit diagram illustrating an operation of a compensation circuit in an initialization period in a display panel according to an exemplary embodiment of the present invention, and FIGS. It is a signal waveform diagram showing input and output.

2 to 4, 7 and 8 , in the display panel 20 according to the exemplary embodiment of the present invention, in the initialization period Initial, the second scan signal SCAN2(N)/S2(n) ) and the emission signal EM(n) are input as gate low voltage VGL, which is a turn-on level, and the first scan signal SCAN1(N)/S1(n) is input as a gate high voltage, which is a turn-off level. (VGH).

During the initialization period (Initial), the first, sixth and eighth switching elements T1, T6 and T8 turn-on in response to the turn-on level of the second scan signal SCAN2(N)/S2(n). Turned on, the fourth switching element T4 is turned on in response to the nth light emission control signal EM(n) of the turn-on level ON.

Accordingly, the reference voltage Vref is applied to the connection node STR of the storage capacitor Cst through the eighth switching element T8, and the initialization voltage Vini is applied to the sixth switching element T6 and the fourth switching element. (T4), and is applied to the node N4, node N3, and node N2 through the first switching element T1, respectively.

As a result, all of the nodes STR, N2, N3, and N4 are initialized to the reference voltage Vref. This initialization operation is to increase the reliability of internal compensation by resetting the potentials of the nodes STR, N2, N3, and N4 to a constant value prior to the sampling (programming) operation.

The reference voltage Vref is a voltage lower than the high potential power supply voltage VDD, and is set near the low potential power supply voltage VSS to be lower than the operating point voltage Voled of the light emitting diode OLED. Accordingly, the light emitting diode OLED does not emit light during the initialization period Initial.

5 is a circuit diagram illustrating a sampling period operation of a compensation circuit in a display panel according to an exemplary embodiment of the present invention.

Referring to FIGS. 2, 3, 5, 7, and 8 , in the display panel 20 according to the exemplary embodiment of the present invention, during a sampling period, a first scan signal SCAN1(N)/S1 (n)) and the second scan signal SCAN2(N)/S2(n) are input as gate low voltage VGL, which is a turn-on level, and the emission signal EM(N) is a turn-off level. It is input as the gate high voltage (VGH).

Here, the initialization period (Initial) is made within one horizontal period (1H), but the sampling (Smapping) period may be made up of two horizontal periods (2H) or more. That is, the display panel 20 according to an exemplary embodiment of the present invention may additionally secure a sampling period twice or more than the initialization period.

The sensing and initialization period (Sensing & Initial) may also be set equal to or shorter than 1 horizontal period (1H). At this time, the first scan signal SCAN1 may be set equal to or shorter than 2 horizontal periods. In addition, in FIG. 13, the holding period th may be set equal to or shorter than one horizontal period.

During the sampling period, the second scan signal SCAN2(N)/S2(n) maintains the turn-on level and the first scan signal SCAN1(N)/S1(n) also maintains the turn-on level. In turn, the second and driving elements T2 and DT are in a turn-on state, and the light emitting signal EM(n) is inverted to a turn-off level, so that the fourth switching element T4 is turned off.

Since the voltage (VDD-Vref=Vdata+Vth), which is the gate-source voltage Vgs of the driving element DT set in the initialization period Initial, is greater than the threshold voltage Vth of the driving element DT, the sampling ( During the smapping period, a driving current flows through the driving element DT.

At this time, the data voltage Vdata is applied to the driving element DT via the second switching element T2 by the turn-on of the second switching element T2, and the turn-on of the first switching element T1 When turned on, the gate electrode and the drain electrode of the driving transistor DT are connected to each other so that the driving element DT is diode-connected, and when the fourth switching element T4 is turned off, the driving current is converted to a diode. It flows along the runoff path. The threshold voltage Vth of the driving element DT is sampled by the driving current flowing along the diode connection path and stored in nodes N2 and N3.

During the sampling period, the reference voltage Vref is continuously applied to the node STR by turning on the eighth switching element T8, and the OLED does not emit light.

During the sampling period, the potential of the node STR is set to the reference voltage Vref, the potentials of the nodes N2 and N3 are set to Vdata+Vth, and the potential of the node N4 is set to the initialization voltage Vini.

6 is a circuit diagram illustrating an operation of a light emitting period of a compensation circuit in a display panel according to an exemplary embodiment of the present invention.

Referring to FIGS. 2, 3, 6, 7, and 8 , in the display panel 20 according to the exemplary embodiment of the present invention, during the emission period, first and second scan signals SCAN1(N ), SCAN2(N)) is input as the gate high voltage VGH, which is a turn-off level, and the emission control signal EM(N) is input as a gate low voltage VGL, which is a turn-on level.

At this time, during the emission period (Emission), the N-1 th emission control signal EM(N-1) is input as the gate low voltage VGL, which is a turn-on level, and the N th emission control signal EM(N) ) is also input as the gate low voltage (VGL), which is the turn-on level.

Accordingly, the third, seventh, and fourth switching elements T3, T7, and T4 are turned on.

Accordingly, the driving power supply VDD is applied to the gate electrode of the driving element DT via the seventh switching element T7 and the storage capacitor Cst, and the driving element DT via the third switching element T3. ) is applied to the first electrode of

The driving element DT is turned on by the driving voltage VDD applied to the gate electrode. Accordingly, the driving element DT outputs the driving power VDD applied to the first electrode to the fourth switching element T4 through the second electrode.

The fourth switching element T4 applies the driving power VDD received from the driving element DT to the light emitting element OLED so that the light emitting element OLED is driven to emit light.

During the emission period, the potential of the gate electrode of the driving element DT is set to (VDD-Vref)+(Vdata+Vref).

Through this, the gate-source voltage (Vgs) of the driving element (DT) capable of compensating for a change in the threshold voltage (Vth) of the driving element (DT) is set, and the driving element (DT) is set as shown in Equation 1 below. A driving current Ioled corresponding to the gate-source voltage Vgs flows.

The potential of the nodes N3 and N4 rises to the operating point voltage Voled of the light emitting diode OLED by the driving current Ioled, and the light emitting diode OLED is turned on, and as a result, the light emitting diode OLED is driven. Light is emitted by the current (Ioled).

Here, K is a constant value determined by the mobility, channel ratio, parasitic capacitance, etc. of the driving element DT, and Vth is the threshold voltage of the driving element DT.

As can be seen from Equation 1, the driving current Ioled of the light emitting diode OLED is not affected by the high potential voltage power supply VDD as a driving power source as well as the threshold voltage Vth of the driving element DT.

In this specification, when scan signals used for initializing pixels and sensing threshold voltages are supplied to neighboring display lines while overlapping each other for a certain period of time, overlapping scan signals are generated with a small number of clocks and a simple circuit configuration. A gate driving circuit may be presented.

As a result of checking the output signals of the compensation circuit in the display panel 20 according to an embodiment of the present invention, as shown in FIG. I was able to confirm.

9 is a diagram illustrating a pixel compensation circuit for using MTO in a display panel according to another embodiment of the present invention.

As shown in FIG. 9, a pixel compensation circuit for utilizing MTO (Middle Temperature Oxide) according to another embodiment of the present invention has the same structure as the pixel compensation circuit shown in FIG. 2, and includes a first switching element T1. , At least one of the sixth switching element T6 and the eighth switching element T8 may be configured as an oxide thin film transistor (Oxide TFT).

That is, in the pixel compensation circuit for using the MTO according to the present invention, at least one of the first switching element T1, the sixth switching element T6, or the eighth switching element T8 in the pixel compensation circuit of FIG. 2 is oxide. There is a difference in that it is replaced by TFT. The remaining TFTs of the sub-pixel may be LTPS TFTs.

The display panel 20 according to the present invention can be utilized in an MTO method using an oxide TFT to reduce power consumption by lowering the scan rate.

Oxide TFTs have lower electron mobility than low-temperature polycrystalline silicon (LTPS) TFTs, so they should be designed with a wider width than LTPS TFTs.

FIG. 10 is a diagram illustrating timing of control signals for driving the pixel compensation circuit of FIG. 9 .

Referring to FIG. 10 , the driving timing of the control signals for the pixel compensation circuit according to another embodiment of the present invention is that the N-th second scan signal SCAN2(N) is 1 horizontal period (1H) in the initialization period (Initial). ), and is a high signal during 2 horizontal periods (2H) in the sampling period (Sampling).

That is, the drive timing of the control signals for the pixel compensation circuit of FIG. 9 is mostly the same as the drive timing shown in FIG. and a high signal during the sampling period, different from the driving timing shown in FIG. 3 .

Therefore, in the driving timing of the control signals of the pixel compensation circuit shown in FIG. 9, the description of the driving timing of the control signals other than the N-th second scan signal SCAN2(N) is the same as that of FIG. 3 and thus omitted. do.

That is, the Nth first scan signal SCAN1(N) shown in FIG. 9, the N−1th light emission control signal EM(N−1), the nth light emission control signal EM(N), and the driving element The driving timings of the source electrode signal DRS of DT, the gate electrode signal DRG of driving element DT, and the reference voltage signal Vref applied to the contact node STR of storage capacitor Cst are shown in FIG. 3 . It is the same as the driving timing of the control signals shown in .

11 is a configuration diagram of a display area of an AAGIP display panel according to another embodiment of the present invention, and FIG. 12 is a configuration diagram showing a display area and a bezel area of the display panel of FIG. 11 .

In FIGS. 11 and 12 , the unit pixel may be composed of red (R), green (G), blue (B), and white (W) sub-pixels, but is not limited thereto, and red (R), green ( G) and blue (B) sub-pixels.

In the display panel 20 according to the present invention, in the display area AA, a plurality of scan wires SL1 to SL2160 disposed in each row and a plurality of data wires disposed in each column intersect, and sub-pixels 1133 are disposed at each intersection. ) can be placed. A light emitting device OLED may be disposed in each sub-pixel 1133 .

The unit pixel area of the display area AA of the display panel 20 according to the present invention includes at least one sub-pixel unit 1133, at least one GIP unit 1131, and at least one GIP internal connection wiring unit 1132. ) can be distinguished.

One GIP unit 1131 may be disposed in at least two or more columns. For example, each GIP unit 1131 may be disposed every two sub-pixel columns, every three sub-pixel columns, or every four sub-pixel columns. Here, since a plurality of GIP units 1131 are arranged in the display area AA at regular intervals, they may be referred to as AAGIP units 1131.

A unit pixel area may include at least three sub-pixels 1133 , and driving elements DT may be disposed in each of the at least three sub-pixels.

The GIP unit 1131 is distributed in unit pixel areas driven by each gate line in the display area AA, and supplies a scan signal (eg, gate pulse) to the corresponding gate line (Stage; not shown). ) may be included.

The GIP unit 1131 may correspond to a GIP element (transistor or capacitor) constituting a stage. That is, in a unit pixel area composed of red (R), green (G), blue (B), and white (W) sub-pixels, GIP elements (transistors or capacitors) constituting a stage (not shown) are distributed. can be placed. A GIP TFT may be disposed in each GIP unit 1131.

One stage for driving one scan line may be disposed in a distributed manner in a plurality of unit pixel areas driven by the corresponding scan line. Of course, two or more stages for driving one scan line may be distributedly arranged in a plurality of unit pixel areas.

If one stage is distributed and arranged in a plurality of unit pixel areas driven by one scan line, the stage is placed in a plurality of unit pixel areas in the middle of the plurality of unit pixel areas driven by the corresponding scan line. Constituting GIP elements (transistors or capacitors) can be distributedly arranged.

In addition, when two stages for driving one scan wire are disposed in a plurality of unit pixel areas driven by the corresponding scan wire, a plurality of unit pixels driven by the corresponding scan wire are located at both edges of the plurality of unit pixels. GIP elements (transistors or capacitors) constituting each stage may be distributedly arranged in the unit pixel area.

11 and 12 show that the GIP units 1131 are disposed in all unit pixel areas, but are not limited thereto.

As shown in FIG. 12 , the GIP unit 1131 may include a scan GIP unit (AAGIP SCAN) and an emitting GIP unit (AAGIP EM). Therefore, it is possible to arrange (①, ②, ③) scan GIP parts (AAGIP SCAN) at regular intervals in the display area (AA), and then arrange (①, ②, ③) light emitting GIP parts (AAGIP EM) at regular intervals. there is.

For example, a scan GIP unit (AAGIP SCAN) and a light emitting GIP unit (AAGIP EM) are arranged for each unit pixel (Pixel), but a scan GIP unit (AAGIP SCAN) is placed in three unit pixels (①, ②, ③) Then, the light emitting GIP unit (AAGIP EM) may be disposed (①, ②, ③) in the next three unit pixels. Of course, it is not limited to this arrangement.

As shown in FIGS. 11 and 12, by arranging the GIP unit 1131 in the display area AA, the gate driving circuit existing in the non-display area is removed, and thus the non-display area on both sides of the display panel 20 is removed. A wider bezel area of the display area may be secured.

The GIP internal connection wiring unit 1132 is an area where connection wires (clock signal line, Q node, QB node, element-to-element connection line, etc.) connecting GIP elements constituting the stage are disposed.

The sub-pixel unit 1133 may include, for example, a first sub-pixel R, a second sub-pixel G, a third sub-pixel B, and a fourth sub-pixel W. Each sub-pixel may include at least one or more sub-sub-pixels (eg, R1, R2, Rn).

In the sub-pixel unit 1133, a plurality of data lines DL1 to DLm, a plurality of reference voltage lines Vref, and first and second constant voltage lines VDD and VSS are vertically arranged, and a plurality of scan lines ( SL) may be arranged in a horizontal direction.

In addition, the arrangement positions of at least three sub-pixel units 1133, the GIP unit 1131, and the GIP internal connection wiring unit 1132 may be varied.

In this way, since the GIP elements constituting the stages of the gate driving circuit are distributedly arranged in the display area AA and at least one stage is arranged within unit pixels driven by one scan line, the display panel 20 The left and right bezel area can be minimized.

Accordingly, the display panel 20 according to another embodiment of the present invention, as shown in FIG. 13 , may further secure a bezel area on the left and right of the display area AA. 13 is a diagram illustrating an example in which a display panel according to another embodiment of the present invention further secures a bezel area by an AAGIP method. That is, in the display panel 20 according to another exemplary embodiment of the present invention, the AAGIP is arranged in such a manner that the control block CTRL is arranged in one unit pixel and the AAGIP is arranged in the next unit pixel in the display area AA. It can be. For example, the control block CTRL is disposed in the first to third sub-pixels R, G, and B of the first unit pixel, and the first to third sub-pixels R, AAGIP is placed in G and B). In this case, one unit pixel is composed of three (R, G, and B) sub-pixels (Sub-PXL). As scan wiring, EM wiring, and all GIP (Gate In Panel) are placed inside the display area (AA), the effect of removing the gate driving circuit in the existing bezel area is obtained, and accordingly Accordingly, more bezel area can be secured.

14 is a diagram showing a scan circuit diagram for scan driving of a GIP unit according to another embodiment of the present invention.

Referring to FIG. 14, the GIP unit 1131 according to another embodiment of the present invention controls the first switching units T1 and Tbv that control the first node (Q node) and the second node (QB node). It may include a second switching unit (T4) and output units (T6, T7) for outputting the signals of the first and second nodes.

In addition, the GIP unit 1131 may further include a first stabilization unit T3 for stabilizing the first node and second stabilization units T5 and T8 for stabilizing the second node.

The GIP unit 1131 includes a plurality of stages that output scan signals (eg, Gate Pulse), and the k-th stage includes a first switching unit T1 and Tbv, a second switching unit T4, and a second switching unit T4. It may include a first stabilization unit T3, second stabilization units T5 and T8, and output units T6 and T7.

In addition, the scan circuit diagram of the GIP unit 1131 is shown in FIG. 15 including transistors T1 to T8, capacitors CQ and CQB, wires GVST, VGL, and VGH, and clock signal wires GCLK1 and GCLK3. As shown in, it can be placed in the GIP unit 1131. 15 is a diagram showing an example of arranging transistors and wires in an AAGIP according to another embodiment of the present invention. Referring to FIG. 15, the GIP unit 1131 includes a scan GIP unit (AAGIP SCAN) and a light emitting GIP unit (AAGIP EM), and the scan GIP unit (AAGIP SCAN) can be disposed in each of three pixels. there is. The scan GIP unit (AAGIP SCAN) may include a first AAGIP SCAN (①), a second AAGIP SCAN (②), and a third AAGIP SCAN (③). A first transistor T1, a node separation transistor Tbv, a sixth transistor T6, and a Q node capacitor CQ may be disposed in the first AAGIP SCAN ① as elements. In addition, the first AAGIP SCAN (①) includes a gate low voltage line (VGL), a first gate clock signal line (GCLK1), a sixth TR-Q connection line (T6_Q), and a first TR-Q connection line (T1_Q). ) and the like can be placed. In addition, a gate low voltage line (VGL) and a gate high voltage line (VGH) may be disposed in the second AAGIP SCAN (②). In addition, the third AAGIP SCAN (③) includes a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a seventh transistor (T7), an eighth transistor (T8) and a QB node capacitor as elements. (CQB) may be placed. In addition, a gate high voltage wire (VGH) may be disposed as a wire in the third AAGIP SCAN (③). And, the output line (SRO), the first TR-Q connection line (T1_Q), and the gate low voltage across the first AAGIP SCAN (①), the second AAGIP SCAN (②), and the third AAGIP SCAN (③) A wiring VGL or the like may be disposed.

Meanwhile, the GIP unit 1131 has a layout (including the above-described transistors T1 to T8, capacitors CQ and CQB, wires GVST, VGL, and VGH, and clock signal wires GCLK1 and GCLK3). layout) can be designed. That is, for the GIP unit 1131, in addition to the aforementioned transistors T1 to T8, capacitors CQ and CQB, wires GVST, VGL, and VGH, and clock signal wires GCLK1 and GCLK3, N 1st scan signal applying wire (S1(N)), Nth 2nd scan signal applying wire (S2(N)), Nth light emitting signal applying wire (EM(N)), N+1 1st scan signal Applied wire (S1(N+1)), N+1st 2nd scan signal applied wire (S2(N+1)), N+1th light emitting signal applied wire (EM(N+1)), etc. are arranged and laid out can design

Referring back to FIG. 14 , the first switching units T1 and Tbv may include a first transistor T1 and a node separation transistor Tbv. In the first transistor T1, the start signal applying line (GVST, SRO_N-1) is connected to the gate electrode, the gate low voltage line (VGL) is connected to the first electrode, and the first node (Q node) is connected to the second electrode ) is connected. The gate electrode of the node separation transistor Tbv is connected to the gate low voltage line VGL, and the second electrode of the first transistor T1 is connected to the first electrode through the first node Q.

The second switching unit T4 may include a fourth transistor T4. In the fourth transistor T4, the N−2 clock signal application line GCLK_N-2 is connected to the gate electrode, the gate low voltage line VGL is connected to the first electrode, and the second node ( QB) is connected.

The output units T6 and T7 may include a sixth transistor T6 outputting the voltage of the first node Q and a seventh transistor T7 outputting the voltage of the second node QB. In the sixth transistor T6, the second electrode of the node separation transistor Tbv is connected to the gate electrode, the wire receiving the Nth clock signal GCLK_N is connected to the first electrode, and the output wire ( SRO) can be connected. In the seventh transistor T7 , the second node QB is connected to the gate electrode, the output line SRO is connected to the first electrode, and the gate high voltage line VGH is connected to the second electrode.

The first stabilization unit T3 may include a third transistor T3. In the third transistor T3 , a gate electrode may be connected to a second node QB, a first electrode may be connected to a first node Q, and a second electrode may be connected to a gate high voltage line VGH.

The second stabilization units T5 and T8 may include a fifth transistor T5 and an eighth transistor T8. In the fifth transistor T5, the start signal applying line (GVST, SRO_N-1) is connected to the gate electrode, the second node (QB) is connected to the first electrode, and the gate high voltage line (VGH) is connected to the second electrode. this can be connected. The eighth transistor T8 has a gate electrode connected to the first electrode of the node separation transistor Tbv, a second node QB connected to the first electrode, and a gate high voltage line VGH connected to the second electrode. can be connected

A Q node capacitor QC is connected between the gate electrode of the sixth transistor T6 and the output line SRO, and a QB node capacitor CQB is connected between the gate electrode and the second electrode of the seventh transistor T7. can

14, in the first transistor T1, the node separation transistor Tbv, and the third to eighth transistors T3 to T8, the first electrode may be a source electrode and the second electrode may be a drain electrode, and vice versa. The first electrode may be a drain electrode, and the second electrode may be a source electrode.

As shown in FIGS. 12 to 15 , the GIP unit 1131 is arranged at regular intervals within the display area AA, so that a bezel area outside the display area AA can be further secured.

As described above, according to the present invention, a display panel capable of securing a layout area for design can be realized by reducing the number of transistors.

Further, according to the present invention, it is possible to realize a display device capable of compensating for driving power drop (VDD IR Drop) by changing the driving timing used in the 2Scan 1EM method as well as reducing the number of transistors in an OLED display device.

As described above, the present invention has been described with reference to the drawings illustrated, but the present invention is not limited by the embodiments and drawings disclosed in this specification, and various modifications are made by those skilled in the art within the scope of the technical idea of the present invention. It is obvious that variations can be made. In addition, although the operational effects according to the configuration of the present invention have not been explicitly described and described while describing the embodiments of the present invention, it is natural that the effects predictable by the corresponding configuration should also be recognized.

10: luminance controller 20: display panel
30: scan driving unit 40: data driving unit
50: light emitting control unit 60: power supply unit
70: timing controller 100: display device
PX: pixel OLED: light emitting element
T1~T4, T6~T8: switching element DT: driving element
Cst: storage capacitor AA: display area
1131: GIP part 1132: GIP internal connection wiring part
1133: sub pixel unit

Claims (21)

light emitting device;
a drive element electrically connected to the light emitting element and controlling a current flowing through the light emitting element;
a storage capacitor coupled to the driving element; and
A compensation circuit compensating for a change in the threshold voltage of the driving element;
In the compensation circuit, a first switching element is connected between the gate electrode and the second electrode of the driving element, data power is applied to the first electrode of the driving element through the second switching element, and driving power is supplied to the third switching element. driving power is applied to the storage capacitor through a seventh switching element, reference power is applied to the storage capacitor through an eighth switching element, and initialization power is applied to the sixth switching element. applied to the light emitting element through a display panel. According to claim 1,
In the first switching element, one of the first electrode and the second electrode is connected to the gate electrode of the driving element, the other is connected to the second electrode of the driving element, and the gate electrode is an n-th second scan wire. connected to the display panel. According to claim 1,
In the second switching element, one of the first electrode and the second electrode is connected to the data power supply, the other is connected to the first electrode of the driving element, and the gate electrode is connected to the n-th first scan wire. panel. According to claim 1,
In the third switching element, one of the first electrode and the second electrode is connected to the first electrode of the driving element, the other is connected to the driving power supply line, and the gate electrode is connected to the n-1 th light emitting control line. , display panel. According to claim 1,
In the fourth switching element, one of the first electrode and the second electrode is connected to the first electrode of the light emitting element, the other is connected to the second electrode of the driving element, and a gate electrode is an n-th light emitting control wire. connected to the display panel. According to claim 1,
In the sixth switching element, one of the first electrode and the second electrode is connected to the initialization power supply line, the other is connected to the first electrode of the light emitting element, and the gate electrode is connected to the nth second scan line, display panel. According to claim 1,
In the seventh switching element, one of the first electrode and the second electrode is connected to a driving power line, the other is connected to the first electrode of the storage capacitor, and a gate electrode is connected to the n-1th light emitting control line. connected, display panel. According to claim 1,
In the eighth switching element, one of a first electrode and a second electrode is connected to a reference power line, the other is connected to the first electrode of the storage capacitor, and a gate electrode is connected to an n-th second scan line. , display panel. According to claim 1,
wherein the first to fourth switching elements, the sixth to eighth switching elements, and the driving element are P-type MOSFET thin film transistors, respectively. According to claim 1,
wherein the first switching element, the sixth switching element, and the eighth switching element are N-type MOSFET thin film transistors. a plurality of sub-pixels in which light emitting elements are arranged in rows and columns; a plurality of scan wires disposed in each row of the plurality of sub-pixels, a plurality of data wires disposed in each column of the plurality of sub-pixels, and a driving element controlling a current flowing through the light emitting element; a storage capacitor coupled to the driving element; and a compensation circuit compensating for a change in threshold voltage of the driving element, wherein the compensation circuit has a first switching element connected between a gate electrode and a third electrode of the driving element, and data power is supplied through a second switching element. is applied to the first electrode of the driving element, driving power is applied to the driving element through a third switching element, driving power is applied to the storage capacitor through a seventh switching element, and reference power is applied to the eighth switching element. a display panel to which initialization power is applied to the storage capacitor and to the light emitting element through a sixth switching element;
a scan driver applying a scan signal to the plurality of gate wires;
a data driver to apply data signals to the plurality of data wires;
a power supply unit for applying high potential power, low potential power, reference power, and initialization power to the display panel; and
a timing controller controlling the scan driver and the data driver;
A display device comprising a. According to claim 11,
The compensation circuit,
A first switching element is connected between a gate electrode and a second electrode of the driving element, a second switching element is connected between the first electrode of the driving element and a data power line, and the first electrode and the driving element are connected. A third switching element is connected between power lines, and a fourth switching element is connected between the first electrode of the light emitting element and the second electrode of the driving element;
A sixth switching element is connected between the first electrode of the light emitting element and an initialization power line, a seventh switching element is connected between the storage capacitor and the driving power line, and an eighth switching element is connected between the storage capacitor and the reference power line. A display device to which a switching element is connected. According to claim 12,
The first switching element is switched by the n-th second scan signal,
The second switching element is switched by the n-th first scan signal,
The third switching element is switched by the n-1th light emission control signal,
The fourth switching element is switched by an n-th light emission control signal,
The sixth switching element is switched by the n-th second scan signal,
The seventh switching element is switched by the n-1th light emission control signal,
The eighth switching element is switched by an n-th second scan signal. According to claim 13,
The display device is driven by dividing the display panel into an initialization period (Initial), a sampling period (Sampling), and an emission period (Emission). According to claim 13,
The n-th first scan signal is a high signal in an initialization period, a low signal for 1H in a sampling period, and a high signal in an emission period;
The n-th second scan signal is a low signal in an initialization period, a low signal for 2H in a sampling period, and a high signal in an emission period;
The n-1 th light emission control signal is a high signal during an initialization period and a sampling period, and a high signal during a light emission period and remaining periods;
The n-th light emission control signal is a high signal during a sampling period and a part of the light emission period, and a low signal during the remaining period. According to claim 13,
The n-th first scan signal is a high signal in an initialization period, a low signal for 1H in a sampling period, and a high signal in an emission period;
The n-th second scan signal is a high signal in an initialization period, a high signal for 2H in a sampling period, and a low signal in an emission period;
The n-1 th light emission control signal is a high signal during an initialization period and a sampling period, and a high signal during a light emission period and remaining periods;
The n-th light emission control signal is a high signal during a sampling period and a part of the light emission period, and a low signal during the remaining period. According to claim 12,
The data voltage signal applied to the source electrode of the driving element is a low signal during a sampling period of 1H and a high signal during the remaining period;
The data voltage signal applied to the gate electrode of the driving element is a low signal during an initialization period of 1H, rises from a low signal to a signal during a sampling period, and is a high signal during an emission period. According to claim 12,
The reference voltage signal applied to the contact node of the storage capacitor is a low signal during an initialization period and a sampling period, and a high signal during an emission period. a display area in which a plurality of scan wires disposed in each row and a plurality of data wires disposed in each column intersect, and sub-pixels are disposed at each intersection;
at least one or more GIP units arranged in at least two or more columns;
a light emitting element disposed in each of the sub-pixels;
a drive element electrically connected to the light emitting element and controlling a current flowing through the light emitting element;
a storage capacitor coupled to the driving element; and
A compensation circuit compensating for a change in the threshold voltage of the driving element;
In the compensation circuit, a first switching element is connected between the gate electrode and the second electrode of the driving element, data power is applied to the first electrode of the driving element through the second switching element, and driving power is supplied to the third switching element. driving power is applied to the storage capacitor through a seventh switching element, reference power is applied to the storage capacitor through an eighth switching element, and initialization power is applied to the sixth switching element. applied to the light emitting element through a display panel. According to claim 19,
The GIP unit may include a plurality of stages which are distributed in unit pixel areas driven by each gate line in the display area and supply scan pulses to the corresponding gate lines;
A display panel comprising a. 21. The method of claim 20,
The unit pixel area includes at least three sub-pixels,
The driving element is disposed in each of the at least three sub-pixels,
A display panel wherein a GIP TFT is disposed in the GIP unit.

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