KR20190135786A - Display device - Google Patents

Abstract

According to the present invention, a display device comprises: a capacitor having a first electrode connected to a first power line; a light emitting diode having a cathode connected to a second power line; a driving transistor having a gate electrode connected to a second electrode of a capacitor and a first electrode connected to a data line; a first transistor having the first and second electrodes respectively connected to the gate electrode of the driving transistor and the second electrode, and the gate electrode connected to a scan line; and a second transistor having the first and second electrodes respectively connected to the second electrode of the driving transistor and an anode of the light emitting diode, and the gate electrode connected to an emission line. A high potential voltage may be applied to the first power line, the high potential voltage and a low potential voltage may be alternately applied to the second power line, and the high potential voltage, the low potential voltage and a data voltage may be alternately applied to the data line. Therefore, a pixel circuit of an internal compensation scheme is implemented by using a small number of transistors, thereby securing a pixel design margin, developing a higher resolution model, and reducing a bezel size by removing a light emitting block through simultaneous light emission.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a pixel structure for simultaneously emitting light emitting elements of a panel.

The active matrix type organic light emitting diode display includes an organic light emitting diode (OLED) that emits light by itself, and has advantages of fast response speed and high luminous efficiency, luminance, and viewing angle.

The organic light emitting diode display arranges pixels including the OLED in a matrix form and adjusts luminance by controlling the amount of light emitted from the OLED according to the gray level of the image data. Each pixel circuit controls the pixel current flowing through the OLED according to the voltage applied between the OLED, which is a light emitting element, a switch transistor or TFT (Thin Film Transistor) for controlling the application of a data voltage corresponding to the gray level, and a gate electrode and a source electrode. A driving TFT, and a capacitor for storing the data voltage.

The electrical characteristics of the OLED and the driving TFT deteriorate with time, and may cause a difference for each pixel, and variations in electrical characteristics between these pixels become a major factor in degrading image quality. In order to compensate for the deviation of the electrical characteristics between the pixels, the electrical characteristics of the pixels (threshold voltage of the driving TFT and electron mobility of the driving TFT) must be compensated for.

An external compensation method and an internal compensation method are proposed to solve the problem of changing the electrical characteristics of pixels. The external compensation method accurately compensates by sensing the characteristic parameter of the driving TFT of each pixel and correcting the input data according to the sensing value, but it takes a long time for sensing and a large source driver IC. On the other hand, the internal compensation scheme can compensate in real time, but there are disadvantages in that the pixel structure is complicated and the aperture ratio is decreased.

Since the pixel circuit of the conventional internal compensation method needs to be connected to many wirings such as an initialization voltage line, two scan signal lines, and a light emitting signal line, it is difficult to secure a margin from a pixel design point of view and thus there is a limit in increasing the resolution.

The present invention contemplates such a situation, and an object of the present invention is to provide an internal compensation circuit structure that overcomes the limitations of pixel design.

It is another object of the present invention to provide a pixel circuit structure that reduces bezel size and improves response speed.

According to an exemplary embodiment, a display device includes: a capacitor having a first electrode connected to a first power line; A light emitting diode having a cathode electrode connected to the second power line; A driving transistor having a gate electrode connected to the second electrode of the capacitor and a first electrode connected to the data line; A first transistor connected to a gate electrode and a second electrode of the driving transistor, respectively, and having a gate electrode connected to a scan line; And a second transistor having a first electrode and a second electrode connected to the second electrode of the driving transistor and an anode electrode of the light emitting diode, respectively, and a gate electrode connected to an emission line.

In one embodiment, a high potential voltage is applied to the first power line, a high potential voltage and a low potential voltage are alternately applied to the second power line, and a high potential voltage, a low potential voltage and a data voltage are alternately applied to the data line. Can be applied as

In one embodiment, the display device may further include a switch for connecting neighboring data lines to each other.

In one embodiment, the switch may be connected to a section in which the light emitting diode emits light.

In another embodiment, a method of driving a display device includes a capacitor having a first electrode connected to a first power line; A light emitting diode having a cathode electrode connected to the second power source; A driving transistor having a gate electrode connected to the second electrode of the capacitor and a first electrode connected to the data line; A first transistor connected to a gate electrode and a second electrode of the driving transistor, respectively, and having a gate electrode connected to a scan line; And a panel including pixels including first and second electrodes connected to the second electrode of the driving transistor and the anode electrode of the light emitting diode, respectively, and a second transistor having a gate electrode connected to an emission line. Running in the apparatus, setting the anode electrode to a high potential voltage and then to a low potential voltage; Sequentially supplying a scan signal to a scan line and applying a data voltage to the data line in a data writing period to detect a threshold voltage of a driving transistor included in pixels provided in the panel and write image data into the pixels; And simultaneously emitting the light emitting diodes of the pixels to which the image data is written by simultaneously applying the emission signal to the emission line in the emission period.

In one embodiment, a high potential voltage is applied to the first power line, a high potential voltage and a low potential voltage are alternately applied to the second power line, and a high potential voltage, a low potential voltage and a data voltage are alternately applied to the data line. Can be applied as

In one embodiment, when setting the anode electrode to a high potential voltage, applying a high potential voltage to the data line and the second power supply line, applying a scan signal for turning off the first transistor to the scan line, and the second transistor Scan to turn on the first transistor and apply a low potential voltage to the data line and the second power supply line when applying the emission signal to turn on the emission line and setting the anode electrode to the low potential voltage. The signal may be applied to the scan line, and an emission signal for turning on the second transistor may be applied to the emission line.

In one embodiment, the gate electrode of the driving transistor may be initialized after the anode electrode is set.

In one embodiment, when initializing the gate electrode of the driving transistor, a low potential voltage is applied to the data line and the second power supply line, a scan signal for turning on the first transistor is applied to the scan line, and the second transistor is applied. An emission signal for turning on may be applied to the emission line.

In one embodiment, the anode electrode may be initialized to a high potential voltage before emitting the light emitting diode.

In one embodiment, when initializing the anode electrode to a high potential voltage, applying a high potential voltage to the data line and the second power supply line, applying a scan signal to the scan line to turn off the first transistor, and a second An emission signal for turning on the transistor may be applied to the emission line.

In one embodiment, a low potential voltage may be applied to the data line prior to setting the anode to turn off the light emitting diode.

In one embodiment, when the light emitting diode is turned off, a low potential voltage is applied to the data line and the second power supply line, a scan signal for turning off the first transistor is applied to the scan line, and the second transistor is turned on. The emission signal to turn on can be applied to the emission line.

In one embodiment, the display device further comprises a switch for connecting the neighboring data lines to each other, the switch may be connected in the emission period.

By reducing the number of transistors and reducing the number of driving signal lines compared to the pixel structure of the internal compensation method which sequentially emits light in units of conventional horizontal lines, a pixel design margin can be secured by increasing the aperture ratio of pixels, and thus a higher resolution model can be developed. Will be.

In addition, the reaction speed is improved according to the impulse driving during the initialization section and the sensing section.

In addition, by adopting a structure that emits light at the same time, the light emitting block for sequentially outputting the light emission signal is removed from the gate driving circuit, thereby reducing the bezel size.

In addition, by sharing charges between adjacent data lines, an effect of reducing IR drop variation and vertical crosstalk phenomenon occurs.

1 is a block diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention.
2 illustrates an equivalent circuit of a pixel according to an embodiment of the present invention,
3 illustrates a waveform diagram of a driving signal for driving the pixel circuit of FIG. 2;
4A to 4G illustrate the connection and operation of the pixel circuit in each section of the waveform diagram of FIG. 3.
5A and 5B illustrate waveforms of configurations and switching signals for applying a high potential power source, a low potential power source, and a data voltage to a data line;
6A and 6B illustrate waveforms of configurations and switching signals for applying high potential power and low potential power to the cathode line,
7A to 7D show the voltages of the main nodes when changing the low potential voltage applied to the pixel circuit,
8A-8D show the voltage of the main node according to the combination of the capacitor values of the storage capacitor and the OLED,
FIG. 9 illustrates a modified embodiment of a waveform diagram of a driving signal for driving the pixel circuit of FIG. 2.
10 is a comparison of the plane of the pixel and the plane of the conventional pixel according to the present invention,
11 is a comparison between the GIP configuration and the conventional GIP configuration according to the present invention,
12A and 12B illustrate waveforms of a configuration signal and a switching signal for separating or connecting data lines by dividing a light emission section and a data write section according to an embodiment of the present invention.
FIG. 13 compares the present invention in which vertical crosstalk is relaxed compared to the conventional structure.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

From the point of view of pixel design, the pixel that adopts internal compensation method to emit light sequentially in horizontal line unit instead of simultaneously emitting pixels in the panel, includes initialization voltage line, scan line for previous pixel line, scan for current pixel line. Since the light emitting line for the line, the current pixel line, passes and covers a large area occupied by the pixel, it is difficult to secure the aperture ratio when the pixel size is reduced to increase the resolution.

In addition, the pixel circuit which sequentially emits the pixel lines in the internal compensation scheme operates in the form of a rolling shutter, and requires a light emission signal to be sequentially applied in addition to two scan signals for data writing and initialization. Therefore, when the gate driving circuit is formed on the panel in the form of a gate drive IC in panel (GIP), in addition to the scan block for generating the scan signal, the number of light emitting blocks for generating the emission signal is required as many as the number of horizontal lines. There is a problem that the circuit becomes larger and the size of the bezel becomes larger.

In the present invention, the pixel circuit for internal compensation is composed of three transistors and one capacitor, thereby reducing the number of circuit components and the number of control signals to ensure the aperture ratio in the pixel design, and eliminate the light emitting block by the simultaneous light emission method. Reduce the bezel size and use impulse driving to speed up the reaction.

1 is a block diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention. The display device according to the present invention may include a display panel 10, a timing controller 11, a data driver circuit 12, a gate driver circuit 13, and a power generator 16.

In the display panel 10, a plurality of data lines 14 arranged in a column direction and a plurality of scan lines 15 arranged in a row direction intersect each other, and pixels PXL are formed at each crossing area. ) Are arranged in a matrix to form a pixel array. The scan lines 15 may include a plurality of scan lines SL for supplying a scan signal for applying a data voltage and a plurality of light emission lines or emission lines for supplying a light emission signal for controlling light emission of the light emitting device. Emission Line (EL).

In the pixel array, the pixel PXL is connected to one of the data lines 14, one of the scan lines SL, and one of the emission lines EL to form a pixel line. The pixel is electrically connected to the data line 14 in response to a scan pulse input through the scan line SL to receive a data voltage, and emits light in response to an emission pulse input through the emission line EL. The light emission of the device can be controlled. Pixels arranged on the same pixel line operate simultaneously according to scan pulses applied from the same scan line SL.

The pixel may receive the high potential driving voltage V _DD and the low potential driving voltage V _SS from the power generator 16, and may include a light emitting device, a driving transistor, a storage capacitor, and two switch transistors. The light emitting device may be an inorganic electroluminescent device or an organic light emitting diode device (OLED). Hereinafter, for convenience, the OLED is described as an example.

The transistors (or TFTs) constituting the pixel may be implemented in a P type or N type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, or a hybrid type in which a P type and an N type are mixed. Although a P type transistor is illustrated in the following embodiments, the present invention is not limited thereto.

Transistors are three-electrode elements that include a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode out of the transistor in the transistor. That is, the carrier flow in the MOSFET flows from the source to the drain.

In the case of an N-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from source to drain in an N-type MOSFET, the direction of current flows from drain to source. In the case of a P-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a P-type MOSFET, current flows from source to drain because holes flow from source to drain.

Note that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET can be changed depending on the applied voltage. In the following embodiments, the invention should not be limited due to the source and drain of the transistor, and the source and drain electrodes may be referred to as first and second electrodes without distinction.

Each pixel PXL includes transistors and capacitors for driving the OLED with a current proportional to the pixel data and compensating for the threshold voltage change of the driving transistor. A detailed pixel circuit structure according to an embodiment of the present invention will be described later. do.

The timing controller 11 supplies the image data RGB transmitted from an external host system (not shown) to the data driving circuit 12. The timing controller 11 receives timing signals such as a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal Data Enable, and a dot clock CLK from a host system. 12 and control signals for controlling the operation timing of the gate driving circuit 13. The control signals include a gate timing control signal GCS for controlling the operation timing of the gate driving circuit 13 and a data timing control signal DCS for controlling the operation timing of the data driving circuit 12.

The timing controller 11 sequentially applies data to all pixels during a period of initializing all pixels during one frame in which image data constituting one screen is applied to pixels constituting the display panel 10. It can be driven by dividing the section and the entire pixel into sections emitting light at the same time.

The data driving circuit 12 converts the digital video data RGB input from the timing controller 11 into an analog data voltage under the control of the timing controller 11 and outputs the analog video voltage to the data lines 14. In this case, the data voltage may be a value corresponding to the image signal to be displayed by the organic light emitting diode.

The gate driving circuit 13 generates a scan signal and an emission signal based on the gate control signal GDC under the control of the timing controller 11, but generates the scan signals in a row sequential manner to connect at least each pixel line. The emission signals may be sequentially provided to one or more scan lines SL, and the emission signals may be simultaneously provided to emission lines EL connected to each pixel line.

The gate driving circuit 13 may be composed of a plurality of gate drive integrated circuits each including a shift register, a level shifter and an output buffer for converting an output signal of the shift register into a swing width suitable for driving a TFT of a pixel. have. Alternatively, the gate driving circuit 13 may be directly formed on the lower substrate of the display panel 10 by a gate drive IC in panel (GIP) method. In the GIP method, the level shifter may be mounted on a printed circuit board (PCB), and the shift register may be formed on the lower substrate of the display panel 10.

The power generation unit 16 generates and supplies a voltage necessary for the operation of the data driving circuit 12 and the gate driving circuit 13 by using an external power source, and drives the high potential driving voltage V _DD and the low potential driving. The voltage V _SS may be generated as a fixed value and applied to the display panel 10.

2 illustrates an equivalent circuit of a pixel according to an exemplary embodiment of the present invention, and FIG. 3 illustrates a waveform diagram of a driving signal for driving the pixel circuit of FIG. 2, wherein the pixel circuit of FIG. 2 includes three transistors. And one capacitor.

The organic light emitting diode OLED emits light by the driving current supplied from the driving transistor DT, and the driving transistor DT controls the driving current applied to the OLED according to its source-gate voltage V _SG . .

The driving transistor DT is connected to the first electrode connected to the data line DATA 14 (the first node N1), the gate electrode connected to the second node N2, and the third node N3. A second electrode may be connected, and since the driving transistor DT is a P type, the first node may be a source electrode and the second node may be a drain electrode.

One electrode of the storage capacitor CST is connected to the high potential power VDD, which is the first power supply, and the other electrode is connected to the second node N2, that is, the gate electrode of the driving transistor DT.

In the first transistor T1, the first electrode and the second electrode are respectively connected to the second node N2 and the third node N3, which are the gate electrode and the second electrode of the driving transistor DT, and the gate electrode is It is connected to the scan line SCAN (n) and is involved in writing a data voltage and sensing a threshold voltage V _TH of the driving transistor DT.

In the second transistor T2, the first electrode and the second electrode are respectively connected to the third node N3, which is the second electrode of the driving transistor DT, and the fourth node N4, which is the anode electrode of the OLED. The electrode is connected to the emission line EM to control the light emission of the OLED.

In the OLED, the anode electrode is connected to the fourth node N4 and the cathode electrode (the fifth node N5) is connected to the cathode line CAT which supplies the second power, which is connected in parallel to the OLED in FIG. 6. OLED capacitors (C _OLEDs ) are parasitic capacitors for OLEDs, rather than being connected as separate devices.

The pixel circuit of FIG. 2 is for pixels included in the n-th pixel line, and the pixel circuit of FIG. 2 includes the n-th scan signal SCAN (n) and an emission signal EM common to all pixel lines. And to control the operation of the second transistors T1 and T2.

In an exemplary embodiment of the present invention, the transistors are implemented as a P type, but the semiconductor types of the transistors are not limited thereto. If the driving transistor DT, the first transistor T1, and the second transistor T2 are implemented in the N type, the scan signal SCAN and the emission signal EM shown in FIG. 3 should be inverted.

The waveform diagram of FIG. 3 divides one frame into first to seventh periods t1 to t7. The first to fourth periods t1 to t4 correspond to a period for initializing all pixels, and the fifth period ( t5) corresponds to a section in which the threshold voltage V _TH of the driving transistor DT is sequentially sensed and data is written from the first pixel line to the last pixel line, and the sixth and seventh sections t6 and t7 are It corresponds to a section for emitting OLEDs of all pixels at the same time.

4A to 4G illustrate the connection and operation of the pixel circuit in each section of the waveform diagram of FIG. 3.

Before the first period t1 of the current frame (kth frame), the potential of the second node N2 is driven at the data voltage DATA (k-1) of the previous frame ((k-1) th frame). (DATA (k-1))-V _TH minus the threshold voltage V _TH of the transistor DT, and the potentials of the third and fourth nodes N3 and N4 are the operating voltage V _{OLED of the OLED} , That is, the voltage of the anode electrode of the OLED.

Referring to FIG. 4A, in the first period t1, the low potential voltage V _SS is applied to the data line DATA to which the high potential voltage V _DD was applied in the light emission period of the previous frame, thereby providing the first node. Becomes the low potential voltage (V _SS ).

In the first period t1, the scan signals SCAN (1) to SCAN (N) of all the pixel lines maintain the high logic level as in the last period of the previous frame so that the first transistor T1 is turned off. The emission signal EM maintains the low logic level as in the last section of the previous frame, so that the second transistor T2 is turned on and the cathode line CAT maintains the low potential voltage V _SS as it is. Keep it.

In the first period t1, the potential of the first electrode N1 of the driving transistor DT becomes the low potential voltage V _SS so that the driving transistor DT is turned on in the reverse direction and the second electrode N3 is turned on. Current flows to the first electrode N1 at, the potential of the gate electrode N2 is kept slightly away from (DATA (k-1))-V _TH , and the second electrode of the driving transistor DT is maintained. The potential of N3 is gradually lowered at the operating voltage V _OLED of the OLED under the influence of the first electrode N1. Since the driving transistor DT is turned on in the reverse direction, the OLED also stops emitting light, and thus, the first period t1 may be referred to as an off period for turning off the OLED.

Referring to FIG. 4B, in the second period t2, the data line DATA and the cathode line CAT are changed from the low potential voltage V _SS to the high potential voltage V _DD , and the scan signal SCAN The emission signal EM maintains the logic level of the first period t1.

As the cathode electrode N5 of the OLED is changed from the low potential voltage V _SS to the high potential voltage V _DD , the potential of the anode electrode N4 of the OLED connected to the OLED capacitor C _OLED is represented by the high potential voltage ( after the larger V _DD) than settle to the high-potential voltage (V _DD). The potential of the second electrode N3 of the driving transistor DT is also increased by the second transistor T2 in the turn-on state above the high potential voltage V _DD , similar to the potential of the anode electrode N4 of the OLED. After that, it is settled to a high potential voltage (V _DD ).

As the voltage of the data line DATA changes, the potential of the first electrode N1 of the driving transistor DT becomes the high potential voltage V _DD , and the potential of the second electrode N3 of the driving transistor DT becomes the potential. Since the state larger than the potential of the first electrode N1 is maintained, the driving transistor DT is turned on in the reverse direction. The potential of the gate electrode N2 of the driving transistor DT maintains a slightly increased value near (DATA (k-1))-V _{TH as} the first electrode N1 and the second electrode N3 change. do.

That is, the anode electrode of the OLED is initialized or set to the high potential voltage V _{DD in} the second period t2.

Referring to FIG. 4C, in the third period t3, the data line DATA and the cathode line CAT are changed from the high potential voltage V _DD to the low potential voltage V _SS , and the scan signal SCAN The emission signal EM maintains the logic level in the same state as the previous section.

The potential of the first electrode N1 of the driving transistor DT becomes the low potential voltage V _SS , and the cathode electrode CAT is changed into the low potential voltage V _SS so that the anode electrode N4 of the OLED is also low potential. voltage (V _SS) by changing the turn-second electrode (N3) of the driving transistor (DT) by turning on the second transistor (T2) in the state is also a low voltage potential (V _SS). Since the potential of the first electrode N1 of the driving transistor DT is lower than that of the gate electrode N2, the driving transistor DT is turned off.

That is, in the third section t3, the anode electrode of the OLED is initialized to the low potential voltage V _SS .

Referring to FIG. 4D, in the fourth period t4, the data line DATA and the cathode line CAT maintain the low potential voltage V _SS , and the emission signal EM also has the same logic as the previous period. Maintaining the level, the scan signals SCAN (1) to SCAN (N) of all pixel lines are changed from the high logic level to the low logic level.

The driving transistor DT and the second transistor T2 maintain the turn-off state and the turn-on state, respectively, and the first transistor T1 is turned on by the scan signal SCAN having a low logic level. .

When the first transistor T1 is turned on, the second node N2 having a potential of (DATA (k-1) -V _TH ) and the third node N3 having a low potential of voltage V _SS are present. Connected with each other, the potentials of the second node N2 and the third node N3 become their intermediate values ((DATA (k-1))-V _TH + V _SS ) / 2, and the turn-on state The potential of the fourth node N4 also becomes ((DATA (k-1))-V _TH + V _SS ) / 2 by the two transistors T2.

That is, in the fourth period t4, the gate electrode N2 of the driving transistor DT is initialized to a potential of ((DATA (k-1))-V _TH + V _SS ) / 2, which is a period after the current frame. When the image data DATA (k) is applied to the image data DATA (k), the potential of the gate electrode N2 of the driving transistor DT is initialized to a value lower than the potential of the first electrode N1 to turn on the driving transistor DT. It is to let.

If the initialization is not sufficient due to the operation of the fourth period t4, when the operations of the second period t2 to the fourth period t4 are repeated, the potential of the gate electrode N2 of the driving transistor DT becomes low potential. It can converge to the voltage V _SS .

In order to initialize the potential of the gate electrode N2 of the driving transistor DT to a value lower than the potential of the first electrode N1 in the fourth period t4, the anode electrode N4 of the OLED in the third period t3. It is necessary to set) to the low potential voltage (V _SS ), and since the OLED electrode N4 of the OLED cannot be directly set to the low potential voltage (V _SS ) while the OLED is turned off while emitting light in the previous frame, Before setting the anode electrode N4 to the low potential voltage V _{SS, it} is necessary to set the high potential voltage V _DD in the second period t2.

Referring to FIG. 4E, in the fifth period t5, the cathode line CAT maintains the low potential voltage V _SS , the emission signal EM changes from a low logic level to a high logic level, and the data Data of N pixels from the first pixel line to the N-th pixel line are sequentially applied to the line DATA, and the N-th scan is performed from the first scan signal SCAN (1) in synchronization with the data of the data line DATA. The signal SCAN (N) is sequentially applied to the corresponding pixel lines.

The scan signal, which was at the low logic level in the fourth section t4, is changed to the high logic level in the beginning of the fifth section t5, and then changes to the low logic level when the scan signal is applied to the corresponding pixel line, and then scans to the next pixel line. When the signal is applied it goes back to the high logic level. That is, after a high logic level scan signal is applied to all pixel lines at the beginning of the fifth period t5, the first scan signal SCAN (1) becomes a low logic level and then returns to the high logic level after a predetermined time elapses. The second scan signal SCAN (2) becomes the low logic level when the first scan signal SCAN (1) changes to the high logic level, and then changes to the high logic level after a predetermined time elapses. Scan pulses having a low logic level are sequentially applied to each pixel line from the signal SCAN (1) to the Nth scan signal.

The scan signals SCAN (1) to SCAN (N) of all the pixel lines become the high logic level at the beginning of the fifth period t5, and the scan signals SCAN (of all the pixel lines even in the second half of the fifth period t5. 1) to SCAN (N) become the high logic level.

In the fifth period t5, a scan signal SCAN (n) having a low logic level is applied to the nth pixel line of the kth frame that is the current frame, and the data voltage DATA (k) of the pixel line is applied. When applied to the data line DATA, the potential of the first node N1, that is, the first electrode N1 of the driving transistor DT becomes DATA (k) and becomes ((DATA (k-1))-V _TH. The driving transistor DT is turned on in the forward direction and turned on by the first transistor T1 that is higher than the potential of the gate electrode N2 and the second electrode N3 initialized to + V _SS ) / 2. The second node N2 and the third node N3 are connected to each other, and the driving transistor DT is diode-connected so that the potential of the gate electrode N2 and the second electrode N3 of the driving transistor DT is the first electrode. DATA (k), which is the potential of (N1), becomes (DATA (k) −V _TH ), which is a value obtained by subtracting the threshold voltage V _TH of the driving transistor DT. The storage capacitor CST stores a voltage corresponding to the difference between the data voltage and the threshold voltage DATA (k) −V _TH .

The emission signal EM changes to a high logic level so that the second transistor T2 is turned off to separate the driving transistor DT from the OLED, so that the anode electrode of the OLED is a potential at the fourth period t4 ( Keep the value of (DATA (k-1))-V _TH + V _SS ) / 2.

Since data is written to all pixels included in the panel 10 sequentially from the first pixel line to the Nth pixel line in the fifth section t5, and a threshold voltage is sensed, the fifth section t5 includes a data write and threshold It may be referred to as a voltage sensing section.

Referring to FIG. 4F, in the sixth period t6, the scan signal SCAN maintains a high logic level, the high potential voltage V _DD is applied to the data line DATA, and the emission signal EM is applied. Is changed from the high logic level to the low logic level, and the potential of the cathode line CAT is changed from the low potential voltage V _{SS to the} high potential voltage V _DD .

The first transistor T1 is turned off by the scan signal SCAN of the high logic level, and the second node N2 maintains the (DATA (k) −V _TH ) potential.

The potential of the first electrode N1 of the driving transistor DT becomes the high potential voltage V _DD , and the driving transistor DT maintains a turn-on state.

According to the potential variation of the cathode line CAT, the anode electrode N4 of the OLED has a lower potential than the cathode electrode N5 so that a reverse voltage is applied to the OLED so that current does not flow in the OLED in the forward direction, and thus the OLED capacitor does not emit light. The potential of the anode electrode N4 of the OLED is changed to the high potential voltage V _DD according to the potential of the cathode line CAT by (C _OLED ). According to the emission signal EM of the low logic level, the second transistor T2 is turned on and the third node N3 and the fourth node N4 are connected to each other so that the second electrode of the driving transistor DT ( The potential of N3) also becomes a high potential voltage V _DD .

That is, the sixth section t6 is a section for initializing the anode electrode N4 of the OLED to the high potential voltage V _DD .

Referring to FIG. 4G, in the seventh period t7, the scan signal SCAN maintains a high logic level, the data line DATA maintains a high potential voltage V _DD , and the emission signal EM Maintaining the low logic level, the cathode line CAT changes from the high potential voltage V _DD to the low potential voltage V _SS .

The cathode electrode N5 of the OLED is lower than the anode electrode N4 so that current flows in the forward direction, and the driving transistor DT in the turn-on state passes the current through the second transistor T2 in the turn-on state to the OLED. The driving transistor DT corresponds to DATA (k) canceled by the threshold voltage V _TH at (DATA (k) −V _TH ), the potential of the gate electrode N2 stored in the storage capacitor CST. Current is passed through the OLED.

The source electrode of the driving transistor DT, that is, the potential of the first electrode N1 is a high voltage voltage V _DD , and the potential of the gate electrode N2 of the driving transistor DT is (DATA (k) -V _TH ). Therefore, the relation for the driving current (I _OLED ) flowing through the OLED is expressed by Equation 1 below.

In Equation 1, m / 2 represents a proportionality constant determined by electron mobility, parasitic capacitance, channel capacitance, and the like of the driving transistor DT.

As shown in Equation 1, since the threshold voltage V _TH component of the driving transistor DT is erased in the relation of the driving current I _OLED , even if the threshold voltage of the driving transistor is changed, the data is compensated for while the threshold voltage is changed. The OLED may emit light with a current corresponding to the data voltage input through the line DATA.

That is, the seventh section t7 corresponds to the section for emitting the OLED.

Meanwhile, when the OLED is emitted by directly applying the seventh section t7 without the sixth section t6, a restored afterimage may occur. That is, at the beginning of the seventh section t7, a current flows through the OLED by the potential of the anode electrode N4 of the OLED in the fifth section t5 and the potential of the cathode electrode N5 of the OLED, thereby emitting the OLED. As a result, the current flowing through the OLED or the current flowing through the driving transistor DT may not be determined only by a value stored in the storage capacitor CST.

5A and 5B show waveform diagrams of configurations and switching signals for applying a high potential power source, a low potential power source, and a data voltage to a data line.

The data driving circuit 12 converts the digital video data RGB input from the timing controller 11 into an analog data voltage V _DATA using a digital-analog converter (DAC), thereby converting the data line DATA 14. Will print

In the pixel circuit of FIG. 2 of the present invention, since the high potential voltage V _DD and the low potential voltage V _SS as well as the data voltage V _DATA must be applied to the data line DATA, the data line DATA is digital. It should be connected to a high potential power supply (VDD) and a low potential power supply (VSS) as well as a DAC that converts video data RGB into an analog data voltage V _DATA .

In FIG. 5A, the data line DATA is connected to the output terminal of the DAC, and is connected to the high potential power VDD and the low potential power VSS through the switches S1 and S2. The switch S1 connects the data line DATA and the high potential power supply VDD to the second, sixth and seventh periods t2, t6, and t7 where the high potential voltage V _DD is applied to the data line DATA. (On) and the switch S2 supplies the data line DATA and the low potential power in the first, third, and fourth sections t1, t3, and t4 to which the low potential voltage V _SS is applied to the data line DATA. Connect (VSS).

6A and 6B show waveform diagrams of configurations and switching signals for applying high potential power and low potential power to the cathode line.

Since the high potential voltage V _DD and the low potential voltage V _SS are applied to the cathode line CAT, the cathode line CAT is connected to the high potential power VDD and the low potential power VSS through the switches S3 and S4. ) Can be connected.

The switch S3 connects the cathode line CAT to the high potential power supply VDD in the second and sixth periods t2 and t6 to which the high potential voltage V _DD is applied to the cathode line CAT. The switch S2 is connected to the first, third to fifth and seventh sections t1, t3 to t5, and t7 to which the low potential voltage V _SS is applied to the cathode line CAT.

7A to 7D show the voltages of the main node when changing the low potential voltage applied to the pixel circuit, and when applying the data voltage of 4V in the first frame and the data voltage of 3V in the second frame. The voltages of the main nodes are shown in the first to fifth sections of the second frame.

Storage capacitor (CST) is 50f, OLED capacitor (COLED) is 20f, high potential voltage (VDD) is 4.6V, scan signal (SCAN) and emission signal (EM) swing from -8V to 8V The low potential voltage V _SS applied to the data line DATA is fixed at −3 V, and the low potential voltage V _SS applied to the cathode line CAT is −3 V (FIG. 11A) and −5 V, respectively. 11B, -7V (FIG. 11C), and -8V (FIG. 11D), the voltages of the main nodes were measured. As the low potential voltage V _SS applied to the cathode line CAT decreases, the variation of the potential of the third node N3 increases.

8A-8D show the voltage of the main node according to a combination of storage capacitor and OLED capacitor values.

The data voltage is 4V, the high potential voltage (VDD) is 4.6V, the low potential voltage (V _SS ) is -3V, the scan signal (SCAN) and the emission signal (EM) swing from -8V to 8V, The storage capacitor CST and the OLED capacitor COLED are conditions of 30f and 20f in FIG. 12A, 30f and 30f in FIG. 12B, 50f and 20f in FIG. 12C, and 50f and 30f in FIG. 12D, respectively.

As the value of the OLED capacitor COLED increases, the change in the potential of the third node N3 increases, and as the value of the storage capacitor CST increases, the change in the potential of the third node N3 decreases.

FIG. 9 illustrates a modified embodiment of a waveform diagram of a driving signal for driving the pixel circuit of FIG. 2. The signal waveform diagram of FIG. 9 is a first section t1 and a sixth section t6, compared to those of FIG. 3. ) Is missing.

In FIG. 3, when the length of the second section t2 is sufficient, the first section t1 may be omitted. The OLED emission is stopped by applying the high potential voltage V _DD to the cathode line CAT, and the anode of the OLED is shown. The electrode N4 may be initialized directly to the high potential voltage V _DD .

In the sixth section t6, the residual afterimage may be reflected by the potential of the anode electrode of the OLED or the second electrode N3 of the driving transistor DT in the early stage of emitting the OLED. ), There is no problem in emitting the OLED while compensating for the threshold voltage of the driving transistor DT.

10 compares the plane of a pixel according to the invention with the plane of a conventional pixel.

The pixel circuit of the present invention reduces four transistors, and reduces the scan signal line (SCAN (n-1)) and the initialization voltage line of the previous pixel line, compared to a pixel circuit of an internal compensation method which sequentially emits light in units of horizontal lines. By eliminating (V _INI ), margins and pixel apertures can be increased in pixel designs for higher resolution model development.

11 is a comparison between the GIP configuration and the conventional GIP configuration according to the present invention.

In order to drive a pixel circuit of an internal compensation method that sequentially emits light in units of horizontal lines, an emission signal EM as well as a scan signal SCAN must be sequentially applied to each pixel line, and a scan signal is applied to the GIP. A scan block and an emission block for generating the N must be provided.

However, in the present invention, since data is sequentially written to all the pixels, and then emits light at the same time, a scan block for sequentially supplying the scan signal SCAN to each pixel line should be provided in the GIP. Since the emission signal EM is applied to the line at the same time, the emission block is not required, thereby reducing the bezel covering the GIP.

In addition, each frame is divided into a first period in which each node initializes, senses a threshold voltage, and writes data, and a second period in which all pixels emit light, and turns off the OLED in the first period and turns on the OLED in the second period. The impulse driving effect can improve the moving picture response time (MPRT) associated with the response time.

12A and 12B illustrate waveforms of configurations and switching signals for separating or connecting data lines by dividing a light emission section and a data write section according to an embodiment of the present invention, and FIG. Compared to the invention, the vertical crosstalk is relaxed compared to the conventional structure.

When voltage values are differently applied to the data lines DATA 14 in the emission period, crosstalk occurs in the vertical direction as shown in the left figure of FIG. 13 due to the voltage drop deviation caused by the resistance.

In order to solve this problem, in the present invention, the data lines are separated from each other when writing data, and when the light is emitted, the data lines can be connected to each other in a mesh form to share charges between adjacent data lines. have. To this end, a switch S5 may be provided between the data lines, the switch S5 may be connected to a seventh section t7 for emitting the OLED of the pixel, and the switch S5 may be disconnected in the remaining sections.

In addition to providing the switch S5 near the data driving circuit 12 in the data line DATA, that is, in the vicinity of the first pixel line, the switch S5 is further provided in the last pixel line far from the data driving circuit 12 to provide data. The potential difference between the lines can be prevented from occurring.

Since the data lines are connected to each other in the emission period to share charges, the potential difference between the data lines may be reduced, and vertical crosstalk may be alleviated as illustrated in the right figure of FIG. 13.

Although FIG. 12B illustrates that the switch S5 is connected only to the seventh period t7, the switch S5 may also be connected to the first to fourth sections t1 to t4 for initializing the main nodes of the pixel circuit.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: data line 15: scan line
16: power generator

Claims (14)

A capacitor having a first electrode connected to the first power line;
A light emitting diode having a cathode electrode connected to the second power line;
A driving transistor having a gate electrode connected to a second electrode of the capacitor and a first electrode connected to a data line;
A first transistor connected to a gate electrode and a second electrode of the driving transistor, respectively, and a first electrode connected to a scan line; And
And a second transistor having a first electrode and a second electrode connected to the second electrode of the driving transistor and an anode electrode of the light emitting diode, respectively, and a gate electrode connected to an emission line. According to claim 1,
A high potential voltage is applied to the first power line, the high potential voltage and a low potential voltage are alternately applied to the second power line, and the high potential voltage, the low potential voltage and the data voltage are alternately applied to the data line. And alternately applied. According to claim 1,
And a switch for connecting neighboring data lines to each other. The method of claim 3, wherein
And the switch is connected to a section in which the light emitting diode emits light. A capacitor having a first electrode connected to the first power line; A light emitting diode having a cathode electrode connected to the second power source; A driving transistor having a gate electrode connected to a second electrode of the capacitor and a first electrode connected to a data line; A first transistor connected to a gate electrode and a second electrode of the driving transistor, respectively, and a first electrode connected to a scan line; And a panel including pixels including first and second electrodes connected to a second electrode of the driving transistor and an anode electrode of the light emitting diode, respectively, and a second transistor having a gate electrode connected to an emission line. In the method of driving the display device,
Setting the anode electrode to a high potential voltage and then to a low potential voltage;
In the data writing period, a scan signal is sequentially supplied to the scan line and a data voltage is applied to the data line to sense threshold voltages of driving transistors included in pixels provided in the panel, and to write image data to the pixels. Making; And
And simultaneously emitting an emission signal to the emission line during an emission period, thereby simultaneously emitting light-emitting diodes of pixels to which the image data is written. The method of claim 5,
The high potential voltage is applied to the first power line, the high potential voltage and the low potential voltage are alternately applied to the second power line, and the high potential voltage, the low potential voltage and data are alternately applied to the data line. And a voltage is applied alternately. The method of claim 6,
When setting the anode electrode to the high potential voltage, the high potential voltage is applied to the data line and the second power supply line, a scan signal for turning off the first transistor is applied to the scan line, and the Applying an emission signal to the emission line for turning on a second transistor;
When setting the anode electrode to the low potential voltage, the low potential voltage is applied to the data line and the second power supply line, a scan signal for turning off the first transistor is applied to the scan line, and And applying an emission signal for turning on a second transistor to the emission line. The method of claim 6,
And after the setting of the anode electrode, initializing the gate electrode of the driving transistor. The method of claim 8,
When initializing a gate electrode of the driving transistor, the low potential voltage is applied to the data line and the second power supply line, and a scan signal for turning on the first transistor is applied to the scan line, 2. A method of driving a display device, comprising applying an emission signal for turning on a transistor to the emission line. The method of claim 6,
And prior to making the light emitting diode emit light, initializing the anode electrode to the high potential voltage. The method of claim 10,
When the anode is initialized to the high potential voltage, the high potential voltage is applied to the data line and the second power supply line, and a scan signal for turning off the first transistor is applied to the scan line. And applying an emission signal to the emission line to turn on the second transistor. The method of claim 6,
Prior to setting the anode electrode, applying the low potential voltage to the data line to turn off the light emitting diode. The method of claim 12,
When the light emission of the light emitting diode is turned off, the low potential voltage is applied to the data line and the second power supply line, a scan signal for turning off the first transistor is applied to the scan line, and the second transistor is applied. And applying an emission signal to turn on the emission line to the emission line. The method of claim 5,
And the display device further comprises a switch for connecting neighboring data lines to each other, the switch being connected to the emission period.

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