KR20230086084A - Display device - Google Patents

Abstract

According to one embodiment of the present invention, a display device comprises: a display panel in which a plurality of sub-pixels of different colors are arranged; a data driver which supplies a plurality of data voltages to the plurality of sub-pixels through a plurality of data wires; a gate driver which supplies a plurality of gate signals to the plurality of sub-pixels through the plurality of gate wires; and a plurality of data initialization elements which initialize the plurality of data voltages to an initialization voltage according to an initialization enable signal, wherein the display device is driven separately into a plurality of initialization sections in which the plurality of data voltages are initialized to the initialization voltage and a plurality of writing sections in which the data voltages are applied to the plurality of sub-pixels, and the plurality of initialization sections and the plurality of writing sections are alternated. Accordingly, horizontal crosstalk can be prevented.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device capable of initializing data lines.

Display devices used in computer monitors, TVs, mobile phones, etc. include Organic Light Emitting Displays (OLEDs) that emit light by themselves, and Liquid Crystal Displays (LCDs) that require a separate light source. there is.

Among these various display devices, an organic light emitting display device includes a display panel including a plurality of sub-pixels and a driver that drives the display panel. The driver includes a gate driver supplying a gate signal to the display panel through a gate line and a data driver supplying a data voltage through a data line. When signals such as a gate signal and a data voltage are supplied to sub-pixels of the organic light-emitting display device, the selected sub-pixels emit light to display an image.

However, when a data voltage applied to one data line changes, ripple may occur in an adjacent data line. Accordingly, output luminance of sub-pixels connected to adjacent data lines may be distorted due to the above-described ripple. Accordingly, horizontal crosstalk may occur in the display panel due to the above-described distortion of the output luminance.

An object of the present invention is to provide a display device capable of preventing horizontal crosstalk.

Another object to be solved by the present invention is to provide a display device capable of regularly generating ripples in data lines.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a display device according to an exemplary embodiment of the present invention provides a display panel in which a plurality of sub-pixels of different colors are disposed, and a plurality of data voltages through a plurality of data wires to the plurality of sub-pixels. A data driver for supplying, a gate driver for supplying a plurality of gate signals to a plurality of sub-pixels through a plurality of gate lines, and a plurality of data initialization elements for initializing a plurality of data voltages to an initialization voltage according to an initialization enable signal. and a plurality of initialization periods in which a plurality of data voltages are initialized with initialization voltages and a plurality of write periods in which data voltages are applied to a plurality of sub-pixels, and the plurality of initialization periods and the plurality of write periods are alternately driven to horizontally Crosstalk can be prevented.

Other embodiment specifics are included in the detailed description and drawings.

In the present invention, ripples are regularly generated in data wires, so that luminance is not distorted only in certain wires, and uniformity of an image can be secured.

In the present invention, a luminance deviation due to a ripple may be reduced by initializing a data wire with an initialization voltage.

Effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a schematic diagram of a display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present invention.
3 is a waveform diagram illustrating a gate signal of a display device according to an exemplary embodiment of the present invention.
4A is a circuit diagram of a pixel of a display device according to an exemplary embodiment during an initial period.
4B is a circuit diagram of a pixel of a display device according to an exemplary embodiment during a sampling period.
4C is a circuit diagram of a pixel of a display device according to an exemplary embodiment during an emission period.
5 is a block diagram illustrating a connection relationship between sub-pixels of a display device according to an exemplary embodiment of the present invention.
6 is a waveform diagram for explaining a data initialization operation of a display device according to an exemplary embodiment of the present invention.
7 is a block diagram illustrating a connection relationship between sub-pixels of a display device according to another exemplary embodiment of the present invention.
8 is a waveform diagram for explaining a data initialization operation of a display device according to another exemplary embodiment of the present invention.
9 is a block diagram illustrating a connection relationship between sub-pixels of a display device according to another exemplary embodiment of the present invention.
10 is a circuit diagram of a sub-pixel of a display device according to another exemplary embodiment of the present invention.
11 is a waveform diagram for explaining a data initialization operation of a display device according to another exemplary embodiment of the present invention.

The advantages and features of the present invention, and how to achieve them, will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited thereto. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists', etc. mentioned in the present invention is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

When an element or layer is referred to as “on” another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or other element intervenes therebetween.

In addition, although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

The area and thickness of each component shown in the drawings is shown for convenience of description, and the present invention is not necessarily limited to the area and thickness of the illustrated component.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Transistors used in the display device of the present invention may be implemented with at least one of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor may be implemented as an oxide semiconductor transistor having an oxide semiconductor as an active layer or an LTPS transistor having low temperature poly-silicon (LTPS) as an active layer. A transistor may include at least a gate electrode, a source electrode and a drain electrode. The transistor may be implemented as a TFT (Thin Film Transistor) on the display panel. The flow of carriers in a transistor flows from the source electrode to the drain electrode. In the case of an n-channel transistor (NMOS), since electrons are carriers, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source electrode to the drain electrode. In the n-channel transistor (NMOS), the direction of current flows from the drain electrode to the source electrode, and the source electrode may be an output terminal. In the case of a p-channel transistor (PMOS), since a carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source electrode to the drain electrode. In the p-channel transistor (PMOS), since holes flow from the source electrode to the drain electrode, current flows from the source to the drain side, and the drain electrode may be an output terminal. Accordingly, it should be noted that the source and drain of the transistor are not fixed because the source and drain may change depending on the applied voltage. In this specification, it is assumed that the transistor is an n-channel transistor (NMOS), but it is not limited thereto, and a p-channel transistor may be used, and the circuit configuration may be changed accordingly.

A gate signal of a transistor used as a switch element swings between a turn on voltage and a turn off voltage. The turn-on voltage is set to a voltage higher than the threshold voltage (Vth) of the transistor, and the turn-off voltage is set to a voltage lower than the threshold voltage (Vth) of the transistor. A transistor is turned on in response to a turn on voltage, while turned off in response to a turn off voltage. In the case of NMOS, the turn-on level voltage may be a high level voltage, and the turn-off level voltage may be a low level voltage. In the case of PMOS, the turn-on level voltage may be a low-level voltage and the turn-off level voltage may be a high-level voltage.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a display device according to an exemplary embodiment of the present invention. Referring to FIG. 1 , the display device 100 includes a display panel 110 , a gate driver 120 , a data driver 130 and a timing controller 140 .

The display panel 110 is a panel for displaying an image. The display panel 110 may include various circuits, wires, and light emitting elements disposed on a substrate. The display panel 110 is divided by a plurality of data lines DL and a plurality of gate lines GL that intersect with each other, and a plurality of pixels connected to the plurality of data lines DL and the plurality of gate lines GL ( PX) may be included. The display panel 110 may include a display area defined by a plurality of pixels PX and a non-display area in which various signal wires or pads are formed. The display panel 110 may be implemented as a display panel 110 used in various display devices such as a liquid crystal display, an organic light emitting display, and an electrophoretic display. Hereinafter, the display panel 110 will be described as a panel used in an organic light emitting diode display, but is not limited thereto.

The timing controller 140 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock through a receiving circuit such as an LVDS or TMDS interface connected to the host system. The timing controller 140 generates timing control signals for controlling the data driver 130 and the gate driver 120 based on the input timing signal.

The data driver 130 supplies data voltages to the plurality of sub-pixels SP. The data driver 130 may include a plurality of source drive integrated circuits (ICs). A plurality of source drive ICs may receive digital video data and a source timing control signal from the timing controller 140 . The plurality of source driver ICs may convert digital video data into gamma voltages in response to the source timing control signal to generate data voltages and supply the data voltages through the data line DL of the display panel 110 . The plurality of source drive ICs may be connected to the data line DL of the display panel 110 through a chip on glass (COG) process or a tape automated bonding (TAB) process. In addition, the source drive ICs may be formed on the display panel 110 or may be formed on a separate PCB board and connected to the display panel 110 .

The gate driver 120 supplies a gate signal to the plurality of sub-pixels SP. The gate driver 120 may include a level shifter and a shift register. The level shifter may shift the level of a clock signal input from the timing controller 140 to a transistor-transistor-logic (TTL) level and then supply the level to the shift register. The shift register may be formed in the non-display area of the display panel 110 by the GIP method, but is not limited thereto. The shift register may include a plurality of stages shifting and outputting a gate signal in response to a clock signal and a driving signal. A plurality of stages included in the shift register may sequentially output gate signals through a plurality of output terminals. As will be described later, the gate signal may include a light emitting signal, a first scan signal, and a second scan signal.

The display panel 110 may include a plurality of sub-pixels SP. The plurality of sub-pixels SP may be sub-pixels SP for emitting light of different colors. For example, each of the plurality of sub-pixels SP may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, but is not limited thereto. The plurality of sub-pixels SP may constitute a pixel PX. That is, the red sub-pixel, the green sub-pixel, and the blue sub-pixel may constitute one pixel PX, and the display panel 110 may include a plurality of pixels PX.

Hereinafter, reference is made to FIG. 2 for a more detailed description of a driving circuit for driving one sub-pixel SP.

2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present invention. 2 illustrates a circuit diagram of one sub-pixel SP among a plurality of sub-pixels SP of the display device 100 .

Referring to FIG. 2 , each sub-pixel SP includes a light emitting element OLED, a driving transistor DT, first to sixth transistors T1 to T6, and a storage capacitor Cst.

The light emitting element OLED emits light by driving current supplied from the driving transistor DT. The anode electrode of the light emitting element OLED is connected to the fourth transistor T4 and the fifth transistor T5, and the cathode electrode of the light emitting element OLED is connected to the input terminal of the low potential voltage VSS.

The driving transistor DT controls the driving current applied to the light emitting element OLED according to its gate-source voltage Vgs. Also, the source electrode of the driving transistor DT is connected to the first node N1, the gate electrode is connected to the second node N2, and the drain electrode is connected to the second and fourth transistors T2 and T4. connected to

The first transistor T1 applies the data voltage Vdata supplied from the data line to the first node N1 that is the source electrode of the driving transistor DT. The first transistor T1 is connected to a source electrode connected to the data line, a drain electrode connected to the first node N1, and a second scan signal line transmitting the Nth first scan signal SCAN1(N). It includes a gate electrode. Accordingly, the first transistor T1 transmits the data voltage Vdata supplied from the data line to the source electrode of the driving transistor DT in response to the Nth first scan signal SCAN1(N) having a turn-on level and a low level. is applied to the first node N1.

The second transistor T2 diode-connects the gate electrode and the drain electrode of the driving transistor DT. The second transistor T2 includes a source electrode connected to the drain electrode of the driving transistor DT, a drain electrode connected to the second node N2 which is the gate electrode of the driving transistor DT, and an Nth first scan signal SCAN1. (N)) and a gate electrode connected to the second scan signal wire for transmitting. Accordingly, the second transistor T2 diode-connects the gate electrode and the drain electrode of the driving transistor DT in response to the N-th first scan signal SCAN1(N) having a turn-on level and a low level.

The third transistor T3 applies the high potential voltage VDD to the first node N1 that is the source electrode of the driving transistor DT. The third transistor T3 includes a source electrode connected to the third node N3 connected to the high potential voltage line transmitting the high potential voltage VDD, a drain electrode connected to the first node N1, and a light emitting signal ( and a gate electrode connected to a light emitting signal wire transmitting EM(N). Accordingly, the third transistor T3 applies the high potential voltage VDD to the first node N1, which is the source electrode of the driving transistor DT, in response to the light emitting signal EM(N) having a low level, which is a turn-on level. do.

The fourth transistor T4 forms a current path between the driving transistor DT and the light emitting element OLED. The fourth transistor T4 includes a source electrode connected to the drain electrode of the driving transistor DT, a drain electrode connected to the light emitting element OLED, and a gate connected to the light emitting signal line for transmitting the light emitting signal EM(N). contains electrodes. Accordingly, the fourth transistor T4 forms a current path between the drain electrode of the driving transistor DT and the light emitting element OLED in response to the emission signal EM(N).

The fifth transistor T5 applies the initialization voltage Vini to the anode electrode of the light emitting element OLED. The fifth transistor T5 includes a source electrode connected to an initialization voltage line transmitting an initialization voltage Vini, a drain electrode connected to an anode electrode of the light emitting device OLED, and an Nth first scan signal SCAN1(N). and a gate electrode connected to a second scan signal line that transmits. Accordingly, the fifth transistor T5 applies the initialization voltage Vini to the anode electrode of the light emitting element OLED in response to the Nth first scan signal SCAN1(N) having a turn-on level and a low level.

The sixth transistor T6 applies the initialization voltage Vini to the second node N2 that is the gate electrode of the driving transistor DT. The sixth transistor T6 includes a source electrode connected to the initialization voltage line transmitting the initialization voltage Vini, a drain electrode connected to the second node N2 which is the gate electrode of the driving transistor DT, and an N-1th transistor T6. and a gate electrode connected to a first scan signal line through which one scan signal SCAN1(N-1) is transmitted. Accordingly, the sixth transistor T6 applies the initialization voltage Vini to the gate electrode of the driving transistor DT in response to the N−1 th first scan signal SCAN1(N−1) of the turn-on level and low level. 2 Apply to node N2.

The storage capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3. That is, one electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor DT, and the other electrode of the storage capacitor Cst is connected to a high potential voltage wire transmitting the high potential voltage VDD.

3 is a waveform diagram illustrating a gate signal of a display device according to an exemplary embodiment of the present invention.

4A is a circuit diagram of a pixel of a display device according to an exemplary embodiment during an initial period.

4B is a circuit diagram of a pixel of a display device according to an exemplary embodiment during a sampling period.

4C is a circuit diagram of a pixel of a display device according to an exemplary embodiment during an emission period.

Referring to FIGS. 3 to 4C , driving of the display device according to an exemplary embodiment of the present invention is as follows.

And, referring to FIGS. 3 and 4A, during the initial period (Initial), the N−1 th first scan signal SCAN1(N−1) is a low level that is a turn-on level, and the N th first scan signal SCAN1 (N)) is a high level that is a turn-off level, and the emission signal EM(N) is a high level that is a turn-off level. Accordingly, the sixth transistor T6 is turned on to apply the initialization voltage Vini to the second node N2. As a result, the gate electrode of the driving transistor DT is initialized to the initialization voltage Vini. The initialization voltage Vini may be selected within a voltage range sufficiently lower than the operating voltage of the light emitting element OLED, and may be set to a voltage equal to or lower than the low potential voltage VSS. And, in the initial period (Initial), the high potential voltage (VDD) is maintained at the third node (N3).

And, referring to FIGS. 3 and 4B, during the sampling period (Sampling), the N-1 th first scan signal SCAN1 (N-1) is a high level that is a turn-off level, and the N-th first scan signal ( SCAN1(N) is a low level, which is a turn-on level, and the emission signal EM(N) is a high level, which is a turn-off level. Also, during the sampling period (Sampling), the first transistor (T1) is turned on, and the data voltage (Vdata) is applied to the first node (N1). When the second transistor T2 is also turned on, the driving transistor DT is diode-connected, and the gate electrode and drain electrode of the driving transistor DT are shorted, thereby operating the driving transistor DT like a diode.

During the sampling period Sampling, current flows between the source and drain of the driving transistor DT. Since the gate electrode and the drain electrode of the driving transistor DT are diode-connected, the voltage at the second node N2 is determined by the current flowing from the source electrode to the drain electrode, and the voltage between the gate and the source of the driving transistor DT ( Vgs) rises until Vth. During the sampling period (Sampling), the voltage of the second node (N2) is charged to a voltage (Vdata + Vth) corresponding to the sum of the data voltage (Vdata) and the threshold voltage (Vth) of the driving transistor (DT).

Meanwhile, during the sampling period (Sampling), the fifth transistor (T5) is turned on to apply the initialization voltage (Vini) to the anode electrode of the light emitting element (OLED). Also, during the sampling period (Sampling), the high potential voltage (VDD) is maintained at the third node (N3).

And, referring to FIGS. 3 and 4C, during the emission period (Emission), the N-1 th first scan signal SCAN1 (N-1) is a high level that is a turn-off level, and the N-th first scan signal SCAN1(N) is a high level, which is a turn-off level, and the emission signal EM(N) is a low level, which is a turn-on level. Accordingly, the third transistor T3 is turned on to apply the high potential voltage VDD to the first node N1. Also, the fourth transistor T4 is turned on to form a current path between the driving transistor DT and the light emitting element OLED. As a result, the driving current passing through the source and drain electrodes of the driving transistor DT is applied to the light emitting element OLED.

During the emission period, the relational expression for the drive current Iled flowing through the light emitting element OLED is as shown in Equation 1 below.

In Equation 1, k represents a proportionality constant determined by the electron mobility, parasitic capacitance, and channel capacitance of the driving transistor DT.

As shown in [Equation 1], the threshold voltage Vth component of the driving transistor DT is canceled in the relational expression of the driving current Iled. This means that the driving current Iled does not change even if the threshold voltage Vth changes in the display device according to the present invention. That is, the display device according to an embodiment of the present invention can program the data voltage regardless of the amount of change in the threshold voltage (Vth).

Hereinafter, FIG. 3 will also be referred to in order to describe the arrangement relationship of a plurality of sub-pixels.

5 is a block diagram illustrating a connection relationship between sub-pixels of a display device according to an exemplary embodiment of the present invention.

5 shows only six sub-pixels (R, G, B) arranged in a 3x2 matrix for convenience of description, and six sub-pixels (R, G, B) arranged in a 3x2 matrix in the display area. ) is repeated.

Referring to FIGS. 1 and 5 , one pixel PX includes three sub-pixels R, G, and B. For example, the pixel PX may include a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B, as shown in FIG. 5 . Also, the first sub-pixel R may be a red sub-pixel, the second sub-pixel G may be a green sub-pixel, and the third sub-pixel B may be a blue sub-pixel. However, it is not limited thereto, and a plurality of sub-pixels may be changed to various colors (Magenta, Yellow, Cyan).

Also, a plurality of sub-pixels R, G, and B of the same color may be arranged in the same column. That is, the plurality of first sub-pixels R may be disposed in the same column, the plurality of second sub-pixels G may be disposed in the same column, and the plurality of third sub-pixels B may be disposed in the same column.

In addition, the sub-pixels R, G, and B arranged in one row are connected to one gate line GL(N-1) and GL(N), so that the first scan signal SCAN1(N-1) , SCAN1(N)) can be authorized.

For example, the sub-pixels R, G, and B arranged in odd-numbered rows are connected to the N-1-th gate line GL(N-1). Accordingly, the N−1 th first scan signal SCAN1(N−1) is applied to the subpixels R, G, and B arranged in odd rows. Also, the sub-pixels R, G, and B arranged in even-numbered rows are connected to the N-th gate line GL(N). Accordingly, the N-th first scan signal SCAN1(N) is applied to the sub-pixels R, G, and B arranged in even-numbered rows.

In addition, the sub-pixels R, G, and B arranged in one row are connected to one high-potential voltage line VDDL and can receive the high-potential voltage VDD.

For example, sub-pixels R, G, and B disposed in odd-numbered rows may be connected to one high-potential voltage line VDDL and receive a high-potential voltage VDD. In addition, the sub-pixels R, G, and B arranged in even-numbered rows are connected to one high-potential voltage line VDDL and can receive the high-potential voltage VDD.

Also, the sub-pixels R, G, and B arranged in one column may be connected to one data line DL_R, DL_G, and DL_B to receive data voltages Vdata_R, Vdata_G, and Vdata_B.

The plurality of first sub-pixels R disposed in odd-numbered columns may be connected to the first data line DL_R and receive the first data voltage Vdata_R. Also, the plurality of second sub-pixels G arranged in even-numbered columns may be connected to the second data line DL_G and receive the second data voltage Vdata_G. Also, the plurality of third sub-pixels B disposed in the third column may be connected to the third data line DL_B and receive the third data voltage Vdata_B.

Further, each of the plurality of data initialization elements INI1 , INI2 , and INI3 is connected to each of the plurality of data lines DL_R , DL_G , and DL_B to initialize each of the plurality of data lines DL_R , DL_G , and DL_B.

The first data initialization element INI1 includes a gate electrode receiving the initialization enable signal INI_EN, a drain electrode receiving the initialization voltage Vini, and a source electrode connected to the first data line DL_R. Accordingly, when the initialization enable signal INI_EN has a low level, which is a turn-on level, the first data initialization element INI1 applies the initialization voltage Vini to the first data line DL_R.

The second data initialization element INI2 includes a gate electrode receiving the initialization enable signal INI_EN, a drain electrode receiving the initialization voltage Vini, and a source electrode connected to the second data line DL_G. Accordingly, when the initialization enable signal INI_EN has a low level, which is a turn-on level, the second data initialization element INI2 applies the initialization voltage Vini to the second data line DL_G.

The third data initialization element INI3 includes a gate electrode receiving the initialization enable signal INI_EN, a drain electrode receiving the initialization voltage Vini, and a source electrode connected to the third data line DL_B. Accordingly, when the initialization enable signal INI_EN has a low level, which is a turn-on level, the third data initialization element INI3 applies the initialization voltage Vini to the third data line DL_B.

6 is a waveform diagram for explaining a data initialization operation of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 6 , a display device according to an exemplary embodiment of the present invention includes a plurality of initialization periods Ti1 and Ti2 for initializing data voltages Vdata_R, Vdata_G, and Vdata_B and a plurality of data voltages Vdata_R, Vdata_G, and Vdata_B. ) may be separately driven in a plurality of writing periods Ts1 and Ts2 applied to the plurality of sub-pixels R, G, and B.

The aforementioned writing period Ts may correspond to the sampling period described with reference to FIG. 4B.

The plurality of initialization periods Ti1 and Ti2 and the plurality of writing periods Ts1 and Ts2 are alternated, the first initialization period Ti1 is disposed before the first writing period Ts1, and the second initialization period ( Ti2) may be disposed before the second writing period Ts2.

That is, as shown in FIG. 6 , the first initialization period Ti1, the first write period Ts1, the second initialization period Ti2, and the second write period Ts2 may be sequentially disposed.

In the first initialization period Ti1, the initialization enable signal INI_EN is at a low level, which is a turn-on level.

Accordingly, in the first initialization period Ti1, the first data initialization element INI1 initializes the first data line DL_R to the initialization voltage Vini, so that the first data voltage Vdata_R corresponds to the initialization voltage Vini. can be In the first initialization period Ti1, the second data initialization device INI2 initializes the second data line DL_G to the initialization voltage Vini, so that the second data voltage Vdata_G corresponds to the initialization voltage Vini. can be In the first initialization period Ti1, the third data initialization element INI3 initializes the third data line DL_B to the initialization voltage Vini, so that the third data voltage Vdata_B corresponds to the initialization voltage Vini. can be

In the subsequent first writing period Ts1, the initialization enable signal INI_EN is at a high level, which is a turn-off level, and the N-1st scan signal SCAN1 (N-1) is a low level, which is a turn-on level. am.

Accordingly, in the first writing period Ts1, the first data voltage Vdata_R representing a specific grayscale is written to the first sub-pixels R of odd-numbered rows, and the second data voltage Vdata_G representing a specific grayscale is written. ) is written into the second sub-pixels G of odd-numbered rows, and the third data voltage Vdata_B representing a specific grayscale is written into the third sub-pixels B of odd-numbered rows.

In the second initialization period Ti2, the initialization enable signal INI_EN is at a low level, which is a turn-on level.

Accordingly, in the second initialization period Ti2, the first data initialization element INI1 initializes the first data line DL_R to the initialization voltage Vini, so that the first data voltage Vdata_R corresponds to the initialization voltage Vini. can be In the second initialization period Ti2, the second data initialization element INI2 initializes the second data line DL_G to the initialization voltage Vini, so that the second data voltage Vdata_G corresponds to the initialization voltage Vini. can be In the second initialization period Ti2, the third data initialization element INI3 initializes the third data line DL_B to the initialization voltage Vini, so that the third data voltage Vdata_B corresponds to the initialization voltage Vini. can be

In the second writing period Ts2 that follows, the initialization enable signal INI_EN is at a high level, which is a turn-off level, and the N-th first scan signal SCAN1(N) is at a low level, which is a turn-on level.

Accordingly, in the second writing period Ts2, the first data voltage Vdata_R representing a specific gray level is written to the first sub-pixel R of an even-numbered row, and the second data voltage Vdata_G representing a specific gray level is written. ) is written into the second sub-pixels G of even-numbered rows, and the third data voltage Vdata_B representing a specific grayscale is written into the third sub-pixels B of odd-numbered rows.

Due to the plurality of initialization periods Ti1 and Ti2 described above, the plurality of data voltages Vdata_R, Vdata_G, and Vdata_B may be periodically initialized.

In addition, the data voltage Vdata_other may not be written to a plurality of sub-pixels to which the first scan signal of a high level, which is a turn-off level, is applied, and may be in a floating state.

Thus, the data voltage Vdata_other stored in the plurality of sub-pixels to which the first scan signal of the high level, which is the turn-off level, is applied may be affected by the aforementioned change in the data voltage. Specifically, referring to FIGS. 5 and 6 , the change in the data voltages Vdata_R, Vdata_G, and Vdata_B in the plurality of initialization periods Ti1 and Ti2 and the plurality of write periods Ts1 and Ts2 described above is the wiring capacitance (Line Cap) causes ripple in the high-potential voltage wiring (VDDL). The ripple generated in the high potential voltage line VDDL is transferred to the data voltage Vdata_other stored in a plurality of sub-pixels to which the first scan signal of the high level, which is a turn-off level, is applied.

For example, as shown in FIG. 6 , since the plurality of data voltages Vdata_R, Vdata_G, and Vdata_B are initialized to the initialization voltage Vini in the first initialization period Ti1, the first high level, which is a turn-off level, is initialized. The data voltage Vdata_other stored in the plurality of sub-pixels to which the scan signal is applied drops to the initialization voltage Vini and then gradually rises.

In the first writing period Ts1, since the plurality of data voltages Vdata_R, Vdata_G, and Vdata_B are converted into data voltages representing a specific gray level, a plurality of sub-subs to which the high-level first scan signal, which is a turn-off level, is applied. The data voltage Vdata_other stored in the pixel rises and then gradually falls.

And, since the plurality of data voltages Vdata_R, Vdata_G, and Vdata_B are initialized to the initialization voltage Vini in the second initialization period Ti2, a plurality of sub-pixels to which the high-level first scan signal, which is a turn-off level, is applied. The stored data voltage Vdata_other drops to the initialization voltage Vini and then gradually rises.

In the second writing period Ts2, since the plurality of data voltages Vdata_R, Vdata_G, and Vdata_B are converted into data voltages representing a specific gray level, a plurality of sub-subs to which the first scan signal of a high level, which is a turn-off level, is applied. The data voltage Vdata_other stored in the pixel rises and then gradually falls.

That is, the display device according to an embodiment of the present invention initializes the data voltages Vdata_R, Vdata_G, and Vdata_B in the plurality of initialization periods Ti1 and Ti2 before the plurality of write periods Ts1 and Ts2, thereby generating a turn-off level. The data voltage Vdata_other stored in the plurality of sub-pixels to which the first scan signal of the high level is applied may swing regularly.

In the case of a conventional display device, since data voltages representing specific gradations applied to a plurality of write sections are not constant, data voltages stored in a plurality of sub-pixels in a floating state swing irregularly, resulting in distortion of luminance in only certain wires. Horizontal crosstalk occurred.

However, in the display device according to an exemplary embodiment of the present invention, ripples are regularly generated in data lines, so that data voltages stored in a plurality of floating sub-pixels may swing regularly. Accordingly, the uniformity of the image can be secured by minimizing the deviation of the ripple transmitted to the plurality of pixels and not distorting the luminance of only certain wires.

In addition, the display device according to an embodiment of the present invention initializes the data voltages Vdata_R, Vdata_G, and Vdata_B in the plurality of initialization sections Ti1 and Ti2 before the plurality of write sections Ts1 and Ts2, thereby reducing the luminance deviation. can reduce

For example, the luminance deviation between 255, the maximum gray level, and 223, which is a difference of 31 gray levels, is 0.26 nit, whereas the luminance deviation between 0 and 31, the lowest gray levels, due to the initialization voltage is only 0.05 nit.

That is, when the data wires are initialized with the initialization voltage in order to implement the lowest grayscale, it can be confirmed that the luminance deviation due to the ripple is reduced.

Hereinafter, a display device according to another exemplary embodiment of the present invention will be described in detail.

Since a display device according to one embodiment of the present invention and a display device according to another embodiment of the present invention have differences in data lines and data control elements, these will be described in detail.

7 is a block diagram illustrating a connection relationship between sub-pixels of a display device according to another exemplary embodiment of the present invention.

7 shows only 6 sub-pixels (RO, GO, BO, RE, GE, BE) arranged in a 3x2 matrix for convenience of description, and 6 sub-pixels arranged in a 3x2 matrix in the display area The arrangement relationship of (RO, GO, BO, RE, GE, BE) is repeated.

1 and 7 , the pixel PX may include first sub-pixels RO and RE, second sub-pixels GO and GE, and third sub-pixels BO and BE. Also, the first sub-pixels RO and RE may be red sub-pixels, the second sub-pixels GO and GE may be green sub-pixels, and the third sub-pixels BO and BE may be blue sub-pixels. However, it is not limited thereto, and a plurality of sub-pixels may be changed to various colors (Magenta, Yellow, Cyan).

Also, a plurality of sub-pixels RO, RE, GO, GE, BO, and BE of the same color may be arranged in the same column. That is, the plurality of first sub-pixels RO and RE are arranged in the same column, the plurality of second sub-pixels GO and GE are arranged in the same column, and the plurality of third sub-pixels BO and BE are arranged in the same column. can be placed.

In addition, the sub-pixels RO, RE, GO, GE, BO, and BE disposed in one row are connected to one gate wire GL(N-1) and GL(N) to generate a first scan signal ( SCAN1(N-1), SCAN1(N)) can be authorized.

For example, the sub-pixels RO, GO, and BO disposed in odd-numbered rows are connected to the N-1-th gate line GL(N-1). Accordingly, the N−1 th first scan signal SCAN1(N−1) is applied to the subpixels RO, GO, and BO disposed in odd rows. Also, the sub-pixels RE, GE, and BE disposed in even-numbered rows are connected to the N-th gate line GL(N). Accordingly, the N-th first scan signal SCAN1(N) is applied to the sub-pixels RE, GE, and BE arranged in even-numbered rows.

Further, the sub-pixels RO, RE, GO, GE, BO, and BE disposed in one row may be connected to one high-potential voltage line VDDL and receive a high-potential voltage VDD.

For example, sub-pixels RO, GO, and BO disposed in odd-numbered rows may be connected to one high-potential voltage line VDDL and receive a high-potential voltage VDD. In addition, the sub-pixels RE, GE, and BE arranged in even-numbered rows are connected to one high-potential voltage line VDDL and may receive the high-potential voltage VDD.

Each of the plurality of data lines DL_R, DL_G, and DL_B may branch into odd data lines SDL_RO, SDL_GO, and SDL_BO and even data lines SDL_RE, SDL_GE, and SDL_BE.

That is, the first data line DL_R may branch into a first odd data line SDL_RO and a first even data line SDL_RE. Also, the second data line DL_G may branch into a second odd data line SDL_GO and a second even data line SDL_GE. Also, the third data line DL_B may branch into a third odd data line SDL_BO and a third even data line SDL_BE.

In addition, each of the plurality of odd data lines SDL_RO, SDL_GO, and SDL_BO is connected to sub-pixels RO, GO, and BO of odd-numbered rows through odd data control elements CC_RO, CC_GO, and CC_BO, and a plurality of even data Each of the wires SDL_RE, SDL_GE, and SDL_BE is connected to the sub-pixels RE, GE, and BE of even-numbered rows through the even data control elements CC_RE, CC_GE, and CC_BE.

That is, the first odd data line SDL_RO is connected to the first sub-pixel RO of an odd-numbered row through the first odd data control element CC_RO, and the second odd data line SDL_GO is connected to the second odd data line SDL_GO. The third odd data wire SDL_BO is connected to the third sub-pixels GO of odd-numbered rows through the control element CC_GO, and the third odd data line SDL_BO is connected to the third sub-pixels of odd-numbered rows through the third odd data control element CC_GO. (GO).

Further, the first even data line SDL_RE is connected to the first sub-pixel RE of an even row through the first even data control element CC_RE, and the second even data line SDL_GE is connected to the second even data line SDL_GE. The third even data line SDL_BE is connected to the third sub-pixels in the even-numbered rows through the control element CC_GE, and the third even-numbered data line SDL_BE is connected to the third sub-pixels in the even-numbered rows through the third even-numbered data control element CC_GE. (GE).

The plurality of odd data control elements (CC_RO, CC_GO, CC_BO) are turned on according to the odd data control signals (CCS_RO, CCS_GO, CCS_BO), and the data voltages (Vdata_R, Vdata_G , Vdata_B) can be applied.

The first odd data control element CC_RO includes a gate electrode receiving the first odd data control signal CCS_RO, a drain electrode connected to the first odd data line SDL_RO, and first sub-pixels RO in odd-numbered rows. It includes a source electrode connected to. Accordingly, when the first odd data control signal CCS_RO is at a low level, which is a turn-on level, the first odd data control element CC_RO generates a first data voltage Vdata_R to the first sub-pixels RO of an odd-numbered row. authorize

The second odd data control element CC_GO includes a gate electrode receiving the second odd data control signal CCS_GO, a drain electrode connected to the second odd data line SDL_GO, and second sub-pixels GO in odd-numbered rows. It includes a source electrode connected to. Accordingly, when the second odd data control signal CCS_GO is at a low level, which is a turn-on level, the second odd data control element CC_GO applies the second data voltage Vdata_G to the second sub-pixel GO of an odd-numbered row. authorize

The third odd data control element CC_BO includes a gate electrode receiving the third odd data control signal CCS_BO, a drain electrode connected to the third odd data line SDL_BO, and third sub-pixels BO in odd-numbered rows. It includes a source electrode connected to. Accordingly, when the third odd data control signal CCS_BO is at a low level that is a turn-on level, the third odd data control element CC_BO generates a third data voltage Vdata_B to the third sub-pixel BO of an odd-numbered row. authorize

The plurality of even data control elements (CC_RE, CC_GE, CC_BE) are turned on according to the even data control signals (CCS_RE, CCS_GE, CCS_BE), and the data voltages (Vdata_R, Vdata_G , Vdata_B) can be applied.

The first even data control element CC_RE includes a gate electrode receiving the first even data control signal CCS_RE, a drain electrode connected to the first even data line SDL_RE, and first sub-pixels RE in even-numbered rows. It includes a source electrode connected to. Accordingly, when the first even data control signal CCS_RE has a low level, which is a turn-on level, the first even data control element CC_RE generates a first data voltage Vdata_R to the first sub-pixel RE of an even-numbered row. authorize

The second even data control element CC_GE includes a gate electrode receiving the second even data control signal CCS_GE, a drain electrode connected to the second even data line SDL_GE, and second sub-pixels GE in even-numbered rows. It includes a source electrode connected to. Accordingly, when the second even data control signal CCS_GE has a low level, which is a turn-on level, the second even data control element CC_GE applies the second data voltage Vdata_G to the second sub-pixel GE of an even row. authorize

The third even data control element CC_BE includes a gate electrode receiving the third even data control signal CCS_BE, a drain electrode connected to the third even data line SDL_BE, and third sub-pixels BE in even-numbered rows. It includes a source electrode connected to. Accordingly, when the third even data control signal CCS_BE has a low level that is a turn-on level, the third even data control element CC_BE generates a third data voltage Vdata_B to the third sub-pixel BE of an even row. authorize

Further, each of the plurality of data initialization elements INI1, INI2, and INI3 is connected to each of the plurality of data lines DL_R, DL_G, and DL_B, and the odd data lines (connected to each of the plurality of data lines DL_R, DL_G, and DL_B) SDL_RO, SDL_GO, SDL_BO) and even data wires (SDL_RE, SDL_GE SDL_BE) can be initialized.

The first data initialization element INI1 includes a gate electrode receiving the initialization enable signal INI_EN, a drain electrode receiving the initialization voltage Vini, and a source electrode connected to the first data line DL_R. Accordingly, when the initialization enable signal INI_EN has a low level, which is a turn-on level, the first data initialization element INI1 generates an initialization voltage Vini to the first odd data line SDL_RO and the first even data line SDL_RE. ) is applied.

The second data initialization element INI2 includes a gate electrode receiving the initialization enable signal INI_EN, a drain electrode receiving the initialization voltage Vini, and a source electrode connected to the second data line DL_G. Accordingly, when the initialization enable signal INI_EN has a low level, which is a turn-on level, the second data initialization element INI2 generates an initialization voltage Vini to the second odd data line SDL_GO and the second even data line SDL_GE. ) is applied.

The third data initialization element INI3 includes a gate electrode to which the initialization enable signal INI_EN is applied, a drain electrode to which the initialization voltage Vini is applied, and a source electrode connected to the third data lines DL_BO and BE. . Accordingly, when the initialization enable signal INI_EN has a low level, which is a turn-on level, the third data initialization element INI3 generates an initialization voltage Vini to the third odd data line SDL_BO and the third even data line SDL_BE. ) is applied.

8 is a waveform diagram for explaining a data initialization operation of a display device according to another exemplary embodiment of the present invention.

In FIG. 8 , for convenience of description, the data voltages applied to the plurality of odd data wires SDL_RO, SDL_GO, and SDL_BO are collectively referred to as odd data voltages Vdata_ODD, and the data voltages applied to the plurality of even data wires SDL_RE, SDL_GE SDL_BE. will be collectively referred to as an even data voltage (Vdata_EVEN).

Referring to FIG. 8 , a display device according to another embodiment of the present invention includes a plurality of initialization periods Ti1 and Ti2 for initializing a plurality of data voltages Vdata_ODD and Vdata_EVEN and a plurality of data voltages Vdata_ODD and Vdata_EVEN. It may include a plurality of write sections Ts1 and Ts2 applied to a plurality of sub-pixels.

The aforementioned writing period Ts may correspond to the sampling period described with reference to FIG. 4B.

The plurality of initialization periods Ti1 and Ti2 and the plurality of writing periods Ts1 and Ts2 are alternated, the first initialization period Ti1 is disposed before the first writing period Ts1, and the second initialization period ( Ti2) may be disposed before the second writing period Ts2.

That is, as shown in FIG. 8 , the first initialization period Ti1, the first write period Ts1, the second initialization period Ti2, and the second write period Ts2 may be sequentially disposed.

In the first initialization period Ti1, the initialization enable signal INI_EN is at a low level, which is a turn-on level, and the plurality of odd data control signals CCS_RO, CCS_GO, and CCS_BO are at a low level, which is a turn-on level.

Accordingly, in the first initialization period Ti1, the first data initialization element INI1 initializes the first odd data line SDL_RO to the initialization voltage Vini, and the second data initialization element INI2 initializes the second odd data line SDL_RO to the initialization voltage Vini. The data line SDL_GO is initialized with the initialization voltage Vini, and the third data initialization element INI3 applies the initialization voltage Vini to the third odd data line SDL_BO. That is, in the first initialization period Ti1, the odd data voltage Vdata_ODD is the initialization voltage Vini.

In the subsequent first writing period Ts1, the initialization enable signal INI_EN is at a high level, which is a turn-off level, and the N-1st scan signal SCAN1 (N-1) is a low level, which is a turn-on level. , and the plurality of odd data control signals CCS_RO, CCS_GO, and CCS_BO are sequentially turned-on levels, which are low levels.

Accordingly, in the first writing period Ts1, the odd data voltage Vdata_ODD representing a specific grayscale is written to the first sub-pixel RO of an odd-numbered row, and then the odd data voltage Vdata_ODD representing a specific grayscale is written in the second sub-pixel GO in the odd-numbered row, and then the odd data voltage Vdata_ODD is written in the third sub-pixel BO in the odd-numbered row.

However, since the plurality of even data control signals CCS_RE, CCS_GE, and CCS_BE have a high level that is a turn-off level in the first initialization period Ti1 and the first writing period Ts1, the plurality of even data lines SDL_RE and SDL_GE SDL_BE) may be in a floating state. Accordingly, the even data voltage Vdata_EVEN is affected by the odd data voltage change Vdata_ODD.

Since the odd data voltage change Vdata_ODD is initialized to the initialization voltage in the first initialization period Ti1, the even data voltage Vdata_EVEN drops to the initialization voltage Vini and then gradually rises.

In the first writing period Ts1, since the odd data voltage change Vdata_ODD is sequentially transitioned to express a specific gray level, the even data voltage Vdata_EVEN repeats a waveform that rises and then gradually falls.

In the second initialization period Ti2 , the initialization enable signal INI_EN has a low level, which is a turn-on level, and the plurality of even data control signals CCS_RE, CCS_GE, and CCS_BE have a low level, which is a turn-on level.

Accordingly, in the second initialization period Ti2, the first data initialization element INI1 initializes the first even data line SDL_RE to the initialization voltage Vini, and the second data initialization element INI2 initializes the second even data line SDL_RE. The data line SDL_GE is initialized with the initialization voltage Vini, and the third data initialization element INI3 applies the initialization voltage Vini to the third even data line SDL_BE. That is, in the second initialization period Ti2 , the even data voltage Vdata_EVEN is the initialization voltage Vini.

In the following second writing period Ts2, the initialization enable signal INI_EN is at a high level, which is a turn-off level, the N-th first scan signal SCAN1(N) is at a low level, which is a turn-on level, and a plurality of The even data control signals CCS_RE, CCS_GE, and CCS_BE are low levels that are turn-on levels sequentially.

Accordingly, in the second writing period Ts2, the even data voltage Vdata_EVEN representing a specific grayscale is written to the first sub-pixel RE of an even-numbered row, and then the even data voltage Vdata_EVEN representing a specific grayscale is written to the second sub-pixel GE of an even-numbered row, and then the even data voltage Vdata_EVEN representing a specific grayscale is written to the third sub-pixel B of an even-numbered row.

However, since the plurality of odd data control signals CCS_RO, CCS_GO, and CCS_BO have a high level that is a turn-off level in the second writing period Ts2 and the second writing period Ts2, the plurality of odd data wires SDL_RO and SDL_GO , SDL_BO) may be in a floating state. Accordingly, the odd data voltage Vdata_ODD is affected by the even data voltage Vdata_EVEN.

Since the even data voltage Vdata_EVEN is initialized to the initialization voltage in the second initialization period Ti2, the odd data voltage Vdata_ODD drops to the initialization voltage and then gradually rises.

In the second writing period Ts2, since the even data voltage Vdata_EVEN is sequentially transitioned to express a specific gray level, the odd data voltage Vdata_ODD repeats a rising and then gradually falling waveform.

That is, the display device according to another embodiment of the present invention regularly swings the data voltages of adjacent data lines by initializing the data voltages in the plurality of initialization sections Ti1 and Ti2 before the plurality of write sections Ts1 and Ts2. can make it

Accordingly, in the display device according to another embodiment of the present invention, ripples are regularly generated in the data lines, so that data voltages stored in a plurality of sub-pixels disposed in different rows may swing regularly. Accordingly, by canceling the deviation of ripples transmitted to a plurality of pixels, the uniformity of the image can be secured without distorting the luminance of only certain wires.

In addition, the display device according to another embodiment of the present invention initializes the data voltages Vdata_R, Vdata_G, and Vdata_B in the plurality of initialization sections Ti1 and Ti2 before the plurality of write sections Ts1 and Ts2, thereby reducing the luminance deviation. can reduce

Hereinafter, a display device according to another embodiment of the present invention will be described in detail.

Since a display device according to another embodiment of the present invention and a display device according to another embodiment of the present invention have differences in arrangement of data initialization elements, this will be described in detail.

9 is a block diagram illustrating a connection relationship between sub-pixels of a display device according to another exemplary embodiment of the present invention.

9 shows only 6 sub-pixels (RO, GO, BO, RE, GE, BE) arranged in a 3x2 matrix for convenience of explanation, and 6 sub-pixels arranged in a 3x2 matrix in the display area The arrangement relationship of (RO, GO, BO, RE, GE, BE) is repeated.

1 and 9 , the pixel PX may include first sub-pixels RO and RE, second sub-pixels GO and GE, and third sub-pixels BO and BE. Also, the first sub-pixels RO and RE may be red sub-pixels, the second sub-pixels GO and GE may be green sub-pixels, and the third sub-pixels BO and BE may be blue sub-pixels. However, it is not limited thereto, and a plurality of sub-pixels may be changed to various colors (Magenta, Yellow, Cyan).

Also, a plurality of sub-pixels RO, RE, GO, GE, BO, and BE of the same color may be arranged in the same column. That is, the plurality of first sub-pixels RO and RE are arranged in the same column, the plurality of second sub-pixels GO and GE are arranged in the same column, and the plurality of third sub-pixels BO and BE are arranged in the same column. can be placed.

In addition, the sub-pixels RO, RE, GO, GE, BO, and BE disposed in one row are connected to one gate wire GL(N-1) and GL(N) to generate a first scan signal ( SCAN1(N-1) and SCAN1(N) and second scan signals SCAN1(N-1) and SCAN2(N) may be applied.

For example, the sub-pixels RO, GO, and BO disposed in odd-numbered rows are connected to the N-1-th gate line GL(N-1). Accordingly, the N-1 th first scan signal SCAN1(N-1) and the N-1 th second scan signal SCAN2(N-1) are applied to the sub-pixels RO, GO, BO arranged in odd-numbered rows. ) is authorized. Also, the sub-pixels RE, GE, and BE disposed in even-numbered rows are connected to the N-th gate line GL(N). Accordingly, the N-th first scan signal SCAN1(N) and the N-th second scan signal SCAN2(N) are applied to the sub-pixels RE, GE, and BE arranged in even-numbered rows.

In addition, as shown in FIG. 9 , in the display device according to another embodiment of the present invention, the sub-pixels RE, GE, and BE disposed in even-numbered rows also include the N−1-th gate wire GL(N-1 )) can be connected to Accordingly, the N-1 th first scan signal SCAN-11(N-1) and the N-1 th second scan signal SCAN-12( N-1)) may be applied, but the connection relationship between the sub-pixel and the gate line may be variously changed according to the circuit structure of the sub-pixel.

Further, the sub-pixels RO, RE, GO, GE, BO, and BE disposed in one row may be connected to one high-potential voltage line VDDL and receive a high-potential voltage VDD.

For example, sub-pixels RO, GO, and BO disposed in odd-numbered rows may be connected to one high-potential voltage line VDDL and receive a high-potential voltage VDD. In addition, the sub-pixels RE, GE, and BE arranged in even-numbered rows are connected to one high-potential voltage line VDDL and may receive the high-potential voltage VDD.

Each of the plurality of data lines DL_R, DL_G, and DL_B may branch into odd data lines SDL_RO, SDL_GO, and SDL_BO and even data lines SDL_RE, SDL_GE, and SDL_BE.

That is, the first data line DL_R may branch into a first odd data line SDL_RO and a first even data line SDL_RE. Also, the second data line DL_G may branch into a second odd data line SDL_GO and a second even data line SDL_GE. Also, the third data line DL_B may branch into a third odd data line SDL_BO and a third even data line SDL_BE.

In addition, each of the plurality of odd data lines SDL_RO, SDL_GO, and SDL_BO is connected to sub-pixels RO, GO, and BO of odd-numbered rows through odd data control elements CC_RO, CC_GO, and CC_BO, and a plurality of even data Each of the wires SDL_RE, SDL_GE, and SDL_BE is connected to the sub-pixels RE, GE, and BE of even-numbered rows through the even data control elements CC_RE, CC_GE, and CC_BE.

That is, the first odd data line SDL_RO is connected to the first sub-pixel RO of an odd-numbered row through the first odd data control element CC_RO, and the second odd data line SDL_GO is connected to the second odd data line SDL_GO. The third odd data wire SDL_BO is connected to the third sub-pixels GO of odd-numbered rows through the control element CC_GO, and the third odd data line SDL_BO is connected to the third sub-pixels of odd-numbered rows through the third odd data control element CC_GO. (GO).

Further, the first even data line SDL_RE is connected to the first sub-pixel RE of an even row through the first even data control element CC_RE, and the second even data line SDL_GE is connected to the second even data line SDL_GE. The third even data line SDL_BE is connected to the third sub-pixels in the even-numbered rows through the control element CC_GE, and the third even-numbered data line SDL_BE is connected to the third sub-pixels in the even-numbered rows through the third even-numbered data control element CC_GE. (GE).

The plurality of odd data control elements (CC_RO, CC_GO, CC_BO) are turned on according to the odd data control signals (CCS_RO, CCS_GO, CCS_BO), and the data voltages (Vdata_R, Vdata_G , Vdata_B) can be applied.

The first odd data control element CC_RO includes a gate electrode receiving the first odd data control signal CCS_RO, a drain electrode connected to the first odd data line SDL_RO, and first sub-pixels RO in odd-numbered rows. It includes a source electrode connected to. Accordingly, when the first odd data control signal CCS_RO is at a low level, which is a turn-on level, the first odd data control element CC_RO generates a first data voltage Vdata_R to the first sub-pixels RO of an odd-numbered row. authorize

The second odd data control element CC_GO includes a gate electrode receiving the second odd data control signal CCS_GO, a drain electrode connected to the second odd data line SDL_GO, and second sub-pixels GO in odd-numbered rows. It includes a source electrode connected to. Accordingly, when the second odd data control signal CCS_GO is at a low level, which is a turn-on level, the second odd data control element CC_GO applies the second data voltage Vdata_G to the second sub-pixel GO of an odd-numbered row. authorize

The third odd data control element CC_BO includes a gate electrode receiving the third odd data control signal CCS_BO, a drain electrode connected to the third odd data line SDL_BO, and third sub-pixels BO in odd-numbered rows. It includes a source electrode connected to. Accordingly, when the third odd data control signal CCS_BO is at a low level that is a turn-on level, the third odd data control element CC_BO generates a third data voltage Vdata_B to the third sub-pixel BO of an odd-numbered row. authorize

The plurality of even data control elements (CC_RE, CC_GE, CC_BE) are turned on according to the even data control signals (CCS_RE, CCS_GE, CCS_BE), and the data voltages (Vdata_R, Vdata_G , Vdata_B) can be applied.

The first even data control element CC_RE includes a gate electrode receiving the first even data control signal CCS_RE, a drain electrode connected to the first even data line SDL_RE, and first sub-pixels RE in even-numbered rows. It includes a source electrode connected to. Accordingly, when the first even data control signal CCS_RE has a low level, which is a turn-on level, the first even data control element CC_RE generates a first data voltage Vdata_R to the first sub-pixel RE of an even-numbered row. authorize

The second even data control element CC_GE includes a gate electrode receiving the second even data control signal CCS_GE, a drain electrode connected to the second even data line SDL_GE, and second sub-pixels GE in even-numbered rows. It includes a source electrode connected to. Accordingly, when the second even data control signal CCS_GE has a low level, which is a turn-on level, the second even data control element CC_GE applies the second data voltage Vdata_G to the second sub-pixel GE of an even row. authorize

The third even data control element CC_BE includes a gate electrode receiving the third even data control signal CCS_BE, a drain electrode connected to the third even data line SDL_BE, and third sub-pixels BE in even-numbered rows. It includes a source electrode connected to. Accordingly, when the third even data control signal CCS_BE has a low level that is a turn-on level, the third even data control element CC_BE generates a third data voltage Vdata_B to the third sub-pixel BE of an even row. authorize

However, in another embodiment of the present invention, a plurality of data lines are disposed inside a plurality of sub-pixels instead of being connected to data initialization elements. Hereinafter, sub-pixels of a display device according to another exemplary embodiment of the present invention will be described with reference to FIG. 10 .

10 is a circuit diagram of a sub-pixel of a display device according to another exemplary embodiment of the present invention.

Referring to FIG. 10 , each sub-pixel SP includes a light emitting element OLED, a driving transistor DT, first to sixth transistors T1 to T6, and a storage capacitor Cst. , and further includes a data initialization element (INI). That is, a data initialization element INI may be disposed in each of the plurality of sub-pixels SP.

The data initialization element INI includes a gate electrode to which the N-1 second scan signal SCAN2(N-1) is applied, a drain electrode to which the initialization voltage Vini is applied, and a data wire to which the data voltage Vdata is applied. and a source electrode connected to (DL). Accordingly, when the initialization enable signal INI_EN is at a low level, which is a turn-on level, the data initialization element INI initializes the data voltage Vdata to the initialization voltage Vini.

The aforementioned data wires may correspond to the odd data wires SDL_RO, SDL_GO, and SDL_BO and the even data wires SDL_RE, SDL_GE, and SDL_BE described in FIG. 9 . Also, the aforementioned N−1 th second scan signal SCAN2(N−1) and the N th second scan signal SCAN2(N) described later may correspond to an initialization enable signal.

11 is a waveform diagram for explaining a data initialization operation of a display device according to another exemplary embodiment of the present invention.

In FIG. 11, for convenience of description, data voltages applied to the plurality of odd data lines SDL_RO, SDL_GO, and SDL_BO are collectively referred to as odd data voltages Vdata_ODD, and data voltages applied to the plurality of even data lines SDL_RE, SDL_GE SDL_BE. will be collectively referred to as an even data voltage (Vdata_EVEN).

Referring to FIG. 11 , a display device according to another embodiment of the present invention includes a plurality of initialization sections Ti1 and Ti2 for initializing a plurality of data voltages Vdata_ODD and Vdata_EVEN, and a plurality of data voltages Vdata_ODD and Vdata_EVEN. A plurality of write sections Ts1 and Ts2 applied to the plurality of sub-pixels may be included.

The aforementioned writing period Ts may correspond to the sampling period described with reference to FIG. 4B.

The plurality of initialization periods Ti1 and Ti2 and the plurality of writing periods Ts1 and Ts2 are alternated, the first initialization period Ti1 is disposed before the first writing period Ts1, and the second initialization period ( Ti2) may be disposed before the second writing period Ts2.

That is, as shown in FIG. 11 , the first initialization period Ti1, the first write period Ts1, the second initialization period Ti2, and the second write period Ts2 may be sequentially arranged.

In the first initialization period Ti1, the N-1 th second scan signal SCAN2 (N-1) corresponding to the initialization enable signal is a low level that is a turn-on level, and a plurality of odd data control signals CCS_RO and CCS_GO , CCS_BO) is a high level that is a turn-off level.

Accordingly, in the first initialization period Ti1 , the data initialization device INI initializes the odd data voltage Vdata_ODD applied to the plurality of odd data lines SDL_RO, SDL_GO, and SDL_BO to the initialization voltage Vini.

In the following first writing period Ts1, the N-1 th first scan signal SCAN1(N-1) is a low level that is a turn-on level, and the plurality of odd data control signals CCS_RO, CCS_GO, and CCS_BO sequentially is a low level that is a turn-on level, and the second scan signal (SCAN2(N-1)) corresponding to the initialization enable signal is a high level that is a turn-off level.

Accordingly, in the first writing period Ts1, the odd data voltage Vdata_ODD representing a specific grayscale is written to the first sub-pixel RO of an odd-numbered row, and then the odd data voltage Vdata_ODD representing a specific grayscale is written in the second sub-pixel GO in the odd-numbered row, and then the odd data voltage Vdata_ODD is written in the third sub-pixel BO in the odd-numbered row.

However, since the plurality of even data control signals CCS_RE, CCS_GE, and CCS_BE have a high level that is a turn-off level in the first initialization period Ti1 and the first writing period Ts1, the plurality of even data lines SDL_RE and SDL_GE SDL_BE) may be in a floating state. Accordingly, the even data voltage Vdata_EVEN is affected by the odd data voltage change Vdata_ODD.

Since the odd data voltage change Vdata_ODD is initialized to the initialization voltage in the first initialization period Ti1, the even data voltage Vdata_EVEN drops to the initialization voltage Vini and then gradually rises.

In the first writing period Ts1, since the odd data voltage change Vdata_ODD is sequentially transitioned to express a specific gray level, the even data voltage Vdata_EVEN repeats a waveform that rises and then gradually falls.

In the second initialization period Ti2, the N-th second scan signal SCAN2(N) corresponding to the next initialization enable signal is a low level that is a turn-on level, and a plurality of even data control signals CCS_RE, CCS_GE, and CCS_BE This is the high level, which is the turn-off level.

Accordingly, in the second initialization period Ti2 , the data initialization element INI initializes the even data voltage Vdata_EVEN applied to the plurality of even data lines SDL_RE, SDL_GE, and SDL_BE to the initialization voltage Vini.

In the following second writing period Ts2, the Nth first scan signal SCAN1(N) is a low level that is a turn-on level, and the plurality of even data control signals CCS_RE, CCS_GE, and CCS_BE are sequentially turned-on levels. It is a low level, and the Nth second scan signal SCAN2(N) corresponding to the next initialization enable signal is a high level, which is a turn-off level.

Accordingly, in the second writing period Ts2, the even data voltage Vdata_EVEN representing a specific grayscale is written to the first sub-pixel RE of an even-numbered row, and then the even data voltage Vdata_EVEN representing a specific grayscale is written to the second sub-pixel GE of an even-numbered row, and then the even data voltage Vdata_EVEN representing a specific grayscale is written to the third sub-pixel B of an even-numbered row.

However, since the plurality of odd data control signals CCS_RO, CCS_GO, and CCS_BO have a high level that is a turn-off level in the second writing period Ts2 and the second writing period Ts2, the plurality of odd data wires SDL_RO and SDL_GO , SDL_BO) may be in a floating state. Accordingly, the odd data voltage Vdata_ODD is affected by the even data voltage Vdata_EVEN.

Since the even data voltage Vdata_EVEN is initialized to the initialization voltage in the second initialization period Ti2, the odd data voltage Vdata_ODD drops to the initialization voltage and then gradually rises.

In the second writing period Ts2, since the even data voltage Vdata_EVEN is sequentially transitioned to express a specific gray level, the odd data voltage Vdata_ODD repeats a rising and then gradually falling waveform.

That is, in the display device according to another embodiment of the present invention, the data voltages of adjacent data lines are regularly adjusted by initializing the data voltages in the plurality of initialization sections Ti1 and Ti2 before the plurality of write sections Ts1 and Ts2. can swing

Accordingly, in the display device according to another embodiment of the present invention, ripples are regularly generated in the data lines, so that data voltages stored in a plurality of sub-pixels disposed in different rows may swing regularly. Accordingly, by canceling the deviation of ripples transmitted to a plurality of pixels, the uniformity of the image can be secured without distorting the luminance of only certain wires.

In addition, the display device according to another embodiment of the present invention initializes the data voltages Vdata_R, Vdata_G, and Vdata_B in the plurality of initialization sections Ti1 and Ti2 before the plurality of writing sections Ts1 and Ts2, thereby resulting in a luminance deviation. can reduce

A display device according to embodiments of the present invention can be described as follows.

A display device according to an exemplary embodiment of the present invention includes a display panel in which a plurality of sub-pixels of different colors are disposed, a data driver supplying a plurality of data voltages to the plurality of sub-pixels through a plurality of data lines, and a plurality of sub-pixels. a gate driver for supplying a plurality of gate signals through a plurality of gate wires, and a plurality of data initialization elements for initializing a plurality of data voltages to an initialization voltage according to an initialization enable signal, wherein the plurality of data voltages are the initialization voltages. A plurality of initialization periods initialized with , and a plurality of write periods in which data voltages are applied to a plurality of sub-pixels are separately driven, and the plurality of initialization periods and the plurality of write periods are alternated to prevent horizontal crosstalk. there is.

According to another feature of the present invention, each of the plurality of data initialization elements may be connected to each of the plurality of data lines to initialize the plurality of data voltages to the initialization voltage.

According to another feature of the present invention, the plurality of data initialization elements include a first data initialization element, a second data initialization element, and a third data initialization element, and a plurality of data lines are connected to a plurality of sub-pixels of different colors. and a first data line, a second data line, and a third data line, wherein the first data initialization element applies an initialization voltage to the first data line while the initialization enable signal is at a turn-on level, and the second data initialization element may apply an initialization voltage to the second data line while the initialization enable signal is at a turn-on level, and the third data initialization device may apply an initialization voltage to the first data line while the initialization enable signal is at a turn-on level.

According to another feature of the present invention, each of the plurality of data wires is branched into an odd data wire and an even data wire, the odd data wire is connected to sub-pixels in an odd row through an odd data control element, and the even data wire is It may be connected to sub-pixels of even-numbered rows through an even data control element.

According to another feature of the present invention, the odd data control element may be controlled according to the odd data control signal, and the even data control element may be controlled according to the even data control signal.

According to another feature of the present invention, the plurality of initialization sections include a first initialization section and a second initialization section, the plurality of write sections include a first write section and a second write section, and the first initialization section includes It may be disposed before the first write period, and the second initialization period may be disposed before the second write period.

According to another feature of the present invention, in the first initialization period, the initialization enable signal is at a turn-on level, the odd data control signal is at a turn-on level, and the plurality of data initialization elements apply an initialization voltage to the plurality of odd data lines. can

According to another feature of the present invention, in the first writing period, the initialization enable signal is at a turn-off level, the odd data control signal is at a turn-on level, and a plurality of data voltages can be written to sub-pixels of odd-numbered rows. .

According to another feature of the present invention, in the second initialization period, the initialization enable signal is at a turn-on level, the even data control signal is at a turn-on level, and the plurality of data initialization elements apply an initialization voltage to a plurality of even data lines. can

According to another feature of the present invention, in the second writing period, the initialization enable signal is at a turn-off level, the even data control signal is at a turn-on level, and a plurality of data voltages can be written to sub-pixels of even-numbered rows. .

According to another feature of the present invention, each of a plurality of data initialization elements may be embedded in a plurality of sub-pixels.

According to another feature of the present invention, in the first initialization period, the initialization enable signal is at a turn-on level, the odd data control signal is at a turn-off level, and the plurality of data initialization elements apply an initialization voltage to a plurality of odd data lines. can do.

According to another feature of the present invention, in the first writing period, the initialization enable signal is at a turn-off level, the odd data control signal is at a turn-on level, and a plurality of data voltages are written to sub-pixels in odd-numbered rows. Device.

According to another feature of the present invention, in the second initialization period, the initialization enable signal is at a turn-on level, the even data control signal is at a turn-off level, and the plurality of data initialization elements apply an initialization voltage to a plurality of even data lines. can do.

According to another feature of the present invention, in the second writing period, the initialization enable signal is at a turn-off level, the even data control signal is at a turn-on level, and a plurality of data voltages can be written to sub-pixels of even-numbered rows. .

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: gate driver
130: data driving unit
140: timing controller
150: light emitting element
PX: pixels
SP: sub pixel
R, RO, RE: first sub-pixel
G, GO, GE: second sub-pixel
B, BO, BE: third sub-pixel
DL: data wire
GL: gate wiring
T1, T2, T3, T4, T5, T6: Transistors
DT: drive transistor
Cst: storage capacitor
N1: first node
N2: second node
N3: third node
Vdata: data voltage
SCAN1: first scan signal
SCAN2: second scan signal
EM: luminous signal
INI: data initialization element
INI_EN: initialization enable signal
Vini: initialization voltage
Ti1: first initialization period
Ti2: Second initialization period
Ts1: first entry period
Ts2: Second entry period
CC_RO, CC_GO, CC_BO: Odd data control element
CC_RE, CC_GE, CC_BE: Even data control elements
CCS_RO, CCS_GO, CCS_BO: odd data control signal
CCS_RE, CCS_GE, CCS_BE: Even data control signals
SDL_RO, SDL_GO, SDL_BO: odd data wiring
SDL_RE, SDL_GE, SDL_BE: Even data wiring

Claims (15)

a display panel on which a plurality of sub-pixels of different colors are disposed;
a data driver supplying a plurality of data voltages to the plurality of sub-pixels through a plurality of data lines;
a gate driver supplying a plurality of gate signals to the plurality of sub-pixels through a plurality of gate lines;
a plurality of data initialization elements configured to initialize the plurality of data voltages to an initialization voltage according to an initialization enable signal;
separate driving into a plurality of initialization periods in which the plurality of data voltages are initialized to the initialization voltages and a plurality of write periods in which the data voltages are applied to the plurality of sub-pixels;
The plurality of initialization sections and the plurality of write sections are alternated. According to claim 1,
wherein each of the plurality of data initialization elements is connected to each of the plurality of data lines to initialize the plurality of data voltages to the initialization voltage. According to claim 2,
The plurality of data initialization elements
a first data initialization element, a second data initialization element, and a third data initialization element;
The plurality of data lines include first data lines, second data lines, and third data lines connected to a plurality of sub-pixels of different colors;
The first data initialization element applies the initialization voltage to the first data line while the initialization enable signal is at a turn-on level;
The second data initialization element applies the initialization voltage to the second data line while the initialization enable signal is at a turn-on level;
wherein the third data initialization element applies the initialization voltage to the first data line while the initialization enable signal is at a turn-on level. According to claim 2,
Each of the plurality of data wires is branched into an odd data wire and an even data wire,
The odd data wires are connected to sub-pixels in odd-numbered rows through odd data control elements;
wherein the even data lines are connected to sub-pixels of even-numbered rows through even-numbered data control elements. According to claim 4,
The odd data control element is controlled according to an odd data control signal;
The even data control element is controlled according to an even data control signal. According to claim 5,
The plurality of initialization intervals include a first initialization interval and a second initialization interval,
The plurality of write sections include a first write section and a second write section,
The first initialization period is disposed before the first writing period;
The second initialization period is disposed before the second writing period. According to claim 6,
In the first initialization period,
The initialization enable signal is a turn-on level,
The odd data control signal is a turn-on level,
The plurality of data initialization elements apply an initialization voltage to a plurality of odd data lines. According to claim 6,
In the first writing section,
The initialization enable signal is a turn-off level,
The odd data control signal is a turn-on level,
wherein the plurality of data voltages are written to the sub-pixels of the odd-numbered rows. According to claim 6,
In the second initialization period,
The initialization enable signal is a turn-on level,
The even data control signal has a turn-on level,
The plurality of data initialization elements apply an initialization voltage to a plurality of even data lines. According to claim 6,
In the second writing section,
The initialization enable signal is a turn-off level,
The even data control signal has a turn-on level,
wherein the plurality of data voltages are written to the sub-pixels of the even-numbered rows. According to claim 6,
Each of the plurality of data initialization elements is embedded in the plurality of sub-pixels. According to claim 11,
In the first initialization period,
The initialization enable signal is a turn-on level,
The odd data control signal is a turn-off level,
The plurality of data initialization elements apply an initialization voltage to a plurality of odd data lines. According to claim 11,
In the first writing section,
The initialization enable signal is a turn-off level,
The odd data control signal is a turn-on level,
wherein the plurality of data voltages are written to the sub-pixels of the odd-numbered rows. According to claim 11,
In the second initialization period,
The initialization enable signal is a turn-on level,
The even data control signal is a turn-off level,
The plurality of data initialization elements apply an initialization voltage to a plurality of even data lines. According to claim 11,
In the second writing section,
The initialization enable signal is a turn-off level,
The even data control signal has a turn-on level,
wherein the plurality of data voltages are written to the sub-pixels of the even-numbered rows.

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