KR20200078995A - Display Device - Google Patents

Abstract

A display device of the present invention includes: a first subpixel group including a pair of subpixels disposed adjacent each other in a vertical direction and sharing a first node to which a data voltage is inputted; a second subpixel group including a pair of subpixels which are disposed adjacent to the first subpixel group in a horizontal direction and disposed adjacent to each other in a vertical direction to share a second node to which a data voltage is inputted; a data line disposed between the first subpixel group and the second subpixel group; a first switch for controlling a connection between the first node and the data line; and a second switch controlling a connection between the second node and the data line. Therefore, the invention provides the display device capable of reducing the number of the data lines.

Description

Display Device

The present invention relates to a display device.

The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as "light emitting device") that emits light by itself, and has a fast response speed, high light emission efficiency, high brightness, and a wide viewing angle.

The organic light emitting display device arranges the subpixels including the light emitting elements in a matrix form and adjusts the luminance of the subpixels according to the gradation of image data. Each of the sub-pixels includes a driving thin film transistor (TFT) that controls a driving current input to the light emitting device according to its gate-source voltage (Vgs). The light emission amount of the light emitting element is proportional to the driving current, and the display gray level is controlled by the light emission amount.

Such a display device includes a data drive IC that supplies a data voltage to each subpixel. As the number of data lines supplying a data voltage to a subpixel increases, the number of output pins of the data drive IC increases. There is a problem in that the more the number of output pins, the higher the price of the data drive IC and the process cost for forming the data lines. Accordingly, research is being conducted to reduce the number of data lines.

An object of the present invention is to provide a display device capable of reducing the number of data lines.

A display device according to an exemplary embodiment of the present invention includes: a first sub-pixel group including a pair of sub-pixels arranged adjacent to each other in a vertical direction and sharing a first node to which data voltage is input; A second sub-pixel group including a pair of sub-pixels arranged adjacent to the first sub-pixel group in a horizontal direction and adjacently arranged in a vertical direction to share a second node to which a data voltage is input; A data line disposed between the first sub-pixel group and the second sub-pixel group; A first switch for controlling the connection between the first node and the data line; And a second switch for controlling the connection between the second node and the data line.

The first sub-pixel group receives the data voltage applied through the data line in response to the turn-on operation of the first switch, and the second sub-pixel group corresponds to the turn-on operation of the first switch. The applied data voltage can be supplied through the line.

The pair of sub-pixels included in the first sub-pixel group and the pair of sub-pixels included in the second sub-pixel group may both receive data voltages at different times.

The pair of sub-pixels included in the first sub-pixel group and the pair of sub-pixels included in the second sub-pixel group may be supplied with different data voltages at a period of one horizontal time.

The first subpixel included in the first subpixel group is supplied with a first data voltage at a first horizontal time, and the second subpixel included in the second subpixel group is a second data voltage at a second horizontal time. Is supplied, the third sub-pixel included in the first sub-pixel group is supplied with a third data voltage at a third horizontal time, and the fourth sub-pixel included in the second sub-pixel group is at a fourth horizontal time. Display device receiving the fourth data voltage.

The first subpixel may emit light at the same time as the second subpixel, and the third subpixel may emit light at the same time as the fourth subpixel.

Each of the first sub-pixel to the fourth sub-pixel may include a switch TFT that is switched to transmit the data voltage and may remain turned on for 2 horizontal hours.

The first switch and the second switch may be turned on alternately twice for 4 horizontal hours.

The subpixel may include a first switch TFT having a gate electrode connected to a scan line and a first electrode connected to the first node or the second node; A driving TFT having a gate electrode connected to a second electrode of the first switch TFT and a first electrode connected to a first power line; A capacitor having one end connected to the second electrode of the first switch TFT and the gate electrode of the driving TFT and the other end connected to the second electrode of the driving TFT; And a light emitting device having a second electrode of the driving TFT and an anode electrode connected to the other end of the capacitor and a cathode electrode connected to a second power line.

The subpixel may include a second switch TFT having a gate electrode connected to the scan line, a first electrode connected to a second electrode of the driving TFT, and an anode electrode of the light emitting device, and a second electrode connected to a sensing line. Can.

The display device according to the present invention provides a pixel array structure and a driving method for driving four sub-pixels receiving different data voltages into one data line. Accordingly, the number of data lines is minimized, thereby reducing the production cost of the display device and shortening the process time.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.
2 is a schematic circuit diagram of a subpixel.
3 is a diagram illustrating a part of a pixel array of a display device according to an exemplary embodiment of the present invention.
4 is a driving waveform diagram of the pixel array of FIG. 3.
5A and 5B are equivalent circuits and driving waveform diagrams of a pixel array corresponding to a first horizontal time t1.
6A and 6B are equivalent circuits and driving waveform diagrams of a pixel array corresponding to the second horizontal time t2.
7A and 7B are equivalent circuits and driving waveform diagrams of a pixel array corresponding to the third horizontal time t3.
8A and 8B are equivalent circuits and driving waveform diagrams of the pixel array corresponding to the fourth horizontal time t4.
9 is a diagram illustrating a pin-map of a data drive IC of a display device according to an embodiment of the present invention.
10 is a view showing a pin-map of a data drive IC of a display device according to a comparative example.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the present embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person having the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. When'include','have','consist of', etc. mentioned in this specification are used, other parts may be added unless'~ only' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship of the two parts is described as'~ on','~ on top','~ on the bottom','~ next to', etc.,'right' Alternatively, one or more other parts may be located between the two parts unless'direct' is used.

In the description of the embodiments, the first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be the second component within the technical spirit of the present invention.

The same reference numerals refer to the same components throughout the specification.

Each of the features of the various embodiments of the present invention may be partially or wholly combined with or combined with each other, technically various interlocking and driving may be possible, and each of the embodiments may be independently implemented with respect to each other or may be implemented together in an association relationship. It might be.

In the electroluminescent display device of the present invention, the pixel circuit may include one or more of an n-channel transistor and a p-channel transistor. Transistors may be implemented with an oxide semiconductor thin film transistor (TFT), an LTPS TFT including a low temperature polysilicon (LTPS). Further, each of the transistors can be implemented with a p-channel TFT or an n-channel TFT. In the embodiment, the transistors of the pixel circuit are mainly described as an example implemented with a p-channel TFT, but the present invention is not limited thereto.

Transistors are three-electrode devices, including gates, sources, and drains. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which a carrier is driven out of the transistor. In the transistor, the carrier flows from source to drain. In the case of an n-channel transistor, since the carrier is electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In n-channel transistors, the direction of current flows from drain to source. In the case of the p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may be changed according to the applied voltage. Therefore, the invention is not limited due to the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal swings between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate on voltage, while it is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage (VGL), and the gate-off voltage may be a gate high voltage (VGH).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following embodiments, the electroluminescent display device is mainly described, but is not limited to, an organic light emitting display device including an organic light emitting material.

Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the subject matter of the present specification, the detailed description will be omitted.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the display device includes an image processing unit 110, a timing control unit 120, a scan driving unit 130, a data driving unit 140, a power supply unit 180, and a display panel 150.

The image processing unit 110 outputs a data signal DATA and a data enable signal DE supplied from the outside. In addition to the data enable signal DE, the image processing unit 110 may output various driving signals such as a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

The timing control unit 120 receives the data enable signal DE and the data signal DATA from the image processing unit 110. The timing control unit 120 may control the gate timing control signal GDC for controlling the operation timing of the scan driver 130 and the data timing for controlling the operation timing of the data driver 140 based on the data enable signal DE. The control signal DDC is output.

The data driver 140 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120 and then data based on the gamma reference voltage. Convert to voltage and output. The data driver 140 outputs data voltages to the data lines DL1 to DLn. The data driver 140 may output the reference voltage Vref to the sensing lines SL1 to SLn and receive sensing data from each subpixel. The data driver 140 may be formed in the form of an integrated circuit (IC).

The scan driver 130 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 outputs a scan signal consisting of a scan high voltage and a scan low voltage through scan lines GL1 to GLm. The scan driver 130 may output a scan signal (Scan) for supplying a data voltage to each subpixel in the image display mode and a sensing scan signal (Sense) for sensing the sensing data of each subpixel in the sensing mode. have. The scan driver 130 is formed in the form of an integrated circuit (IC) or a gate-in-panel method on the display panel 150.

The power supply unit 180 is connected to the first power line EVDD and the second power line EVSS disposed on the display panel 150. The power supply unit 180 supplies a first potential power (high potential voltage) to the first power line EVDD, and outputs a second potential power (low potential voltage) to the second power line EVSS. The first potential power (high potential voltage) and the second potential power (low potential voltage) transmitted through the first power line EVDD and the second power line EVSS are subpixels SP of the display panel 150. ).

Data lines DL1 to DLn and sensing lines SL1 to SLn arranged in the vertical direction and scan lines GL1 to GLm arranged in the horizontal direction cross the display panel 10, and subpixels ( SP) are arranged in a matrix form. The subpixels SP may include a light emitting device (OLED). The self-light emitting device, OLED, includes an anode electrode and a cathode electrode, and an organic compound layer formed therebetween, and generates a visible light when a power voltage is applied to the anode electrode and the cathode electrode. Each of the subpixels SP may be one of a red (R) subpixel, a green (G) subpixel, a blue (B) subpixel, and a white (W) subpixel, and the red (R), green (G) ), blue (B), and white (W) subpixels may constitute one unit pixel for color realization.

2 is a schematic circuit diagram of a subpixel.

As shown in FIG. 2, one sub-pixel SP has a first switch TFT SW1 and a first switch TFT connected to a gate electrode to the scan line GL1 and a first electrode connected to the data line DL1. The gate electrode is connected to the second electrode of (SW1) and the first electrode is connected to the first power line (EVDD), and the second electrode and the driving TFT (DR) of the first switch TFT (SW1) are connected. A capacitor (Cst) having one end connected to the gate electrode and the other end connected to the second electrode of the driving TFT (DR), an anode electrode connected to the second electrode of the driving TFT (DR) and the other end of the capacitor (Cst), and a second power source. The cathode electrode may be connected to the line EVSS.

The first switch TFT (SW1) is a gate electrode of the first data line (DL1) and one end of the capacitor (Cst) and the driving TFT (DR) in response to the scan signal (Scan) supplied through the first scan line (GL1) Connect this connected node. Accordingly, the data voltage Vdata supplied through the first data line DL1 may be stored in the capacitor Cst.

The driving TFT DR supplies a driving current to the light emitting device OLED by adjusting the current amount according to the data voltage Vdata stored in the capacitor Cst.

The second switch TFT SW2 connects the source terminal of the first sensing line SL1 and the driving TFT DR in response to the sensing scan signal Sense supplied through the second scan line GL2. Accordingly, the reference voltage Vref may be supplied to the source terminal of the driving TFT DR through the first sensing line SL1 or the voltage or current of the source terminal of the driving TFT DR may be sensed.

In the above, a subpixel having a 3T (Transistor) 1C (Capacitor) structure has been described as an example, but it may be composed of 3T2C, 4T2C, 5T1C, and 6T2C.

3 is a circuit diagram illustrating a part of a pixel array of a display device according to an exemplary embodiment of the present invention.

The pixel array according to an embodiment of the present invention may be controlled in units of four subpixels SP1, SP2, SP3, and SP4. The four sub-pixels SP1, SP2, SP3, and SP4 are sub-pixels receiving different data voltages, an R sub-pixel including a red light-emitting element OLED_R, and a G sub-pixel including a green light-emitting element OLED_G. , A B subpixel including a blue light emitting element (OLED_B), and a W subpixel including a white light emitting element (OLED_W).

One data line DL1 and one sensing line SL1 may be allocated to the four subpixels SP1, SP2, SP3, and SP4. The first sub-pixel and the second sub-pixel may be arranged on the first horizontal line HL1, and the third and fourth sub-pixels may be arranged on the second horizontal line HL2. The first sub-pixel is an R sub-pixel including a red light-emitting element (OLED_R), the second sub-pixel is a G sub-pixel including a green light-emitting element (OLED_G), the third sub-pixel includes a blue light-emitting element (OLED_B) The B subpixel and the fourth subpixel may include a W subpixel including a white light emitting device (OLED_W).

The four sub-pixels SP1, SP2, SP3, and SP4 may be divided into two sub-pixel groups SG1 and SG2.

The first sub-pixel group SG1 includes a pair of sub-pixels SP1 and SP3 arranged adjacent to each other in the vertical direction to share the first node N1 to which the data voltage is input.

The second sub-pixel group SG2 includes a pair of sub-pixels SP2 and SP4 arranged adjacent to each other in the vertical direction to share the second node N2 to which the data voltage is input.

The data line DL1 and the sensing line SL1 are disposed between the first sub-pixel group SG1 and the second sub-pixel group SG2, and the first node and the data line of the first sub-pixel group SG1 ( The first switch T1 for controlling the connection between DL1) and the second switch T2 for controlling the connection between the second node of the second subpixel group SG2 and the data line DL1 are connected. Accordingly, the first sub-pixel group is supplied with the data voltage applied through the data line in response to the turn-on operation of the first switch, and the second sub-pixel group is applied through the data line in response to the turn-on operation of the second switch. Data voltage can be supplied. The pair of sub-pixels SP1 and SP3 included in the first sub-pixel group and the pair of sub-pixels SP2 and SP4 included in the second sub-pixel group receive different data voltages at a period of one horizontal time. Can. The data voltage supply operation may be controlled by the first to fourth scan signals Scan1 to Scan4.

The first switch and the second switch and each of the subpixels SP1, SP2, SP3, and SP4 correspond to the data lines DL1 to DL2 according to the scan signals Scan1 to Scan4 input to the scan lines GL1 to GL4. ) Is controlled.

The first switch includes a gate electrode receiving the second scan signal Scan2, a first electrode connected to the data line, and a second electrode connected to the first node N1. Accordingly, the first switch T1 is turned on by the second scan signal Scan2 input through the second scan line GL2 to connect the data line and the first node N1.

The second switch includes a gate electrode receiving the third scan signal Scan3, a first electrode connected to the data line, and a second electrode connected to the second node N2. Accordingly, the second switch T2 is turned on by the third scan signal Scan3 input through the third scan line GL3 to connect the data line and the second node N2.

The first sub-pixel group SG1 includes a pair of sub-pixels SP1 and SP3 arranged adjacent to each other in the vertical direction to share the first node N1 to which the data voltage is input.

In the first sub-pixel SP1, the first switch TFT SW1 has a gate electrode connected to the first scan line Scan1, a first electrode connected to the first node N1, and a gate of the driving TFT DR The second electrode is connected to the electrode. In the driving TFT DR, the gate electrode is connected to the second electrode of the first switch TFT SW1, the first electrode is connected to the first power line EVDD, and the second electrode is connected to the anode electrode of the light emitting element OLED_R. Connected. A capacitor Cst is connected between the second electrode of the first switch TFT SW1 and the second electrode of the driving TFT DR. In the light emitting device OLED_R, an anode electrode is connected to the second electrode of the driving TFT DR, and a cathode electrode is connected to the second power line EVSS. In the second switch TFT SW2, a gate electrode is connected to the first scan line Scan1, a first electrode is connected to a second electrode of the driving TFT DR, and a second electrode is connected to the sensing line SL1.

In the third sub-pixel SP3, the first switch TFT SW1 has a gate electrode connected to a fourth scan line Scan4, a first electrode connected to a first node N1, and a gate of the driving TFT DR The second electrode is connected to the electrode. In the driving TFT DR, the gate electrode is connected to the second electrode of the first switch TFT SW1, the first electrode is connected to the first power line EVDD, and the second electrode is connected to the anode electrode of the light emitting element OLED_B. Connected. A capacitor Cst is connected between the second electrode of the first switch TFT SW1 and the second electrode of the driving TFT DR. In the light emitting device OLED_R, an anode electrode is connected to the second electrode of the driving TFT DR, and a cathode electrode is connected to the second power line EVSS. In the second switch TFT SW2, a gate electrode is connected to the fourth scan line Scan4, a first electrode is connected to a second electrode of the driving TFT DR, and a second electrode is connected to the sensing line SL1.

As described above, the first subpixel and the third subpixel of the first subpixel group SG1 share the first node N1 to which data is input, and when the first switch T1 is turned on, the data line DL1. Data voltage Vdata can be input from. When the first scan signal is input while the first switch T1 is turned on, the first switch TFT SW1 of the first sub pixel SP1 is turned on to input the data voltage Vdata to the first sub pixel. When the fourth scan signal is input while the first switch T1 is turned on, the first switch TFT SW1 of the third sub pixel SP3 is turned on to input the data voltage Vdata to the third sub pixel.

The second sub-pixel group SG2 includes a pair of sub-pixels SP2 and SP4 arranged adjacent to each other in the vertical direction to share the second node N2 to which the data voltage is input.

In the second sub-pixel SP2, the first switch TFT SW1 has a gate electrode connected to a first scan line Scan1, a first electrode connected to a second node N2, and a gate of the driving TFT DR The second electrode is connected to the electrode. In the driving TFT DR, the gate electrode is connected to the second electrode of the first switch TFT SW1, the first electrode is connected to the first power line EVDD, and the second electrode is connected to the anode electrode of the light emitting element OLED_W. Connected. A capacitor Cst is connected between the second electrode of the first switch TFT SW1 and the second electrode of the driving TFT DR. In the light emitting device OLED_W, an anode electrode is connected to the second electrode of the driving TFT DR, and a cathode electrode is connected to the second power line EVSS. In the second switch TFT SW2, a gate electrode is connected to the first scan line Scan1, a first electrode is connected to a second electrode of the driving TFT DR, and a second electrode is connected to the sensing line SL1.

In the fourth sub-pixel SP4, the first switch TFT SW1 has a gate electrode connected to a fourth scan line Scan4, a first electrode connected to a second node N2, and a gate of the driving TFT DR The second electrode is connected to the electrode. In the driving TFT DR, the gate electrode is connected to the second electrode of the first switch TFT SW1, the first electrode is connected to the first power line EVDD, and the second electrode is connected to the anode electrode of the light emitting element OLED_G. Connected. A capacitor Cst is connected between the second electrode of the first switch TFT SW1 and the second electrode of the driving TFT DR. In the light emitting device OLED_G, the anode electrode is connected to the second electrode of the driving TFT DR, and the cathode electrode is connected to the second power line EVSS. In the second switch TFT SW2, a gate electrode is connected to the fourth scan line Scan4, a first electrode is connected to a second electrode of the driving TFT DR, and a second electrode is connected to the sensing line SL1.

As described above, the second subpixel and the fourth subpixel of the second subpixel group SG2 share the second node N2 to which data is input, and when the second switch T2 is turned on, the data line DL1. Data voltage Vdata can be input from. When the first scan signal is input while the second switch T2 is turned on, the first switch TFT SW1 of the second subpixel SP2 is turned on to input the data voltage Vdata to the second subpixel. When the fourth scan signal is input while the second switch T2 is turned on, the first switch TFT SW1 of the fourth sub pixel SP4 is turned on to input the data voltage Vdata to the fourth sub pixel.

4 is a driving waveform diagram of the pixel array of FIG. 3.

The first scan signal Scan1 is supplied at a turn-on level from the first period t1 to the second period t2. Accordingly, the first switch TFT SW1 of the first subpixel SP1 of the first subpixel group SG1 and the second subpixel SP2 of the second subpixel group SG2 is turned on, respectively. When the first scan signal Scan1 is switched to the off level, the first sub-pixel SP1 and the second sub-pixel SP2 emit light according to the input data voltage.

The second scan signal Scan2 is supplied at a turn-on level during the first period t1 and the third period t3. Accordingly, in the first period t1 and the third period t3, the first switch T1 is turned on to supply the data voltage Vdata to the first node N1 of the first sub-pixel group SG1.

The third scan signal Scan3 is supplied at a turn-on level during the second period t2 and the fourth period t4. Accordingly, the second switch T2 is turned on in the second period t2 and the fourth period t4 to supply the data voltage Vdata to the second node N2 of the second sub-pixel group SG2.

The fourth scan signal Scan4 is supplied at a turn-on level from the third period t3 to the fourth period t4. Accordingly, the first switch TFT SW1 of the third subpixel SP3 of the first subpixel group SG2 and the fourth subpixel SP4 of the second subpixel group SG2 is turned on, respectively. When the fourth scan signal Scan4 is switched to the off level, the third subpixel SP3 and the fourth subpixel SP4 emit light by the input data voltage.

According to the above driving waveform, the first sub-pixel SP1 included in the first sub-pixel group SG1 is supplied with the first data voltage during the first horizontal time t1, and is applied to the second sub-pixel group SG2. The second subpixel SP2 included is supplied with a second data voltage during the second horizontal time t2, and the third subpixel SP3 included in the first subpixel group SG1 has a third horizontal time ( The third data voltage may be supplied during t3), and the fourth subpixel SP4 included in the second subpixel group SG2 may be supplied with the fourth data voltage during the first horizontal time t1.

Hereinafter, a method of driving a pixel array at each horizontal time will be described in detail with reference to FIGS. 5 to 8.

5A and 5B are equivalent circuits and driving waveform diagrams of a pixel array corresponding to a first horizontal time t1.

In the first horizontal time t1, the first scan signal Scan1 is input at an on level, the second scan signal Scan2 is input at an on level, and the third scan signal Scan3 is input at an off level, The fourth scan signal Scan4 is input at an off level.

The first subpixel SP1 of the first subpixel group SG1 and the first subpixel SP2 of the second subpixel group SG2 as the first scan signal Scan1 is input at the on level. Each of the switch TFTs SW1 is turned on.

As the second scan signal Scan2 is input at the on level, the first switch T1 is turned on and the data voltage Vdata input to the data line is input to the first node N1. Since the first switch TFT SW1 of the first sub-pixel SP1 connected to the first node N1 is turned on, the data voltage Vdata is input to the first sub-pixel SP1.

Since the third scan signal Scan3 is input at an off level, the second switch T2 is turned off.

Since the fourth scan signal Scan1 is input at an off level, the first switch TFT SW1 of the third subpixel SP3 and the fourth subpixel SP4 is turned off.

As described above, during the first horizontal time t1, the data voltage Vdata input to the data line is applied to the first node N1 by the first switch T1, and the data voltage is applied to the first subpixel SP1. (Vdata) is input.

6A and 6B are equivalent circuits and driving waveform diagrams of a pixel array corresponding to the second horizontal time t2.

At the second horizontal time t2, the first scan signal Scan1 is input at an on level, the second scan signal Scan2 is input at an off level, and the third scan signal Scan3 is input at an on level, The fourth scan signal Scan4 is input at an off level.

The first subpixel SP1 of the first subpixel group SG1 and the first subpixel SP2 of the second subpixel group SG2 as the first scan signal Scan1 is input at the on level. Each of the switch TFTs SW1 is turned on.

As the third scan signal Scan2 is input at the on level, the second switch T2 is turned on and the data voltage Vdata input to the data line is input to the second node N2. Since the first switch TFT SW1 of the second sub-pixel SP2 connected to the second node N2 is turned on, the data voltage Vdata is input to the second sub-pixel SP2.

Since the second scan signal Scan3 is input at an off level, the first switch T1 is turned off.

Since the fourth scan signal Scan1 is input at an off level, the first switch TFT SW1 of the third subpixel SP3 and the fourth subpixel SP4 is turned off.

As described above, during the second horizontal time t2, the data voltage Vdata input to the data line is applied to the second node N2 by the second switch T2, and the data voltage is applied to the second subpixel SP2. (Vdata) is input.

While the first scan signal is input at the on level at the first horizontal time t1 and the second horizontal time t2, the first subpixel and the second subpixel are sequentially charged, and thereafter, the first scan When the signal is switched to the off level, the first sub-pixel and the second sub-pixel emit light according to the charged data voltage.

7A and 7B are equivalent circuits and driving waveform diagrams of a pixel array corresponding to the third horizontal time t3.

At the third horizontal time t3, the first scan signal Scan1 is input at an off level, the second scan signal Scan2 is input at an on level, and the third scan signal Scan3 is input at an off level, The fourth scan signal Scan4 is input at an on level.

As the fourth scan signal Scan4 is input at the on level, the first subpixel SP3 of the first subpixel group SG1 and the first subpixel SP4 of the second subpixel group SG2 Each of the switch TFTs SW1 is turned on.

As the second scan signal Scan2 is input at the on level, the first switch T1 is turned on and the data voltage Vdata input to the data line is input to the first node N1. Since the first switch TFT SW1 of the third sub-pixel SP3 connected to the first node N1 is turned on, the data voltage Vdata is input to the third sub-pixel SP3.

As the first scan signal Scan1 is input at an off level, the first sub-pixel and the second sub-pixel emit light according to the charged data voltage.

Since the third scan signal Scan3 is input at an off level, the second switch T2 is turned off.

As described above, the data voltage Vdata input to the data line is applied to the first node N1 by the first switch T1 during the third horizontal time t1, and the data voltage is applied to the third subpixel SP3. (Vdata) is input. In addition, in the third horizontal time t1, the first subpixel and the second subpixel emit light according to the charged data voltage.

8A and 8B are equivalent circuits and driving waveform diagrams of a pixel array corresponding to the fourth horizontal time t4.

At the fourth horizontal time t4, the first scan signal Scan1 is input at an off level, the second scan signal Scan2 is input at an off level, and the third scan signal Scan3 is input at an on level, The fourth scan signal Scan4 is input at an on level.

As the fourth scan signal Scan4 is input at the on level, the first subpixel SP3 of the first subpixel group SG1 and the first subpixel SP4 of the second subpixel group SG2 Each of the switch TFTs SW1 is turned on.

As the third scan signal Scan2 is input at the on level, the second switch T2 is turned on and the data voltage Vdata input to the data line is input to the second node N2. Since the first switch TFT SW1 of the fourth sub-pixel SP4 connected to the second node N2 is turned on, the data voltage Vdata is input to the fourth sub-pixel SP4.

As the first scan signal Scan1 is input at an off level, the first sub-pixel and the second sub-pixel emit light according to the charged data voltage.

Since the second scan signal Scan3 is input at an off level, the first switch T1 is turned off.

As described above, during the fourth horizontal time t4, the data voltage Vdata input to the data line is applied to the second node N2 by the second switch T2, and the data voltage is applied to the fourth subpixel SP4. (Vdata) is input.

While the fourth scan signal is input at the on level at the third horizontal time t3 and the fourth horizontal time t4, the third subpixel and the fourth subpixel are sequentially charged, and thereafter, the fourth scan When the signal is switched to the off level, the third and fourth subpixels emit light according to the charged data voltage.

As described above, the present invention sets a pair of sub-pixels adjacent in the vertical direction to a sub-pixel group to share a data input node, and a data input node and a data line between adjacent sub-pixel groups in the horizontal direction. Data lines can be shared by connecting a switch that connects them. Accordingly, since the data voltage can be supplied to four sub-pixels through one data line, the number of data lines can be reduced to 1/4.

9 and 10 show a pin map of the data drive IC. The data drive IC outputs a data voltage to the data lines connected to the output pin, and outputs a reference voltage Vref to the sensing lines. The pin map shows the output pin of the data drive IC to which the data line and the sensing line are connected.

9 shows a pin map 100 of a data drive IC applied to a conventional display device. As shown in FIG. 9, the output pin of the conventional data drive IC includes a first power output pin (EVDD), a reference voltage output pin (VREF), and a data voltage output pin (DATA).

In a conventional pixel array, one data line is connected to each subpixel. Therefore, the data voltage output pin DATA is an output pin for outputting the R data voltage VR to a data line to which the R subpixel is connected, and an output for outputting a G data voltage VG to the data line to which the G subpixel is connected. A pin, an output pin for outputting the B data voltage VB to the data line to which the B subpixel is connected, and an output pin for outputting the W data voltage VW to the data line to which the W subpixel is connected must be included.

10 illustrates a pin map 200 of a data drive IC applied to a display device according to an embodiment of the present invention.

In the pixel array of the present invention, one data line is connected to every four subpixels. That is, R data voltage VR, G data voltage VG, B data voltage VB, and W data voltage VW are supplied to one data line. Therefore, compared to the number of data voltage output pins DATA of FIG. 9, the data voltage can be supplied to the pixel array with only 1/4 output pins.

As the number of output pins is reduced, the data drive IC price can be reduced, and the process cost and process time required to connect the data line to the data drive IC can be reduced.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the technical configuration of the present invention described above is in other specific forms without changing the technical spirit or essential features of the present invention by those skilled in the art to which the present invention pertains. It will be understood that it can be practiced. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. In addition, all modifications or variations derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

110: image processing unit 120: timing control unit
130: scan driver 140: data driver
150: display panel 1 180: power supply

Claims (10)

A first sub-pixel group including a pair of sub-pixels arranged adjacent to each other in the vertical direction and sharing a first node to which a data voltage is input;
A second sub-pixel group including a pair of sub-pixels arranged adjacent to the first sub-pixel group in a horizontal direction and adjacent to a vertical direction to share a second node to which a data voltage is input;
A data line disposed between the first sub-pixel group and the second sub-pixel group;
A first switch for controlling the connection between the first node and the data line; And
A second switch for controlling the connection between the second node and the data line;
Display device comprising a. According to claim 1,
The first sub-pixel group,
In response to the turn-on operation of the first switch receives the data voltage applied through the data line,
The second sub-pixel group
A display device that receives a data voltage applied through the data line in response to a turn-on operation of the second switch. According to claim 1,
A display device that receives a data voltage at different times between a pair of subpixels included in the first subpixel group and a pair of subpixels included in the second subpixel group. According to claim 3,
A display device receiving different data voltages at a period of one horizontal time between a pair of sub-pixels included in the first sub-pixel group and a pair of sub-pixels included in the second sub-pixel group. According to claim 1,
The first sub-pixel included in the first sub-pixel group is supplied with a first data voltage at a first horizontal time,
The second sub-pixel included in the second sub-pixel group receives a second data voltage at a second horizontal time,
The third sub-pixel included in the first sub-pixel group is supplied with a third data voltage at a third horizontal time,
The fourth subpixel included in the second subpixel group is a display device that receives a fourth data voltage at a fourth horizontal time. The method of claim 5,
The first sub-pixel starts emitting light at the same time as the second sub-pixel,
The third sub-pixel is a display device that starts emitting light at the same time as the fourth sub-pixel. According to claim 1,
Each of the first sub-pixel to the fourth sub-pixel is included,
A switch TFT that is switched to transmit the data voltage is a display device in which a turn-on state is maintained for 2 horizontal hours. The method of claim 7,
The first switch and the second switch are alternately turned on and off twice for 4 horizontal hours. According to claim 1,
The sub-pixel,
A first switch TFT having a gate electrode connected to a scan line and a first electrode connected to the first node or the second node;
A driving TFT having a gate electrode connected to a second electrode of the first switch TFT and a first electrode connected to a first power line;
A capacitor having one end connected to the second electrode of the first switch TFT and the gate electrode of the driving TFT and the other end connected to the second electrode of the driving TFT; And
A display device including a second electrode of the driving TFT and an anode electrode connected to the other end of the capacitor and a cathode electrode connected to a second power line. The method of claim 9,
The sub-pixel,
And a second switch TFT having a gate electrode connected to the scan line, a first electrode connected to the second electrode of the driving TFT, and an anode electrode of the light emitting element, and a second electrode connected to a sensing line.

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