KR20190018804A - Display panel using gate driving circuit - Google Patents

Abstract

The present invention relates to a display device using a gate operating circuit. The display device includes: a substrate including a display area and a non-display area; a pixel circuit placed in the display area; and a pair of scan operating circuits generating output signals reversed in the non-display area. The pixel circuit includes: at least one n type transistor; and at least one p type transistor. One of the scan operating circuits includes: first and third transistors having a gate electrode connected with a first node; and second and fourth transistors having a gate electrode connected with a second node. The first and second transistors and the third and fourth transistors are connected in series, respectively. Since a second output signal, which is generated from a node shared by the third and fourth transistors, and a first output signal, which is generated from a node shared by the first and second transistors, are reversed, the number of components for a gate operating circuit, which is able to provide a gate signal to the n type transistor and the p type transistor, is minimized, and thus, the reliability is able to be improved, and also, since an area for the placement of the gate operating circuit is able to be reduced, a display device with a narrow bezel is able to be made.

Description

DISPLAY PANEL USING GATE DRIVING CIRCUIT < RTI ID = 0.0 >

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel using a gate driving circuit, and more particularly, to a display panel using a gate driving circuit for implementing a narrow-bezel display panel by minimizing the number of transistors constituting a gate driving circuit.

Currently, various display devices are being developed and marketed. For example, a liquid crystal display device (LCD), a field emission display device (FED), an electrophoretic display device (EPD), an electro-wetting display devices such as a display device (EWD), an organic light emitting display device (OLED), and a quantum dot display device (QD).

As various technologies for implementing display devices have been developed and various products have been mass produced, technologies for developing a design desired by consumers are developed rather than techniques for operating display devices. One of them is to maximize the display screen. This is because the non-display area surrounding the display screen, that is, the bezel is minimized and the size of the display screen is maximized, so that the user can improve the immersion feeling on the display screen and diversify the design of the product.

Driving circuits for transmitting driving signals to a pixel array constituting a display screen are disposed on the bezel. When the signal supplied from the driver circuits drives the pixel circuit, the pixel array emits light. A gate driver circuit is arranged to transfer a gate signal to the gate line of the pixel circuit, and a data driver circuit is arranged to transfer the data signal to the data line of the pixel circuit. The gate driving circuit may include a scan driving circuit for controlling the gate electrodes of the scan transistors or switch transistors of the pixel circuit, and an emission driving circuit for controlling the gate electrodes of the emission transistors. Therefore, the area where the gate driving circuit and the data driving circuit are disposed can be reduced, thereby minimizing the bezel.

Techniques for reducing the power consumption of the display device as the resolution of the display device increases and the power consumption increase have been developed. In order to reduce the power consumption, it is possible to drive the pixels at a low speed by lowering the frame rate for a specific period of time. For example, in the case of the mobile model, the power consumption can be reduced by performing normal driving such as 60 Hz and 120 Hz in the practical use mode and 1 Hz in the standby mode.

Since the data update period is lengthened at low speed driving, a flicker may be seen when a leakage current occurs in the pixel. Therefore, when a switch transistor having a long off-period is used as an n-type oxide transistor having a low off-current, a flicker phenomenon can be reduced by reducing a leakage current in a low-speed driving. The driving transistor of the pixel circuit can be realized as a p-type polycrystalline transistor having high mobility and low energy consumption and excellent reliability. That is, in the case of a display panel in which a pixel circuit including both an n-type transistor and a p-type transistor is arranged, a separate scan driving circuit is required to control the n-type transistor and the p-type transistor. In addition, since the n-type transistor and the p-type transistor have different turn-on voltages, one of the scan driving circuits must include an inverter. Since the display panel further includes an inverter in addition to the conventional scan driver circuit and the emission driver circuit, the area occupied by the gate driver circuit is increased, making it difficult to implement a narrow bezel display device.

The inventors of the present invention recognized the above-mentioned problems and invented a gate driving circuit for minimizing the size of a gate driving circuit, and invented a display panel to which such a gate driving circuit was applied.

A problem to be solved according to the embodiment of the present invention is to provide a gate drive circuit which does not include an inverter to provide a gate voltage to a gate electrode of an n-type transistor or a p-type transistor in a display panel including both n-type transistors and p- Thereby minimizing the components of the gate driving circuit and improving the reliability of the gate driving circuit.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

In a display panel according to an embodiment of the present invention, a display panel includes a substrate including a display region and a non-display region, a pixel circuit in the display region, and a non-display region, The first scan driving circuit includes a pull-up transistor, a pull-down transistor, and an auxiliary transistor. The gate electrode of the auxiliary transistor includes a first scan driving circuit and a second scan driving circuit, A first electrode of the auxiliary transistor is connected to a wiring to which a reset signal is applied, and a second electrode of the auxiliary transistor is connected to a gate electrode of the pull-down transistor. Accordingly, the components of the gate driving circuit capable of providing the gate signal to the n-type transistor and the p-type transistor can be minimized and reliability can be improved, and the area in which the gate driving circuit is disposed can be reduced, A display device can be implemented.

In a display panel according to an embodiment of the present invention, a display panel includes a substrate including a display region and a non-display region, a pixel circuit in the display region, and a non-display region, Wherein the first scan driver circuit includes a pull-up transistor, a pull-down transistor, a first sub-transistor, and a second sub-transistor, and the gate electrode of the first sub-transistor includes a second scan driver circuit and a second scan driver circuit, A second electrode of the first auxiliary transistor is connected to a gate electrode of the pull-down transistor, a gate electrode of the second auxiliary transistor is connected to a wiring provided with a reset signal, The first electrode of the second auxiliary transistor is connected to the wiring provided with the gate low voltage and the second electrode of the second auxiliary transistor is connected to the first And connects to the first electrode of the auxiliary transistor. Accordingly, components of the gate driver circuit capable of generating mutually inverted output signals can be minimized, reliability can be improved, and the area in which the gate driver circuit is disposed can be reduced, so that the display panel of the narrow bezel is realized .

In the display panel according to an embodiment of the present invention, the display panel includes a substrate including a display region and a non-display region, a pixel circuit provided in the display region and including an n-type transistor and a p-type transistor, A first scan driving circuit and a second scan driving circuit for generating output signals inverted from each other, wherein the first scan driving circuit includes a wiring for providing an output signal of the second scan driving circuit and a wiring for providing a reset signal And a reset signal is provided to the transistor arranged to control the voltage applied to the gate electrode of the pull-down transistor constituting the first scan driving circuit. As a result, components of the gate driver circuit capable of generating mutually inverted output signals are minimized, reliability is improved, and the area in which the gate driver circuit is disposed can be reduced, so that a narrow bezel display panel can be realized .

The details of other embodiments are included in the detailed description and drawings.

According to embodiments of the present invention, the first scan driving circuit includes a pull-up transistor having a gate electrode connected to the Q node, a pull-down transistor having a gate electrode connected to the QB node, By including the auxiliary transistor capable of applying the signal, the inverted output signal can be generated without using the inverter driving circuit, so that the size of the gate driving circuit can be reduced.

According to embodiments of the present invention, the first scan driving circuit includes a pull-up transistor having a gate electrode connected to the Q node, a pull-down transistor having a gate electrode connected to the QB node, 1 auxiliary transistor, and a second auxiliary transistor controlled in accordance with a reset signal, and applying a gate-low voltage to the QB node by the first and second auxiliary transistors allows the inverted output A signal can be generated, so that the size of the gate drive circuit can be reduced.

In addition, according to embodiments of the present invention, by controlling the voltage applied to the QB node by the first and second auxiliary transistors connected to the wiring to which the reset signal and the second scan signal are applied, the inverter driving circuit is used It is possible to generate an inverted output signal without reducing the size of the gate drive circuit.

The scope of the claims is not limited by the matters described in the description of the specification, as the contents of the description in the problems, the solutions to the problems, and the effects described above do not specify the essential features of the claims.

1 is a block diagram showing a display device according to an embodiment of the present invention.
2 is a circuit diagram showing a pixel circuit according to an embodiment of the present invention.
FIG. 3A is a circuit diagram showing the operation in the normal driving mode of the pixel circuit shown in FIG. 2. FIG.
FIG. 3B is a timing chart of the pixel circuit shown in FIG. 3A.
4A is a circuit diagram showing an operation in a sensing driving mode of the pixel circuit shown in FIG.
4B is a timing chart of the pixel circuit shown in FIG. 4A.
5 is a block diagram illustrating a gate drive circuit according to an embodiment of the present invention.
6 is a circuit diagram showing a first scan driving circuit according to the first embodiment of the present invention.
7A is a timing chart showing a signal when the first scan driving circuit shown in FIG. 6 is in a normal driving mode.
7B is a timing chart showing signals when the first scan driving circuit shown in FIG. 6 is in a sensing driving mode.
8 is a circuit diagram showing a first scan driving circuit according to the second embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if a temporal posterior relationship is described by 'after', 'after', 'after', 'before', etc., 'May not be contiguous unless it is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments herein may be combined or combined with each other, partially or wholly, and technically various interlocking and driving are possible, and that the embodiments may be practiced independently of each other, It is possible.

In this specification, the pixel circuit and the gate driving circuit formed on the substrate of the display panel may be implemented by n-type or p-type transistors. For example, the transistor may be implemented as a transistor of a metal oxide semiconductor field effect transistor (MOSFET) structure. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. For example, the flow of carriers in a transistor flows from a source to a drain. In the case of an n-type transistor, since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so as to flow from the source to the drain. In an n-type transistor, the direction of the current flows from the drain to the source because electrons flow from the source to the drain. In the case of a p-type transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. Since the holes of the p-type transistor flow from the source to the drain, current flows from the source to the drain. The source and the drain of the transistor are not fixed, and the source and drain of the transistor can be changed according to the applied voltage.

In the following, the gate on voltage may be the voltage of the gate signal that the transistor may be turned on. The gate off voltage may be a voltage that allows the transistor to be turned off. In a p-type transistor, the gate-on voltage may be a logic low voltage (VL) and the gate-off voltage may be a logic high voltage (VH). In an n-type transistor, the gate-on voltage may be a logic high voltage and the gate-off voltage may be a logic low voltage.

Hereinafter, a display panel using a gate driving circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram showing a display device according to an embodiment of the present invention. 1 is a block diagram illustrating a display device in which a pixel circuit capable of external compensation is disposed, and the constituent elements of the display device are not limited thereto.

The display device 100 includes a display panel 10, a drive IC (drive integrated circuit) 20, a memory 30, a host system 40, and the like.

A screen for displaying an input image on the display panel 10 includes a plurality of pixels P connected to signal wirings. Each of the pixels P may include red, green, and blue sub-pixels for color implementation, and may include a white sub-pixel. The area where the pixels P are disposed and the screen is displayed is referred to as a display area DA and the area other than the display area DA is referred to as a non-display area, and the non-display area may be referred to as a bezel.

The signal wirings may include data lines for supplying the analog data voltage Vdata to the pixels P and gate lines for supplying the gate signals to the pixels P. [ The gate signal may include two or more signals depending on the configuration of the pixel circuit. The pixel circuit to be described below includes a first scan signal Scan1, a second scan signal Scan2, and an emission signal EM. The signal wirings may further include a sensing wiring used to sense the electrical characteristics of the pixels P. [

The pixels P of the display panel 10 are arranged in a matrix form to constitute a pixel array, but are not limited thereto. The pixels P may be arranged in various forms such as a pixel sharing shape, a stripe shape, and a diamond shape in addition to a matrix shape. Each pixel P may be connected to any one of the data lines, one of the sensing lines, and at least one of the gate lines. Each pixel P is configured to receive a high potential power supply voltage and a low potential power supply voltage from a power generation unit. To this end, the power generator may supply the high-potential power supply voltage to the pixels P through the high-potential power supply voltage wiring. Then, the power generator can supply the low-potential power supply voltage to the pixels P through the low-potential power supply voltage wiring. The power generator may be included in the drive IC 20. [

The drive IC 20 modulates the input image data with the compensation value of the pixel P set in advance on the basis of the electric property sensing result of the pixel P and generates the data voltage corresponding to the modulated data V- And a timing control section 21 for controlling the operation timings of the data driving circuit 28 and the gate driving circuit 15. [ The data driving circuit 28 of the drive IC 20 generates compensation data by adding a preset compensation value to the data of the input image, converts the compensation data into a data voltage Vdata, and supplies the compensation data to the data lines. The data driving circuit 28 includes a data driver 25, a compensation unit 26, a compensation memory 27, and the like. The data driver 25 may include a sensing unit 22 and a data voltage generator 23, but is not limited thereto.

The timing control unit 21 may generate timing signals from a video signal input from the host system 40. [ For example, a gate timing control signal (GTC) for controlling the operation timing of the gate driving circuit 15 based on a vertical synchronizing signal, a horizontal synchronizing signal, a dot clock signal, and a data enable signal, And a data timing control signal (DTC) for controlling the operation timing of the data driver 25.

The data timing control signal DTC may include, but is not limited to, a source start pulse, a source sampling clock, and a source output enable signal, . The source start pulse controls the data sampling start timing of the data voltage generating section 23. [ The source sampling clock is a clock signal that controls the sampling timing of data based on a rising or falling edge. The source output enable signal controls the output timing of the data voltage generator 23. [

The gate timing control signal GTC may include, but is not limited to, a gate start pulse, a gate shift clock, and the like. The gate start pulse is applied to a stage that produces the first output to activate the operation of the stage. The gate shift clock is a clock signal commonly input to the stages and is a clock signal for shifting the gate start pulse. The gate start pulse may be referred to as a gate start voltage, and the gate shift clock may be referred to as a gate clock signal.

The data voltage generator 23 uses a digital-to-analog converter (DAC) for converting a digital signal into an analog signal in a normal driving mode for reproducing an input image on a screen Thereby generating a data voltage Vdata of the input image and supplying the generated data voltage Vdata to the pixels P through the data lines.

In the sensing driving mode for measuring the electrical characteristic deviations of the pixels P before shipment or during product driving, the data voltage generator 23 converts the test data received from the gray-scale luminance measuring system to the sensing data voltage And supplies the sensing data voltage to the sensing target pixel P of the display panel 10 through the data lines. The gradation-luminance measurement system senses the electrical characteristics of each of the pixels P and compensates for the electrical characteristic deviation between the pixels P based on the sensing result, in particular, the compensation of the pixel P compensating the threshold voltage deviation of the driving transistor And the compensation value of the pixel P is stored in the memory 30 or the previously stored value is updated. The memory 30 may be implemented with a compensation memory 27 and a single memory. Also, the memory 30 may be a flash memory, but is not limited thereto.

The gradation-luminance measurement system used in the sensing driving mode may be electrically connected to the memory 30 during the sensing driving mode operation.

The compensation value is loaded from the memory 30 into the compensation memory 27 of the drive IC 20 when power is applied to the display device 100 in the normal drive mode. The compensation memory 27 of the drive IC 20 may be, but is not limited to, double data rate synchronous dynamic RAM (DDR SDRAM) or SRAM.

The sensing unit 22 can sense the electrical characteristics of the driving transistor by sampling the source voltage of the driving transistor according to the current of the driving transistor. The sensing unit 22 may be configured to sense the electrical characteristics of each of the pixels P in the pre-shipment aging process and transmit the sensed electrical characteristics to the grayscale-luminance measurement system.

The compensation unit 26 modulates the data of the input image with the compensation value read from the compensation memory 27 and transmits the modulated data V-DATA to the data voltage generation unit 23. [

The host system 40 may be any one of a TV system, a set top box, a navigation system, a personal computer (PC), a home theater system, a mobile system, a wearable system, and a virtual reality system . FIG. 1 illustrates the configuration of a mobile system, and the configuration of a driving circuit of a display device may be changed according to the host system 40. FIG.

2 is a circuit diagram showing a pixel circuit according to an embodiment of the present invention.

The pixel circuit of FIG. 2 includes a light emitting device EL, a driving transistor DT, a capacitor Cs, a first scan transistor ST1, a second scan transistor ST2, and a third scan transistor ST3 . The first scan transistor ST1 and the second transistor STT may be implemented as n-type transistors and the second scan transistor ST2 and the third scan transistor ST3 may be implemented as p-type transistors. 2, the pixel circuit in which the first scan transistor ST1 and the drive transistor DT are implemented by n-type transistors is exemplified, but the present invention is not limited thereto. The embodiments of FIGS. 5 and 8 will be described below. The first scan transistor ST1, the second scan transistor ST2, and the third scan transistor ST3 are implemented by two types of transistors, that is, n type or p type. . 5 and 8 are not limited to the pixel circuits implemented with the four transistors and the one capacitor shown in FIG. 2, but may be applied to pixel circuits implemented with two types of transistors of n type and p type .

The driving transistor DT and the first scan transistor ST1 are n-type transistors. For example, the n-type transistor may be implemented as an oxide transistor including an oxide semiconductor layer with a small off current. Off current is a leakage current flowing between the source and the drain of the transistor in the off state of the transistor. A transistor element having a small off current has a small leakage current even when the off state is long, so that the luminance change of the pixels can be minimized when the pixels are driven at a low speed. For example, the low speed drive may be a 1 Hz drive.

If the semiconductor channel layer of the driving transistor DT is close to the backplane, a flow of unwanted electric charge flowing into the semiconductor channel layer of the driving transistor in the backplane may be generated according to the voltage applied to the driving transistor. This charge flow in the back plane causes a change in the threshold voltage of the driving transistor DT, and a change in the threshold voltage of the driving transistor causes a change in current and luminance of the light emitting element EL, resulting in a residual image on the screen. The oxide transistor applied to the driving transistor DT and the first scan transistor ST1 may have a structure capable of preventing the charge inflow from the backplane.

The second scan transistor ST2 and the third scan transistor ST3 are p-type transistors. For example, a p-type transistor may be implemented with a polysilicon transistor including a semiconductor layer formed of low temperature poly silicon (LTPS) with high mobility. Likewise, if the driver transistor DT is implemented with a polysilicon transistor and the semiconductor layer is close to the backplane, the pixels may be vulnerable to afterimage.

As mentioned above, the electroluminescent display device of the present invention can drive the pixels at low speed by lowering the frame rate in order to reduce the power consumption in the still image. In this case, since the data update period becomes longer, flicker may be seen when leakage current occurs in the pixel. The user can feel the flicker when the luminance of the pixels fluctuates periodically. If the first scan transistor ST1 having a long off period is used as the oxide transistor having a small off current, the leakage current can be reduced in the low-speed driving, thereby reducing the flicker phenomenon.

The light emitting device EL includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. The cathode of the light emitting element EL is connected to the low potential power supply voltage VSS and the anode is connected to the source electrode of the driving transistor DT.

The driving transistor DT is a driving element for adjusting the current flowing in the light emitting element EL according to the gate-source voltage Vgs. The driving transistor DT includes a drain electrode connected to the first node (node1), a gate electrode connected to the second node (node2), and a source electrode connected to the third node (node3). The second node node2 is connected to the gate electrode of the driving transistor DT, one electrode of the capacitor Cs, and the source of the first scan transistor ST1. The capacitor Cs is connected between the second node (node2) and the third node (node3). The high-potential power supply voltage VDD is applied to the driving transistor DT through the first node node1.

The first scan transistor ST1 is turned on according to the first scan signal Scan1 and supplies the reference voltage Vref to the second node node2. The first scan transistor ST1 includes a gate electrode connected to a wiring to which a first scan signal Scan1 is applied, a drain electrode connected to a wiring to which a reference voltage Vref is applied, DT). ≪ / RTI > The reference voltage Vref may be a voltage within a range of the data voltage Vdata. For example, the reference voltage Vref is -1.5V, the high-potential power supply voltage VDD is 8V, the data voltage Vdata is 0V to -6V, and the low-potential power supply voltage VSS is 0V.

The second scan transistor ST2 is turned on in response to the second scan signal Scan2 to form a current path between the third node N3 and the wire to which the data voltage Vdata is applied. The second scan transistor ST2 includes a gate electrode connected to a wiring to which a second scan signal Scan2 is applied, a source electrode connected to a wiring to which a data voltage Vdata is applied, DT and a drain electrode connected to the anode of the light emitting device EL and the other electrode of the capacitor Cs.

The third scan transistor ST3 is connected between the wiring to which the high potential power supply voltage VDD is applied and the drain electrode of the driving transistor DT so that the high potential power supply voltage VDD is applied in response to the emission signal EM And switches the current path between the wiring to be driven and the driving transistor DT. The third scan transistor ST3 includes a gate electrode connected to the wiring to which the emission signal EM is applied, a drain electrode connected to the drain electrode of the driving transistor DT through the first node node1, And a source electrode to which a high-potential power-supply voltage VDD is applied through a wiring to which a voltage VDD is applied. Hereinafter, the operation of the pixel circuit will be described.

FIG. 3A is a circuit diagram showing the operation in the normal driving mode of the pixel circuit shown in FIG. 2. FIG. FIG. 3B is a timing chart of the pixel circuit shown in FIG. 3A. In Fig. 3B, 1H represents one horizontal period in which data is written to the pixel.

The normal driving mode includes a programming period for applying a data voltage (Vdata) to light a pixel and an emission period for allowing the light emitting element (EL) to emit light by flowing a constant current through the light emitting element (EL). 3A and 3B show the programming period DTp in the normal driving mode of the pixel circuit. Each of the first scan signal Scan1, the second scan signal Scan2 and the emission signal EM applied to the pixel circuit swings between the logic low voltage VL and the logic high voltage VH.

During the programming period DTp, the first scan transistor ST1 is turned on in accordance with the gate-on voltage VH of the first scan signal Scan1 and the gate-on voltage VL of the second scan signal Scan2 The second scan transistor ST2 is turned on and the third scan transistor ST3 is turned off according to the gate off voltage VH of the emission signal EM. Accordingly, the reference voltage Vref is applied to the second node node2, and the data voltage Vdata is applied to the third node node3. In this case, in order to turn off the third scan transistor ST3 in order to prevent the drive transistor DT from being turned on and emitting light in a period other than the emission period, the first scan signal Scan1 and the second scan signal The emission signal EM can maintain the gate-off voltage for 1H, which is the gate-on voltage state. For example, the emission signal EM maintains the gate-off voltage for 2H. During the emission period, the first transistor T1 and the second transistor T2 are turned off, the third transistor T3 is turned on, and the light emitting element EL emits light due to the current output from the driving transistor.

The first scan transistor ST1 and the second scan transistor ST2 are simultaneously turned on and off in the normal driving mode. For this purpose, the gate drive circuit must be capable of outputting logic high voltage (VH) and logic low voltage (VL) at the same time. In other words, a gate driver circuit capable of outputting two output voltages opposite to each other must be used for the display panel.

4A is a circuit diagram showing an operation in a sensing driving mode of the pixel circuit shown in FIG. 4B is a timing chart of the pixel circuit shown in FIG. 4A.

In the sensing driving mode, the threshold voltage of the driving transistor DT is sensed. The sensing driving mode may be performed during a blank period between a frame and a frame, and may be performed collectively on all the pixels before shipment after manufacture of the display panel. The sensing driving mode includes a black data input period STb, a holding period STh, a programming period STp, and a sensing period STs. 4A shows the current path of the pixel circuit in the programming period STp in the sensing driving mode.

When the sensing driving mode is started, the first scan transistor ST1 and the second scan transistor ST2 are turned on during the black data input period STb to apply the reference voltage Vref to the gate electrode of the driving transistor DT And the black data voltage is applied to the source electrode of the driving transceiver DT to initialize the gate electrode and the source electrode of the driving transistor DT and remove the noise that may be included in sensing.

The sensing voltage can be applied to the gate electrode and the source electrode of the driving transistor DT during the programming period STp through the holding period STh subsequent to the black data input period STb. In the holding period STh, the first scan transistor ST1 and the second scan transistor ST2 are turned off.

During the programming period STp, the first scan transistor ST1 and the second scan transistor ST2 are turned on to apply a sensing voltage required for sensing to the gate electrode and the source electrode of the driving transistor DT.

The first scan transistor ST1 is turned off during the sensing period STs and the second scan transistor ST2 is turned on to sense the voltage of the third node node3 through the wiring to which the data voltage Vdata is input do. In this case, the second scan transistor ST2 may be referred to as a sensing transistor.

The black data input period STb is performed again before proceeding to the normal driving mode, thereby canceling the noise due to the voltage applied to the gate electrode and the drain electrode of the driving transistor DT.

In the sensing driving mode, the logic low voltage VL is applied to the emission signal EM to turn on the third scan transistor ST3. In order to sense the current due to the threshold voltage of the driving transistor DT, a certain voltage must be applied to the drain electrode of the driving transistor DT. Therefore, the logic high voltage VL may be applied to the third node (node3) through the third scan transistor ST3 turned on by applying the logic low voltage VL to the emission signal EM.

Referring to FIGS. 3A, 3B, 4A, and 4B, the first scan signal Scan1 and the second scan signal Scan2 are inverted signals in the normal driving mode. In the sensing driving mode, It is a signal that is not inverted. The gate driving circuit for outputting the first scan signal Scan1 and the second scan signal Scan2 includes a first scan driving circuit and a second scan driving circuit. The first scan driver circuit may output the output signal inverted from the output signal output from the second scan driver circuit. The first scan driver circuit may output the output signal output from the second scan driver circuit and the inverted output signal It should also be able to output.

5 is a block diagram illustrating a gate drive circuit according to an embodiment of the present invention. Fig. 5 provides a gate signal applied to the pixel circuit of Fig. Fig. 5 can be applied to the display panel shown in Fig.

The gate drive circuit includes a first scan drive circuit, a second scan drive circuit, and an emission drive circuit. Each of the first scan driving circuit, the second scan driving circuit, and the emission driving circuit may include a plurality of stages each including a shift register. Fig. 5 shows as an example the (n-2) th stage, (n-1) th stage, nth stage and (n + 1) th stage of the plurality of stages.

The first scan driving circuit will be described later and the second scan driving circuit will be described first.

The second scan driver circuit includes a second scan clock signal 2 (G2CLK1) input to the second scan stages Scan2 (n-2) to Scan2 (n + 1) and the second scan stages, a second gate clock signal (G2CLK2), a gate low voltage (VGL), a gate high voltage (VGH), and a gate start voltage (GVST). The second scan stages output the output signal while shifting the gate start voltage GVST corresponding to the second gate clock signal 1 (G2CLK1) and the second gate clock signal 2 (G2CLK2). The gate start voltage GVST is input to the first scan stage and the output signal of the previous scan stage of each scan stage is input to the second scan stage instead of the gate start voltage GVST. Specifically, the output signal of the n-th first scan stage Scan1 (n) is input to the gate line of the n-th pixel row P (n) and the output signal of the (n + 1) +1)). the output signal of the nth second scan stage Scan2 (n) may correspond to the second scan signal Scan2 of the nth pixel row P (n).

The first scan driving circuit includes a first gate clock signal 1 (G1CLK1) input to the first scan stages (Scan1 (n-2) to Scan1 (n + 1) 2 (G1CLK2), a gate low voltage (VGL), a gate high voltage (VGH), and a reset signal (RST). The first scan stages receive the output voltage output from the second scan stage instead of the gate start voltage. The first scan stages output one output signal according to the reset signal RST and the output signal of the second scan stage corresponding to the first gate clock signal 1 (G1CLK1) and the first gate clock signal 2 (G1CLK2). More specifically, the output signal of the n-th second scan stage Scan2 (n) is input to the start signal of the n-th first scan stage Scan1 (n) and the gate of the n- Line. the output signal of the nth first scan stage Scan1 (n) may correspond to the first scan signal Scan1 of the nth pixel row P (n).

The second scan signal Scan2 is input to the gate electrode of the p-type transistor, and the first scan signal Scan1 is input to the gate electrode of the n-type transistor. The gate-on voltage VGH of the n-type transistor is a voltage opposite to the gate-on voltage VGL of the p-type transistor. The first scan signal Scan1 may be inverted by the second scan signal Scan2 depending on the driving mode and the first scan signal Scan1 may be the same signal as the second scan signal Scan2. Thus, the first scan stages may be implemented by receiving the output signals of the second scan stages. In this case, the first scan stages may output the first scan signal Scan1 using the second scan signal Scan2 and the reset signal RST.

The emission driving circuit includes an emission clock signal 1 (EMCLK1), an emission clock signal 2 (EMCLK2), an emission clock signal 2 (EMCLK2), and an emission clock signal 2 Emission low voltage (VEH), Emission start voltage (EMVST) are applied. The emission stages output one output signal while shifting the emission start voltage EMVST corresponding to the emission clock signal 1 (EMCLK1) and the emission clock signal 2 (G2CLK2). For example, the output signal of the n-th emission stage EM (n) is input to the start signal of the (n + 1) -th emission stage EM (n + 1) n). Specifically, the output signal of the n-th emission stage EM (n) may correspond to the emission signal EM of the n-th pixel row P (n).

The gate drive circuit includes a first gate clock signal 1 (G1CLK1) and a first gate clock signal 2 (G1CLK2), a second gate clock signal 1 (G2CLK1) and a second gate clock signal 2 (G2CLK2) (EMCLK1) and the emission clock signal 2 (EMCLK2). However, the present invention is not limited thereto.

6 is a circuit diagram showing a first scan driving circuit according to the first embodiment of the present invention. Concretely, it is a circuit diagram constituting each of the plurality of first scan stages shown in FIG. FIG. 7A is a timing chart showing a signal when the first scan driving circuit shown in FIG. 6 is in the normal driving mode, FIG. 7B is a timing chart showing a signal when the first scan driving circuit shown in FIG. to be.

Referring to FIG. 6, the transistors constituting the first scan stages are all p-type transistors. Each of the first scan stages includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a sixth transistor T6, a seventh transistor T7, And a first capacitor C1 and a second capacitor C2. The sixth transistor T6 connected to the Q node Q may be referred to as a pull-up transistor and the seventh transistor T7 connected to the QB node QB may be referred to as a pull- (pull-down transistor). The fourth transistor T4, to which the reset signal RST is applied and the gate electrode is connected to the wiring to which the second scan signal Scan2 is applied, may be referred to as a first auxiliary transistor.

The Q node Q charges the gate electrode of the sixth transistor T6 and the QB node QB discharges the gate electrode of the seventh transistor T7. In this case, since the transistors constituting the first scan stages are p-type transistors, the charge means the turn-on voltage of the transistor, and the discharge means the turn-off voltage of the transistor.

The first electrode of the sixth transistor T6 is connected to the wiring to which the gate low voltage VGL is applied and the second electrode is connected to the node where the first scan signal Scan1 of the first scan stage is outputted.

The first electrode of the seventh transistor T7 is connected to the node where the first scan signal Scan1 of the first scan stage is outputted and the second electrode of the seventh transistor T7 is connected to the wiring to which the gate high voltage VGH is applied.

The gate electrode of the fourth transistor T4 is connected to the wiring to which the second scan signal Scan2 of the second scan stage is applied, the first electrode of the fourth transistor T4 is connected to the wiring to which the reset signal RST is applied, Is connected to QB node QB.

Referring to FIG. 7A, the first scan driving circuit outputs a signal in which the second scan signal (Scan2) is inverted in the normal driving mode. In this case, the reset signal RST maintains the logic low voltage VL. The first scan transistor ST1 and the second scan transistor ST2 of the pixel circuit must be turned on during the programming period DTp in the normal driving mode so that the first scan signal Scan1 and the second scan signal Scan2 are inverted .

When the second scan signal Scan2 is a logic low voltage VL, the fourth transistor T4 is turned on and the reset signal RST is applied to the QB node QB. In the normal driving mode, the logic low voltage VL is applied to the QB node QB since the reset signal RST is the logic low voltage VL. The logic low voltage VL applied to the QB node QB turns on the seventh transistor T7 and the gate high voltage VGH is output to the first scan signal Scan1.

When the second scan signal Scan2 is at a logic high voltage VH, the fourth transistor T4 is turned off and the logic low voltage VL is applied to the Q node Q to turn on the sixth transistor T6. The gate low voltage VGL is outputted as the first scan signal Scan1. In this case, the operation of the concrete first scan driving circuit will be described later.

Referring to FIG. 7B, the first scan driving circuit outputs a signal in which the second scan signal (Scan2) is not inverted in a part of the sensing period (STs) during the sensing driving mode. In this case, the reset signal RST maintains the logic high voltage VH. During the sensing period STs in the sensing driving mode, the first scan transistor ST1 of the pixel circuit is turned off and the second scan transistor ST2 is turned on. Therefore, the first scan signal Scan1 and the second scan signal Scan2 ) Are both logic low voltages (VL).

When the second scan signal Scan2 is a logic low voltage VL, the fourth transistor T4 is turned on and the reset signal RST is applied to the QB node QB. In the sensing driving mode, since the reset signal RST is the logic high voltage VH, the logic high voltage VH is applied to the QB node QB. The logic high voltage VH applied to the QB node QB turns off the seventh transistor T7. The sixth transistor T6 is turned on by charging the Q node Q with the logic low voltage VL so that the gate low voltage VGL is output as the first scan signal Scan1. In this case, the operation of the concrete first scan driving circuit will be described later.

The first scan signal Scan1 and the second scan signal Scan2 are inverted signals in the black data input period STb, the holding period STh and the programming period STp of the sensing driving mode. Therefore, the reset signal RST ) To the logic low voltage VL.

According to the first embodiment of the present invention, the first scan driving circuit includes a sixth transistor T6 having a gate electrode connected to the Q node Q, a seventh transistor T7 having a gate electrode connected to the QB node QB, And a fourth transistor T4 capable of applying a reset signal to the QB node QB in accordance with an output signal of the second scan driving circuit, thereby generating an inverted output signal without using the inverter driving circuit Therefore, the size of the gate drive circuit can be reduced.

The first embodiment according to the present invention controls the voltage applied to the QB node QB according to the reset signal so that the output signal of the first scan driving circuit and the output signal of the second scan driving circuit The output signal of the first scan driving circuit can be prevented from inverting the output signal of the second scan driving circuit when the pixel circuit is in the sensing driving mode.

A fourth transistor T4 connected to the Q node QB or QB node QB for generating a first scan signal Scan1 which is not inverted or inverted according to the second scan signal Scan2, ) Connected to the Q node Q and the QB node QB in addition to the seventh transistor T7 and the seventh transistor T7 to charge and discharge the Q node Q and the QB node QB.

A wiring to which the first gate clock signal 1 (G1CLK1) is applied to the gate electrode of the first transistor T1, a wiring to which the gate low voltage VGL is applied to the first electrode, a Q node Q to the second electrode do.

A gate high voltage VGH is applied to the QB node QB, the Q electrode Q and the second electrode of the first transistor T1 and the second electrode of the second transistor T2. It is connected to the wiring.

The first gate clock signal 1 (G1CLK1) and the gate electrode of the first transistor T1, the QB node QB and the gate electrode of the second transistor T2 are connected to the gate electrode of the third transistor T3, A wire to which the gate high voltage VGH is applied and a second electrode of the second transistor T2 are connected to the second electrode.

A wiring to which the second scan signal Scan2 is applied to the gate electrode of the fourth transistor T4, a wiring to which the reset signal RST is applied to the first electrode, a QB node QB to the second electrode, T2, and the first electrode of the third transistor are connected.

The first scan stages include a first capacitor (C1) and a second capacitor (C2). The first electrode of the first capacitor C1 is connected to the Q node Q and the second electrode of the first capacitor C1 is connected to the node where the first scan signal Scan1 is output. The first electrode of the second capacitor C2 is connected to the QB node QB and the second electrode is connected to the wiring to which the gate high voltage VGH is applied.

Hereinafter, a description will be made with reference to Figs. 7A and 7B.

The logic low voltage VL is applied to the QB node QB when the reset signal RST and the second scan signal Scan2 are at the logic low voltage VL in the normal driving mode so that the seventh transistor T7 is turned on And the gate high voltage VGH is output as the first scan signal Scan1. In this case, since the first gate clock signal 1 (G1CLK1) is at a logic high voltage (VH), the first transistor T1 and the third transistor T3 are turned off and the logic low voltage VL of the QB node QB is turned off. The second transistor T2 is turned on by the gate high voltage VGH and the gate high voltage VGH is applied to the Q node Q so that the sixth transistor T6 is turned off.

In the normal driving mode, when the reset signal RST is the logic low voltage VL and the second scan signal Scan2 is the logic high voltage VH, the fourth transistor T4 is turned off. When the first gate clock signal 1 (G1CLK1) is a logic low voltage (VL), the first transistor T1 and the third transistor T3 are turned on so that the gate low voltage VGL is applied to the Q node Q A gate high voltage VGH is applied to the QB node QB. Then, the second transistor T2 is turned off by the gate high voltage VGH applied to the QB node QB. Accordingly, the seventh transistor T7 is turned off, the sixth transistor T6 is turned on, and the gate low voltage VGL is output as the first scan signal Scan1.

In the normal driving mode, when the reset signal RST is the logic low voltage VL and the second scan signal Scan2 is the logic high voltage VH, the fourth transistor T4 is turned off. When the first gate clock signal 1 (G1CLK1) is a logic high voltage (VH), the first transistor T1 and the third transistor T3 are turned off so that the Q node QB and the QB node QB are floating but the voltages of the Q node Q and the QB node QB are maintained by the first capacitor C1 and the second capacitor C2. Accordingly, the seventh transistor T7 is maintained in the turned-off state and the sixth transistor T6 is maintained in the turned-on state, so that the gate low voltage VGL is output as the first scan signal Scan1.

When the reset signal RST is the logic high voltage VH and the second scan signal Scan2 is the logic low voltage VL in the sensing period STS of the sensing driving mode, the fourth transistor T4 is turned on, The seventh transistor T7 is turned off since the high voltage VH is applied to the QB node QB. When the first gate clock signal 1 (G1CLK1) is a logic low voltage (VL), the first transistor T1 and the third transistor T3 are turned on so that the gate low voltage VGL is applied to the Q node Q , The gate high voltage VGH is applied to the QB node QB. Accordingly, the sixth transistor T6 is turned on and the seventh transistor T7 is turned off, so that the gate low voltage VGL is output as the first scan signal Scan1.

When the reset signal RST is the logic high voltage VH and the second scan signal Scan2 is the logic low voltage VL in the sensing period STS of the sensing driving mode and the first gate clock signal 1 (G1CLK1) The first transistor T1 and the third transistor T3 are turned off and the fourth transistor T4 is turned on so that the logic high voltage VH is applied to the QB node QB The second transistor T2 and the seventh transistor T7 are turned off. In this case, since the Q node Q is floated, the Q node Q is held at the gate-low voltage VGL by the first capacitor C1. Therefore, the sixth transistor T6 is maintained in the turned-on state, and the gate low voltage VGL is output as the first scan signal Scan1.

The first embodiment according to the present invention controls the voltage applied to the QB node QB according to the reset signal RST so that the output signal of the first scan driving circuit and the output signal of the second scan driving circuit The output signal of the first scan driving circuit can be prevented from inverting the output signal of the second scan driving circuit when the pixel circuit is in the sensing driving mode.

8 is a circuit diagram showing a first scan driving circuit according to the second embodiment of the present invention. Concretely, it is a circuit diagram constituting each of the plurality of first scan stages shown in FIG. 7A and 7B are timing diagrams when the first scan driving circuit of FIG. 8 is in the normal driving mode and in the sensing driving mode.

Referring to FIG. 8, the transistors constituting the first scan stages are all p-type transistors. Each of the first scan stages includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, A seventh transistor T7, and a first capacitor C1 and a second capacitor C2. The sixth transistor T6 connected to the Q node Q may be referred to as a pull-up transistor and the seventh transistor T7 connected to the QB node QB may be referred to as a pull- (pull-down transistor). The fifth transistor T5 having the gate electrode connected to the reset signal RST is connected to the second auxiliary transistor and the second auxiliary transistor and is connected to a fourth transistor connected to a wiring to which the second scan signal Scan2 is applied. (T4) may be referred to as a first auxiliary transistor.

The Q node Q charges the gate electrode of the sixth transistor T6 and the QB node QB discharges the gate electrode of the seventh transistor T7. As in the first embodiment of the present invention, since the transistors constituting the first scan stages are p-type transistors, the charge means the turn-on voltage of the transistor, and the discharge means the turn-off voltage of the transistor.

The first electrode of the sixth transistor T6 is connected to the wiring to which the gate low voltage VGL is applied and the second electrode is connected to the node where the first scan signal Scan1 of the first scan stage is outputted.

The first electrode of the seventh transistor T7 is connected to the node where the first scan signal Scan1 of the first scan stage is outputted and the second electrode of the seventh transistor T7 is connected to the wiring to which the gate high voltage VGH is applied.

The gate electrode of the fourth transistor T4 is connected to the wiring to which the second scan signal Scan2 of the second scan stage is applied, the first electrode is connected to the second electrode of the fifth transistor T5, The electrode is connected to the QB node QB.

The gate electrode of the fifth transistor T5 is connected to the wiring to which the reset signal RST is applied and the first electrode of the fifth transistor T5 is connected to the wiring to which the gate low voltage VGL is applied, To the first electrode of the second transistor.

The fourth transistor T4 is turned on / off by the second scan signal Scan2 and the fifth transistor T5 is turned on / off by the reset signal RST. In the first embodiment of the present invention, the reset signal RST is generated by the power generator as a power supply voltage such as a gate low voltage VGL or a gate high voltage VGH, but the logic low voltage VL and the logic high A variable device is needed to swing the voltage (VH). In the second embodiment of the present invention, since the reset signal RST can be generated in the oscillator like a clock signal by adding the fifth transistor T5, a separate variable device is not required.

Referring to FIG. 7A, the first scan driving circuit outputs a signal in which the second scan signal (Scan2) is inverted in the normal driving mode. In this case, since the reset signal RST maintains the logic low voltage VL, the fifth transistor T5 maintains the turn-on state. The first scan transistor ST1 and the second scan transistor ST2 of the pixel circuit must be turned on during the programming period DTp in the normal driving mode so that the first scan signal Scan1 and the second scan signal Scan2 are inverted .

When the second scan signal Scan2 is a logic low voltage VL, the fourth transistor T4 is turned on and the gate low voltage VGL is applied to the QB node QB. The logic low voltage VL applied to the QB node QB turns on the seventh transistor T7 and the gate high voltage VGH is output to the first scan signal Scan1.

When the second scan signal Scan2 is at a logic high voltage VH, the fourth transistor T4 is turned off and the logic low voltage VL is applied to the Q node Q to turn on the sixth transistor T6. The gate low voltage VGL is outputted as the first scan signal Scan1. In this case, the operation of the concrete first scan driving circuit will be described later.

Referring to FIG. 7B, the first scan driving circuit outputs a signal in which the second scan signal (Scan2) is not inverted in a part of the sensing period (STs) during the sensing driving mode. In this case, since the reset signal RST maintains the logic high voltage VH, the fifth transistor T5 maintains the turn-off state. During the sensing period STs in the sensing driving mode, the first scan transistor ST1 of the pixel circuit is turned off and the second scan transistor ST2 is turned on. Therefore, the first scan signal Scan1 and the second scan signal Scan2 ) Are both logic low voltages (VL).

When the second scan signal Scan2 is a logic low voltage VL, the fourth transistor T4 is turned on but the fifth transistor T5 is turned off, so that the gate low voltage VGL is applied to the QB node QB. . In this case, since the Q node Q is charged with the logic low voltage VL, the sixth transistor T6 is turned on to output the gate low voltage VGL as the first scan signal Scan1. The operation of the first scan driving circuit will be described later in detail.

The first scan signal Scan1 and the second scan signal Scan2 are inverted signals in the black data input period STb, the holding period STh and the programming period STp of the sensing driving mode. Therefore, the reset signal RST ) To the logic low voltage VL.

Therefore, according to the second embodiment of the present invention, the QB node QB (QB) is connected by the fourth transistor T4 and the fifth transistor T5 connected to the wiring to which the reset signal RST and the second scan signal Scan2 are applied, ), It is possible to generate the inverted output signal without using the inverter driving circuit, and thus the size of the gate driving circuit can be reduced.

The second embodiment according to the present invention controls the voltage applied to the QB node QB according to the reset signal RST so that the output signal of the first scan driving circuit and the output signal of the second scan driving circuit The output signal of the first scan driving circuit may be inverted when the pixel circuit is in the sensing driving mode, and the output signal of the second scan driving circuit may not be inverted.

A fourth transistor T4 connected to the Q node QB or QB node QB for generating a first scan signal Scan1 which is not inverted or inverted according to the second scan signal Scan2, ) Connected to the Q node Q and the QB node QB in addition to the sixth transistor T6 and the seventh transistor T7 to charge and discharge the Q node QB and the QB node QB .

A wiring to which the first gate clock signal 1 (G1CLK1) is applied to the gate electrode of the first transistor T1, a wiring to which the gate low voltage VGL is applied to the first electrode, a Q node Q to the second electrode do.

A gate high voltage VGH is applied to the QB node QB, the Q electrode Q and the second electrode of the first transistor T1 and the second electrode of the second transistor T2. It is connected to the wiring.

The first gate clock signal 1 (G1CLK1) and the gate electrode of the first transistor T1, the QB node QB and the gate electrode of the second transistor T2 are connected to the gate electrode of the third transistor T3, A wire to which the gate high voltage VGH is applied and a second electrode of the second transistor T2 are connected to the second electrode.

The second scan signal Scan2 is applied to the gate electrode of the fourth transistor T4. The second electrode of the fifth transistor T5 is connected to the first electrode of the transistor T5. The QB node QB is connected to the second electrode of the fifth transistor T5. The gate electrode of the second transistor T2, and the first electrode of the third transistor.

A wiring to which the reset signal RST is applied to the gate electrode of the fifth transistor T5, a wiring to which the gate low voltage VGL is applied to the first electrode, a first electrode of the first transistor T1, And is connected to the first electrode of the fourth transistor T4.

The first scan stages include a first capacitor (C1) and a second capacitor (C2). The first electrode of the first capacitor C1 is connected to the Q node Q and the second electrode of the first capacitor C1 is connected to the node where the first scan signal Scan1 is output. The first electrode of the second capacitor C2 is connected to the QB node QB and the second electrode is connected to the wiring to which the gate high voltage VGH is applied.

Hereinafter, a description will be made with reference to Figs. 7A and 7B.

The logic low voltage VL is applied to the QB node QB when the reset signal RST and the second scan signal Scan2 are at the logic low voltage VL in the normal driving mode so that the seventh transistor T7 is turned on And the gate high voltage VGH is output as the first scan signal Scan1. In this case, since the first gate clock signal 1 (G1CLK1) is at a logic high voltage (VH), the first transistor T1 and the third transistor T3 are turned off and the logic low voltage VL of the QB node QB is turned off. The second transistor T2 is turned on by the gate high voltage VGH and the gate high voltage VGH is applied to the Q node Q so that the sixth transistor T6 is turned off.

The fifth transistor T5 is turned on and the fourth transistor T4 is turned on when the reset signal RST is the logic low voltage VL and the second scan signal Scan2 is the logic high voltage VH in the normal driving mode Off. When the first gate clock signal 1 (G1CLK1) is a logic low voltage (VL), the first transistor T1 and the third transistor T3 are turned on so that the gate low voltage VGL is applied to the Q node Q A gate high voltage VGH is applied to the QB node QB. Then, the second transistor T2 is turned off by the gate high voltage VGH applied to the QB node QB. Accordingly, the seventh transistor T7 is turned off, the sixth transistor T6 is turned on, and the gate low voltage VGL is output as the first scan signal Scan1.

The fifth transistor T5 is turned on and the fourth transistor T4 is turned on when the reset signal RST is the logic low voltage VL and the second scan signal Scan2 is the logic high voltage VH in the normal driving mode Off. When the first gate clock signal 1 (G1CLK1) is a logic high voltage (VH), the first transistor T1 and the third transistor T3 are turned off so that the Q node QB and the QB node QB are floating but the voltages of the Q node Q and the QB node QB are maintained by the first capacitor C1 and the second capacitor C2. Accordingly, the seventh transistor T7 is maintained in the turned-off state and the sixth transistor T6 is maintained in the turned-on state, so that the gate low voltage VGL is output as the first scan signal Scan1.

The fourth transistor T4 is turned on when the reset signal RST is the logic high voltage VH and the second scan signal Scan2 is the logic low voltage VL in the sensing period STs of the sensing driving mode, 5 transistor T5 is turned off. When the first gate clock signal 1 (G1CLK1) is a logic low voltage (VL), the first transistor T1 and the third transistor T3 are turned on so that the gate low voltage VGL is applied to the Q node Q , The gate high voltage VGH is applied to the QB node QB. Accordingly, the sixth transistor T6 is turned on and the seventh transistor T7 is turned off, so that the gate low voltage VGL is output as the first scan signal Scan1.

When the reset signal RST is the logic high voltage VH and the second scan signal Scan2 is the logic low voltage VL in the sensing period STS of the sensing driving mode and the first gate clock signal 1 (G1CLK1) The first transistor Tl, the third transistor T3 and the fifth transistor T5 are turned off and the fourth transistor T4 is turned on when the high voltage VH is applied. The QB node QB floats because the fourth transistor T4 is turned on but the fifth transistor T5 is turned off. In this case, the QB node QB maintains the logic high voltage VH by the second capacitor C2, so that the second transistor T2 and the seventh transistor T7 are turned off. Since the Q node Q is also floating, the Q node Q is held at the gate-low voltage VGL by the first capacitor C1. Therefore, the sixth transistor T6 is maintained in the turned-on state, and the gate low voltage VGL is output as the first scan signal Scan1.

The second embodiment according to the present invention controls the voltage applied to the QB node QB in accordance with the reset signal RST so that the output signal of the first scan driving circuit and the output signal of the second scan driving circuit The output signal of the first scan driving circuit can be prevented from inverting the output signal of the second scan driving circuit when the pixel circuit is in the sensing driving mode.

The logic low voltage VL may be the same as the gate low voltage VGL and the logic high voltage VH may be the same voltage as the gate high voltage VGH.

A display panel using a gate driving circuit according to an embodiment of the present invention can be described as follows.

In a display panel according to an embodiment of the present invention, a display panel includes a substrate including a display region and a non-display region, a pixel circuit in the display region, and a non-display region, The first scan driving circuit includes a pull-up transistor, a pull-down transistor, and an auxiliary transistor. The gate electrode of the auxiliary transistor includes a first scan driving circuit and a second scan driving circuit, A first electrode of the auxiliary transistor is connected to a wiring to which a reset signal is applied, and a second electrode of the auxiliary transistor is connected to a gate electrode of the pull-down transistor. Accordingly, the components of the gate driving circuit capable of providing the gate signal to the n-type transistor and the p-type transistor can be minimized and reliability can be improved, and the area in which the gate driving circuit is disposed can be reduced, A display device can be implemented.

The pixel circuit may include at least one n-type transistor and at least one p-type transistor.

The pixel circuit includes a driving transistor, a scan transistor connected to a gate electrode of the driving transistor, and a sensing transistor connected to a source electrode of the driving transistor. The scanning transistor may be an n-type transistor and the sensing transistor may be a p-type transistor.

The n-type transistor includes an oxide semiconductor layer, and the p-type transistor may include a polysilicon semiconductor layer.

The reset signal may be a logic low voltage when the pixel circuit is in the normal drive mode and a logic high voltage when the pixel circuit is in the sensing drive mode.

When the reset signal is a logic low voltage, the output signal of the first scan driving circuit and the output signal of the second scan driving circuit may be inverted output signals.

When the reset signal is a logic high voltage, the output signal of the first scan driving circuit and the output signal of the second scan driving circuit may be inverted output signals.

The first electrode of the pull-up transistor is connected to the wiring provided with the gate-low voltage, the second electrode of the pull-up transistor is connected to the first electrode of the pull-down transistor, The two electrodes can be connected to a wiring provided with a gate high voltage which is higher than the gate low voltage.

The first scan driver circuit may further include a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor, wherein a gate electrode of the first transistor is connected to a wiring provided with a clock signal, A first electrode of the transistor is connected to a wiring provided with a gate low voltage, a second electrode of the first transistor is connected to a gate electrode of the pull-up transistor, a gate electrode of the second transistor is connected to a gate electrode of the pull- The first electrode of the second transistor is connected to the gate electrode of the pull-up transistor, the second electrode of the second transistor is connected to the wiring provided with the gate high voltage, and the gate electrode of the third transistor is connected to the wiring The first electrode of the third transistor is connected to the second electrode of the auxiliary transistor, and the second electrode of the third transistor is connected to the The first capacitor is connected between the gate electrode of the pull-up transistor and the second electrode of the pull-up transistor, and the second capacitor is connected between the gate electrode of the pull-down transistor and the wiring provided with the gate high voltage have.

In a display panel according to an embodiment of the present invention, a display panel includes a substrate including a display region and a non-display region, a pixel circuit in the display region, and a non-display region, Wherein the first scan driver circuit includes a pull-up transistor, a pull-down transistor, a first sub-transistor, and a second sub-transistor, and the gate electrode of the first sub-transistor includes a second scan driver circuit and a second scan driver circuit, A second electrode of the first auxiliary transistor is connected to a gate electrode of the pull-down transistor, a gate electrode of the second auxiliary transistor is connected to a wiring provided with a reset signal, The first electrode of the second auxiliary transistor is connected to the wiring provided with the gate low voltage and the second electrode of the second auxiliary transistor is connected to the first And connects to the first electrode of the auxiliary transistor. Accordingly, components of the gate driver circuit capable of generating mutually inverted output signals can be minimized, reliability can be improved, and the area in which the gate driver circuit is disposed can be reduced, so that the display panel of the narrow bezel is realized .

The pixel circuit may include at least one n-type transistor and at least one p-type transistor.

The pixel circuit includes a driving transistor, a scan transistor connected to the gate electrode of the driving transistor, and a sensing transistor connected to a source electrode of the driving transistor. The scanning transistor may be an n-type transistor and the sensing transistor may be a p-type transistor.

The n-type transistor includes an oxide semiconductor layer, and the p-type transistor may include a polysilicon semiconductor layer.

The reset signal may be a logic low voltage when the pixel circuit is in the normal drive mode and may be a logic high voltage when the pixel circuit is in the sensing drive mode.

When the reset signal is a logic low voltage, the output voltage of the first scan driving circuit and the output voltage of the second scan driving circuit may be inverted output voltages.

The output voltage of the first scan driving circuit and the output voltage of the second scan driving circuit may be non-inverted output voltages when the reset signal is a logic high voltage.

The first electrode of the pull-up transistor is connected to the wiring provided with the gate-low voltage, the second electrode of the pull-up transistor is connected to the first electrode of the pull-down transistor, The two electrodes can be connected to a wiring provided with a gate high voltage which is higher than the gate low voltage.

The first scan driver circuit may further include a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor, wherein a gate electrode of the first transistor is connected to a wiring provided with a clock signal, A first electrode of the transistor is connected to a wiring provided with a gate low voltage, a second electrode of the first transistor is connected to a gate electrode of the pull-up transistor, a gate electrode of the second transistor is connected to a gate electrode of the pull- The first electrode of the second transistor is connected to the gate electrode of the pull-up transistor, the second electrode of the second transistor is connected to the wiring provided with the gate high voltage, and the gate electrode of the third transistor is connected to the wiring The first electrode of the third transistor is connected to the second electrode of the auxiliary transistor, and the second electrode of the third transistor is connected to the The first capacitor is connected between the gate electrode of the pull-up transistor and the second electrode of the pull-up transistor, and the second capacitor is connected between the gate electrode of the pull-down transistor and the wiring provided with the gate high voltage .

In the display panel according to an embodiment of the present invention, the display panel includes a substrate including a display region and a non-display region, a pixel circuit provided in the display region and including an n-type transistor and a p-type transistor, A first scan driving circuit and a second scan driving circuit for generating output signals inverted from each other, wherein the first scan driving circuit includes a wiring for providing an output signal of the second scan driving circuit and a wiring for providing a reset signal And a reset signal is provided to the transistor arranged to control the voltage applied to the gate electrode of the pull-down transistor constituting the first scan driving circuit. As a result, components of the gate driver circuit capable of generating mutually inverted output signals are minimized, reliability is improved, and the area in which the gate driver circuit is disposed can be reduced, so that a narrow bezel display panel can be realized .

The output voltage of the first scan driving circuit and the output voltage of the second scan driving circuit may be inverted output voltages when the reset signal is a logic low voltage and the output of the first scan driving circuit when the reset signal is a logic high voltage And the output voltage of the second scan driving circuit may be an output voltage that is not inverted with respect to each other.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

100: display device
10: Display panel
15: Gate drive circuit
20: Drive IC
21: Timing control section
22: sensing unit
23: Data voltage generator
25:
26:
27: Compensation memory
28: Data driving circuit
30: Memory
40: Host system

Claims (20)

A substrate including a display region and a non-display region;
A pixel circuit in the display area; And
A first scan driving circuit and a second scan driving circuit provided in the non-display area to generate output signals inverted from each other,
Wherein the first scan driving circuit includes a pull-up transistor, a pull-down transistor, and an auxiliary transistor,
A gate electrode of the auxiliary transistor is connected to a wiring through which an output signal of the second scan driving circuit is outputted,
A first electrode of the auxiliary transistor is connected to a wiring to which a reset signal is applied,
And the second electrode of the auxiliary transistor is connected to the gate electrode of the pull-down transistor. The method according to claim 1,
Wherein the pixel circuit includes at least one n-type transistor and at least one p-type transistor. 3. The method of claim 2,
Wherein the pixel circuit includes a driving transistor, a scan transistor connected to a gate electrode of the driving transistor, and a sensing transistor coupled to a source electrode of the driving transistor,
Wherein the scan transistor is an n-type transistor and the sensing transistor is a p-type transistor. 3. The method of claim 2,
Wherein the n-type transistor includes an oxide semiconductor layer, and the p-type transistor includes a polysilicon semiconductor layer. The method according to claim 1,
Wherein the reset signal is a logic low voltage when the pixel circuit is in a normal drive mode and is a logic high voltage when the pixel circuit is in a sensing drive mode. 6. The method of claim 5,
And the output signal of the first scan driving circuit and the output signal of the second scan driving circuit are inverted output signals when the reset signal is a logic low voltage. 6. The method of claim 5,
And the output signal of the first scan driving circuit and the output signal of the second scan driving circuit are non-inverted output signals when the reset signal is a logic high voltage. The method according to claim 1,
Wherein the pull-up transistor and the pull-down transistor are connected in series with each other,
A first electrode of the pull-up transistor is connected to a wiring provided with a gate low voltage,
A second electrode of the pull-up transistor is connected to a first electrode of the pull-
And the second electrode of the pull-down transistor is connected to a wiring provided with a gate high voltage which is higher than the gate low voltage. 9. The method of claim 8,
The first scan driving circuit may further include a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor,
A gate electrode of the first transistor is connected to a wiring provided with a clock signal,
A first electrode of the first transistor is connected to a wiring provided with the gate low voltage,
A second electrode of the first transistor is connected to a gate electrode of the pull-up transistor,
A gate electrode of the second transistor is connected to a gate electrode of the pull-down transistor,
A first electrode of the second transistor is connected to a gate electrode of the pull-up transistor,
A second electrode of the second transistor is connected to the wiring provided with the gate high voltage,
A gate electrode of the third transistor is connected to a wiring provided with the clock signal,
A first electrode of the third transistor is connected to a second electrode of the auxiliary transistor,
A second electrode of the third transistor is coupled to the gate high voltage,
The first capacitor is connected between the gate electrode of the pull-up transistor and the second electrode of the pull-up transistor,
And the second capacitor is connected between the gate electrode of the pull-down transistor and the wiring provided with the gate high voltage. A substrate including a display region and a non-display region;
A pixel circuit in the display area; And
A first scan driving circuit and a second scan driving circuit provided in the non-display area to generate output signals inverted from each other,
Wherein the first scan driving circuit includes a pull-up transistor, a pull-down transistor, a first auxiliary transistor, and a second auxiliary transistor,
A gate electrode of the first auxiliary transistor is connected to a wiring through which an output signal of the second scan driving circuit is outputted,
A second electrode of the first auxiliary transistor is connected to a gate electrode of the pull-down transistor,
A gate electrode of the second auxiliary transistor is connected to a wiring provided with a reset signal,
A first electrode of the second auxiliary transistor is connected to a wiring provided with a gate low voltage,
And a second electrode of the second auxiliary transistor is connected to the first electrode of the first auxiliary transistor. 11. The method of claim 10,
Wherein the pixel circuit includes at least one n-type transistor and at least one p-type transistor. 12. The method of claim 11,
Wherein the pixel circuit includes a driving transistor, a scan transistor connected to a gate electrode of the driving transistor, and a sensing transistor connected to a source electrode of the driving transistor,
Wherein the scan transistor is an n-type transistor and the sensing transistor is a p-type transistor. 13. The method of claim 12,
Wherein the n-type transistor includes an oxide semiconductor layer, and the p-type transistor includes a polysilicon semiconductor layer. 11. The method of claim 10,
Wherein the reset signal is a logic low voltage when the pixel circuit is in a normal drive mode and is a logic high voltage when the pixel circuit is in a sensing drive mode. 15. The method of claim 14,
And the output voltage of the first scan driving circuit and the output voltage of the second scan driving circuit are inverted output voltages when the reset signal is a logic low voltage. 15. The method of claim 14,
And the output voltage of the first scan driving circuit and the output voltage of the second scan driving circuit are non-inverted output voltages when the reset signal is a logic high voltage. 11. The method of claim 10,
Wherein the pull-up transistor and the pull-down transistor are connected in series with each other,
A first electrode of the pull-up transistor is connected to a wiring provided with the gate-low voltage,
A second electrode of the pull-up transistor is connected to a first electrode of the pull-
And the second electrode of the pull-down transistor is connected to a wiring provided with a gate high voltage which is higher than the gate low voltage. 18. The method of claim 17,
The first scan driving circuit may further include a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor,
A gate electrode of the first transistor is connected to a wiring provided with a clock signal,
A first electrode of the first transistor is connected to a wiring provided with the gate low voltage,
A second electrode of the first transistor is connected to a gate electrode of the pull-up transistor,
A gate electrode of the second transistor is connected to a gate electrode of the pull-down transistor,
A first electrode of the second transistor is connected to a gate electrode of the pull-up transistor,
A second electrode of the second transistor is connected to the wiring provided with the gate high voltage,
A gate electrode of the third transistor is connected to a wiring provided with the clock signal,
A first electrode of the third transistor is connected to a second electrode of the auxiliary transistor,
A second electrode of the third transistor is coupled to the gate high voltage,
The first capacitor is connected between the gate electrode of the pull-up transistor and the second electrode of the pull-up transistor,
And the second capacitor is connected between the gate electrode of the pull-down transistor and the wiring provided with the gate high voltage. A substrate including a display region and a non-display region;
A pixel circuit provided in the display region and including an n-type transistor and a p-type transistor; And
A first scan driving circuit and a second scan driving circuit provided in the non-display area to generate output signals inverted from each other,
Wherein the first scan driving circuit is connected to a wiring for providing an output signal of the second scan driving circuit and a wiring for providing a reset signal,
And the reset signal is provided to a transistor arranged to control a voltage applied to a gate electrode of a pull-down transistor constituting the first scan driving circuit. The method according to claim 1,
The output voltage of the first scan driving circuit and the output voltage of the second scan driving circuit are inverted output voltages when the reset signal is a logic low voltage,
And the output voltage of the first scan driving circuit and the output voltage of the second scan driving circuit are non-inverted output voltages when the reset signal is a logic high voltage.

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