KR20220093764A - Gate Driving Circuit and Organic Light Emitting Display using the same - Google Patents

Abstract

The present invention relates to a gate driving circuit and an organic light emitting display using the same, which reduce the size of a bezel and enable stable driving even at low speed driving. The gate driving circuit of the present invention has a plurality of stages connected cascadingly. An n^th stage includes: a node controller for controlling voltages of a first node and a second node according to a start signal or an output of a previous stage and a first clock signal; an output unit for outputting a gate-on voltage or a gate-off voltage according to the voltages of the first and second nodes; and a stabilization unit for stabilizing the first node by a second clock signal.

Description

Gate Driving Circuit and Organic Light Emitting Display using the same}

The present invention relates to a gate driving circuit capable of stably driving even at a low speed and to an organic light emitting diode display using the same.

In the information society, many technologies have been developed in the field of display devices for displaying visual information as images or images. Among display devices, the organic light emitting diode display uses an organic light emitting diode, which is a self-luminous element that emits light through the recombination of electrons and holes, so that it has a fast response speed, high luminance, low driving voltage, ultra-thin film formation, and free shape. It can be realized as a next-generation display.

An organic light emitting diode display includes a display panel including data lines, scan lines, a plurality of sub-pixels formed at intersections of data lines and scan lines, a gate driving circuit supplying scan signals to the scan lines, and the data and a data driving circuit for supplying data voltages to the lines.

Each sub-pixel of the display panel includes an organic light emitting diode (hereinafter, referred to as 'OLED') and a pixel circuit independently driving the organic light emitting diode.

The pixel circuit includes a driving TFT (Driving Thin Film Transistor) for controlling a driving current flowing through the OLED according to a gate-source voltage, a capacitor for maintaining a gate-source voltage of the driving TFT constant for one frame, and a gate and at least one switching thin film transistor (TFT) for programming a gate-source voltage of the driving TFT in response to a signal, a sensing TFT for sensing characteristics of the driving TFT, and the like.

The gate driving circuit may be directly formed on the same substrate together with circuit elements constituting each pixel circuit. A gate driving circuit directly formed on the substrate of the display panel together with circuit elements constituting each pixel circuit will be referred to as a “Gate In Panel (GIP) circuit”.

For the TFTs constituting the pixel circuit, a LTPS (Low Temperature Poly Silicon) TFT with excellent on current characteristics and an oxide semiconductor TFT with excellent off current characteristics are applied, and a gate driving circuit is used. The constituting TFT is an LTPS TFT with excellent on-current characteristics.

However, in recent years, in order to simplify driving and improve image quality, all pixel circuits are composed of oxide semiconductor TFTs with excellent off current characteristics, and the GIP circuits are combined with LTPS TFTs to realize narrow bezels. It became necessary to develop a technology for applying an oxide semiconductor TFT.

An object of the present invention is to provide a gate driving circuit capable of stably driving even at a low speed by continuously maintaining a low voltage at the Q node of the gate driving circuit, and an organic light emitting diode display using the same.

A gate driving circuit according to an embodiment of the present invention for achieving the above object includes a plurality of stages connected cascadingly, and the nth stage is based on a start signal or an output of the previous stage and a first clock signal. A node control unit for controlling voltages of the first and second nodes, an output unit for outputting a gate-on voltage or a gate-off voltage according to the voltages of the first and second nodes, and a clock signal applied to the next stage A stabilizing unit for stabilizing the first node may be provided.

The stabilization unit includes a TFT having a first electrode connected to a clock signal supply line for supplying a clock signal of the next stage and a gate electrode connected to the first node, and between a second electrode of the TFT and the first node. It may be configured by having a capacitor connected thereto.

In addition, an organic gate light emitting display device according to an embodiment of the present invention for achieving the above object includes a display panel including data lines, gate lines, and sub-pixels, and an input image to the data lines. a data driving circuit for supplying a data signal, and a gate driving circuit for supplying a gate signal to the gate lines, wherein the gate driving circuit includes a plurality of stages connected cascadingly, and the nth stage includes a start signal or A node controller for controlling voltages of the first node and the second node according to the output of the previous stage and the first clock signal, and an output unit for outputting a gate-on voltage or a gate-off voltage according to the voltages of the first and second nodes and a stabilizing unit for stabilizing the first node by a clock signal applied to the next stage.

The gate driving circuit according to the present invention having the above characteristics and the organic light emitting display device using the same have the following effects.

The gate-on voltage is always applied to the second TFT that applies the start signal or the output signal of the previous stage to the first node Q to the first node Q, and the second TFT (Gate Bias Stress) causes the second TFT ( Even when a leakage current is generated in T12), the first node is pumped by the stabilizing unit, so that the gate driving circuit can be stably driven.

In particular, since the first node Q may be maintained at the gate-on voltage for a long time, the gate driving circuit may be stably driven even when driving at a low speed.

In addition, since the gate driving circuit can be stably driven even when driving at a low speed, display quality can be improved.

1 is a diagram illustrating a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram schematically showing a circuit configuration of a shift register in the gate driving circuit 120 .
3A and 3B are diagrams schematically illustrating a pass gate circuit and an edge trigger circuit.
4 is a diagram illustrating in detail a GIP circuit of the gate driving circuit according to the first comparative example.
FIG. 5 is a diagram showing input/output waveforms of the circuit shown in FIG. 4 .
6 is a diagram illustrating in detail a GIP circuit of the gate driving circuit according to the first embodiment of the present invention.
FIG. 7 is a diagram showing input/output waveforms of the circuit shown in FIG. 6 .
8 is a diagram illustrating in detail a GIP circuit of a gate driving circuit according to a second comparative example.
FIG. 9 is a diagram showing input/output waveforms of the circuit shown in FIG. 8 .
10 is a detailed diagram showing the GIP circuit of the gate driving circuit according to the second embodiment of the present invention.
FIG. 11 is a diagram showing input/output waveforms of the circuit shown in FIG. 10 .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only the embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains It is provided to fully understand the scope of the invention, and the present invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiment of the present invention are exemplary, and therefore the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially identical elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When "includes", "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it may be interpreted as the plural unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship between two components is described as 'on One or more other elements may be interposed between those elements in which 'directly' or 'directly' are not used.

1st, 2nd, etc. may be used to distinguish the components, but the functions or structures of these components are not limited to the ordinal number or component name attached to the front of the component. Since the claims are described based on essential elements, the ordinal numbers before the component names in the claims and the ordinal numbers before the component names in the embodiments may not match.

The following embodiments can be partially or wholly combined or combined with each other, and technically various interlocking and driving are possible. Each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

In the present invention, each of the GIP circuit and the pixel circuit of the gate driving circuit includes a plurality of transistors. The transistor may be implemented as a TFT of a metal-oxide-semiconductor FET (MOSFET) structure, and may be an oxide TFT including an oxide semiconductor or an LTPS TFT including low temperature polysilicon (LTPS). The oxide TFT may be implemented as an n-type TFT (NMOS), and the LTPS TFT may be implemented as a p-type TFT (PMOS). In each of the GIP circuit and the pixel circuit of the gate driving circuit, both an n-type TFT (NMOS) and a p-type TFT (PMOS) may be formed.

A MOSFET is a three-electrode device including a gate, a source and a drain. The source is an electrode that supplies a carrier to the transistor. In the MOSFET, carriers start flowing from the source. The drain is the electrode through which carriers exit the MOSFET. In a MOSFET, the flow of carriers flows from source to drain. In the case of an n-type TFT (NMOS), since carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-type TFT (NMOS), the direction of current flows from the drain to the source. In the case of a p-type TFT (PMOS), since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT (PMOS), since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the TFT are not fixed. For example, the source and drain may be changed according to an applied voltage. Therefore, the invention is not limited by the source and drain of the TFT. In the following description, the source and drain of the TFT will be referred to as first and second electrodes.

The gate signal output from the GIP circuit of the gate driving circuit swings between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the TFT, and the gate-off voltage is set to a voltage lower than the threshold voltage of the TFT. The TFT is turned on in response to the gate-on voltage, while it is turned off in response to the gate-off voltage.

Hereinafter, various embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following embodiments, the electroluminescent display will be mainly described with respect to the organic light emitting display including the organic light emitting material. It should be noted that the technical concept of the present specification is not limited to the organic light emitting diode display. For example, the present invention can be applied to a gate driving circuit of a digital flat panel display that requires a gate driving circuit, for example, a liquid crystal display (LCD) or a quantum dot display (QD) without significant change.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

A display device according to an exemplary embodiment of the present specification includes a display panel 100 and a display panel driving circuit.

The display panel 100 includes an active area AA for displaying data of an input image. It is a screen on which video data of an input image is displayed in the active area AA. The pixel array of the active area AA includes a plurality of data lines DL, a plurality of gate lines GL crossing the data lines DL, and pixels arranged in a matrix form. In addition to the matrix form, the arrangement of the pixels may be formed in various ways, such as a form in which pixels emitting the same color are shared, a stripe form, a diamond form, and the like.

Each of the pixels may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels 101 includes a pixel circuit. The pixel circuit includes a light emitting element, a plurality of TFTs, and a capacitor in the case of an electroluminescent display device. The pixel circuit is connected to the data line DL and the gate line GL. In FIG. 1 , “D1 to D3” indicated by circles are data lines, and “Gn-2 to Gn” are gate lines.

Touch sensors may be disposed on the display panel 100 . The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors may be implemented as on-cell type or add-on type touch sensors disposed on the screen of the display panel or embedded in a pixel array. can

A driving circuit for driving the display panel 100 includes a data driving circuit 110 and a gate driving circuit 120 . The display panel driving circuit writes input image data to pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

The display panel driving circuit may operate in a low refresh driving mode (Tlrr). The low-speed driving mode Tlrr may be set to reduce power consumption of the display device when the input image does not change by a preset number of frames by analyzing the input image. In other words, in the low-speed driving mode Tlrr, when a still image is input for a predetermined time or more, the refresh rate of the pixels is lowered, thereby controlling the data writing period of the pixels to be long, thereby reducing power consumption. The low speed driving mode Tlrr is not limited when a still image is input. For example, when the display device operates in the standby mode or when a user command or an input image is not input to the display panel driving circuit for a predetermined time or more, the display panel driving circuit may operate in the low speed driving mode.

The data driving circuit 110 converts digital data DATA of an input image received from the timing controller 130 every frame in a normal driving mode (Tnor) into a data voltage, and then converts the data voltage to data It is supplied to the lines DL. The data driving circuit 110 outputs a data voltage using a digital-to-analog converter (hereinafter, referred to as “DAC”) that converts digital data into a gamma compensation voltage. In the low-speed driving mode, the driving frequency of the data driving unit 110 is lowered under the control of the timing controller 130 .

The data driving circuit 110 outputs the data voltage of the input image in every frame period in the normal driving mode Tnor.

The data driver 110 outputs the data voltage of the input image in some frame periods in the low speed driving mode Tlrr and does not generate an output in the remaining frame periods. Accordingly, the driving frequency and power consumption of the data driving circuit 110 in the low-speed driving mode may be lower than those in the normal driving mode.

The data driving circuit 110 outputs a data voltage to be supplied to pixels of all lines of the display panel 100 within the vertical active period VA. When the pixel array of the display panel 100 includes N*M pixels, the display panel 100 includes M data lines DL. The data voltage may be divided into a video data voltage for display and a data voltage for sensing. The data voltage for display is the data voltage of the input image. The sensing data voltage is a data voltage for sensing electrical characteristics of the sub-pixel. The data voltage for sensing is a preset specific voltage regardless of the data of the input image.

The gate driving circuit 120 may be formed in the bezel region BZ in which an image is not displayed on the display panel 100 . The gate driving circuit 120 outputs a gate signal under the control of the timing controller 130 to select pixels in which the data voltage is charged through the gate lines GL. The gate driving circuit 120 outputs a gate signal using one or more shift registers and shifts the gate signal. The gate driving circuit 120 shifts the gate signal supplied to the gate lines at a constant shift timing up to a predetermined specific gate line within the vertical active period, and then temporarily holds ( holding). Subsequently, the gate driving circuit 120 supplies a gate signal to a specific gate line, and then shifts the gate pulse supplied to the remaining gate lines at a constant shift timing. Accordingly, in the vertical active period, the first and second gate signals are applied only to a specific gate line with a predetermined holding time interposed therebetween, and one gate signal is applied to the other gate lines.

The driving frequency of the gate driving circuit 120 may be lowered under the control of the timing controller 130 in the low speed driving mode. Accordingly, the driving frequency and power consumption of the gate driving circuit 120 are lower than those in the normal driving mode.

The timing controller 130 receives digital video data DATA of an input image and a timing signal synchronized with the digital video data DATA from the host system. The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The host system may be any one of a TV (Television), a set-top box, a navigation system, a personal computer (PC), a home theater, a mobile device, and a wearable device. In the mobile device and the wearable device, the data driving circuit 110 , the timing controller 130 , the level shifter 140 , and the like may be integrated into one drive IC.

The timing controller 130 includes a low-speed driving control module for lowering driving frequencies of the display panel driving circuits 110 and 120 . As described above, the low-speed driving mode is not limited to a still image.

The timing controller 130 multiplies the input frame frequency by i times in the normal driving mode to set the input frame frequency×i (i is a positive integer greater than 0) Hz for the operation timing of the display panel driving circuits 110 and 120 can be controlled. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase-Alternating Line) scheme.

The timing controller 130 lowers the driving frequencies of the display panel driving circuits 110 and 120 in the low-speed driving mode. For example, the timing controller 130 may lower the driving frequency of the display panel driving circuit to a level of 1 Hz so that data is written to the pixels once per second. The frequency of the low-speed drive mode is not limited to 1 Hz. Accordingly, the pixels of the display panel 100 may maintain an already charged data voltage without charging a new data voltage for most of the time in the low-speed driving mode.

The timing controller 130 includes a data timing control signal DDC for controlling the operation timing of the data driving circuit 110 based on the timing signals Vsync, Hsync, and DE received from the host system, and the gate driving circuit 120 . ) to generate a gate timing control signal GDC for controlling the operation timing of the .

The level shifter 140 converts the voltage of the gate timing control signal GDC output from the timing controller 130 into a gate-on voltage and a gate-off voltage and supplies it to the gate driving circuit 120 . A low level voltage of the gate timing control signal GDC is converted into a gate low voltage VGL, and a high level voltage of the gate timing control signal GDC is converted into a gate high voltage VGH. is converted to

In the case of an n-type TFT (NMOS), the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of a p-type TFT (PMOS), the gate-on voltage may be the gate low voltage VGL, and the gate-off voltage may be the gate high voltage VGH.

The gate timing control signal GDC includes a start pulse (Gate Start Pulse, VST), a clock (Gate Shift Clock, CLK), and the like. The start pulse is generated once at the beginning of each frame period and is input to the gate driving circuit 120 . The start pulse VST controls the start timing of the gate driving circuit 120 in every frame period. The clock CLK controls shift timing of the gate signal output from the gate driving circuit 120 .

FIG. 2 is a diagram schematically showing a circuit configuration of a shift register in the gate driving circuit 120 . 3A and 3B are diagrams schematically illustrating a pass gate circuit and an edge trigger circuit.

The shift register of the gate driving circuit 120 includes dependently connected stages ST(n-1) to ST(n+2). The shift register receives the start pulse (VST) or the scan signal (Vgout(n-1)~Vgout(n+2)) or carry signal (CAR1~CAR4) received from the previous stage as the start pulse and outputs it according to the clock timing. (Gout(n-1)) to Gout(n+2)) are generated. Hereinafter, the start signal is a start pulse (VST) or a scan signal (Vgout(n-1) to Vgout(n+2)) or a carry signal (CAR1 to CAR4) generated from the previous stage and applied to the VST node of the next stage ) means

Each stage may be implemented as a pass-gate circuit as shown in FIG. 3A or an edge trigger circuit as shown in FIG. 3B.

In the pass gate circuit, the clock CLK is input to the pull-up transistor Tup that is turned on/off according to the voltage of the Q node. In contrast, in the edge trigger circuit, the gate-on voltage VGL is supplied to the pull-up transistor Tup that is turned on/off according to the voltage of the Q node, and the start signal VST and the clock CLK are inputted. The pull-down transistor Tdn is turned on/off according to the voltage of the QB node.

In the pass gate circuit, the Q node floats in a pre-charged state according to the start signal. When the clock CLK is applied to the pull-up transistor Tup while the Q node is floating, the Q node voltage rises by bootstrapping and the voltage of the output signal Gout(n) is changed to the gate-on voltage. .

The edge trigger circuit generates the output signal Gout(N) with the same waveform as the phase of the start signal because the voltage of the output signal Gout(n) is changed to the voltage of the start signal in synchronization with the edge of the clock CLK. . Changing the start signal waveform also changes the waveform of the output signal accordingly. In an edge trigger circuit, the input signal overlaps the output signal.

It is difficult for the pass gate circuit to generate an output signal out of phase with the input signal. If the transistors of the pass gate circuit are implemented as p-type TFTs (PMOS), a gate-on voltage waveform for the p-type transistor may be output. When the pass gate circuit is implemented with p-type transistors (PMOS), an inverter circuit for inverting the voltage of the output node is further required to output the gate-on voltage waveform of the n-type TFT. When the inverter circuit is connected to the output terminal of the pass gate circuit, the area of the GIP circuit increases, so that the bezel of the display device becomes wider by that amount. A method of inverting the phase of the clock signal input to the pass gate circuit may be considered. However, in this method, the desired output waveform cannot be obtained because the Q node voltage is not increased because the Q node is not bootstrapped due to the inversion of the clock signal.

The edge trigger circuit may generate an out-of-phase output signal. For example, according to an embodiment of the present invention, the edge trigger circuit may implement the transistors of the edge trigger circuit as p-type TFTs as shown in FIG. 4 to obtain the gate-on voltage waveform of the n-type TFT without an inverter circuit. can

The gate driving circuit according to the present invention is implemented based on an edge trigger circuit.

first embodiment

Before describing the gate driving circuit according to the first embodiment of the present invention, the GIP circuit of the first comparative example will be described as follows.

4 is a diagram illustrating in detail a GIP circuit of the gate driving circuit according to Comparative Example 1, and FIG. 5 is a diagram illustrating input/output waveforms of the circuit illustrated in FIG. 4 .

The GIP circuit of the first comparative example shown in FIG. 4 is an nth (n is a positive integer) stage circuit. The transistors shown in Fig. 4 are composed of a p-type TFT (PMOS) and an n-type TFT (NMOS). Here, the p-type TFT is an LTPS TFT including low-temperature polysilicon (LTPS), and the n-type TFT is an oxide TFT including an oxide semiconductor.

4 and 5 , the n-th stage of the first comparative example includes a plurality of TFTs T1 to T4 and T6 to T7 and a single capacitor Cq.

In the n-th stage of the first comparative example, as shown in FIG. 4 , the first electrode is connected to the input terminal of the start signal VST or the output terminal Vgout(n-1) of the previous stage, and the first clock signal CLK1 supply line A gate electrode is connected to , and a second electrode is connected to the N node N, and is turned on/off according to the first clock signal CLK1 to obtain a start signal VST or an output signal Vgout(n-1) of the previous stage. )) to the N node (N), the first electrode is connected to the N node (N), the gate electrode is connected to the gate-on voltage (VGL) supply line, and the first node ( A second TFT (T2) connected to Q) and turned on/off according to the gate-on voltage VGL to connect the N node (N) and the first node (Q), and the gate-on voltage ( VGL) a first electrode is connected to the supply line, a gate electrode is connected to a first node (Q), and a second electrode is connected to a second node (QB) to turn on according to the voltage of the first node (Q) A third TFT T3 that is turned off and supplies the gate-on voltage VGL to the second node QB, the first electrode is connected to the second node QB, and the gate electrode is connected to the first node Q is connected and the second electrode is connected to the gate-off voltage (VGH) supply line to be turned on/off according to the voltage of the first node (Q) to supply the gate-off voltage (VGH) to the second node (QB) The first electrode is connected to the fourth TFT T4 and the gate-on voltage VGL supply line, the gate electrode is connected to the first node Q, and the second electrode is connected to the output terminal OUT to the first node The first electrode is connected to the pull-up TFT T6 that is turned on/off according to the voltage of Q and outputs the gate-on voltage VGL to the output terminal OUT, and the gate-off voltage VGH supply line, The gate electrode is connected to the second node QB and the second electrode is connected to the output terminal OUT, and is turned on/off according to the voltage of the second node QB to output the gate-off voltage VGH to the output terminal OUT. The pull-down TFT (T7) outputted to and the pull-up TFT (T6) It is connected between the first electrode and the second electrode and is configured to include a capacitor Cq for bootstrapping the first node Q.

Here, the first TFT ( T1 ), the second TFT ( T2 ), the fourth TFT ( T4 ), the pull-up TFT ( T6 ) and the pull-down TFT ( T7 ) are p-type TFTs (PMOS), and the third TFT ( T3) is It is an n-type TFT (NMOS).

The operation of the n-th stage of the comparative example of the comparative example configured as described above is as follows.

5, the start signal VST, the clock signals CLK1 and CLK2, and the output signals Vgout(n-1), Vgout(n), Vgout(n+1) of each stage have a high level (High Level) corresponds to the gate-off voltage VGH, the start signal VST, the respective clock signals CLK1 and CLK2, and the output signals Vgout(n-1), Vgout(n), Vgout(n+1) of each stage ) corresponds to the gate-on voltage VGL.

As shown in FIG. 5 , in a state in which the start signal VST or the output signal Vgout(n-1) of the previous stage is input at a high level, the first clock signal CLK1 is gated on When a voltage (Low level) is applied (t1), the first node Q is charged to a gate-off voltage (High Level) through the first and second TFTs T1 and T2.

When the first node Q is charged to the gate-off voltage (High Level), the third TFT T3 is turned on, and thus the second node QB is charged to the gate-on voltage (Low Level; VGL). do.

Accordingly, the pull-up TFT T6 is turned off and the pull-down TFT T7 is turned on to output the gate-off voltage High Level (VGH) as the output signal Vgout(n).

Then, after the 4H period, in a state in which the start signal VST or the output signal Vgout(n-1) of the previous stage is input at a low level, the first clock signal CLK1 is again the gate-on voltage When applied at a (low level) (t2), the first node Q is charged to a gate-on voltage (low level) through the first and second TFTs T1 and T2.

When the first node Q is charged to the gate-on voltage (Low Level), the third TFT T3 is turned off and the fourth TFT T4 is turned on, so that the second node QB is charged with a gate-off voltage (High Level; VGH).

Accordingly, the pull-up TFT T6 is turned on and the pull-down TFT T7 is turned off, thereby outputting the gate-on voltage Low Level (VGL) as the output signal Vgout(n).

After a time point t2 when the first clock signal CLK1 is again applied as a gate-on voltage (low level), the voltage applied to the gate of the second TFT T2 and the voltage applied to the first electrode Source are be on the same level. That is, the gate-source voltage Vgs of the second TFT T2 becomes 0V.

Since Vgs of the second TFT T2 is 0V, the second TFT T2 is turned off, and the first node Q is floated. And, since the floating first node Q is bootstrapped by the capacitor Cq, a voltage lower than the gate-on voltage VGL is maintained.

However, since the gate-on voltage VGL is always applied to the gate of the second TFT T2 , a leakage current is generated in the second TFT T2 due to the gate bias stress.

As such, when a leakage current is generated in the second TFT (T2), the voltage of the first node (Q) rises, which may cause a malfunction of the gate driving circuit. In particular, when driving at a low speed such as 1 Hz, since the first node Q must maintain the gate-on voltage for a long time, an output abnormality of the gate driving circuit occurs due to the leakage current of the second TFT T2.

The gate driving circuit according to the first embodiment of the present invention is to solve the problem of the gate driving circuit of the first comparative example.

6 is a diagram illustrating in detail a GIP circuit of the gate driving circuit according to the first embodiment of the present invention. The GIP circuit shown in Fig. 6 is an nth (n is a positive integer) stage circuit. The transistors shown in FIG. 6 are exemplified by a p-type TFT (PMOS) and an n-type TFT (NMOS), but are not limited thereto. Here, the p-type TFT may be an LTPS TFT including low-temperature polysilicon (LTPS), and the n-type TFT may be an oxide TFT including an oxide semiconductor.

FIG. 7 is a diagram showing input/output waveforms of the circuit shown in FIG. 6 .

The output Vgout illustrated in FIGS. 6 and 7 may be the scan signal SCAN or the emission control signal EM.

6 and 7 , the n-th stage of the gate driving circuit 120 according to the first embodiment of the present invention includes a plurality of TFTs T1 to T7 and a plurality of capacitors Cq and q1. can do.

The nth stage is a node controller 11 that controls voltages of the first node Q and the second node QB according to a start signal VST or Vgout(n-1) and a first clock signal CLK1 and an output unit 13 for outputting a gate-on voltage VGL or a gate-off voltage VGH according to the voltages of the first and second nodes Q and QB, and a clock signal CLK2 It may be configured with a stabilizing unit 12 for stabilizing the node Q.

The node controller 11 has a first electrode connected to the start signal VST input terminal or an output terminal Vgout(n-1) of the previous stage, a gate electrode connected to a first clock signal CLK1 supply line, and N The second electrode is connected to the node N and turned on/off according to the first clock signal CLK1 to transmit the start signal VST or the output signal Vgout(n-1) of the previous stage to the N node N ) applied to the first TFT (T1); The first electrode is connected to the N node (N), the gate electrode is connected to the gate-on voltage (VGL) supply line, and the second electrode is connected to the first node (Q) to turn- according to the gate-on voltage (VGL) a second TFT (T2) that is turned on/off to connect the N node (N) and the first node (Q); The first electrode is connected to the gate-on voltage (VGL) supply line, the gate electrode is connected to the first node (Q), and the second electrode is connected to the second node (QB) to the voltage of the first node (Q). a third TFT (T3) which is turned on/off accordingly to supply the gate-on voltage (VGL) to the second node (QB); and the first electrode is connected to the second node QB, the gate electrode is connected to the first node Q, and the second electrode is connected to the gate-off voltage VGH supply line, so that the voltage of the first node Q Accordingly, the fourth TFT T4 may be turned on/off to supply the gate-off voltage VGH to the second node QB.

The output unit 13 has a first electrode connected to a gate-on voltage (VGL) supply line, a gate electrode connected to a first node Q, and a second electrode connected to an output terminal OUT to a first node ( a pull-up TFT T6 that is turned on/off according to the voltage of Q) to output the gate-on voltage VGL to the output terminal OUT; The first electrode is connected to the gate-off voltage VGH supply line, the gate electrode is connected to the second node QB, and the second electrode is connected to the output terminal OUT to turn on according to the voltage of the second node QB. - a pull-down TFT T7 that is turned on/off and outputs the gate-off voltage VGH to the output terminal OUT; and a first capacitor Cq connected between the gate electrode and the second electrode of the pull-up TFT T6 to bootstrap the first node Q.

The stabilizing unit 12 is a fifth TFT in which a first electrode is connected to a supply line of the second clock signal CLK2 , a gate electrode is connected to a first node Q, and a second electrode is connected to a first node Q (T5); and a second capacitor q1 connected between the second electrode of the fifth TFT T5 and the first node Q.

Here, the first TFT (T1), the second TFT (T2), the fourth TFT (T4), the fifth TFT (T5), the pull-up TFT (T6) and the pull-down TFT (T7) are p-type TFTs (PMOS), The third TFT (T3) is an n-type TFT (NMOS). That is, the first TFT ( T1 ), the second TFT ( T2 ), the fourth TFT ( T4 ), the fifth TFT ( T5 ), the pull-up TFT ( T6 ) and the pull-down TFT ( T7 ) are LTPS TFTs, and the third TFT ( T3) is an oxide semiconductor TFT.

In addition, the first to fourth TFTs T1 , T2 , T3 , and T4 may be configured as dual TFTs as indicated by a circle in FIG. 10 . Also, the second clock signal CLK2 is a clock signal input to the gate of the first TFT T1 of the next stage (n+1).

The operation of the n-th stage of the gate driving circuit according to the first embodiment of the present invention configured as described above will be described below.

7, the start signal VST, the clock signals CLK1, CLK2, and the output signals Vgout(n-1), Vgout(n), Vgout(n+1) of each stage have a high level (High Level) corresponds to the gate-off voltage VGH, the start signal VST, the respective clock signals CLK1 and CLK2, and the output signals Vgout(n-1), Vgout(n), Vgout(n+1) of each stage ) may correspond to the gate-on voltage VGL.

The start signal VST and the output signals Vgout(n-1), Vgout(n), and Vgout(n+1) maintain a high level for 4H.

One period of each of the clock signals CLK1 and CLK2 has a period of 4H, a low level of each of the clock signals CLK1 and CLK2 maintains a period of 2H-1u, and the A high level (Low Level) may maintain a period of 2H+1u. The second clock signal CLK2 is shifted by about 1u from the first clock signal CLK1.

As shown in FIG. 7 , in a state in which the start signal VST or the output signal Vgout(n-1) of the previous stage is input at a high level, the first clock signal CLK1 is gated on. When a voltage (Low level) is applied (t1), the first node Q is charged to a gate-off voltage (High Level) through the first and second TFTs T1 and T2.

When the first node Q is charged to the gate-off voltage (High Level), the third TFT T3 is turned on, and thus the second node QB is charged to the gate-on voltage (Low Level; VGL). do.

Accordingly, the pull-up TFT T6 is turned off and the pull-down TFT T7 is turned on to output the gate-off voltage High Level (VGH) as the output signal Vgout(n).

Then, after the 4H period, in a state in which the start signal VST or the output signal Vgout(n-1) of the previous stage is input at a low level, the first clock signal CLK1 is again the gate-on voltage When applied at a (low level) (t2), the first node Q is charged to a gate-on voltage (low level) through the first and second TFTs T1 and T2.

When the first node Q is charged to the gate-on voltage (Low Level), the third TFT T3 is turned off and the fourth TFT T4 is turned on, so that the second node QB is charged with a gate-off voltage (High Level; VGH).

Accordingly, the pull-up TFT T6 is turned on and the pull-down TFT T7 is turned off, thereby outputting the gate-on voltage Low Level (VGL) as the output signal Vgout(n).

After a time point t2 when the first clock signal CLK1 is again applied as a gate-on voltage (low level), the voltage applied to the gate of the second TFT T2 and the voltage applied to the first electrode Source are be on the same level. That is, the gate-source voltage Vgs of the second TFT T2 becomes 0V.

Since Vgs of the second TFT T2 is 0V, the second TFT T2 is turned off, and the first node Q is floated. And, since the floating first node Q is bootstrapped by the capacitor Cq, a voltage lower than the gate-on voltage VGL is maintained.

In this process, since the gate-on voltage VGL is always applied to the gate of the second TFT T2, a leakage current is generated in the second TFT T12 due to the gate bias stress. can be

However, due to the stabilization unit 12 , the first node Q is not affected by the leakage current of the second TFT T2 .

That is, when the first node Q is charged to the gate-off voltage (High Level), the fifth TFT T5 of the stabilizing unit 12 is turned off, so that the second clock signal CLK2 is transmitted to the first node (Q) is not affected.

Conversely, when the first node Q is charged to the gate-on voltage (Low Level), the fifth TFT T5 of the stabilizing unit 12 is turned on. Accordingly, the second clock signal CLK2 pumps the first node Q through the second capacitor q1.

As described above, even if a leakage current is generated in the second TFT T2 due to the gate bias stress, the voltage of the first node Q continuously maintains the gate-on voltage by the stabilization unit 12 . can be maintained as In addition, since the first node Q can be maintained at the gate-on voltage for a long time even when driving at a low speed such as 1 Hz, the gate driving circuit can be stably driven even when driving at a low speed.

second embodiment

Before describing the gate driving circuit according to the second embodiment of the present invention, the GIP circuit of the second comparative example will be described as follows.

8 is a diagram illustrating in detail a GIP circuit of the gate driving circuit of Comparative Example 2, and FIG. 9 is a diagram illustrating input/output waveforms of the circuit illustrated in FIG. 8 .

The GIP circuit of the second comparative example shown in FIG. 8 is an nth (n is a positive integer) stage circuit. The transistors shown in Fig. 8 are all composed of a p-type TFT (PMOS). Here, the p-type TFT is an LTPS TFT including low-temperature polysilicon (LTPS).

8 and 9 , the n-th stage of the second comparative example includes a plurality of TFTs T11 to T15 and T6 to T7 and three capacitors CQ, CB, and CN.

In the n-th stage of the second comparative example, as shown in FIG. 8 , the first electrode is connected to the input terminal of the start signal VST or the output terminal Vgout(n-1) of the previous stage, and the first clock signal CLK1 supply line is connected to the gate electrode, and the second electrode is connected to the N1 node N1 and is turned on/off according to the first clock signal CLK1 to obtain the start signal VST or the output signal Vgout(n-1) of the previous stage. )) to the N1 node N1, the first electrode is connected to the N1 node N1, the gate electrode is connected to the gate-on voltage (VGL) supply line, and the first node ( A second TFT T12 connected to Q) and turned on/off according to the gate-on voltage VGL to connect the N1 node N1 and the first node Q, and the gate-off voltage ( VGH) the first electrode is connected to the supply line, the gate electrode is connected to the input terminal of the start signal (VST) or the output terminal (Vgout(n-1)) of the previous stage, and the second electrode is connected to the N2 node (N2) to start The third TFT T13 is turned on/off according to the signal VST or the output Vgout(n-1) of the previous stage to supply the gate-off voltage VGH to the N2 node N2, and a start signal (VST) The first electrode is connected to the input terminal or the output terminal (Vgout(n-1)) of the previous stage, the gate electrode is connected to the N2 node N2, and the second electrode is connected to the second node QB. a fourth TFT (T14) that is turned on/off according to the voltage of the node (N2) and supplies the start signal (VST) or the output (Vgout(n-1)) of the previous stage to the second node (QB); The first electrode is connected to the gate-off voltage (VGH) supply line, the gate is connected to the N1 node (N1), and the second electrode is connected to the second node (QB) to turn according to the voltage of the N1 node (N1) - The fifth TFT T15 that is turned on/off and supplies the gate-off voltage VGH to the second node QB, the first electrode is connected to the gate-on voltage VGL supply line, and the first node ( A pull-up in which the gate electrode is connected to Q) and the second electrode is connected to the output terminal OUT, and is turned on/off according to the voltage of the first node Q to output the gate-on voltage VGL to the output terminal OUT The first electrode is connected to the TFT T17 and the gate-off voltage VGH supply line, the gate electrode is connected to the second node QB, and the second electrode is connected to the output terminal OUT, so that the second node QB ) is turned on/off according to the voltage of the pull-down TFT T18 to output the gate-off voltage VGH to the output terminal OUT, and is connected between the gate electrode and the second electrode of the pull-up TFT T17 to the first A first capacitor Cq for bootstrapping the node Q, a second capacitor CB connected between the gate-off voltage VGH supply line and the second node QB, and a first clock signal (CLK1) is configured to include a third capacitor (CN) connected between the input terminal and the N2 node (N2).

Here, the first to fifth TFTs T11, T12, T13, T14, and T15, the pull-up TFT T17, and the pull-down TFT T18 are p-type TFTs (PMOS).

The operation of the n-th stage of the comparative example of the comparative example configured as described above is as follows.

In FIG. 9 , the high level of the start signal VST, the clock signals CLK1 and CLK2, and the output signals Vgout(n-1), Vgout(n), and Vgout(n+1) of each stage corresponds to the gate-off voltage VGH, the start signal VST, the respective clock signals CLK1 and CLK2, and the output signals Vgout(n-1), Vgout(n), Vgout(n+1) of each stage ) corresponds to the gate-on voltage VGL.

As shown in FIG. 9 , in a state in which the start signal VST or the output signal Vgout(n-1) of the previous stage is input at a high level, the first clock signal CLK1 is gated on When the voltage (low level) is applied (t1), the first node Q is charged to the gate-off voltage (high level) through the first and second TFTs T11 and T12.

When the first node Q is charged to the gate-off voltage (high level), the third TFT T13 is turned off, and the gate-on voltage VGL is charged to the third capacitor CN in the previous frame. Therefore, the fourth TFT 14 is turned on and the second node QB is charged with the gate-on voltage (Low level; VGL) of the first clock signal CLK1.

Accordingly, the pull-up TFT T17 is turned off and the pull-down TFT T18 is turned on, thereby outputting a gate-off voltage High Level (VGH) as an output signal Vgout(n).

Then, after the 4H period, in a state in which the start signal VST or the output signal Vgout(n-1) of the previous stage is input at a low level, the first clock signal CLK1 is again the gate-on voltage When applied at (low level) (t2), the first node Q is charged to the gate-on voltage (low level) through the first and second TFTs T11 and T12.

When the first node Q is charged to the gate-on voltage (Low Level), the third TFT T13 and the fifth TFT T15 are turned on, and the fourth TFT T14 is turned off. , the second node QB is charged with a gate-off voltage (High Level; VGH).

Accordingly, the pull-up TFT T17 is turned on and the pull-down TFT T18 is turned off, and outputs the gate-on voltage Low Level (VGL) as the output signal Vgout(n).

After a time point t2 when the first clock signal CLK1 is again applied as a gate-on voltage (low level), the voltage applied to the gate of the second TFT T12 and the voltage applied to the first electrode Source are be on the same level. That is, the gate-source voltage Vgs of the second TFT T12 becomes 0V.

Since Vgs of the second TFT T12 is 0V, the second TFT T12 is turned off, and the first node Q is floated. And, since the floating first node Q is bootstrapped by the capacitor CQ, a voltage lower than the gate-on voltage VGL is maintained.

However, since the gate-on voltage VGL is always applied to the gate of the second TFT T12 , a leakage current is generated in the second TFT T12 due to the gate bias stress.

As such, when a leakage current is generated in the second TFT T12 , the voltage of the first node Q rises, which may cause a malfunction of the gate driving circuit. In particular, when driving at a low speed such as 1 Hz, since the first node Q must maintain the gate-on voltage for a long time, an output abnormality of the gate driving circuit occurs due to the leakage current of the second TFT T12 .

The gate driving circuit according to the second embodiment of the present invention is to solve the problem of the gate driving circuit of the second comparative example.

10 is a detailed diagram showing the GIP circuit of the gate driving circuit according to the second embodiment of the present invention. The GIP circuit shown in Fig. 10 is an nth (n is a positive integer) stage circuit. The transistors shown in FIG. 6 are exemplified as p-type TFTs (PMOS), but are not limited thereto. Here, the p-type TFT may be an LTPS TFT including low-temperature polysilicon (LTPS).

FIG. 11 is a diagram showing input/output waveforms of the circuit shown in FIG. 10 .

The output Vgout illustrated in FIGS. 10 and 11 may be a scan signal SCAN or a light emission control signal EM.

10 and 11, the n-th stage of the gate driving circuit 120 according to the second embodiment of the present invention includes a plurality of TFTs T11 to T18, a plurality of capacitors CQ, CB, CN, q1) may be included.

The nth stage is a node controller 11 that controls voltages of the first node Q and the second node QB according to a start signal VST or Vgout(n-1) and a first clock signal CLK1 and an output unit 13 for outputting a gate-on voltage VGL or a gate-off voltage VGH according to voltages of the first and second nodes Q and QB, and the first output unit 13 according to a clock signal CLK2 It may be configured with a stabilizing unit 12 for stabilizing the node Q.

The node controller 11 has a first electrode connected to the start signal VST input terminal or an output terminal Vgout(n-1) of the previous stage, a gate electrode connected to a first clock signal CLK1 supply line, and N1 . The second electrode is connected to the node N1 and turned on/off according to the first clock signal CLK1 to transmit the start signal VST or the output signal Vgout(n-1) of the previous stage to the N1 node N1 ), the first electrode is connected to the N1 node (N1), the gate electrode is connected to the gate-on voltage (VGL) supply line, and the second electrode is connected to the first node (Q). The second TFT ( T12 ) connected and turned on/off according to the gate-on voltage VGL to connect the N1 node (N1) and the first node (Q), and the first to the gate-off voltage (VGH) supply line The electrode is connected, the gate electrode is connected to the input terminal of the start signal VST or the output terminal Vgout(n-1) of the previous stage, and the second electrode is connected to the N2 node N2 to obtain the start signal VST or the previous stage The third TFT T13 is turned on/off according to the output Vgout(n-1) of the third TFT T13 for supplying the gate-off voltage VGH to the N2 node N2, and the input terminal of the start signal VST or the previous stage The first electrode is connected to the output terminal Vgout(n-1) of Accordingly, the fourth TFT T14 is turned on/off to supply the start signal VST or the output Vgout(n-1) of the previous stage to the second node QB, and the gate-off voltage VGH is supplied. The first electrode is connected to the line, the gate is connected to the N1 node N1, and the second electrode is connected to the second node QB, and is turned on/off according to the voltage of the N1 node N1 to turn off the gate. a fifth TFT (T15) supplying the voltage (VGH) to the second node (QB), and a second capacitor (CB) connected between the gate-off voltage (VGH) supply line and the second node (QB); A third capacitor CN connected between the input terminal of the first clock signal CLK1 and the N2 node N2 may be provided.

The output unit 13 has a first electrode connected to a gate-on voltage (VGL) supply line, a gate electrode connected to a first node Q, and a second electrode connected to an output terminal OUT to a first node ( a pull-up TFT T17 that is turned on/off according to the voltage of Q) and outputs the gate-on voltage VGL to the output terminal OUT; The first electrode is connected to the gate-off voltage VGH supply line, the gate electrode is connected to the second node QB, and the second electrode is connected to the output terminal OUT to turn on according to the voltage of the second node QB. - a pull-down TFT T18 that is turned on/off and outputs the gate-off voltage VGH to the output terminal OUT; and a first capacitor CQ connected between the gate electrode and the second electrode of the pull-up TFT T17 to bootstrap the first node Q.

The stabilizing unit 12 includes a sixth TFT in which a first electrode is connected to the second clock signal CLK2 supply line, a gate electrode is connected to a first node Q, and a second electrode is connected to the first node Q. (T16); and a fourth capacitor q1 connected between the second electrode of the sixth TFT T16 and the first node Q.

Here, the first to sixth TFTs T11, T12, T13, T14, T15, and T16, the pull-up TFT T17, and the pull-down TFT T18 are all p-type TFTs (PMOS). That is, the first to sixth TFTs T11 , T12 , T13 , T14 , T15 , and T16 , the pull-up TFT T17 , and the pull-down TFT T18 may be LTPS TFTs.

The first to fifth TFTs T11 , T12 , T13 , T14 , and T15 may be configured as dual TFTs, as indicated by a circle in FIG. 10 . In addition, the second clock signal CLK2 is a clock signal input to the gate of the first TFT T11 of the next stage (n+1).

The operation of the nth stage of the gate driving circuit according to the second embodiment of the present invention configured as described above will be described below.

11, the high level of the start signal VST, each clock signal CLK1, CLK2, and the output signals Vgout(n-1), Vgout(n), Vgout(n+1) of each stage corresponds to the gate-off voltage VGH, the start signal VST, the respective clock signals CLK1 and CLK2, and the output signals Vgout(n-1), Vgout(n), Vgout(n+1) of each stage ) may correspond to the gate-on voltage VGL.

The start signal VST and the output signals Vgout(n-1), Vgout(n), and Vgout(n+1) maintain a high level for 4H.

One period of each of the clock signals CLK1 and CLK2 has a period of 4H, a low level of each of the clock signals CLK1 and CLK2 maintains a period of 2H-1u, and the A high level (Low Level) may maintain a period of 2H+1u. The second clock signal CLK2 is shifted by about 1u from the first clock signal CLK1 .

11 , in a state in which the start signal VST or the output signal Vgout(n-1) of the previous stage is input at a high level, the first clock signal CLK1 is gated on When the voltage (low level) is applied (t1), the first node Q is charged to the gate-off voltage (high level) through the first and second TFTs T11 and T12.

When the first node Q is charged to the gate-off voltage (high level), the third TFT T13 is turned off, but in the previous frame, the third capacitor CN charges the gate-on voltage VGL. Thus, the fourth TFT T14 is turned on, and the second node QB is charged with the low level (VGL) voltage of the first clock signal.

Accordingly, the pull-up TFT T17 is turned off and the pull-down TFT T18 is turned on, thereby outputting a gate-off voltage High Level (VGH) as an output signal Vgout(n).

Then, after the 4H period, in a state in which the start signal VST or the output signal Vgout(n-1) of the previous stage is input at a low level, the first clock signal CLK1 is again the gate-on voltage When applied at (low level) (t2), the first node Q is charged to the gate-on voltage (low level) through the first and second TFTs T11 and T12.

When the first node Q is charged to the gate-on voltage (Low Level), the third TFT T13 and the fifth TFT T15 are turned on, and the fourth TFT T14 is turned off. , the second node QB is charged with a gate-off voltage (High Level; VGH).

Accordingly, the pull-up TFT T17 is turned on and the pull-down TFT T18 is turned off, and outputs the gate-on voltage Low Level (VGL) as the output signal Vgout(n).

After a time point t2 when the first clock signal CLK1 is again applied as a gate-on voltage (low level), the voltage applied to the gate of the second TFT T12 and the voltage applied to the first electrode Source are be on the same level. That is, the gate-source voltage Vgs of the second TFT T12 becomes 0V.

Since Vgs of the second TFT T12 is 0V, the second TFT T12 is turned off, and the first node Q is floated. And, since the floating first node Q is bootstrapped by the capacitor CQ, a voltage lower than the gate-on voltage VGL is maintained.

In this process, since the gate-on voltage VGL is always applied to the gate of the second TFT T12, a leakage current is generated in the second TFT T12 due to the gate bias stress. can be

However, due to the stabilization unit 12 , the first node Q is not affected by the leakage current of the second TFT T12 .

That is, since the sixth TFT T16 of the stabilizing unit 12 is turned off when the first node Q is charged to the gate-off voltage (High Level), the second clock signal CLK2 is applied to the first node (Q) is not affected.

Conversely, when the first node Q is charged to the gate-on voltage (Low Level), the sixth TFT T16 of the stabilizing unit 12 is turned on. Accordingly, the second clock signal CLK2 pumps the first node Q through the fourth capacitor q1.

As described above, even if a leakage current is generated in the second TFT T12 due to the gate bias stress, the voltage of the first node Q continuously maintains the gate-on voltage by the stabilizing unit 12 . can be maintained as In addition, since the first node Q can be maintained at the gate-on voltage for a long time even when driving at a low speed such as 1 Hz, the gate driving circuit can be stably driven even when driving at a low speed.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

11: node control unit 12: stabilization unit
13: output unit 100: display panel
110: data driving circuit 120: gate driving circuit
130: timing controller 140: level shifter

Claims (15)

Having a plurality of stages connected dependently,
The nth (n is a natural number) stage,
a node controller for controlling voltages of the first node and the second node according to the start signal or the output of the previous stage and the first clock signal;
an output unit outputting a gate-on voltage or a gate-off voltage according to voltages of the first and second nodes; and
A gate driving circuit comprising a stabilizing unit for stabilizing the first node by a second clock signal. The method of claim 1,
The node control unit,
a first TFT turned on/off according to a first clock signal to apply a start signal or an output signal of a previous stage to the N node;
a second TFT turned on/off according to the gate-on voltage to connect the N node and the first node;
a third TFT turned on/off according to the voltage of the first node to supply the gate-on voltage to the second node; and
and a fourth TFT turned on/off according to the voltage of the first node to supply a gate-off voltage to the second node. The method of claim 1,
the output unit,
a pull-up TFT turned on/off according to the voltage of the first node to output the gate-on voltage;
a pull-down TFT turned on/off according to the voltage of the second node to output the gate-off voltage; and
and a first capacitor connected between a gate electrode and a second electrode of the pull-up TFT to bootstrap the first node. The method of claim 1,
The stabilization unit,
a fifth TFT having a first electrode connected to a second clock signal supply line for supplying the second clock signal and a gate electrode connected to the first node; and
and a second capacitor connected between the second electrode of the fifth TFT and the first node. 5. The method of claim 4,
The second clock signal is the same signal as the first clock signal applied to the node controller of the next stage (n+1). 5. The method according to any one of claims 2 to 4,
The first TFT, the second TFT, the fourth TFT, the fifth TFT, the pull-up TFT, and the pull-down TFT are low-temperature polysilicon TFTs, and the third TFT (T3) is an oxide semiconductor TFT. The method of claim 1,
The node control unit,
a first TFT turned on/off according to a first clock signal to apply a start signal or an output signal of a previous stage to the N1 node;
a second TFT turned on/off according to the gate-on voltage to connect the N1 node and the first node;
a third TFT turned on/off according to the start signal or an output signal of a previous stage to supply the gate-off voltage to the N2 node;
a fourth TFT turned on/off according to the voltage of the N2 node to supply the start signal or the output signal of the previous stage to the second node;
and a fifth TFT turned on/off according to the voltage of the N1 node to supply the gate-off voltage to the second node. 8. The method of claim 7,
The node control unit,
A gate driving circuit further comprising: a second capacitor connected between the second node and a gate-off voltage supply line for supplying the gate-off voltage; and a third capacitor connected between the first clock signal input terminal and the N2 node. . The method of claim 1,
The stabilization unit,
a sixth TFT having a first electrode connected to a second clock signal supply line for supplying the second clock signal and a gate electrode connected to the first node; and
and a fourth capacitor connected between the second electrode of the sixth TFT and the first node. 10. The method of claim 9,
The second clock signal is the same signal as the first clock signal applied to the node controller of the next stage. 10. The method according to claim 7 or 9,
The first to sixth TFTs are low-temperature polysilicon TFTs. 8. The method according to claim 2 or 7,
The start signal maintains a high level for 4H,
One period of the first and second clock signals has a period of 4H, the low levels of the first and second clock signals maintain a period of 2H-1u, and the high levels of the first and second clock signals have a period of 2H The gate driving circuit maintains a +1u period, and the second clock signal is shifted by about 1u from the first clock signal. a display panel including data lines, gate lines, and sub-pixels;
a data driving circuit for supplying a data signal of an input image to the data lines; and
a gate driving circuit for supplying a gate signal to the gate lines;
The gate driving circuit is
Having a plurality of stages connected dependently,
The nth (n is a natural number) stage,
a node controller for controlling voltages of the first node and the second node according to the start signal or the output of the previous stage and the first clock signal;
an output unit outputting a gate-on voltage or a gate-off voltage according to voltages of the first and second nodes; and
and a stabilizing unit for stabilizing the first node in response to a second clock signal. 14. The method of claim 13,
The stabilization unit,
a TFT having a first electrode connected to a second clock signal supply line for supplying the second clock signal and a gate electrode connected to the first node; and
and a capacitor connected between the second electrode of the TFT and the first node. 15. The method of claim 14,
and the second clock signal is the same as the first clock signal applied to the node controller of the next stage.

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