KR102605975B1 - Display apparatus - Google Patents

Abstract

A display device according to an embodiment of the present invention includes a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels disposed in an area where the plurality of gate lines and the plurality of data lines intersect. A gate driver for supplying a gate signal to the gate line, a data driver for supplying a data signal to the plurality of data lines, a demultiplexer unit for distributing the data signal to the plurality of data lines, the gate driver, the data driver, and the A timing controller that controls the operation timing of the demultiplexer unit, and a level shifter that supplies a control signal and a pseudo control signal to at least one of the demultiplexer unit and the gate driver, wherein the level shifter sequentially operates the demultiplexer unit or the gate driver. outputs a first control signal and a second control signal applied to, outputs a first pseudo control signal generated in an inverse phase of the first control signal and the second control signal, and outputs a first control signal to the demultiplexer unit or the gate driver unit. A third control signal and a fourth control signal applied sequentially are output, and a second pseudo control signal generated in an inverse phase of the third control signal and the fourth control signal is output.

Description

DISPLAY APPARATUS}

The present invention relates to a display device.

Display devices include liquid crystal displays and electroluminescent displays. Electroluminescent displays can be divided into inorganic light emitting displays and organic light emitting diode displays depending on the material of the light emitting layer. You can.

Generally, a display device includes a display panel for displaying an image, a gate driver for supplying gate signals to the gate lines of the display panel, a data driver for supplying data signals to the data lines of the display panel, and a gate driver and data. It includes a timing controller to control the operation timing and output of the driver. Additionally, a level shifter can convert the voltage level of a signal output from the timing controller.

Meanwhile, a gate enable signal may be sequentially input into the display panel to supply a gate signal to the gate lines of the display panel or a data signal to the data lines. At this time, electro-magnetic interference (EMI) noise may occur due to the gate enable signal.

The technical problem to be solved by the present invention is to provide a display device with improved electro-magnetic interference (EMI) in the display panel.

A display device according to an embodiment of the present invention includes a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels disposed in an area where the plurality of gate lines and the plurality of data lines intersect. A gate driver for supplying a gate signal to the gate line, a data driver for supplying a data signal to the plurality of data lines, a demultiplexer unit for distributing the data signal to the plurality of data lines, the gate driver, the data driver, and the A timing controller that controls the operation timing of the demultiplexer unit, and a level shifter that supplies a control signal and a pseudo control signal to at least one of the demultiplexer unit and the gate driver, wherein the level shifter sequentially operates the demultiplexer unit or the gate driver. outputs a first control signal and a second control signal applied to, outputs a first pseudo control signal generated in an inverse phase of the first control signal and the second control signal, and outputs a first control signal to the demultiplexer unit or the gate driver unit. A third control signal and a fourth control signal applied sequentially are output, and a second pseudo control signal generated in an inverse phase of the third control signal and the fourth control signal is output.

The demultiplexer unit includes a first switch element connected between the data driver and the first data line and supplying the data signal to the first data line in response to a first MUX signal, between the data driver and the second data line. A second switch element is connected to and supplies the data signal to the second data line in response to a second MUX signal, and is disposed between the first switch element and the second switch element, and provides a first pseudo MUX signal. It may include a first pseudo switch element to which is applied.

The source electrode and drain electrode of the first pseudo switch element may be connected to ground.

The demultiplexer unit is connected between the data driver and the third data line, and a third switch element that supplies the data signal to the third data line in response to a third MUX signal, between the data driver and the fourth data line. A fourth switch element is connected to and supplies the data signal to the fourth data line in response to a fourth MUX signal, and is disposed between the third switch element and the fourth switch element, and provides a second pseudo MUX signal. It may further include a second pseudo switch element to which is applied.

The source electrode and drain electrode of the second pseudo switch element may be connected to the ground.

The ground may be connected to the level shifter.

The level shifter is configured to include a first pseudo gate clock signal generated in the opposite phase of the first gate clock signal applied to the first gate line and the second gate clock signal applied to the second gate line, and a first pseudo gate clock signal applied to the third gate line. A second pseudo gate clock signal generated in the opposite phase of the third gate clock signal and the fourth gate clock signal applied to the fourth gate line may be output.

The display panel may further include a first pseudo GCLK element to which the first pseudo gate clock signal is applied and a second pseudo GCLK element to which the second pseudo gate clock signal is applied.

A source electrode and a drain electrode of each of the first pseudo GCLK device and the second pseudo GCLK device may be connected to ground.

A display device according to another embodiment of the present invention includes a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels disposed in an area where the plurality of gate lines and the plurality of data lines intersect, and a display panel driver for writing data into pixels, the display panel having a first switch element connected to a first signal line disposed on the display panel and turned on by a first control signal; and It further includes a second switch element connected to a second signal line disposed on the display panel and turned on by a second control signal, and a ground wire is disposed between the first switch element and the second switch element. .

The display panel has a third switch element connected to a third signal line disposed on the display panel and turned on by a third control signal, and disposed between the second switch element and the third switch element, Further comprising a first pseudo switch element to which a first pseudo control signal is applied, wherein the second control signal and the third control signal sequentially turn on the second switch element and the third switch element, The first pseudo control signal includes an anti-phase signal of the second control signal and an anti-phase signal of the third control signal, and the source electrode and drain electrode of the first pseudo switch element may be connected to the ground wire.

The ground wire is formed of the same material as the plurality of gate lines, and the ground wire may be connected to the source electrode and drain electrode of the first pseudo switch element through a contact hole formed in the display panel.

The first signal line and the second signal line may each be a data line, and the first control signal and the second control signal may each be a MUX signal.

The first signal line and the second signal line may each be a gate line, and the first control signal and the second control signal may each be a GCLK signal.

A method of driving a display device according to an embodiment of the present invention includes supplying a gate signal to a plurality of gate lines, supplying a data signal to a plurality of data lines, and the plurality of gate lines and the plurality of data lines. and supplying a control signal and a pseudo control signal to at least one of the plurality of gate lines and the plurality of data lines, and in the step of supplying the control signal and the pseudo control signal, the Outputting a first control signal and a second control signal, outputting a first pseudo control signal generated in an anti-phase of the first control signal and the second control signal, the plurality of gate lines and the plurality of data lines A third control signal and a fourth control signal that are applied sequentially to at least one of the control signals are output, and a second pseudo control signal that is generated in an anti-phase of the third control signal and the fourth control signal is output.

The demultiplexer according to an embodiment of the present invention has a first switch element connected to the first data line and turned on by the first MUX signal, and a first switch element connected to the second data line and turned on by the second MUX signal. a second switch element, and a first pseudo switch element disposed between the first switch element and the second switch element and to which a first pseudo MUX signal is applied, wherein the first MUX signal and the second MUX The signal sequentially turns on the first switch element and the second switch element, and the first pseudo MUX signal includes an anti-phase of the first MUX signal and an anti-phase of the second MUX signal, The source electrode and drain electrode of the first pseudo switch element are connected to ground.

A third switch element connected to the third data line and turned on by the third MUX signal, a fourth switch element connected to the fourth data line and turned on by the fourth MUX signal, and the third switch element connected to the third data line and turned on by the third MUX signal. A second pseudo switch element is disposed between the switch element and the fourth switch element and to which a second pseudo MUX signal is applied, and the third MUX signal and the fourth MUX signal are connected to the third switch element and the fourth switch element. Turns on four switch elements sequentially, wherein the second pseudo MUX signal includes an anti-phase of the third MUX signal and an anti-phase of the fourth MUX signal, and the source electrode and drain of the second pseudo switch element An electrode is connected to the ground, the ground is disposed on a gate layer, and the source electrode and drain electrode of the first pseudo switch element and the source electrode and drain electrode of the second pseudo switch element are connected to the ground through a contact hole. can be connected

A ground guard connected to the ground and extending from the gate layer to the source-drain layer may be disposed between the second switch element and the third switch element.

According to an embodiment of the present invention, a display device with improved EMI within the display panel can be obtained. In particular, according to an embodiment of the present invention, a display device with improved EMI caused by a gate enable signal input into the display panel can be obtained.

Additionally, according to the implementation of the present invention, the number of additionally disposed switch elements can be minimized to improve EMI.

1 is a display device according to an embodiment of the present invention.
Figure 2 is a circuit diagram showing the switch elements (M1, M2) of the demultiplexer unit.
Figure 3 is an example of a 1:3 demultiplexer, and Figure 4 is an example of a 1:4 demultiplexer.
FIG. 5 is a diagram schematically showing the shift register of the gate driver 120.
Figure 6 shows a demultiplexer unit according to an embodiment of the present invention.
Figure 7 shows the waveform of a signal applied to the demultiplexer unit according to an embodiment of the present invention.
Figure 8 shows the connection relationship between a demultiplexer unit and a level shifter according to an embodiment of the present invention.
Figure 9 is an implementation example of a demultiplexer unit according to an embodiment of the present invention.
Figure 10 is a cross-sectional view of the array of the demultiplexer unit according to an embodiment of the present invention.
Figure 11 shows a path in which current is output from a source, passes through a load, and then returns to the source.
12 to 14 show a method of connecting the pseudo switch element of the demultiplexer to the ground according to an embodiment of the present invention.
Figure 15 shows a demultiplexer unit according to another embodiment of the present invention.
Figure 16 shows the waveform of a signal applied to the demultiplexer unit according to another embodiment of the present invention.
Figure 17 shows a GIP circuit according to an embodiment of the present invention.
Figure 18 is a waveform of a signal applied to the GIP circuit according to an embodiment of the present invention.
Figure 19 shows EMI measurement results according to the application of a demultiplexer according to an embodiment of the present invention.

Since the present invention can be subject to various changes and can have various embodiments, specific embodiments will be illustrated and described in the drawings. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention.

Terms containing ordinal numbers, such as second, first, etc., may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, the second component may be referred to as the first component without departing from the scope of the present invention, and similarly, the first component may also be referred to as the second component. The term and/or includes any of a plurality of related stated items or a combination of a plurality of related stated items.

The terms used in this application are only used to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as “comprise” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. It should be understood that this does not exclude in advance the possibility of the existence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the technical field to which the present invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and unless explicitly defined in the present application, should not be interpreted in an ideal or excessively formal sense. No.

Hereinafter, embodiments will be described in detail with reference to the attached drawings, but identical or corresponding components will be assigned the same reference numbers regardless of reference numerals, and duplicate descriptions thereof will be omitted.

In the display device according to an embodiment of the present invention, the display panel driving circuit, pixel array, level shifter, etc. may include transistors. Transistors can be implemented as Oxide TFT (Thin Film Transistor) containing an oxide semiconductor, LTPS TFT containing Low Temperature Poly Silicon (LTPS), etc. Each of the transistors may be implemented as a transistor with a p-channel MOSFET (metal-oxide-semiconductor field effect transistor) or n-channel MOSFET structure.

A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal transitions between Gate On Voltage and Gate Off Voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate on voltage, while the transistor is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage (Gate High Voltage, VGH), and the gate-off voltage may be the gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be the gate low voltage (VGL) and the gate-off voltage may be the gate high voltage (VGH).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

Referring to FIG. 1, a display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The display panel 100 includes a pixel array (AA) that displays pixel data of an input image. Pixel data of the input image is displayed in pixels of the pixel array (AA). The pixel array AA includes a plurality of data lines DL, a plurality of gate lines GL crossing the data lines DL, and pixels arranged in a matrix form. In addition to the matrix form, pixels can be arranged in various forms, such as sharing pixels emitting the same color, stripe form, or diamond form.

When the resolution of the pixel array AA is n*m, the pixel array AA may include n pixel columns and m pixel lines L1 to Lm that intersect the pixel columns. A pixel column contains pixels arranged along the y-axis direction. A pixel line includes pixels arranged along the x-axis direction. 1 horizontal period (1H) is the time divided by 1 frame period by the number of m pixel lines (L1 to Lm). Pixel data can be written to pixels of 1 pixel line in 1 horizontal period (1H).

Each pixel may be divided into red subpixel, green subpixel, and blue subpixel to implement color. Each of the pixels may further include a white subpixel. Each of the subpixels 101 includes a pixel circuit. The pixel circuit includes a pixel electrode, a plurality of thin film transistors (TFTs), and a capacitor. The pixel circuit is connected to the data line (DL) and gate line (GL).

Touch sensors may be disposed on the display panel 100 to implement a touch screen. Touch input can be sensed using separate touch sensors or sensed through pixels. Touch sensors can be implemented as on-cell type or add-on type touch sensors placed on the screen of the display panel or embedded in the pixel array. You can.

The display panel driving circuit includes a data driver 110, a gate driver 120, and a timing controller 130 for controlling the operation timing of the driving circuits 110 and 120. The display panel driving circuit writes data of the input image to the pixels of the display panel 100 under the control of the timing controller 130.

The data driver 110 converts pixel data (V-DATA) of the input image received as a digital signal from the timing controller 130 every frame into an analog gamma compensation voltage and outputs a data signal (Vdata). The data driver 110 supplies the data signal Vdata to the data lines DL. The data driver 110 may output a data signal (Vdata) using a digital to analog converter (hereinafter referred to as “DAC”) that converts a digital signal into an analog gamma compensation voltage. At this time, an output buffer is further disposed between the digital-analog converter of the data driver 110 and the data line (DL), and the output buffer transfers the data voltage from the digital-analog converter to the data line (DL) in response to the source output enable signal. It can be output as .

The gate driver 120 may be formed in the bezel area BZ of the display panel 100 where images are not displayed. The gate driver 120 receives the gate timing control signal received from the level shifter 140, generates a gate signal (or scan signal, GATE), and supplies it to the gate lines GL. The gate signal GATE applied to the gate lines GL turns on switch elements of subpixels to select pixels in which the voltage of the data signal Vdata is charged. The gate signal (GATE) may be generated as a pulse signal that swings between the gate high voltage (VGH) and the gate low voltage (VGL). The gate driver 120 may shift the gate signal using a shift register. The gate driver 120 may be implemented in the form of a gate-in-panel (GIP) made of a combination of thin film transistors on the display panel 100.

The timing controller 130 may control the operation timing of the display panel drivers 110 and 120 by multiplying the input frame frequency by i times the input frame frequency Хi (i is a positive integer greater than 0) Hz. The input frame frequency may be 60Hz in the NTSC (National Television Standards Committee) method and 50Hz in the PAL (Phase-Alternating Line) method.

The timing controller 130 receives pixel data of the input image and a timing signal synchronized therewith from the host system 200. Pixel data of the input image received by the timing controller 130 is a digital signal. The timing controller 130 transmits pixel data to the data driver 110. The timing signal may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (DCLK), and a data enable signal (DE). Since the vertical period and horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync) may be omitted. The data enable signal (DE) has a period of 1 horizontal period (1H).

The display panel driving circuit may further include a demultiplexer unit 150.

The demultiplexer unit 150 sequentially connects one channel of the data driver 110 to a plurality of data lines DL and time-divides the data voltage output from one channel of the data driver 110 to the data lines DL. By distributing, the number of channels of the data driver 110 can be reduced. The demultiplexer unit 150 includes a plurality of switch elements as shown in FIG. 2.

The timing controller 130 includes a data timing control signal for controlling the data driver 110 based on the timing signal received from the host system 200, a gate timing control signal for controlling the gate driver 120, and a demultiplexer unit. A MUX control signal, etc. for controlling the switch elements of (150) may be generated. The gate timing control signal may include a start pulse (Gate Start Pulse (VST)), a shift clock (GCLK), etc. The start pulse (VST) controls the start timing of the gate driver 120 every frame period. The shift clock GCLK controls the shift timing of the gate signal output from the gate driver 120. The timing controller 130 may generate a control signal to control the level shifter 140.

The host system 200 may be any one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, a mobile system, and a wearable system. In mobile devices and wearable devices, the data driver 110, timing controller 130, level shifter 140, etc. may be integrated into one drive IC (not shown).

In a mobile system, the host system 200 may be implemented as an Application Processor (AP). The host system 200 may transmit pixel data of the input image to the drive IC through MIPI (Mobile Industry Processor Interface). The host system 200 may be connected to the drive IC through a flexible printed circuit (FPC) 310, for example.

The level shifter 140 converts the voltage of the control signal received from the timing controller 130. For example, the level shifter 140 converts the high logic voltage (or high potential input voltage) of the input signal received into the digital signal voltage level into the gate high voltage (VGH), and the low logic voltage (or low potential input voltage) of the input signal. Converts the potential input voltage) into the gate low voltage (VGL).

The output signal of the level shifter 140 may be applied to at least one of the demultiplexer unit 150, the gate driver 120, the data driver 110, the touch sensor driver (not shown), and the power supply unit 400.

The display device according to an embodiment of the present invention may further include a power supply unit 400.

The power supply unit 400 uses a DC-DC converter to generate direct current (DC) voltage necessary to drive the pixel array of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, buck-boost converter, etc. The power unit 400 adjusts the direct current input voltage from the host system 200 to a gamma reference voltage (VGMA) and a gate high voltage (VGH, VEH). Direct current voltages such as gate low voltage (VGL, VEL), half VDD (HVDD), and common voltage of pixels can be generated. The gamma reference voltage (VGMA) is supplied to the data driver 110. The half VDD voltage is as low as 1/2 voltage compared to VDD and can be used as the output buffer driving voltage of the source drive IC. The gamma reference voltage (VGMA) is divided by gray level through a voltage dividing circuit and supplied to the DAC of the data driver 110.

Figure 2 is a circuit diagram showing the switch elements (M1, M2) of the demultiplexer unit.

Referring to FIG. 2, the output buffer (AMP) included in one channel (CH1, CH2) in the data driver 110 may be connected to neighboring data lines DL1 to 4 through the demultiplexer unit 150. . The data lines DL1 to 4 may be connected to the pixel electrodes 1011 to 1014 of the subpixels through the TFT.

The demultiplexer unit 150 includes a plurality of demultiplexers 21 and 22. The demultiplexers 21 and 22 may be 1:N demultiplexers with one input node and N output nodes (N is two or more positive integers). The demultiplexers 21 and 22 of the demultiplexer unit 150 are illustrated as 1:2 demultiplexers in FIG. 2, but are not limited thereto. For example, each of the demultiplexers 21 and 22 may be implemented as a 1:3 demultiplexer and sequentially connect one channel to three data lines in the data driver 110. Alternatively, each of the demultiplexers 21 and 22 may be implemented as a 1:4 demultiplexer or a 1:6 demultiplexer. Figure 3 is an example of a 1:3 demultiplexer, and Figure 4 is an example of a 1:4 demultiplexer.

In FIG. 1 , the demultiplexer unit 150 is shown as being formed directly on the substrate of the display panel 100, but it is not limited thereto and may be integrated into one drive IC along with the data driver 110.

The demultiplexer unit 150 uses switch elements M1 and M2 to convert the data signal Vdata1 output through the first channel CH1 of the data driver 110 to the first and second data lines DL1, The data signal Vdata2 output through the second channel CH2 of the data driver 110 is divided into the third and third channels using the first demultiplexer 21 for time division distribution to DL2 and the switch elements M1 and M2. It may include a second demultiplexer 22 that performs time division distribution to the fourth data lines DL3 and DL4.

The level shifter 140 may output first and second MUX signals (MUX1 and MUX2) in response to the MUX control signal received from the timing controller 130.

The first switch element M1 may be turned on in response to the gate high voltage VGH of the first MUX signal MUX1. At this time, the output buffer AMP of the first channel CH1 may be connected to the first data line DL1 through the first switch element M1. At the same time, the output buffer AMP of the second channel CH2 may be connected to the third data line DL3 through the first switch element M1.

Thereafter, the second switch element M2 may be turned on in response to the gate high voltage VGH of the second MUX signal MUX2. At this time, the output buffer AMP of the first channel CH1 may be connected to the second data line DL2 through the second switch element M2. At the same time, the output buffer AMP of the second channel CH2 may be connected to the fourth data line DL4 through the second switch element M2.

FIG. 5 is a diagram schematically showing the shift register of the gate driver 120. The shift register of the gate driver 120 includes dependently connected stages [SR(n-1) to (n+2)]. The shift register receives a start pulse (VST) or carry signal (CAR) and generates an output signal [OUT(n-1))~(n+2)] in accordance with the clock (CLK) timing. The carry signal (CAR) may be output from the previous stage.

Each of the stages [SR(n-1) to (n+2)] includes a control unit 60 that charges and discharges the Q node and QB node, and charges the gate line according to the Q node voltage to raise the waveform of the gate signal ( rising) and may include a buffer that discharges the gate line according to the QB node voltage. The buffer may include a pull-up transistor (Tu) and a pull-down transistor (Td). The output signals [OUT(n-1) to (n+2)] of the stages [SR(n-1) to (n+2)] are gate signals sequentially applied to the gate lines.

According to an embodiment of the present invention, an attempt is made to improve EMI noise in a display panel by using a control signal and a pseudo control signal supplied to at least one of the demultiplexer unit and the gate driver unit.

FIG. 6 is a demultiplexer unit according to an embodiment of the present invention, FIG. 7 is a waveform of a signal applied to the demultiplexer unit according to an embodiment of the present invention, and FIG. 8 is a demultiplexer unit according to an embodiment of the present invention. This is the connection relationship of the level shifter. FIG. 9 is an implementation example of a demultiplexer unit according to an embodiment of the present invention, and FIG. 10 is a cross-sectional view of an array of a demultiplexer unit according to an embodiment of the present invention. The demultiplexer unit 150 may include a plurality of demultiplexers, and hereinafter, for convenience of explanation, one demultiplexer will be used as an example.

Referring to Figures 6 to 8, the demultiplexer includes a first switch element (M1), a second switch element (M2), a third switch element (M3), and a fourth switch element (M4). Here, the first switch element (M1), the second switch element (M2), the third switch element (M3), and the fourth switch element (M4) are connected to the data driver 110 and the neighboring data lines DL1 to 4. There can be connections between them. Data lines DL1 to 4 may be connected to pixel electrodes of subpixels through TFTs. The demultiplexer uses the first switch element (M1), the second switch element (M2), the third switch element (M3), and the fourth switch element (M4) to output a data signal through one channel of the data driver 110. (Vdata) may be time-divided and distributed to the first to fourth data lines DL1 to 4.

The level shifter 140 may output first to fourth MUX signals (MUX1, MUX2, MUX3, and MUX4) in response to the output of the timing controller 130.

Referring to Figures 6 and 7, the first switch element (M1) is turned on in response to the gate high voltage (VGH) of the first MUX signal (MUX1), and then the second switch element (M2) is turned on in response to the gate high voltage (VGH) of the first MUX signal (MUX1). It may be turned on in response to the gate high voltage (VGH) of the signal (MUX2). Then, the third switch element (M3) is turned on in response to the gate high voltage (VGH) of the third MUX signal (MUX3), and then the fourth switch element (M4) is turned on in response to the gate high voltage (VGH) of the fourth MUX signal (MUX4). It may then be turned on in response to voltage (VGH). When the first switch element (M1) is turned on, the data signal (Vdata) is supplied to the first data line (DL1), and when the second switch element (M2) is turned on, the data signal (Vdata) is supplied to the first data line (DL1). 2 is supplied to the data line DL2, and when the third switch element M3 is turned on, the data signal Vdata is supplied to the third data line DL3 and the fourth switch element M4 is turned on. When turned on, the data signal Vdata may be supplied to the fourth data line DL4. Accordingly, the data signal Vdata may be time-divided and distributed to the first to fourth data lines DL1 to 4.

At this time, the first to fourth switch elements (M1, M2, M3, M4) may be disposed in the display panel, and the first to fourth switch elements (M1, M2, M3, M4) may be applied to the first to fourth switch elements (M1, M2, M3, M4). 4 EMI noise may occur within the display panel due to MUX signals (MUX1, MUX2, MUX3, MUX4).

According to an embodiment of the present invention, it is intended to cancel EMI noise using anti-phase signals of the first to fourth MUX signals (MUX1, MUX2, MUX3, and MUX4).

To this end, the demultiplexer according to an embodiment of the present invention is a first pseudo switch to which a first pseudo MUX signal (PMUX 1) generated in the opposite phase of the first MUX signal (MUX 1) and the second MUX signal (MUX2) is applied. It further includes a device (PM1). In addition, the demultiplexer according to an embodiment of the present invention is a second pseudo switch element to which a second pseudo MUX signal (PMUX 2) generated in the opposite phase of the third MUX signal (MUX 3) and the fourth MUX signal (MUX4) is applied. (PM2) may further be included. At this time, the first pseudo switch element (PM1) is disposed between the first switch element (M1) and the second switch element (M2), and the second pseudo switch element (PM2) is disposed between the third switch element (M3) and the fourth switch element (M3). It may be disposed between the switch elements M4. At this time, the first pseudo MUX signal (PMUX 1) and the second pseudo MUX signal (PMUX 2) may be output from the level shifter 140.

At this time, the first pseudo MUX signal (PMUX 1) may include both the anti-phase of the first MUX signal (MUX 1) and the anti-phase of the second MUX signal (MUX2). And, the second pseudo MUX signal (PMUX 2) may include both the anti-phase of the third MUX signal (MUX 3) and the anti-phase of the fourth MUX signal (MUX4). In other words, one pseudo MUX signal includes all the anti-phases of multiple MUX signals, so one pseudo switch element can be used to cancel EMI noise caused by multiple switch elements, and the EMI noise used to cancel EMI noise can be canceled out. The total number of transistors and the area occupied by the transistors can be reduced.

Meanwhile, referring to FIGS. 6 to 10, the source electrode and drain electrode of the first pseudo switch element PM1 are connected to each other, the source electrode and drain electrode of the second pseudo switch element PM2 are connected to each other, and the 1 The source electrode and drain electrode of the pseudo switch element PM1 and the source electrode and drain electrode of the second pseudo switch element PM2 may be connected to the ground (GND).

When the source and drain electrodes of the first pseudo switch element (PM1) are connected to each other and the source and drain electrodes of the second pseudo switch element (PM2) are connected to each other, the source electrode and the drain electrode of the first pseudo switch element (PM1) are connected to each other. Since a channel is formed between the drain electrodes and the source and drain electrodes of the second pseudo switch element (PM2), malfunctions due to the source and drain electrodes of the first pseudo switch element (PM1) and the second pseudo switch element (PM1) are formed. Malfunctions caused by the source and drain electrodes of the pseudo switch element (PM2) can be prevented.

In addition, when the first pseudo switch element (PM1) and the second pseudo switch element (PM2) are connected to the ground (GND), the return path of the current can be shortened, thereby minimizing electromagnetic waves radiated to the atmosphere and EMI. The noise reduction efficiency can be further increased. Figure 11 shows a path in which current is output from a source, passes through a load, and then returns to the source. Referring to FIG. 11(a), it can be seen that while the current returns to the source, it is radiated into the atmosphere in the form of electromagnetic waves. Electromagnetic waves radiated into the atmosphere may act as another noise within the display panel 100. On the other hand, when there is a ground in the return path of the current as shown in FIG. 11(b), the current returns through the ground, so electromagnetic waves radiated to the atmosphere can be minimized.

Meanwhile, referring to FIGS. 9 and 10, a ground guard (GND_G), which is a ground wire connected to the level shifter 140, is disposed between the second switch element (M2) and the third switch element (M3), and the first pseudo The switch element (PM1) and the second pseudo switch element (PM2) may be connected to the ground guard (GND_G). At this time, the ground wire is formed of the same material as the plurality of data lines, and may be connected to the source electrode or drain electrode of the first pseudo switch element PM1 through a contact hole (CNT) formed in the display panel. According to this, the return path of the current to the first pseudo switch element (PM1) and the second pseudo switch element (PM2) can be minimized, and thus electromagnetic waves radiated to the atmosphere can be further reduced.

A first pseudo switch element (PM1) is disposed between the first switch element (M1) and the second switch element (M2), and a second pseudo switch is disposed between the third switch element (M3) and the fourth switch element (M4). It can be seen that the element (PM2) is disposed.

In this way, when an anti-phase signal for a plurality of switch elements is applied to one pseudo switch element, there is no need to arrange pseudo switch elements for each switch element, so the number of pseudo switch elements, the area occupied by the pseudo switch elements, and the cost are reduced. It can be reduced.

At this time, the drain electrode of the first switch element (M1) and the drain electrode of the first pseudo switch element (PM1) are separated from each other, and the drain electrode of the third switch element (M3) and the drain electrode of the second pseudo switch element (PM2) are separated from each other. It can be seen that the electrodes are separated from each other. Accordingly, malfunctions that may occur when the drain electrode of the first switch element (M1) and the drain electrode of the first pseudo switch element (PM1) are connected, and the drain electrode of the third switch element (M3) and the second pseudo switch element ( Malfunctions that may occur by connecting the drain electrode of PM2) can be prevented.

Meanwhile, the drain electrode of the first pseudo switch element (PM1) and the source and drain electrodes of the second pseudo switch element (PM2) may be connected to the ground wired to the gate layer through the contact hole (CNT) formed in the display panel. . In addition, a ground guard (GND_G) connected to the level shifter 140 is disposed between the second switch element (M2) and the third switch element (M3), and the ground guard (GND_G) contacts the ground wired to the gate layer. It can be connected through a hole (CNT).

Here, a single 1:4 demultiplexer is described as an example, but embodiments of the present invention are not limited thereto. The same structure can be applied to the two 1:2 multiplexers shown in FIG. 2. For example, when the first switch element (M1) and the second switch element (M2) are connected to the first channel, and the third switch element (M3) and the fourth switch element (M4) are connected to the second channel, The anti-phase signals of the first switch element (M1) and the second switch element (M2) are simultaneously applied to the first pseudo switch element (PM1), and the third switch element (M3 and M3) are applied to the second pseudo switch element (PM2). The anti-phase signal of the fourth switch element M4 may be applied simultaneously.

12 to 14 show a method of connecting the pseudo switch element of the demultiplexer to the ground according to an embodiment of the present invention. Here, the ground line (GND) refers to the ground connected to the pseudo switch element of the demultiplexer.

Referring to FIG. 12, in a structure where the data driver 110, timing controller 130, and level shifter 140 are separated, the ground line (GND) connected to the pseudo switch element is directly connected to the ground pin of the level shifter 140. can be connected

Alternatively, referring to FIG. 13, in a structure where the data driver 110, timing controller 130, and level shifter 140 are separated, the ground line (GND) connected to the pseudo switch element is the source within the display panel 100. -Can be connected to a ground ring (GND ring) disposed on the drain layer. Here, the ground ring (GND ring) disposed on the source-drain layer in the display panel 100 is formed along the edge of the display panel 100 and may be a ground connected to the level shifter 140. At this time, the ground line (GND) is disposed on the gate layer and may be connected to the ground ring (GND ring) through the contact hole (CNT).

Alternatively, referring to FIG. 14, in a TDDI structure in which the data driver 110, timing controller 130, and level shifter 140 are integrated into one chip, the ground line of the pseudo switch element may be directly connected to the ground pin of TDDI. there is.

Figure 15 is a demultiplexer unit according to another embodiment of the present invention, and Figure 16 is a waveform of a signal applied to the demultiplexer unit according to another embodiment of the present invention. The demultiplexer unit 150 may include a plurality of demultiplexers, and hereinafter, for convenience of explanation, one demultiplexer will be used as an example.

Referring to FIG. 15, the demultiplexer includes a first switch element (M1), a second switch element (M2), and a third switch element (M3). Here, the first switch element (M1), the second switch element (M2), and the third switch element (M3) may be connected between the data driver 110 and the neighboring data lines DL1 to 3. Data lines DL1 to 3 may be connected to pixel electrodes of subpixels through TFTs. The demultiplexer uses the first switch element (M1), the second switch element (M2), and the third switch element (M3) to convert the data signal (Vdata) output through one channel of the data driver 110 into the first to third switch elements. Time division can be distributed to 3 data lines (DL1 to 3).

The level shifter 140 may output first to third MUX signals (MUX1, MUX2, and MUX3) in response to the output of the timing controller 130.

After the first switch element (M1) is turned on in response to the gate high voltage (VGH) of the first MUX signal (MUX1), the second switch element (M2) is turned on in response to the gate high voltage (VGH) of the second MUX signal (MUX2). The third switch element M3 may be turned on in response to the gate high voltage VGH of the third MUX signal MUX3. When the first switch element (M1) is turned on, the data signal (Vdata) is supplied to the first data line (DL1), and when the second switch element (M2) is turned on, the data signal (Vdata) is supplied to the first data line (DL1). 2 is supplied to the data line DL2, and when the third switch element M3 is turned on, the data signal Vdata may be supplied to the third data line DL3. Accordingly, the data signal Vdata may be time-dividedly distributed to the first to third data lines DL1 to 3.

According to an embodiment of the present invention, it is intended to cancel EMI noise using anti-phase signals of the first to third MUX signals (MUX1, MUX2, and MUX3).

To this end, the demultiplexer according to an embodiment of the present invention is a first pseudo switch to which a first pseudo MUX signal (PMUX 1) generated in the opposite phase of the first MUX signal (MUX 1) and the second MUX signal (MUX2) is applied. It further includes a device (PM1). In addition, the demultiplexer according to an embodiment of the present invention may further include a second pseudo switch element (PM2) to which a second pseudo MUX signal (PMUX 2) generated in the opposite phase of the third MUX signal (MUX 3) is applied. there is. At this time, the first pseudo switch element (PM1) is disposed between the first switch element (M1) and the second switch element (M2), and a ground guard is provided between the second switch element (M2) and the third switch element (M3). may be disposed, and the second pseudo switch element PM2 may be disposed on a side of the third switch element M3. At this time, the first pseudo MUX signal (PMUX 1) and the second pseudo MUX signal (PMUX 2) may be output from the level shifter 140.

At this time, the first pseudo MUX signal (PMUX 1) may include both the anti-phase of the first MUX signal (MUX 1) and the anti-phase of the second MUX signal (MUX2). And, the second pseudo MUX signal (PMUX 2) may include the opposite phase of the third MUX signal (MUX 3). In other words, since EMI noise caused by three switch elements can be canceled using two pseudo switch elements, the total number of transistors used to cancel EMI noise and the area occupied by the transistors can be reduced.

According to another embodiment of the present invention, when the demultiplexer includes a first switch element (M1), a second switch element (M2), and a third switch element (M3), one pseudo MUX signal is the first MUX signal. It may include all of the anti-phase of (MUX 1), the anti-phase of the second MUX signal (MUX 2), and the anti-phase of the third MUX signal (MUX 3). According to this, since EMI noise caused by three switch elements can be canceled using one pseudo switch element, the total number of transistors used to cancel EMI noise and the area occupied by the transistors can be reduced.

Meanwhile, embodiments of the present invention may be applied to cancel EMI noise according to a control signal applied to the gate driver as well as the demultiplexer unit.

When the gate driver 120 is implemented in the form of a gate-in-panel (GIP) disposed within the display panel 100, the gate clock, which is one of the gate timing control signals of the gate driver 120, The (GCLK) signal controls the shift timing of the gate signal output from the gate driver 120. That is, at this time, the timing controller 130 may generate a control signal to control the level shifter 140.

Figure 17 shows a GIP circuit according to an embodiment of the present invention, and Figure 18 is a waveform of a signal applied to the GIP circuit according to an embodiment of the present invention.

Referring to FIG. 17, the level shifter 140 supplies gate signals (GATE #1 to GATE #N) generated according to the gate timing control signal to gate lines (GL #1 to GL #N). The gate signal (GATE #1 to GATE #N) applied to the gate lines (GL #1 to GL #N) turns on the switch elements of the subpixels to select pixels in which the voltage of the data signal is charged.

As shown in FIG. 18, the gate clock (GCLK) signal among the gate timing control signals controls the shift timing of the gate signal. To this end, the phase of a plurality of GCLK signals (GCLK1 to GCLK4) applied to the gate lines may be sequentially shifted.

At this time, EMI noise may be generated within the display panel 100 due to a plurality of GCLK signals (GCLK1 to GCLK4).

According to an embodiment of the present invention, it is intended to cancel EMI noise using anti-phase signals of the first to fourth GCLK signals (GCLK1, GCLK2, GCLK3, and GCLK4).

To this end, the GIP circuit according to an embodiment of the present invention is a first GCLK signal to which a first pseudo GCLK signal (PGCLK 1) generated in the opposite phase of the first GCLK signal (GCLK 1) and the second GCLK signal (GCLK 2) is applied. It further includes a pseudo GCLK element (PG1). In addition, the GIP circuit according to an embodiment of the present invention is a second pseudo GCLK signal (PGCLK 2) generated in the opposite phase of the third GCLK signal (GCLK 3) and the fourth GCLK signal (GCLK 4) is applied. It may further include a GCLK element (PG2). At this time, the first pseudo GCLK element PG1 is disposed between the first gate line GL1 and the second gate line GL2, and the second pseudo GCLK element PG2 is disposed between the third gate line GL3 and the fourth gate line GL3. It may be placed between the gate lines (GL4). At this time, the first pseudo GCLK signal (PGCLK 1) and the second pseudo GCLK signal (PGCLK 2) may be output from the level shifter 140.

At this time, the first pseudo GCLK signal (PGCLK 1) may include both the anti-phase of the first GCLK signal (GCLK 1) and the anti-phase of the second GCLK signal (GCLK 2). Additionally, the second pseudo GCLK signal (PGCLK 2) may include both the anti-phase of the third GCLK signal (GCLK 3) and the anti-phase of the fourth GCLK signal (GCLK 4). In other words, since EMI noise caused by a plurality of switch elements can be canceled using one pseudo switch element, the total number of transistors used to cancel EMI noise and the area occupied by the transistors can be reduced.

Meanwhile, the source and drain electrodes of the first pseudo GCLK element (PG1) are connected to each other, the source and drain electrodes of the second pseudo GCLK element (PG2) are connected to each other, and the source and drain electrodes of the first pseudo GCLK element (PG1) are connected to each other. The electrode and drain electrode and the source electrode and drain electrode of the second pseudo GCLK element PG2 may be connected to the ground. According to this, the current applied to the first pseudo GCLK element PG1 and the current applied to the second pseudo GCLK element PG2 may return to the shortest path. Accordingly, electromagnetic waves radiated into the atmosphere can be minimized, and the reduction efficiency of EMI noise can be further increased. In addition, since a channel is formed between the source electrode and the drain electrode of the first pseudo GCLK element PG1 and a channel is formed between the source electrode and the drain electrode of the second pseudo GCLK element PG2, the first pseudo GCLK element ( It is possible to prevent malfunctions caused by the source and drain electrodes of the second pseudo GCLK element (PG1) and malfunctions caused by the source and drain electrodes of the second pseudo GCLK element (PG2).

Figure 19 shows EMI measurement results according to the application of a demultiplexer according to an embodiment of the present invention.

Figure 19(a) shows a first pseudo switch element in which an anti-phase signal of the first MUX signal and the second MUX signal is applied between the first switch element and the second switch element in the demultiplexer including the first to fourth switch elements. This is the result of actually measuring EMI in a structure in which a second pseudo switch element to which an anti-phase signal of the third MUX signal and the fourth MUX signal is applied is disposed between the third switch element and the fourth switch element.

Figure 19(b) shows a first pseudo switch element in which an anti-phase signal of the first MUX signal and the second MUX signal is applied between the first switch element and the second switch element in the demultiplexer including the first to fourth switch elements. Arrange a second pseudo switch element to which an anti-phase signal of the third MUX signal and the fourth MUX signal is applied between the third switch element and the fourth switch element, and place the first pseudo switch element and the second pseudo switch element. This is the result of actual EMI measurement in a structure connected to the ground.

Referring to FIGS. 19(a) and 19(b), it can be seen that the demultiplexer according to an embodiment of the present invention has an EMI noise improvement effect. In particular, it can be seen that the EMI noise improvement effect is higher in a structure in which the first pseudo switch element and the second pseudo switch element are connected to the ground.

In this specification, terms such as first to fourth switch elements and first to second pseudo switch elements are used to describe the components of the embodiment of the present invention, but the order or order of the corresponding components is defined by the terms. is not limited.

Although the present invention has been described above with reference to preferred embodiments, those skilled in the art may make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that you can do it.

100: display panel
110: data driving unit
120: Gate driver
130: Timing controller
140: level shifter
150: Demultiplexer unit

Claims (18)

A display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels disposed in an area where the plurality of gate lines and the plurality of data lines intersect,
A gate driver that supplies gate signals to the plurality of gate lines,
a data driver that supplies data signals to the plurality of data lines;
A demultiplexer unit distributing the data signal to the plurality of data lines,
A timing controller that controls the operation timing of the gate driver, the data driver, and the demultiplexer, and
A level shifter that supplies a control signal and a pseudo-control signal to at least one of the demultiplexer unit and the gate driver unit,
The demultiplexer unit,
A first switch element connected between the data driver and the first data line and supplying the data signal to the first data line in response to a first control signal,
A second switch element connected between the data driver and the second data line and supplying the data signal to the second data line in response to a second control signal, and
It is disposed between the first switch element and the second switch element, and includes a first pseudo switch element to which a first pseudo control signal is applied,
The level shifter is,
Outputting the first control signal, the second control signal, and the first pseudo control signal,
The first pseudo control signal includes an anti-phase pulse with respect to the pulse of the first control signal and an anti-phase pulse with respect to the pulse of the second control signal and is applied to the gate electrode of the first pseudo switch element. . delete According to paragraph 1,
A display device wherein the source electrode and drain electrode of the first pseudo switch element are connected to ground. According to paragraph 3,
The demultiplexer unit,
A third switch element connected between the data driver and the third data line and supplying the data signal to the third data line in response to a third control signal,
A fourth switch element connected between the data driver and the fourth data line and supplying the data signal to the fourth data line in response to a fourth control signal, and
It further includes a second pseudo switch element disposed between the third switch element and the fourth switch element and to which a second pseudo control signal is applied,
The level shifter is,
further output the third control signal, the fourth control signal, and the second pseudo control signal,
The second pseudo control signal includes an anti-phase pulse with respect to the pulse of the third control signal and an anti-phase pulse with respect to the pulse of the fourth control signal and is applied to the gate electrode of the second pseudo switch element. . According to paragraph 4,
A display device wherein the source electrode and drain electrode of the second pseudo switch element are connected to the ground. According to clause 5,
The ground is connected to the level shifter. A display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels disposed in an area where the plurality of gate lines and the plurality of data lines intersect,
A gate driver that supplies gate signals to the plurality of gate lines,
a data driver that supplies data signals to the plurality of data lines;
A demultiplexer unit distributing the data signal to the plurality of data lines,
A timing controller that controls the operation timing of the gate driver, the data driver, and the demultiplexer, and
A level shifter that supplies a control signal and a pseudo-control signal to at least one of the demultiplexer unit and the gate driver unit,
The level shifter outputs a first clock signal, a second clock signal, and a first pseudo clock signal,
The first pseudo clock signal includes an anti-phase pulse with respect to the pulse of the first clock signal and an anti-phase pulse with respect to the pulse of the second clock signal and is applied to the gate electrode of the first pseudo clock switch element. . In clause 7,
The level shifter further outputs a third clock signal, a fourth clock signal, and a second pseudo clock signal,
The second pseudo clock signal includes an anti-phase pulse with respect to the pulse of the third clock signal and an anti-phase pulse with respect to the pulse of the fourth clock signal and is applied to the gate electrode of the second pseudo clock switch element. . According to clause 8,
A display device in which a source electrode and a drain electrode of each of the first pseudo clock switch element and the second pseudo clock switch element are connected to ground. A display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels disposed in an area where the plurality of gate lines and the plurality of data lines intersect, and
A display panel driver for writing data into the pixels,
The display panel is,
A first switch element connected to a first signal line disposed on the display panel and turned on by a first control signal,
a second switch element connected to a second signal line disposed on the display panel and turned on by a second control signal;
A third switch element connected to a third signal line disposed on the display panel and turned on by a third control signal, and
It further includes a first pseudo switch element disposed between the first switch element and the second switch element to which a first pseudo control signal is applied,
A display device in which a ground wire disposed between the second switch element and the third switch element is connected to a source electrode and a drain electrode of the first pseudo switch element. delete According to clause 10,
The ground wire is formed of the same material as the plurality of data lines, and the ground wire is connected to a source electrode or a drain electrode of the first pseudo switch element through a contact hole formed in the display panel. According to clause 10,
The first signal line and the second signal line are each a data line, and the first control signal and the second control signal are each a MUX signal. According to clause 10,
The display device wherein the first signal line and the second signal line are each a gate line, and the first control signal and the second control signal are each a GCLK signal. delete A first switch element connected to the first data line and turned on by the first MUX signal,
A second switch element connected to the second data line and turned on by the second MUX signal, and
It includes a first pseudo switch element disposed between the first switch element and the second switch element and to which a first pseudo MUX signal is applied,
The first MUX signal and the second MUX signal sequentially turn on the first switch element and the second switch element,
The first pseudo MUX signal includes an anti-phase pulse with respect to the pulse of the first MUX signal and an anti-phase pulse with respect to the pulse of the second MUX signal and is applied to the gate electrode of the first pseudo switch element,
A demultiplexer in which the source electrode and drain electrode of the first pseudo switch element are connected to ground. According to clause 16,
A third switch element connected to the third data line and turned on by the third MUX signal,
A fourth switch element connected to the fourth data line and turned on by the fourth MUX signal, and
It includes a second pseudo switch element disposed between the third switch element and the fourth switch element and to which a second pseudo MUX signal is applied,
The third MUX signal and the fourth MUX signal sequentially turn on the third switch element and the fourth switch element,
The second pseudo MUX signal includes an anti-phase pulse with respect to the pulse of the third MUX signal and an anti-phase pulse with respect to the pulse of the fourth MUX signal and is applied to the gate electrode of the second pseudo switch element,
The source electrode and drain electrode of the second pseudo switch element are connected to the ground,
The ground is disposed on a gate layer of the display panel, and the source electrode and drain electrode of the first pseudo switch element and the source electrode and drain electrode of the second pseudo switch element are connected to the ground through a contact hole. According to clause 17,
A demultiplexer in which a ground guard is disposed between the second switch element and the third switch element and is connected to the ground and extends from the gate layer to the source-drain layer.

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