KR20150077896A - Gate driving circuit and organic light emitting diode display device using the same - Google Patents

Abstract

The present invention relates to a gate driving circuit capable of simplifying a circuit structure for successively outputting a scan signal and a light emitting control signal, stabilizing the output of light emitting control signals, and improving reliability, and an organic light emitting diode display device using the same. It includes a display panel where sub pixels respond to a light emitting control signal and display an image with a compensation data voltage; a gate driving circuit which generates and outputs scan pulses and light emitting control signals and drives the light emitting control lines and the display panel the gate line; and a power supply part which supplies a high potential and low potential voltage sources to the power lines of the display panel and also supplies the compensation data voltage to a compensation power line. The gate driving circuit includes shift stages which are subordinately connected to each other and successively output scan pulses, and inverters which simultaneously receives the scan pulses successively outputted to the gate lines and successively outputs and maintains a light emitting signal according to each of the scan pulses.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to a gate driving circuit for simplifying a circuit structure for sequentially outputting a scan signal and a light emission control signal, respectively, while stabilizing the output of the light emission control signals, thereby improving the reliability thereof, and an organic light emitting diode will be.

BACKGROUND ART [0002] Recently, flat panel displays that are emerging include liquid crystal displays (LCDs), field emission displays, plasma display panels, and organic light emitting diodes Emitting Display).

For example, in order to sequentially drive the gate lines formed on the liquid crystal panel or the organic light emitting diode display panel, a shift register for sequentially supplying scan pulses to the gate lines is required.

The shift register includes a plurality of stages for outputting scan pulses, and each stage sequentially outputs one scan pulse. The scan pulses are sequentially supplied to the respective gate lines of the image display panel to sequentially scan the gate lines.

In recent years, in the case of an organic light emitting diode display panel, pixel structures for displaying an image by compensating a data voltage with a separately compensated reference voltage are applied, and sequentially driving emission control lines in addition to a scan pulse driving gate lines The light emission control signals need to be output separately.

The gate driving circuit formed in the organic light emitting diode display panel includes a shift register for sequentially supplying scan pulses to the gate lines, and a shift register for sequentially supplying the emission control signals to the emission control lines. did. However, in the conventional gate control circuit which sequentially outputs the scan pulses and the emission control signals, the number of shift registers increases more than twice, so that the design structure becomes complicated and the size and layout area of the gate control circuit increases I had to deal with various problems.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a gate driving circuit which can simplify a circuit structure for sequentially outputting scan signals and emission control signals, And an organic light emitting diode display using the same.

According to an aspect of the present invention, there is provided a gate driving circuit comprising: a plurality of shift stages connected to each other to sequentially output scan pulses; And a plurality of inverters for simultaneously receiving the scan pulses sequentially output to the gate lines and sequentially outputting and maintaining emission control signals in accordance with the respective scan pulses.

Wherein each of the plurality of inverters comprises at least one first pull-up inverting element for charging the pull-up node with a high potential voltage source and controlling an output period of the light emission control signal outputted through the first control element, Down node during a period in which the scan pulse is supplied, and at least one second pull-down node for connecting the output terminal of the emission control signal to the low potential voltage source through the second control element, - at least one first pull-down inverting element for discharging the pull-up node during the charge period of the pull-down node, and at least one pull- Down inverting element for connecting the first pull-down voltage source to the low-potential voltage source.

Wherein the at least one second pull-down inverting element receives the respective emission control signals directly from an output terminal from which the emission control signals are output, And discharges it with the potential voltage source.

The gate of the second pull-down inverting element is electrically connected to the output terminal from which the emission control signal is output, and the pull-down node to which the source terminal is connected is turned on by the emission control signal, Terminal is connected to the low potential voltage source to which the terminal is connected.

According to another aspect of the present invention, there is provided an organic light emitting diode (OLED) display device using a gate driving circuit, comprising: a plurality of sub- ; A gate driving circuit for generating and outputting a plurality of scan pulses and emission control signals to drive gate lines and emission control lines of the display panel; And a power supply unit for supplying high-potential and low-potential voltage sources to the power supply lines of the display panel and supplying the compensation data voltages to the compensation power supply line, wherein the gate drive circuits are connected to each other, And a plurality of inverters for simultaneously receiving the scan pulses sequentially output to the gate lines and sequentially outputting and maintaining the emission control signals in accordance with the respective scan pulses. .

Each of the plurality of inverters includes at least one first pull-up inverting element for charging the pull-up node with the high potential voltage source and controlling an output period of the light emission control signal outputted through the first control element, Down node during a period during which the scan pulse is supplied and connecting the output terminal of the emission control signal to the low potential voltage source through a second control element, Down inverting element for discharging the pull-up node during a charge period of the pull-down node and at least one first full-down inverting element for discharging the pull-up node during the full- And at least one second pull-down inverting element for connecting the down node to the low potential voltage source.

Wherein the at least one second pull-down inverting element receives the respective emission control signals directly from an output terminal from which the emission control signals are output, And discharges it with the potential voltage source.

The gate of the second pull-down inverting element is electrically connected to the output terminal from which the emission control signal is output, and the pull-down node to which the source terminal is connected is turned on by the emission control signal, Terminal is connected to the low potential voltage source to which the terminal is connected.

The gate driving circuit and the organic light emitting diode display using the gate driving circuit according to the present invention having various technical features as described above can simplify the structure of the gate driving circuit for sequentially outputting the scan signal and the emission control signal, can do.

In addition, the output of the light emission control signals generated and output in the simplified structure can be stabilized and the reliability thereof can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a configuration diagram showing a gate drive circuit according to an embodiment of the present invention; Fig.
Fig. 2 is a circuit diagram of a shift stage and an inverter shown in Fig. 1; Fig.
FIG. 3 is a waveform diagram showing control signals and output signals input to / output from the shift stage and the inverter of FIG. 2;
FIG. 4 is a view illustrating an organic light emitting diode display device using the gate driving circuit of FIG. 1;

Hereinafter, a gate driver circuit and an organic light emitting diode display device using the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram showing a gate driving circuit according to an embodiment of the present invention.

The gate driving circuit shown in FIG. 1 includes a plurality of shift stages ST1 to ST5 which are connected to one another and sequentially output scan pulses Gout1 to Gout5; And

A plurality of scan signals Gout1 to Gout5 sequentially output to the gate lines and sequentially outputting and maintaining the emission control signals EM Out1 to EM Out1 according to the scan pulses Gout1 to Gout5, Of inverters IV1 to IV5.

The plurality of shift stages ST1 to ST5 sequentially generate scan pulses Gout1 to Gout5 in response to an external start signal VST and a plurality of clock signals CLK1 to CLK4, Line and inverters IV1 to IV5. More specifically, when the first shift stage ST1 outputs the first scan pulse Gout1, the second stage ST2 then outputs the second scan pulse Gout2, and then the third stage ST3 And outputs the third scan pulse Gout3. Finally, the nth stage (not shown, n is a natural number of 2 or more) outputs the last scan pulse.

As described above, each of the shift stages ST1 to STn drives the gate line connected to itself by using the scan pulses Gout1 to Gout5, and uses the scan pulses Gout1 to Gout5, And controls the operation of the stage.

Each of the plurality of inverters IV1 to IV5 is simultaneously supplied with scan pulses Gout1 to Gout5 which are respectively connected to the output stages of the shift stages ST1 to ST5 and output to the gate lines. Emission control signals EM Out 1 to EM (EM Out 1 to EM 8) of a polarity inverted form from the input scan pulses Gout 1 to Gout 5, respectively, are supplied from the outside with a light emission start signal (EVST) and a plurality of control clocks (ECLK 1 to ECLK 5) Out1) and sequentially outputs them.

FIG. 2 is a circuit diagram of a shift stage and an inverter shown in FIG. 1, and FIG. 3 is a waveform diagram showing control signals and output signals input to / output from the shift stage and the inverter of FIG.

Each of the shift stages (e.g., the first stage) shown in FIG. 2 includes at least one pull-up switching device Tbv (not shown) for controlling the charging of the first control node Q to the high potential voltage source VDD The second control node QB is charged with the at least one clock signal CLK4 and the high potential voltage source VDD while the first control node Q is charged. And the first control node Q is connected to the first node N1 and the second node N2 to output the clock signal CLK1 of the present stage at the current stage as the scan pulse GOut1, And an output switching element T6 and a second output switching element T7 for connecting the output terminal of the scan pulse GOut1 to the low potential voltage source VSS upon charging of the second control node QB.

The pull-up switching device Tbv and the pull-down switching devices T3 to T5 and T8 and the first and second output switching devices T6 and T7 of the respective shift stages ST1 to ST5 are shown in Fig. And receives at least one clock signal of the start signal VST and the plurality of clock signals CLK1 to CLK4. Then, the scan signal GOut1 is outputted through the first output switching element T6 by sequentially turning on or off in response to the clock signals inputted thereto.

The first shift stage ST1 as the first stage is basically supplied with high potential and low potential voltage sources VDD and VSS and is supplied with at least one of the first to fifth clock signals CLK1 to CLK5 And further receives the start signal VST. The remaining shift stages ST2 to ST5 except for the first shift stage ST1 are connected to the high and low potential voltage sources VDD and VSS and the plurality of clock signals CLK1 to CLK5 except for the start signal VST At least one clock signal pulse is supplied.

Referring to FIG. 3, the first to fifth clock signals CLK1 to CLK5 may be periodically generated to have an amplitude of a gate low voltage level and a gate high voltage level. The first to fifth clock signals CLK1 to CLK5 are supplied to the respective shift stages to be generated so as to simultaneously maintain an active state (high period) for a predetermined period between clock signals generated adjacent to each other and circulated to each other. More specifically, in the case of the second clock signal CLK2, a phase delay of 1/2 to 2/3 pulse width is generated from the first clock signal CLK1, and the third clock signal CLK3 is generated in phase 2 to 3/4 of the pulse width of the third clock signal CLK3, and the fourth clock signal CLK4 is generated by a phase delay of 1/2 to 2/3 of the pulse width of the second clock signal CLK2, . The first clock signal CLK1 is output with a phase delay of 1/2 to 2/3 of the pulse width of the fifth clock signal CLK5. Accordingly, the clock signals output in the adjacent periods remain at a high state simultaneously with each other for a predetermined period of time. For example, the pulse width of the first clock signal CLK1 (the pulse width of the high state) and the pulse width of the second clock signal CLK2 (the pulse width of the high state) are the same, and the first clock signal CLK1, The second half of the second clock signal CLK2 is superimposed on the first half of the second clock signal CLK2. At this time, the overlapping period between the pulse width of the first clock signal CLK1 and the pulse width of the second clock signal CLK2 corresponds to about 1/3 to 1/2 pulse width section.

The first shift stage ST1 sequentially generates the first scan pulse Gout1 in response to the start signal VST and the plurality of clock signals CLK1, CLK4 and CLK5 shown in FIG. 3, The second shift stage ST2 outputs the second scan pulse Gout2 in response to the plurality of clock signals CLK1, CLK2 and CLK5, The third stage ST3 outputs the third scan pulse Gout3, and finally, the last stage outputs the last scan pulse.

Each of the plurality of inverters IV1 to IVn shown in Figs. 1 and 2 charges the pull-up node Q with a high potential voltage source VDD and outputs a light emission control signal Up inverting elements T9 and T12 for controlling the output period of the scan signal EM Out11, a capacitor C2 for maintaining the pull-up node Q in a charged state, and a scan pulse Gout Up node EB to charge the pull-down node EB during the supplied period and connect the output end of the emission control signal EM out to the low potential voltage source VSS via the second control element T13. At least one first pull-down inverting element (T10, T13, T14) for discharging the pull-up node (Q) during the charging period of the pull-down node (EB) At least one second pull-down inverting element T17 for connecting the pull-down node EB to the low potential voltage source VSS during the period during which the emission control signal EM out is output, Respectively.

The first pull-up inverting element T9 and the second pull-up inverting element T18 of each of the inverters IV1 through IVn are controlled by the inverter start signal ERST and the plurality of control pulses ECLK1 To ECLK5). Then, the light emission control signal EM out is outputted through the second control element T13 by being sequentially turned on or off in response to the control pulses inputted to the controller.

The at least one second pull-down inverter T17 is turned on during the period during which the emission control signal EM out is output, that is, during the period in which the pull-up node Q is charged, To be surely discharged so as not to remain. To this end, at least one second pull-down inverting element T17 is directly supplied with each light emission control signal EM out from the output terminal from which each light emission control signal EM out is output, Discharges the pull-down node EB to the low potential voltage source (VSS) in response to the control signal EM out.

For example, the gate terminal of the second pull-down inverting element T17 is electrically connected to the output terminal from which the light emission control signal EM out is outputted, and is turned on according to each light emission control signal EM out A pull-down node (EB) to which a source terminal is connected is connected to a low potential voltage source (VSS) to which a drain terminal is connected. By discharging the pull-down node EB by directly receiving the emission control signal EM out, the amount of the pull-down node EB current during the emission control signal EM out is minimized and maintained .

The first inverter IV1 as the first inverter is basically supplied with the high and low potential voltage sources VDD and VSS and receives the inverter start signal ERST together with the first and third control pulses ECLK1 and ECLK3 It is supplied. The remaining inverters IV2 to IV5 except for the first inverter IV1 are connected to the high potential and low potential power sources VDD and VSS and the plurality of control pulses ECLK1 to ECLK5 except for the inverter start signal ERST. At least one control pulse is supplied.

Referring to FIG. 3, the first to fifth control pulses ECLK1 to ECLK5 may be periodically generated to have an amplitude of a gate low voltage level and a gate high voltage level. The first to fifth control pulses ECLK1 to ECLK5 are supplied to the respective shift stages so as to be generated so as to simultaneously maintain an active state (high period) for a predetermined period between clock signals generated adjacent to each other, and circulated to each other.

The first shift stage ST1 sequentially generates the first scan pulse Gout1 in response to the start signal VST and the plurality of clock signals CLK1, CLK4 and CLK5 shown in FIG. 3, The second shift stage ST2 outputs the second scan pulse Gout2 in response to the plurality of clock signals CLK1, CLK2 and CLK5, The third stage ST3 outputs the third scan pulse Gout3, and finally the nth stage outputs the last scan pulse.

Each of the plurality of inverters IV1 to IV5 is supplied with at least one of the light emission start signal EVST and the plurality of control clocks ECLK1 to ECLK5 from the outside and outputs the input scan pulses Cout1 to Gout5, And sequentially outputs the emission control signals EM Out1 to EM Out1 in the polarity reversed form with delay.

FIG. 4 is a configuration diagram illustrating an organic light emitting diode display device using the gate driving circuit of FIG. 1. Referring to FIG.

The organic light emitting diode display device shown in FIG. 4 includes a display panel 1 in which a plurality of sub-pixels P are arranged to display an image with a compensated data voltage in response to emission control signals EM1 to EMn; Generates and outputs a plurality of scan pulses Cout1 to Gout5 and emission control signals EM Out1 to EM Out1 to drive the gate lines GL1 to GLn and the emission control lines EL1 to ELn of the display panel 1 A gate drive circuit (2); A data driver 3 for driving the data lines DL1 to DLm of the display panel 1; A power supply for supplying the high potential and low potential voltages VDD and VSS to the power supply lines PL1 to PLm of the display panel 1 and supplying the initialization voltage V_init or the compensation voltage to the compensation power supply line CPL, A supply unit 4; And a timing control unit 5 for supplying image data from the outside to the data driver 3 in a state of being aligned with the driving of the display panel 1.

The display panel 1 displays a plurality of subpixels P arranged in a matrix form in each pixel region so that each subpixel P has a light emitting diode OLED and the light emitting diode OLED independently And a pixel circuit for driving the pixel circuit. Specifically, each sub-pixel P as shown in FIG. 2 has a gate line GL, a data line DL, a compensation power line CPL, a light emission control line EL, and a power line PL And a light emitting diode (OLED) connected between the pixel circuit and the low potential voltage (VSS) and equivalently represented by a diode.

The gate drive circuit 2 generates and outputs a plurality of scan pulses Cout1 to Gout5 and emission control signals EM Out1 to EM Out1 to control the gate lines GL1 to GLn of the display panel 1 and the emission control lines (ST1 to ST5) and a plurality of inverters (IV1 to IV5), which have been described in detail with reference to Figs. 1 to 3, in order to drive the transistors EL1 to ELn. Thus, the description of the plurality of shift stages ST1 to ST5 and the plurality of inverters IV1 to IV5 will be described in detail with reference to Figs. 1 to 3 above.

The emission control signals EM1 to EMn sequentially output are supplied to the driving transistor DT during a period in which a current flows through the OLED, that is, during a period during which an image is displayed, Thereby adjusting the period of time that is supplied to the electrode. At this time, the gate driving circuit 2 generates and supplies each of the emission control signals EM1 to EMn so that the emission control signals EM1 to EMn maintain the turn-off level during the period when the initialization voltage is applied to each sub-pixel P. [ That is, in response to the gate control signals GVS from the timing controller 5, the gate drive circuit 2 supplies the respective emission control signals G1 and G2 during the period in which the initialization voltage V_init is supplied during the driving period of each sub- The emission control signals EM1 to EMn are sequentially generated and supplied to the emission control lines EL1 to ELn sequentially so that the emission control signals EM1 to EMn are supplied to the turn-off level.

The data driving unit 3 is connected to the timing control unit 5 using a source start signal SSP and a source shift clock SSC among data control signals DVS from the timing control unit 5. [ That is, the analog data voltage. In response to a source output enable (SOE) signal, a data voltage is supplied to each data line DL1 to DLm. Specifically, the data driver 3 latches the digital image data Data input in accordance with the SSC, and then, in response to the SOE signal, outputs the gate-on signal to the gate lines GL1 to GLn every 1 horizontal period 1 And supplies the data voltages of the horizontal lines to the data lines DL1 to DLm.

The timing controller 5 aligns image data RGB input from the outside in accordance with the size and resolution of the display panel 1 and supplies the aligned digital image data Data to the data driver 3. The timing control unit 5 uses the sync signals input from the outside, for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, Gate and data control signals GVS and DVS and supplies them to the gate drive circuit 2 and the data driver 3, respectively. Particularly, the timing controller 5 controls each of the emission control signals EM1 to EMn to turn off in a period in which the gate drive circuit 2 supplies the initialization voltage V_init during the driving period of each subpixel P And supplies the generated gate control signal GVS to the gate drive circuit 2. [

As described above, in the present invention, the structure of the gate drive circuit for sequentially outputting the scan signal and the emission control signal is simplified by designing the structure as a plurality of shift stages ST1 to ST5 and inverters IV1 to IV5 And can be configured. In addition, by using at least one second pull-down inverting element T17 to ensure that the amount of current does not remain in the pull-down node EB during the period during which the light emission control signal EM out is output, The output of the control signals can be stabilized and the reliability thereof can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (8)

A plurality of shift stages connected to each other in a dependent manner and sequentially outputting scan pulses; And
And a plurality of inverters for simultaneously receiving the scan pulses sequentially output to the gate lines and sequentially outputting and maintaining emission control signals in accordance with the respective scan pulses. The method according to claim 1,
Each of the plurality of inverters
At least one first pull-up inverting element for charging the pull-up node with a high potential voltage source and controlling an output period of the light emission control signal outputted through the first control element,
A capacitor for maintaining the pull-up node in a charged state,
At least one second pull-up inverting element for charging the pull-down node during the supply of the scan pulse and connecting the output terminal of the emission control signal to the low potential voltage source through the second control element,
At least one first pull-down inverting element for discharging said pull-up node during a charge period of said pull-down node, and
And at least one second pull-down inverting element for connecting the pull-down node to the low potential voltage source during a period during which the emission control signal is output. 3. The method of claim 2,
The at least one second pull-down inverting element
Wherein each of the emission control signals is directly supplied from an output terminal from which the emission control signals are output, and the pull-down node is discharged to the low potential voltage source in response to each emission control signal. The method of claim 3,
The gate terminal of the second pull-down inverting element
The pull-down node to which the source terminal is connected is connected to the low potential voltage source to which the drain terminal is connected by being turned on according to each emission control signal, Gate drive circuit. A display panel in which a plurality of sub-pixels are formed to display an image with a compensated data voltage in response to a light emission control signal;
A gate driving circuit for generating and outputting a plurality of scan pulses and emission control signals to drive gate lines and emission control lines of the display panel; And
And a power supply unit for supplying a high potential and a low potential voltage source to the power supply lines of the display panel and supplying the compensation data voltage to the compensation power supply line,
The gate drive circuit
A plurality of shift stages connected to each other in a dependent manner and sequentially outputting scan pulses,
And a plurality of inverters sequentially receiving the scan pulses sequentially output to the gate lines and sequentially outputting and maintaining the emission control signals according to the scan pulses. 6. The method of claim 5,
Each of the plurality of inverters
At least one first pull-up inverting element for charging the pull-up node with the high potential voltage source to control an output period of the light emission control signal outputted through the first control element,
A capacitor for maintaining the pull-up node in a charged state,
At least one second pull-up inverting element for charging the pull-down node during the supply of the scan pulse and connecting the output terminal of the emission control signal to the low potential voltage source through a second control element,
At least one first pull-down inverting element for discharging said pull-up node during a charge period of said pull-down node, and
And at least one second pull-down inverting element for connecting the pull-down node to the low potential voltage source during a period during which the emission control signal is output. The method according to claim 6,
The at least one second pull-down inverting element
Wherein each of the emission control signals is directly supplied from an output terminal from which the emission control signals are output, and the pull-down node is discharged to the low potential voltage source in response to each emission control signal. Device. 8. The method of claim 7,
The gate terminal of the second pull-down inverting element
The pull-down node to which the source terminal is connected is connected to the low potential voltage source to which the drain terminal is connected by being turned on according to each emission control signal, The organic light emitting diode display device.

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