KR102089325B1 - Organic light emitting diode display device and method for driving the same - Google Patents

Abstract

The present invention prevents pixel driving errors and defects that may be caused by overlapping control signals of sub-pixels adjacent to each other when driving sub-pixels of the display panel, thereby preventing display image deterioration and driving errors and damage of driving elements. An organic light emitting diode display and a driving method for improving the reliability, the plurality of sub-pixels in response to the emission control signal display panel formed to display an image with a compensation data voltage; A gate driver driving the gate lines and emission control lines of the display panel; A data driver driving data lines of the display panel; A power supply unit supplying high and low potential voltages to power lines of the display panel and supplying an initialization voltage to the compensation power line; And during the period in which an initialization voltage is applied to the sub-pixels, control the gate driver so that each emission control signal supplied through the emission control lines maintains a turn-off level, and receives image data from the outside. It is characterized in that it is provided with a timing control unit that is appropriately aligned to the driving of the display panel and supplied to the data driving unit.

Description

Organic light emitting diode display and its driving method {ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention prevents pixel driving errors and defects that may be caused by overlapping control signals of sub-pixels adjacent to each other when driving sub-pixels of the display panel, thereby preventing display image deterioration and driving errors and damage of driving elements. It relates to an organic light emitting diode display and a driving method for improving the reliability.

Recently, flat panel displays that have emerged include liquid crystal displays, field emission displays, plasma display panels, and organic light emitting diode displays. Emitting Display). Among them, the organic light emitting diode display device is a self-emission device that emits an organic light emitting layer through recombination of electrons and holes, and has high luminance, low driving voltage, and is capable of ultra-thinning, and is expected to be a next-generation display device.

Each of the plurality of sub-pixels constituting the organic light emitting diode display includes an organic light emitting diode composed of an organic light emitting layer between an anode and a cathode, and a pixel circuit that drives each organic light emitting diode independently.

The pixel circuit includes a plurality of switching transistors and at least one capacitor and driving transistor. The plurality of switching transistors charge the data signal to the capacitor in response to the control signals generated in units of every horizontal period. In addition, the driving transistor adjusts the gradation of each pixel by adjusting the magnitude of the current supplied to the organic light emitting diode to correspond to the magnitude of the image voltage charged in the capacitor in response to the separate emission signal.

In recent years, a variety of pixel structures for displaying high-resolution images have emerged, but there are limitations in simplifying the pixel structure and the pixel driving period, and thus there are limitations in designing and implementing high-resolution panels. Accordingly, by overlapping and driving control signals and emission signals for driving sub-pixels adjacent to each other, a method of extending the image signal compensation and charging period of each sub-pixel has been proposed and applied.

However, in the driving method in which the control signals and the emission signals overlap each other and are driven between adjacent pixels, an abnormal current such as overcurrent occurs due to superimposition of the control signals and the emission signals between adjacent sub-pixels. For example, in the period in which the current sub-pixel is initialized by the control signal of the previous sub-pixel, the light emission signal of the current sub-pixel overlaps, causing an error that the high potential driving voltage is simultaneously supplied. In this case, overcurrent occurs and flows between the initialization voltage and the high-potential driving voltage in the current-stage sub-pixel, and thus there is a problem of deterioration in image quality due to variation in the initialization voltage and damage to the driving element due to overcurrent.

The present invention is to solve the above problems, and when driving the sub-pixels of the display panel, by preventing pixel driving errors and defects that may be caused by overlapping control signals of sub-pixels adjacent to each other, the display quality deteriorates and An object of the present invention is to provide an organic light emitting diode display device and a driving method for preventing driving errors and damages of driving elements and improving reliability.

An organic light emitting diode display device according to an embodiment of the present invention for achieving the above object is a plurality of sub-pixels in response to the emission control signal display panel formed to display an image with a compensation data voltage; A gate driver driving the gate lines and emission control lines of the display panel; A data driver driving data lines of the display panel; A power supply unit supplying high and low potential voltages to power lines of the display panel and supplying an initialization voltage to the compensation power line; And during the period in which an initialization voltage is applied to the sub-pixels, control the gate driver so that each emission control signal supplied through the emission control lines maintains a turn-off level, and receives image data from the outside. It is characterized in that it is provided with a timing control unit that is appropriately aligned to the driving of the display panel and supplied to the data driving unit.

The gate driver sequentially controls the light emission control signals such that each light emission control signal is supplied at a turn-off level during a period in which an initialization voltage is supplied during the driving period of each sub-pixel in response to gate control signals from the timing controller. It is characterized in that to generate and sequentially supply to the light emission control lines.

At least one sub-pixel among the plurality of sub-pixels includes a first and second switching element, a light emission control switching element, a driving switching element, and first and second capacitors, and the first switching element is the gate Turned on according to the scan signal supplied through the line to transfer the data voltage from the data line to a first node to which the output terminal of the first switching element, the gate terminal of the driving switching element, and the first capacitor are commonly connected. Supply, the second switching element is turned on according to the scan signal of the previous stage to supply the initialization voltage to the source terminal of the driving switching element and the second node to which the light emitting diode is connected, wherein the light emission control switching element is Turned on according to the emission control signal to connect the high potential voltage to the drain electrode of the driving switching element, The group driving switching element is characterized in that when a high potential voltage is supplied to the drain electrode through the light emission control switching element, the amount of light emitted from the light emitting diode is adjusted by controlling the amount of current supplied to the light emitting diode according to the voltage level of the first node. do.

The frame period for each sub-pixel or the driving period of one horizontal line is divided into an initialization period, a sampling period, a data injection period, and a light emission period, and the first and second switching elements are turned on during the initialization period. The first and second nodes are initialized to a preset initialization voltage Vini, and each light emission control signal is maintained and supplied at a turn-off level so that the light emission control switching element maintains a turn-off state. It is characterized by.

In addition, a method of driving an organic light emitting diode display device according to an exemplary embodiment of the present invention for achieving the above object includes a display panel formed to display an image with a compensation data voltage in a plurality of sub-pixels in response to a light emission control signal. A method of driving an organic light emitting diode display, comprising: driving a gate line and light emission control lines of the display panel; Driving data lines of the display panel; Supplying high and low potential voltages to power lines of the display panel and supplying an initialization voltage to the compensation power line; And controlling a gate driver to maintain a turn-off level of each light emission control signal supplied through the light emission control lines during a period in which an initialization voltage is applied to the sub-pixels.

In the driving of the light emission control lines, the light emission control signal is sequentially generated so that the light emission control signals are supplied at a turn-off level during a period in which an initialization voltage is supplied during the driving period of each sub-pixel, and the light emission control line is generated. It is characterized by sequentially supplying them.

At least one sub-pixel among the plurality of sub-pixels includes a first and second switching element, a light emission control switching element, a driving switching element, and first and second capacitors, and the first switching element is the gate Turned on according to the scan signal supplied through the line to transfer the data voltage from the data line to a first node to which the output terminal of the first switching element, the gate terminal of the driving switching element, and the first capacitor are commonly connected. Supply, the second switching element is turned on according to the scan signal of the previous stage to supply the initialization voltage to the source terminal of the driving switching element and the second node to which the light emitting diode is connected, wherein the light emission control switching element is Turned on according to the emission control signal to connect the high potential voltage to the drain electrode of the driving switching element, The group driving switching element is characterized in that when a high potential voltage is supplied to the drain electrode through the light emission control switching element, the amount of light emitted from the light emitting diode is adjusted by controlling the amount of current supplied to the light emitting diode according to the voltage level of the first node. do.

The frame period for each sub-pixel or the driving period of one horizontal line is divided into an initialization period, a sampling period, a data injection period, and a light emission period, and the first and second switching elements are turned on during the initialization period. The first and second nodes are initialized to a preset initialization voltage Vini, and each light emission control signal is maintained and supplied at a turn-off level so that the light emission control switching element maintains a turn-off state. It is characterized by.

The organic light emitting diode display device of the present invention having the above characteristics and a driving method thereof prevents pixel driving errors and defects that may be caused by overlapping control signals of sub-pixels adjacent to each other when driving the sub-pixels of the display panel. By doing so, it is possible to prevent display image deterioration and driving errors and damages of the driving elements, and to improve the reliability.

1 is a block diagram showing an organic light emitting diode display according to an exemplary embodiment of the present invention.
2 is an equivalent circuit diagram of one sub-pixel of the display panel shown in FIG. 1;
3 is a waveform diagram illustrating a method of driving an organic light emitting diode display device according to the present invention.
4 is a timing diagram showing a voltage change amount for each of the first and second nodes when driving the pixel circuit of each sub-pixel.
5 is a block diagram schematically illustrating a shift register provided in the gate driver of FIG. 1.
6 is a circuit diagram of a configuration of one stage shown in FIG. 5;
7 is a waveform diagram showing control signals and output signals input / output to the shift register of FIG. 6.
8 is a block diagram schematically showing still another shift register and an inverter provided in the gate driver of FIG. 1.
9 is a circuit diagram of a configuration of an emission control stage and an inverter shown in FIG. 8;
10 is a waveform diagram showing control signals and output signals input / output to the light emission control stage and the inverter of FIG. 9.

Hereinafter, an organic light emitting diode display device and a driving method according to an embodiment of the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

1 is a block diagram showing an organic light emitting diode display according to an exemplary embodiment of the present invention. 2 is an equivalent circuit diagram of one sub-pixel of the display panel shown in FIG. 1.

The organic light emitting diode display illustrated in FIG. 1 includes: a display panel 1 in which a plurality of sub-pixels P are formed to display an image with a compensation data voltage in response to the emission control signals EM1 to EMn; A gate driver 2 for driving the gate lines GL1 to GLn and the emission control lines EL1 to ELn of the display panel 1; A data driver 3 for driving the data lines DL1 to DLm of the display panel 1; Power supplying the high and low potential voltages (VDD, VSS) to the power supply lines (PL1 to PLm) of the display panel (1) as well as supplying the initialization voltage (V_init, or compensation voltage) to the compensation power supply line (CPL) Supply section 4; And during the period in which the initialization voltage is applied to each sub-pixel P, the gate driving unit 2 is controlled such that the respective emission control signals EM1 to EMn maintain the turn-off level, and image data from the outside is received. It is provided with a timing control section (5) to be appropriately aligned to the driving of the display panel (1) and supplied to the data driving section (3).

In the display panel 1, a plurality of sub-pixels P are arranged in a matrix form in each pixel area to display an image, and each sub-pixel P is independent of the light emitting diode OLED and the light emitting diode OLED. It is provided with a pixel circuit driven by. Specifically, each sub-pixel P as shown in FIG. 2 has a gate line GL, a data line DL, a compensation power line CPL, a light emission control line EL, and a power line PL And a pixel circuit connected to) and a light emitting diode (OLED) connected between the pixel circuit and the low potential voltage (VSS) and equivalently represented by a diode. Here, the high potential voltage VDD has a higher voltage level than the low potential voltage VSS. In addition, the low potential voltage VSS may be ground or ground voltage.

The pixel circuit of each sub-pixel P includes first and second switching elements T1 and T2, a light emission control switching element ET, a driving switching element DT, and first and second capacitors Cst and Cdt. It is configured to include.

The first and second switching elements T1 and T2, the light emission control switching element ET, and the driving switching element DT may be composed of an NMOS transistor or a PMOS transistor, and the like, hereinafter, the first and second switching elements ( T1, T2), the light emission control switching element (ET), the driving switching element (DT) will be described an example consisting of an NMOS transistor.

The first switching element T1 is turned on or off according to the scan signal Scan supplied through the gate line GLn, and the data voltage from the data line DL is first node ( N1). The first node N1 is a node to which the output terminal of the first switching element T1 and the gate terminal of the driving switching element DT are commonly connected. The first switching element T1 is turned on in an initialization period, a sampling period, and a data injection period during each horizontal period (initialization period, sampling period, data injection period, and light emission period), and thus the data line DL and the first node ( N1) to form a current path.

The second switching element T2 is turned on or off according to the scan signal of the previous stage, and the source terminal and the light emitting diode of the driving switching element DT drive the initialization voltage V_init applied as a compensation voltage when turned on (OLED) is supplied to the connected second node (N2). The second switching element T2 supplies the reference voltage Vini to the second node N2 so that the data voltage is compensated by being turned on in the initialization period during each horizontal period.

The emission control switching element ET is turned on or off according to the emission signal EM, and when turned on, connects the high potential voltage source VDD to the drain electrode of the driving switching element DT. The light emission control switching element ET is turned on in the sampling period and the light emission period during each horizontal period to connect the high potential voltage source VDD to the drain electrode of the driving switching element DT.

The driving switching element DT is supplied with a high potential voltage VDD to the source electrode through the light emission control switching element ET, and determines the amount of current supplied to the light emitting diode OLED according to the voltage level of the first node N1. By controlling, the light emission amount of the light emitting diode (OLED) is adjusted.

The light emitting diode (OLED) includes an organic layer formed between an anode electrode and a cathode electrode connected to a pixel circuit. The operation sequence and light emission process of the pixel circuit and the light emitting diode OLED will be described in detail later with reference to the attached driving waveform diagram.
The first capacitor Cst is connected between the first node N1 and the second node N2, and the second capacitor Cdt is between a high potential voltage source VDD terminal and the second node N2. Is connected to.

The gate driver 2 scans in response to a gate control signal GVS from the timing controller 5, for example, a gate start pulse (GSP) and a plurality of gate shift clocks (GSC). A signal (eg, a gate voltage of low logic) is sequentially generated, and a pulse width of a scan signal is controlled according to a gate output enable (GOE) signal. Then, the scan signals are sequentially supplied to the gate lines GL1 to GLn. Here, the gate-off voltage (eg, the gate voltage of low logic) is supplied during a period in which the scan signal is not supplied to the gate lines GL1 to GLn.

Further, the gate driver 2 sequentially generates high or low logic light emission control signals EM1 to EMn and supplies them to the light emission control lines EL1 to ELn. Here, the sequentially output light emission control signals EM1 to EMn are periods in which a current flows through the light emitting diode OLED, that is, a period in which an image is displayed and the high potential voltage source VDD is a driving switching element DT. It is to adjust the period supplied to the drain electrode of the. At this time, the gate driver 2 generates and supplies each light emission control signal EM1 to EMn to maintain a turn-off level during a period in which an initialization voltage is applied to each sub-pixel P. That is, the gate driving unit 2 responds to the gate control signals GVS from the timing control unit 5 during each driving period of the sub-pixels P during the period during which the initialization voltage V_init is supplied. The emission control signals EM1 to EMn are sequentially generated so that the EM1 to EMn) are supplied at a turn-off level, and are sequentially supplied to the emission control lines EL1 to ELn.

The data driver 3 uses the source start pulse (SSP) and the source shift clock (SSC) among the data control signals DVS from the timing controller 5 to control the timing controller 5. The digital image data (Data) input from is converted into an analog voltage, that is, an analog data voltage. In addition, a data voltage is supplied to each data line DL1 to DLm in response to a source output enable (SOE) signal. Specifically, the data driver 3 latches the digital image data Data input according to the SSC, and then every 1 horizontal cycle in which a gate-on signal is supplied to each gate line GL1 to GLn in response to the SOE signal. Data voltages for horizontal lines are supplied to each data line DL1 to DLm.

The timing controller 5 aligns the image data RGB input from the outside according to the size and resolution of the display panel 1, and supplies the aligned digital image data Data to the data driver 3. In addition, the timing control unit 5 uses synchronization signals input from the outside, for example, dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync. The gate and data control signals GVS and DVS are generated and supplied to the gate driver 2 and the data driver 3, respectively. In particular, the timing controller 5 supplies the light emission control signals EM1 to EMn to turn-off levels during the period in which the initialization voltage V_init is supplied during the driving period of the sub-pixels P by the gate driver 2. The gate control signal GVS is generated to be supplied to the gate driver 2.

3 is a waveform diagram illustrating a method of driving an organic light emitting diode display device according to the present invention. And, FIG. 4 is a timing diagram showing the amount of voltage change for each of the first and second nodes when driving the pixel circuit of each sub-pixel.

Referring to FIGS. 3 and 4, a frame period for each sub-pixel or a driving period of one horizontal line is divided into an initialization period, a sampling period, a data writing period, and a light emission period, and is driven separately. You can. At this time, initialization may be performed using a horizontal period of the previous stage.

First, in the initialization period (Intial), the first and second switching elements T1 and T2 are turned on. During this initialization period, the first and second nodes N1 and N2 are initialized with a preset initialization voltage Vini. In the initialization period, the emission control signals EM1 to EMn are maintained and supplied at a turn-off level, so that the emission control switching element ET maintains a turn-off state. Accordingly, the high potential voltage VDD is not supplied to the first node N1 including the driving switching element DT.

In the sampling period Sampling, the data voltage is supplied to the first node N1 through the first switching element T1 while the light emission control switching element ET and the driving switching element DT are turned on. Then, as the current flowing through the driving switching element DT flows into the second node N2, the threshold voltage Vth of the driving switching element DT is sensed. At this time, the voltage level of the second node N2 converges from the initialization voltage Vini to “VDD-Vth”.

In the data writing period (Data writing), the data voltage is injected to the first node N1, and since the second node N2 is in the floating state, it rises by the changed voltage to maintain the sampling value of the previous period.

In the next light emission period, the light emission control switching element ET and the driving switching element DT are turned on. The driving transistor DT supplies a driving current to the light emitting diode OLED according to the voltage level of the first node N1 injected in the previous period.

As described above, in the present invention, while the image voltage charged in each sub-pixel is compensated with the initialization voltage, the emission control signals EM1 to EMn are maintained at the turn-off level during the initialization period during the driving period of each sub-pixel. And by being supplied, it is possible to prevent pixel driving errors and defects that may be caused by overlapping of control signals of sub-pixels adjacent to each other.

5 is a block diagram schematically illustrating a shift register provided in the gate driver of FIG. 1. And, FIG. 6 is a circuit diagram of a stage shown in FIG. 5, and FIG. 7 is a waveform diagram showing control signals and output signals input / output to the shift register of FIG. 6.

As illustrated in FIG. 5, the gate driver 2 includes a plurality of stages GD 1st to GD nth that are connected to each other and sequentially output scan signals 1st GDO to nth GDO. Each stage GD 1st to GD nth includes a start signal VST and a plurality of clock signals GCLK1 to GCLK4 input from the timing controller 5 or the outside, that is, the start signal VST shown in FIG. 7 and The scan signals GD out n are sequentially generated in response to the plurality of clock signals GCLK1 to GCLK4, and are sequentially supplied to the gate lines GL1 to GLn.

As shown in FIG. 6, each stage GD 1st to GD nth charges a pull-up node to control at least one pull-up switching element Tbv controlling the output of the first output switching element T6. , A plurality of pull-down switching elements T3, T4, T5, and T8 are provided to charge the pull-down node and discharge the pull-up node to control the output of the second output switching element T7. The pull-up switching elements Tbv and pull-down switching elements T3, T4, T5, T8 of each stage GD 1st to GD nth, and the first and second output switching elements T6, T7 respectively The scan signal GD out n through the first output switching element T6 is sequentially turned on or off in response to the start signal VST and the plurality of clock signals GCLK1 to GCLK4 shown in FIG. 7. ).

FIG. 8 is a block diagram schematically showing another shift register and an inverter provided in the gate driver of FIG. 1. In addition, FIG. 9 is a circuit diagram of one light emission control stage and an inverter shown in FIG. 8, and FIG. 10 is a waveform diagram showing control signals and output signals input / output to the light emission control stage and the inverter of FIG. 9.

As illustrated in FIG. 8, the gate driver 2 is connected to each other in a plurality of emission control stages (EMG 1st to EMG nth) that sequentially output shift signals and emission control signals in response to each shift signal ( EMG Out n, EM1 to EMn) are provided with a plurality of inverters sequentially output.

Each light emission control stage (EMG 1st to EMG nth) is a start signal (VST) and a plurality of clock signals (GCLK1 to GCLK4) input from the timing controller (5) or the outside, that is, the start signal (VST) shown in FIG. ) And a plurality of clock signals (GCLK1 to GCLK4) sequentially generate shift signals, which are sequentially supplied to respective inverters.

As shown in FIG. 9, each light emission control stage (EMG 1st to EMG nth) is configured in the same manner as each stage (GD 1st to GD nth) of FIG. 6, and sequentially generates shift signals, respectively. It is supplied sequentially to the inverter. At this time, pull-up switching elements Tbv and pull-down switching elements T3, T4, T5, and T8 of each light emission control stage EMG 1st to EMG nth, and first and second output switching elements T6, T7) each of which is sequentially turned on or off in response to the start signal VST and the plurality of clock signals GCLK1 to GCLK4 shown in FIG. 7, thereby shifting the signal through the first output switching element T6 (GD out n) is output.

Each inverter also includes a plurality of pull-up inverting elements T9 and T11, a plurality of pull-down inverting elements T10 and T14, and third and fourth output switching elements T12 and T13, The emission control signals EMG Out n, EM1 to EMn are output through the third output switching element T12 in response to the emission control start signal EMGVST and the plurality of clock signals EMGCLK1 to EMCLK4 shown in FIG. 10. do.

On the other hand, the present invention described above is not limited to the above-described embodiments and the accompanying drawings, it is possible to various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention, the technical field to which the present invention pertains It will be obvious to those with conventional knowledge.

Claims (8)

A display panel in which a plurality of sub-pixels are configured to display an image with a compensation data voltage in response to the emission control signal;
A gate driver driving the gate lines and emission control lines of the display panel;
A data driver driving data lines of the display panel;
A power supply unit supplying high and low potential voltages to power lines of the display panel and supplying an initialization voltage to the compensation power line; And
During the period in which an initializing voltage is applied to the sub-pixels, each light emission control signal supplied through the light emission control lines controls the gate driver to maintain a turn-off level, and displays image data from the outside. It is provided with a timing control unit that is appropriately aligned to the driving of the panel and supplied to the data driving unit.
At least one sub-pixel among the plurality of sub-pixels,
A light emitting diode disposed between power lines supplying the high potential and low potential voltage,
A driving switching element disposed between the power supply line supplying the high potential voltage and the light emitting diode to control the amount of current supplied to the light emitting diode according to the voltage level of the first node;
A first switching element that is turned on according to a scan signal supplied through the gate line and supplies a data voltage from the data line to the first node;
A second switching element which is turned on according to the scan signal of the previous stage and supplies the initialization voltage to the second node to which the driving switching element and the light emitting diode are connected,
A light-emitting control switching device that is turned on according to the light emission control signal and supplies the high potential voltage to the driving switching device;
A first capacitor connected between the first node and the second node,
And a second capacitor connected between the second node and a power line supplying the high potential voltage,
The frame period for each sub-pixel or the driving period of one horizontal line is divided into an initialization period, a sampling period, a data injection period, and a light emission period, and is driven.
In the initialization period
The scan signal supplied through the gate line and the scan signal of the previous stage are controlled so that the first and second switching elements are turned on, so that the first and second nodes are initialized to a preset initialization voltage Vini. , The emission control signal is maintained and supplied at a turn-off level so that the emission control switching element maintains a turn-off state,
In the sampling period
The scan signal supplied through the gate line and the scan signal of the previous stage are controlled so that the first switching element is turned on and the second switching element T2 is turned off, and the light emission control switching element ET is controlled. The organic light emitting diode display device, characterized in that the emission control signal is controlled to turn on. According to claim 1,
In the data injection period
The first switching element is turned on, the scan signal supplied through the gate line and the scan signal of the previous stage are controlled so that the second switching element is turned off, and the light emission control switching element is turned off. An organic light emitting diode display device characterized in that the emission control signal is controlled. According to claim 1,
In the light emission period
The scan signal supplied through the gate line and the scan signal of the previous stage are controlled so that the first and second switching elements T1 and T2 are turned off, and the light emission is performed so that the light emission control switching element is turned on. An organic light emitting diode display device characterized in that the control signal is controlled. delete delete delete delete delete

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