KR20120072816A - Organic light emitting diode display device - Google Patents

Abstract

PURPOSE: An organic light emitting diode display device is provided to prevent abnormal emission by making a plurality of TFT turned-off prior to the first applying point. CONSTITUTION: A display panel(2) defines intersection pixels. A gate driving unit(4) supplies a plurality of gate signals to a plurality of gate lines. A data driving unit(6) supplies a data voltage to a plurality of data lines. A timing controller(8) controls a gate driving unit and data driving unit. A plurality of gate light testing switching elements supply a gate high voltage to a plurality of gate lines. A plurality of data light testing switching elements supply a data inspection signal to a plurality of data lines.

Description

Organic light emitting diode display device {ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE}

The present invention is to solve the above problems, and relates to an organic light emitting diode display device that can prevent the abnormal light emission phenomenon caused by the application of a high potential driving voltage at the beginning of the drive.

Recently, an organic light emitting diode (OLED) display device, which displays an image by controlling an emission amount of an organic light emitting layer, has been spotlighted as a flat panel display device that can reduce weight and volume, which is a disadvantage of a cathode ray tube (CRT). .

In the OLED display, a plurality of pixels are arranged in a matrix to display an image. Each pixel includes an OLED and a pixel driver that adjusts the luminance of each pixel by adjusting an amount of current flowing through the OLED. The pixel driver includes a plurality of thin film transistors (hereinafter referred to as TFTs) and at least one capacitor. The pixel driver is supplied with a data voltage, a plurality of control signals for driving a plurality of TFTs, a high potential driving voltage, and the like.

The pixel driver is driven by dividing the image display period into an initialization period, a threshold voltage sensing period of the driving TFT, and an emission period according to a plurality of control signals.

On the other hand, the nodes connected to the plurality of TFTs remain in a floating state until the driving of the OLED display is first started and the plurality of control signals are supplied to the pixel driver. However, when a high potential driving voltage is initially supplied to the pixel driver at the beginning of driving in which the nodes connected to the plurality of TFTs maintain the floating state, the current path from the pixel driver to the OLED is because the plurality of TFTs are not surely turned off. Is formed. Accordingly, in the conventional OLED display, unwanted current is supplied to the OLED at the initial driving time and at the time when the high potential driving voltage is first applied, thereby causing an abnormal emission phenomenon such as flickering.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an OLED display device capable of preventing abnormal light emission phenomenon caused by the application of a high potential driving voltage at the initial stage of driving.

In order to achieve the above object, an organic light emitting diode display according to an exemplary embodiment of the present invention may include a display panel defining an intersection pixel of a plurality of gate lines and a plurality of data lines; A gate driver supplying a plurality of gate signals to the plurality of gate lines; A data driver supplying data voltages to the plurality of data lines; A timing controller controlling the gate driver and the data driver; A plurality of gate lighting test switching elements corresponding to the plurality of gate lines in a one-to-one manner and supplying a gate high voltage to the plurality of gate lines in response to a first switching signal; And a plurality of data lighting inspection switching elements corresponding to the plurality of data lines in a one-to-one manner and supplying a data inspection signal to the plurality of data lines in response to a second switching signal.

The first switching signal is output in a low state from a first time point to a third time point, is output in the gate high state after the third time point, and the first time point is a power-on time point of the organic light emitting diode display. The third time point is a time point at which the gate driver starts supplying the plurality of gate signals to the plurality of gate lines, and a high potential driving voltage is applied to the display panel between the first time point and the third time point. This is the second time point that is applied first.

The pixel includes an organic light emitting diode and a plurality of switching elements for independently driving the organic light emitting diodes, wherein the plurality of switching elements are turned off in a period from the first time point to the third time point. do.

The plurality of gate signals may not be output in a period from the first time point to the third time point.

The plurality of switching elements are P type thin film transistors.

In addition, to achieve the above object, an organic light emitting diode display according to another exemplary embodiment of the present invention includes a display panel that defines an intersection pixel of a plurality of gate lines and a plurality of data lines; A timing controller configured to output a plurality of gate control signals and a plurality of data control signals; A shift register configured to output a shift register out signal in response to the plurality of gate control signals; A gate signal output unit configured to generate a plurality of gate signals in response to the shift register-out-signal, and supply the plurality of gate signals to the plurality of gate lines; And a light emission controller configured to supply a gate high voltage to the plurality of gate lines from a driving start time until the gate signal output unit outputs the plurality of gate signals. And a data driver supplying data voltages to the plurality of data lines in response to the plurality of data control signals.

The gate signal output unit may include a first switching device configured to supply a gate low voltage to a first node in response to a k th clock pulse; A second switching element configured to supply the gate high voltage to the first node in response to the shift register out signal; A third switching element configured to supply the gate low voltage to the first node according to a potential of a second node; A fourth switching element configured to output the Gyer low voltage to the plurality of gate lines according to the potential of the first node; A fifth switching device configured to output the gate high voltage to the plurality of gate lines in response to the shift register out signal; A first capacitor coupled between a k + 2 clock pulse supply line and the first node; And a second capacitor connected between the first node and the second node.

The light emission controller may include a sixth switching element configured to supply the gate high voltage to the first node in response to a switching signal; And a seventh switching device configured to output the gate high voltage to the plurality of gate lines in response to the switching signal.

The switching signal may be output in a low state from the driving start time until the gate signal output unit outputs the plurality of gate signals.

The first to seventh switching elements are P type thin film transistors.

According to an exemplary embodiment of the present invention, a plurality of TFTs provided in each pixel P and connected to the plurality of gate lines GL are turned off before the first application point P2 of the high potential driving voltage. Accordingly, there is an effect that can prevent the abnormal light emission phenomenon caused by the application of the high potential driving voltage in the early stage of driving.

1 is a configuration diagram of an OLED display according to a first embodiment of the present invention.
FIG. 2 is a driving waveform diagram of the first and second switching signals G_EN and D_EN shown in FIG. 1.
FIG. 3 is a circuit diagram of the pixel P shown in FIG. 1.
FIG. 4 is a driving waveform diagram of the pixel P shown in FIG. 3.
5 is a circuit diagram for explaining the cause of abnormal light emission.
6 is a circuit diagram for explaining the effect of the first embodiment of the present invention.
7 is a configuration diagram of the gate driver 4 according to the second embodiment of the present invention.
FIG. 8 is a driving waveform diagram of the gate driver 4 shown in FIG. 7.

Hereinafter, an OLED display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

According to an exemplary embodiment of the present invention, a plurality of TFTs provided in each pixel P and connected to the plurality of gate lines GL are turned off before the first application point P2 of the high potential driving voltage. To this end, the embodiment of the present invention is characterized in that the gate high voltage VGH is supplied to the plurality of gate lines GL from the first application point of the high potential driving voltage P2 to the start point of the display period P3.

Meanwhile, in the exemplary embodiment of the present invention, the TFT may be configured as a P type or an N type, and will be described as a P type TFT for convenience of description below. Therefore, the gate high voltage VGH is a voltage for turning off the TFT, and the gate low voltage VGL is a voltage for turning on the TFT. In describing the pulse type signal, the gate high voltage VGH is defined as a “high state VGH”, and the gate low voltage VGL is defined as a “low state VGL”.

Hereinafter, the above-described embodiments of the present invention will be described by dividing the first and second embodiments.

1 is a configuration diagram of an OLED display according to a first embodiment of the present invention.

An OLED display shown in FIG. 1 includes a display panel 2 defining an intersection pixel P of a plurality of gate lines GL and a plurality of data lines DL; A gate driver 4 driving a plurality of gate lines GL; A data driver 6 driving a plurality of data lines DL; And a timing controller 8 for controlling the driving timing of the gate driver 4 and the data driver 6.

The display panel 2 includes a data lighting inspection section 10 and a gate lighting inspection section 12 each having a plurality of lighting inspection TFTs (TD, TG) for lighting inspection. In FIG. 1, the data lighting inspection unit 10 and the gate lighting inspection unit 12 are separately shown from the display panel 2 for convenience of description, but the data lighting inspection unit 10 and the gate lighting inspection unit 12 are displayed in the display panel ( 2) is built in.)

Here, the data lighting inspection section 10 is provided with a plurality of data lighting inspection TFTs (TD). Here, the plurality of data lighting test TFTs TD are connected in one-to-one correspondence with the plurality of data lines DL. The plurality of data lighting check TFTs TD supply the data checking signal D_sig to the plurality of data lines DL in response to the second switching signal D_EN.

The gate lighting inspection section 12 includes a plurality of gate lighting inspection TFTs TG. Here, the plurality of gate lighting check TFTs TD are connected in one-to-one correspondence with the plurality of gate lines GL. The plurality of gate lighting check TFTs TG supply the gate high voltage VGH to the plurality of gate lines GL in response to the first switching signal G_EN.

In the related art, the data lighting inspection unit 10 and the gate lighting inspection unit 12 were provided for the lighting inspection of the display panel 2, and remained unnecessary in the display period of actually displaying the image. The first embodiment of the present invention is characterized in that the gate high voltage VGH is supplied to the plurality of gate lines GL by using the gate lighting inspection unit 12 which is not used in actual driving.

FIG. 2 is a driving waveform diagram of the first and second switching signals G_EN and D_EN shown in FIG. 1. In FIG. 2, P1 denotes a "power on time (hereinafter referred to as a first time point) of the OLED display device", P2 denotes "the first application point of the high potential driving voltage (hereinafter referred to as a second time point)", and P3 denotes a "display period." Starting time point (hereinafter, referred to as a third time point). Here, the third time point P3 is a time point at which the gate driver 4 starts supplying a plurality of gate signals to the plurality of gate lines GL.

Referring to FIG. 2, it can be seen that the second time point P2 is between the first time point P1 and the third time point P3. In this case, the first switching signal G_EN is output in the low state VGL from the first time point P1 to the third time point P3 and in the high state VGH after the third time point P3. Accordingly, the plurality of gate lighting inspection TFTs TG are turned on from the first time point P1 to the third time point P3 to supply the gate high voltages VGH to the plurality of gate lines GL. In addition, the plurality of gate lighting check TFTs TG are turned off after the third time point P3 to block the interference to the plurality of gate lines GL.

On the other hand, the second switching signal D_EN is continuously output to the high state VGH after the first time point P1. Accordingly, the plurality of data lighting check TFTs TD are turned off after the first time point P1 to block the interference to the plurality of data lines DL.

Accordingly, the plurality of TFTs connected to the plurality of gate lines GL and provided in each pixel P may be turned off from the first time point P1 to the third time point P3 and supplied to the OLED. It can cut off the current and prevent the initial abnormal emission.

The configuration of the first embodiment of the present invention will be described in detail as follows.

Referring to FIG. 1, the timing controller 8 arranges the image data RGB, which is input from the outside, to the data driver 6 in alignment with the size and resolution of the display panel 2. The timing controller 8 may include a gate using a synchronization signal input from the outside, for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, or the like. And generate data control signals GCS and DCS and supply them to the gate driver 4 and the data driver 6, respectively.

The gate driver 4 receives a plurality of gate signals in response to a gate control signal GCS from the timing controller 8, for example, a gate start pulse GSP, a plurality of clock pulses CLK1 to CLK4, and the like. Is generated and supplied to the gate line GL. Here, the plurality of gate signals include a light emission signal EM and a scan signal SCAN, which are replaced with the description of the pixel driver. The gate driver 4 may be embedded in at least one side of the display panel 2 in the form of a gate in panel.

The data driver 6 uses the source start pulse SSP, the source shift clock SSC, and the like among the data control signals DCS from the timing controller 8. The image data RGB inputted from the data is converted into a data voltage Vdata. The data driver 4 supplies the converted data voltage Vdata to the plurality of data lines DL in response to a source output enable (SOE) signal.

FIG. 3 is a circuit diagram of the pixel P shown in FIG. 1. 4 is a driving waveform diagram of the pixel P shown in FIG. 3.

The pixel P shown in FIG. 3 includes an OLED and a pixel driver that independently drives the OLED. The pixel driver includes first to fourth thin film transistors (hereinafter, referred to as TFTs) T1 to T4, a driving TFT DT, and a capacitor C. FIG. The OLED is connected between the pixel driver and the low potential driving voltage (VSS) supply line, and is equivalently represented by a diode.

The pixel driver is supplied from the data voltage Vdata, the reference voltage Vref, the high potential driving voltage VDD, and the plurality of gate lines GL, and is supplied from the first to fourth TFTs. A plurality of control signals SCAN and EM for controlling the T1 to T4 are supplied. In this case, the high potential driving voltage VDD has a potential higher than the low potential driving voltage VSS. The reference voltage Vref has a potential between the high potential driving voltage VDD and the low potential driving voltage VSS. Also, the low potential drive voltage VSS is typically set to the ground voltage.

The first TFT T1 supplies the data voltage Vdata to the first node N1 in response to the scan signal SCAN. Here, the first node N1 is a node to which the output terminal of the first TFT T1 and the output terminal of the second TFT T2 are commonly connected.

The second TFT T2 supplies the reference voltage Vref to the first node N1 in response to the light emission signal EM.

The third TFT T3 connects the drain electrode d of the driving TFT DT and the second node to each other in response to the scan signal SCAN. The second node N2 is a node connected to the gate electrode g of the driving TFT DT.

The fourth TFT T4 connects the drain electrode of the driving TFT DT and the anode electrode of the OLED to each other in response to the light emission signal EM.

The driving TFT DT is supplied with the high potential driving voltage VDD to the source electrode s, and controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the potential of the second node.

The capacitor C is connected between the first node N1 and the second node N2.

The OLED is composed of an anode electrode connected to the pixel driver, a cathode electrode supplied with a low potential driving voltage, and an organic layer formed between the anode electrode and the cathode electrode.

 Referring to FIG. 4, the pixel driver outputs the first period ① during which the scan signal SCAN and the emission signal EM are output in the low state VGL, and the scan signal SCAN is output in the high state VGH. A second period (2) during which the light emission signal EM is output in the low state VGL, and a third period (3) during which the light emission signal EM is output in the high state VGH and output as the scan signal SCAN Driven by dividing into.

Specifically, the first period ① is a period in which the first to fourth TFTs T1 to T4 are turned on to initialize the first and second nodes N1 and N2. The second period ② is a period in which the first and third TFTs T1 and T3 are turned on to program the data voltage Vdata and sense the threshold voltage of the driving TFT DT. The third period ③ is a period during which the OLED emits light by supplying a driving current to the OLED according to the potential of the second node N2.

However, the scan signal SCAN and the emission signal EM are not supplied to the pixel P as described above from the first time point P1 to the third time point P3. Accordingly, each node of the pixel P maintains a floating state between the first time point P1 and the third time point P3. At this time, when the high potential driving voltage VDD is supplied to the pixel P at the second time point P2, each of the TFTs T1 to T4 and DT of the pixel P is not surely turned off. Is formed and current is supplied to the OLED.

In order to prevent this, as shown in FIG. 6, the gate high voltage VGH from the plurality of gate lines GL in the period from the first time point P1 to the third time point P3 is shown in FIG. 6. ) Is supplied. Accordingly, in the period from the first time point P1 to the third time point P3, the first to fourth TFTs DT are turned off and current supply to the OLED is cut off.

As described above, according to the first embodiment of the present invention, the gate high voltages are applied to the plurality of gate lines GL by using the gate lighting inspection unit 12 from the first time point P1 to the third time point P3. VGH). Accordingly, it is possible to block the supply of unwanted current to the OLED to prevent the initial abnormal emission phenomenon. In addition, since the first embodiment uses a plurality of gate lighting check TFTs TG when the gate high voltages VGH are supplied to the plurality of gate lines GL, there is no need to provide a separate switching device. have.

Hereinafter, an OLED display according to a second embodiment of the present invention will be described. Like the first embodiment, the second embodiment supplies the gate high voltage VGH to the plurality of gate lines GL in the period from the first time point P1 to the third time point P3. To this end, the first embodiment uses the gate lighting inspection unit 12, but in the second embodiment, the gate driver 4 has a plurality of gate lines in a period from the first time point P1 to the third time point P3. Further provided is a TFT for supplying a gate high voltage VGH to GL).

Basically, the second embodiment has the same configuration as the first embodiment, and the gate driver 4 will be described in detail below.

7 is a configuration diagram of the gate driver 4 according to the second embodiment of the present invention. 8 is a driving waveform diagram of the gate driver 4 shown in FIG. 7.

The gate driver 4 illustrated in FIG. 7 includes a gate signal output unit 14 and a light emission controller 16.

The gate signal output unit 14 generates a plurality of gate signals SCAN and EM in the image display period (after the third time point P3) and supplies them to the plurality of gate lines GL.

The light emission controller 16 supplies the gate high voltage VGH to the plurality of gate lines GL during the initial driving period, that is, the period from the first time point P1 to the third time point P3.

In detail, the gate signal output unit 14 includes fifth to ninth TFTs T5 to T9 and second and third capacitors C2 and C3.

The fifth TFT T5 supplies the gate low voltage VGL to the third node N3 in response to the second clock pulse CLK2.

The sixth TFT T6 supplies the gate high voltage VGH to the third node N3 in response to the shift register out signal SRO. Here, the shift register out signal SRO is a signal provided from a shift register (not shown). The shift register is included in the gate driver 4 and sequentially outputs the shift register-out-signal SRO in response to the plurality of gate control signals GCS.

The seventh TFT T7 supplies the gate low voltage VGL to the third node N3 according to the potential of the fourth node N4. The fourth node N4 is an output terminal and is a node connected to the gate line GL.

The eighth TFT T8 outputs the gate low voltage VGL to the gate line GL according to the potential of the third node N3.

The ninth TFT T9 outputs the gate high voltage VGH to the gate line GL in response to the shift register out signal SRO.

The second capacitor C2 is connected between the fourth clock pulse CLK4 supply line and the third node N3.

The third capacitor C3 is connected between the third node N3 and the fourth node N4.

The light emission controller 16 includes tenth and eleventh TFTs T10 and T11.

The tenth TFT T10 supplies the gate high voltage VGH to the third node N3 in response to the third switching signal SOC.

The eleventh TFT T11 outputs the gate high voltage VGH to the gate line GL in response to the third switching signal SOC.

On the other hand, the third switching signal SOC for controlling the light emission controller 16 is output in the low state VGL from the first time point P1 to the third time point P3, and high after the third time point P3. It is output as the state VGH. Accordingly, the tenth and eleventh TFTs T10 and T11 are turned on from the first time point P1 to the third time point P3. Then, the tenth TFT T10 supplies the gate high voltage VGH to the third node N3 to turn off the eighth TFT T8. The eleventh TFT T11 outputs the gate high voltage VGH to the gate line GL.

As described above, the second embodiment of the present invention uses a plurality of gate lines GL by using the light emission controller 16 of the gate driver 4 during the period from the first time point P1 to the third time point P3. ) To supply the gate high voltage VGH. Accordingly, it is possible to block the supply of unwanted current to the OLED to prevent the initial abnormal emission phenomenon.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

10: data lighting inspection unit 12: gate lighting inspection unit

Claims (10)

A display panel defining pixels at intersections of the plurality of gate lines and the plurality of data lines;
A gate driver supplying a plurality of gate signals to the plurality of gate lines;
A data driver supplying data voltages to the plurality of data lines;
A timing controller controlling the gate driver and the data driver;
A plurality of gate lighting test switching elements corresponding to the plurality of gate lines in a one-to-one manner and supplying a gate high voltage to the plurality of gate lines in response to a first switching signal; And
And a plurality of data lighting test switching elements corresponding to the plurality of data lines one-to-one and supplying a data test signal to the plurality of data lines in response to a second switching signal. The method of claim 1,
The first switching signal is output in a low state from a first time point to a third time point, and is output in the gate high state after the third time point.
The first time point indicates a power-on time point of the organic light emitting diode display, and the third time point is a time point at which the gate driver starts supplying the plurality of gate signals to the plurality of gate lines. And a second time point at which the high potential driving voltage is first applied to the display panel between the time point and the third time point. The method of claim 2,
The pixel includes an organic light emitting diode and a plurality of switching elements for independently driving the organic light emitting diode.
The plurality of switching elements are turned off in a period from the first time point to the third time point. The method of claim 3, wherein
The plurality of gate signals are not output in a period from the first time point to the third time point. The method of claim 3, wherein
And the plurality of switching elements are P type thin film transistors. A display panel defining pixels at intersections of the plurality of gate lines and the plurality of data lines;
A timing controller configured to output a plurality of gate control signals and a plurality of data control signals;
A shift register configured to output a shift register out signal in response to the plurality of gate control signals; A gate signal output unit configured to generate a plurality of gate signals in response to the shift register-out-signal, and supply the plurality of gate signals to the plurality of gate lines; And a light emission controller configured to supply a gate high voltage to the plurality of gate lines from a driving start time until the gate signal output unit outputs the plurality of gate signals. And
And a data driver for supplying data voltages to the plurality of data lines in response to the plurality of data control signals. The method according to claim 6,
The gate signal output unit
A first switching element configured to supply a gate low voltage to the first node in response to a k th clock pulse;
A second switching element configured to supply the gate high voltage to the first node in response to the shift register out signal;
A third switching element configured to supply the gate low voltage to the first node according to a potential of a second node;
A fourth switching element configured to output the Gyer low voltage to the plurality of gate lines according to the potential of the first node;
A fifth switching device configured to output the gate high voltage to the plurality of gate lines in response to the shift register out signal;
A first capacitor coupled between a k + 2 clock pulse supply line and the first node; And
And a second capacitor connected between the first node and the second node. The method of claim 7, wherein
The light emission controller
A sixth switching element configured to supply the gate high voltage to the first node in response to a switching signal; And
And a seventh switching element configured to output the gate high voltage to the plurality of gate lines in response to the switching signal. The method of claim 8,
The switching signal is
And the gate signal output unit is output in a low state from the driving start time until the gate signal output unit outputs the plurality of gate signals. The method of claim 9,
And the first to seventh switching elements are P-type thin film transistors.

Images