KR101747730B1 - Organic light emitting diode display device - Google Patents

Abstract

The present invention relates to an organic light emitting diode (OLED) display device capable of reducing power consumption, in which pixels are defined at intersections of a plurality of gate lines and a plurality of data lines, and each of the pixels is driven by an organic light emitting diode A display panel including a drive switching element for supplying a current; A timing controller including an average luminance extraction unit for extracting and outputting an average image level from an input image and a voltage recovery adjustment unit for outputting a voltage recovery signal when the average image level is lower than a reference average image level; And a gate driver for supplying a plurality of gate signals to the plurality of gate lines in response to a gate control signal provided from the timing controller; The pixel includes a first period in which the pixel driver is initialized, a second period in which the data voltage is programmed in the pixel driver, and a second period in which the driving current is supplied to the organic light emitting diode 3 periods and a fourth period in which the gate voltage charges the plurality of data lines; And the data driver includes a voltage recovery unit for recovering and storing charges charged in the plurality of data lines in response to the voltage recovery signal.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display device capable of reducing power consumption.

2. Description of the Related Art [0002] Organic light emitting diodes (OLED) display devices for displaying images by controlling the amount of light emitted from an organic light emitting layer have been spotlighted by a flat panel display capable of reducing weight and volume, which are disadvantages of a cathode ray tube (CRT) .

In an OLED display device, a plurality of pixels are arranged in a matrix form to display an image. Each pixel includes an OLED and a pixel driver that adjusts the amount of current flowing through the OLED to adjust the brightness of each pixel. Here, the pixel driver includes a plurality of thin film transistors (TFTs) and at least one capacitor. The pixel driver is supplied with a data voltage, a plurality of control signals for driving a plurality of TFTs, a high potential driving voltage, and the like.

The pixel driver includes a first period in which the pixel driver is initialized, a second period in which the data voltage is programmed and a threshold voltage of the driving TFT is sensed, and a third period in which the OLED emits light according to the potential of the gate node of the driving TFT Respectively.

Here, the second period is a period during which the data voltage is programmed to the gate node of the driving TFT, and the third period is a period during which the driving TFT supplies the driving current to the OLED according to the gate voltage of the driving TFT including the data voltage.

On the other hand, if the first period is restarted after the third period, the gate voltage of the driving TFT is initialized to a reference voltage having a relatively low potential. That is, the gate voltage of the driving TFT used in the third period is substantially discarded while being initialized in the first period. This process is repeated every frame, which increases the power consumption.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an organic light emitting diode display device capable of reducing power consumption.

According to an aspect of the present invention, there is provided an organic light emitting diode (OLED) display device including pixels at intersections of a plurality of gate lines and a plurality of data lines, each of the pixels defining an organic light emitting diode A display panel including a drive switching element for supplying a drive current; A timing controller including an average luminance extraction unit for extracting and outputting an average image level from an input image and a voltage recovery adjustment unit for outputting a voltage recovery signal when the average image level is lower than a reference average image level; A gate driver for supplying a plurality of gate signals to the plurality of gate lines in response to a gate control signal provided from the timing controller; And a data driver for supplying a data voltage to the plurality of data lines in response to a data control signal provided from the timing controller; The pixel includes a first period in which the pixel driver is initialized, a second period in which the data voltage is programmed in the pixel driver, and a second period in which the driving current is supplied to the organic light emitting diode 3 periods and a fourth period in which the gate voltage charges the plurality of data lines; And the data driver includes a voltage recovery unit for recovering and storing charges charged in the plurality of data lines in response to the voltage recovery signal.

The data driver includes: a shift register for sequentially outputting a sampling signal; A latch unit latching the image data provided from the timing controller in response to the sampling signal for one horizontal line and outputting the same at the same time; A DAC unit for converting image data provided from the latch unit into the data voltage and outputting the data voltage; And an output buffer unit having an operational amplifier connected to the output terminal of the voltage recovery unit and supplying the data voltage output from the DAC unit to the plurality of data lines.

Wherein the voltage recovery unit includes: a voltage recovery switching element that is switching-controlled in response to the voltage recovery signal; And a voltage recovery capacitor connected between the voltage recovery switching device and the base voltage source.

The pixel includes a driving switching element for adjusting the driving current according to a potential of a second node; A first switching element for supplying the data voltage to the first node in response to a scan signal; A second switching element for supplying a reference voltage to the first node in response to the light emitting signal; A third switching element for connecting the drain electrode of the driving switching element and the second node to each other in response to the scan signal; A fourth switching element for connecting the drain electrode and a third node connected to the anode electrode of the organic light emitting diode in response to the emission signal; A fifth switching element for supplying the reference voltage to the third node in response to an initialization signal; And a capacitor connected between the first node and the second node.

And the scan signal, the emission signal, and the initialization signal are output in the first period.

And the scan signal and the initialization signal are output in the second period.

And the emission signal is output in the third period.

And the scan signal and the voltage recovery signal are output in the fourth period.

The first to fifth switching elements and the driving switching element are P-type thin film transistors.

Wherein a high potential driving voltage is supplied to a source electrode of the driving switching element and a low potential driving voltage is supplied to a cathode electrode of the organic light emitting diode and the high potential driving voltage has a relatively higher potential than the low potential driving voltage , And the reference voltage has a potential between the high potential driving voltage and the low potential driving voltage.

The present invention can reduce the power consumption because the gate voltage of the driving TFT (DT) used in the light emission period is recovered and reused in the data driver (6).

1 is a configuration diagram of an OLED display device according to an embodiment of the present invention.
Fig. 2 is a configuration diagram of the timing control unit 8 shown in Fig.
Fig. 3 is a configuration diagram of the data driver 6 shown in Fig.
4 is a configuration circuit diagram of the pixel P shown in Fig.
5 is a driving waveform diagram of the pixel P shown in Fig.
6 is a simulation for explaining the effect of the embodiment of the present invention.

Hereinafter, an organic light emitting diode display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, the TFT may be configured as a P type or an N type, and in the embodiment, the TFT is configured as a P type for convenience of explanation. Thus, the gate high voltage VGH is a voltage for turning off the TFT, and the gate low voltage VGL is a voltage for turning on the TFT. In describing a pulse-shaped signal, the gate high voltage (VGH) state is defined as "high state", and the gate low voltage (VGL) state is defined as "low state".

1 is a configuration diagram of an OLED display device according to an embodiment of the present invention. 2 is a block diagram of the timing controller 8 shown in FIG.

1 includes a display panel 2, a timing control unit 8, a gate driving unit 4, and a data driving unit 6.

The display panel 2 defines pixels P at the intersection of a plurality of gate lines GL and a plurality of data lines DL.

Referring to FIG. 2, the timing controller 8 controls the driving timing of the gate driver 4 and the data driver 6. To this end, the timing controller 8 controls the timing controller 8 using a synchronous signal input from the outside, that is, a horizontal synchronous signal HSync, a vertical synchronous signal VSync, a dot clock DCLK, and a data enable signal DE, And a control signal generator 10 for generating and outputting a data control signal GCS and a data control signal DCS.

Here, the gate control signal GCS includes a plurality of clock pulses having different phase differences and a gate start pulse (GSP) for instructing the gate driver 4 to start driving. The data control signal DCS includes a source output enable (SOE) for controlling the output period of the data driver 6, a source start pulse (SSP) for instructing the start of data sampling, And a source shift clock (SSC) for controlling the sampling timing of the clock signal.

The timing controller 8 includes an image arranging unit 12 for arranging an input image RGB in accordance with the driving of the display panel 2 and supplying the image to the data driver 6, (APL) extracted from the average brightness extracting unit 14 and a reference average picture level (APL) extracted from the average picture level (APL) And a voltage recovery adjustment unit 16 for outputting a voltage recovery signal VCS by comparison.

The voltage recovery adjustment unit 16 analyzes the average picture level APL extracted by the average luminance extraction unit 14 to determine the potential of the data voltage Vdata to be supplied to the pixel P. [ Here, the relationship between the average image level APL and the data voltage Vdata to be supplied to the pixel P is as follows.

That is, the higher the average image level APL, the closer the image to be displayed on the display panel 2 to the white gradation, and the data voltage Vdata to be supplied to the pixel P becomes relatively low. The lower the average picture level APL is, the closer the image to be displayed on the display panel 2 is to the black gradation, and the data voltage Vdata to be supplied to the pixel P becomes relatively higher.

Therefore, the voltage recovery adjustment unit 16 determines that the data voltage Vdata to be supplied to the pixel P is relatively high and outputs the voltage recovery signal VCS when the average image level APL is lower than the reference average image level do. The voltage recovery adjustment unit 16 determines that the data voltage Vdata to be supplied to the pixel P is relatively low and outputs the voltage recovery signal VCS when the average image level APL is higher than the reference average image level Do not.

If the TFT of the embodiment is of the N type, the higher the average picture level APL, the higher the data voltage Vdata to be supplied to the pixel P becomes. In this case, the voltage recovery adjustment unit 16 determines that the data voltage Vdata to be supplied to the pixel P is relatively high and outputs the voltage recovery signal VCS when the average image level APL is higher than the reference average image level, .

Here, the voltage recovery signal VCS is a signal for recovering the supplied data voltage (Vdata) component having a relatively high potential relative to the pixel P, and will be described later in detail.

The gate driving unit 4 receives a gate control signal GCS from the timing control unit 8 in response to a plurality of clock pulses, a gate start pulse, a gate shift clock, Generates a gate signal and supplies it to the gate line GL. Here, the plurality of gate signals include the scan signal SCAN, the emission signal EM, and the initialization signal INIT.

Fig. 3 is a configuration diagram of the data driver 6 shown in Fig.

The data driver 6 converts the video data RGB supplied from the timing controller 8 into a data voltage Vdata in response to the data control signal DCS supplied from the timing controller 8, To the line DL.

3, the data driver 6 includes a shift register 14, a latch unit 16, a DAC unit 18, and an output buffer unit 20.

The shift register 14 sequentially outputs the sampling signal in accordance with the source sampling clock SSC.

The latch unit 16 samples the image data RGB supplied from the timing control unit 8 in response to the sampling signal and latches data for one horizontal line. The latch unit 16 simultaneously outputs the latched image data in accordance with the source output enable (SOE) signal.

The DAC unit 18 outputs the gamma voltage corresponding to the image data provided from the latch unit 16 as a data voltage.

The output buffer unit 20 includes an operational amplifier AMP for supplying the data voltages output from the DAC unit 18 to a plurality of data lines DL. The output buffer unit 20 serves to minimize signal attenuation of the data voltage Vdata supplied to the data line DL.

On the other hand, the voltage recovery unit 24 is provided in the output stage 22 of the operational amplifier (AMP). The voltage recovery unit 24 is responsive to the voltage recovery signal VCS provided from the timing control unit 8, And collects and stores the electric charge charged in the line DL. To this end, the voltage recovery unit 24 includes a voltage recovery TFT (VT) that is switching-controlled in response to a voltage recovery signal (VCS), a voltage recovery capacitor Cst connected between the voltage recovery TFT and the base voltage source (GND) ).

The voltage recovery unit 24 stores the charges charged in the plurality of data lines DL in the voltage recovery capacitor Cst in response to the voltage recovery signal VCS. At this time, the charge stored in the voltage recovery capacitor (Cst) can be reused as a bias power in the data driver (6).

4 is a configuration circuit diagram of the pixel P shown in Fig.

The pixel P shown in FIG. 4 includes a pixel driver that independently drives the OLED and the OLED.

Specifically, the pixel driver includes first to fifth TFTs T1 to T5, a driving TFT DT, and a capacitor C. The OLED is connected between the pixel driving part and the low potential driving voltage (VSS) supply line and is equivalently represented by a diode.

The pixel driver is supplied with a data voltage Vdata, a reference voltage Vref, a high potential driving voltage VDD and a plurality of gates for controlling the first to fifth TFTs T1 to T5, Signals (SCAN, EM, INIT) are supplied.

Here, the high-potential driving voltage VDD has a potential that is relatively higher than the low-potential driving voltage VSS. The low potential driving voltage VSS can be set to the ground voltage. The reference voltage Vref has a potential between the high potential driving voltage VDD and the low potential driving voltage VSS. The plurality of gate signals SCAN, EM, and INIT include a scan signal SCAN, a light emission signal EM, and an initialization signal INIT.

The first TFT T1 supplies the data voltage Vdata to the first node N1 in response to the scan signal SCAN. Here, the first node N1 is a node to which the output terminals of the first TFT T1 and the second TFT T2 are commonly connected.

The second TFT T2 supplies the reference voltage Vref to the first node N1 in response to the emission signal EM.

The third TFT T3 connects the drain electrode d of the driving TFT DT and the second node N2 to each other in response to the scan signal SCAN. Here, the second node N2 is a node connected to the gate electrode g of the driving TFT DT.

The fourth TFT T4 connects the drain electrode d of the driving TFT DT and the third node N3 to each other in response to the emission signal EM. Here, the third node N3 is a node connected to the anode electrode of the OLED.

The fifth TFT T5 supplies the reference voltage Vref to the third node N3 in response to the initialization signal INIT.

The driving TFT DT adjusts the amount of emitted light of the OLED by controlling the amount of current supplied to the OLED in accordance with the potential of the second node N2 supplied with the high potential driving voltage VDD to the source electrode s.

The capacitor C is connected between the first node N1 and the second node N2.

The OLED is composed of an anode electrode connected to the pixel driving unit, a cathode electrode supplied with a low potential driving voltage (VSS), and an organic layer formed between the anode electrode and the cathode electrode.

Hereinafter, a method of driving the pixel P including the pixel driver will be described in detail.

5 is a driving waveform diagram of the pixel P shown in Fig.

In FIG. 5, reference numeral " 1 " denotes a period in which the pixel driver is initialized (hereinafter referred to as a first period), 2 denotes a period in which the data voltage Vdata is programmed in the pixel driver (Hereinafter, referred to as " second period ") during which the data line GL is charged to the second node N2 voltage of the third period (3) , The fourth period).

In the first period (1), the scan signal SCAN, the emission signal EM, and the initialization signal INIT are outputted in a low state.

Then, the first to fifth TFTs T1 to T5 are turned on, and the first and second nodes N1 and N2 are initialized to the reference voltage Vref.

During the second period (2), the scan signal SCAN is outputted in a low state; The light emission signal EM and the initialization signal INIT are outputted in a high state.

Then, the first TFT (T1) is turned on and the data voltage (Vdata) is supplied to the first node (N1).

On the other hand, in the second period (2), the threshold voltage Vth of the driving TFT DT is sensed. Specifically, in the second period (2), the fourth TFT T4 is turned off, and a current flowing in the driving TFT DT flows into the second node N2. The potential of the second node N2 is set such that the potential difference between the gate electrode g and the source electrode s of the driving TFT DT is lower than the potential of the driving TFT DT And rises until it reaches the threshold voltage (Vth).

That is, when the potential of the second node N2 converges to VDD + Vth from the reference voltage Vref in the second period (2) and the potential of the second node N2 becomes VDD + Vth, The TFT DT is turned off.

In the third period (3), the emission signal EM is outputted in a low state; The scan signal SCAN and the initialization signal INIT are outputted in a high state.

Then, the second and fourth TFTs T2 and T4 are turned on and the first, third and fifth TFTs T1, T3 and T5 are turned off. Thus, the reference voltage Vref is supplied to the first node N1 through the fourth TFT T4. At this time, if the potential of the first node N1 changes from the data voltage Vdata to the reference voltage Vref, the potential of the second node N2 becomes "VDD + Vth" due to the coupling phenomenon of the capacitor C, (VDD + Vth + {C1 / (C1 + CTFT)} (Vref-Vdata) " Here, "C1" represents the capacitance of the first capacitor (C), and "CTFT" represents the parasitic capacitance of the driver TFT (DT). At this time, since the fourth TFT T4 is turned on, a driving current is supplied to the OLED, and the OLED emits light.

Specifically, " Vgs "represents a potential difference between the gate electrode g and the source electrode s of the driving TFT DT, and" Vth " Represents a threshold voltage of the driving TFT DT, and "? &Quot; represents a constant value determined by the mobility of the driving TFT DT and the parasitic capacitance.

Accordingly, the OLED driving current is summarized as shown in Equation (2).

Referring to Equation 2, it can be seen that the OLED driving current is not influenced by the threshold voltage Vth of the driving TFT DT and the high potential driving voltage VDD.

Therefore, the embodiment of the present invention compensates for the change of the threshold voltage Vth of the driving TFT DT and the change of the high-potential driving voltage VDD due to the deterioration that may be generated during the manufacturing process or the image display, It is possible to provide brightness and improve display quality.

On the other hand, in the related art, the second node N2 that has maintained the light emission voltage in the third period (3) is initialized to the reference voltage Vref in the first period (1). That is, the light emitting voltage of the third period (3) is substantially discarded as it becomes the first period (1), which increases the power consumption.

The embodiment includes a fourth period (4) for charging the data line DL using the light emission voltage so that the light emission voltage of the third period (3) is not discarded.

Specifically, in the fourth period (4), the scan signal SCAN is outputted in a low state; The light emission signal EM and the initialization signal INIT are outputted in a high state.

Then, the second TFT T2 is turned off so that the first node N1 is floated, and the first TFT T1 is turned on so that the data line DL and the first node N1 are connected to each other . At this time, the data line DL is in a floating state like the first node N1.

Thus, the second node N2 emits a voltage to charge the first node N1 and the data line DL which are floated by the electrostatic induction action of the capacitor C. Here, the charges charged in the data line DL are recovered and stored in the voltage recovery unit 24.

The voltage recovery unit 24 recovers and stores the charge charged to the data line DL only when the emission voltage is relatively high. On the other hand, the voltage recovery adjustment unit 16 compares the average image level APL of the input image data RGB with the reference average image level to determine the potential of the light emission voltage. When the average image level APL is lower than the reference average image level, the voltage recovery adjustment unit 16 determines that the light emission voltage is relatively high and outputs the voltage recovery signal VCS. At this time, the voltage recovery signal VCS is preferably output in the fourth period (4) as shown in FIG.

6 is a simulation for explaining the effect of the embodiment of the present invention. Specifically, FIG. 6 shows the potentials of the first and second nodes N1 and N2 according to the embodiment.

Referring to FIG. 6, it can be seen that the second node N2 maintains the light emitting voltage in the third period (3), and the potential decreases while charging the data line DL in the fourth period (4). A region). That is, the embodiment is recovered to the data driver 6 as much as the emission voltage is lowered in the fourth period (4) in contrast to the third period (3). The voltage recovered in the data driver 6 is reused as a bias power of the data driver 6, and as a result, power consumption can be reduced.

As described above, the embodiment of the present invention can reduce the power consumption because the gate voltage of the driving TFT DT used in the light emission period is recovered and reused by the data driver 6.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

VCS: voltage recovery signal 24: voltage recovery unit

Claims (10)

A display panel defining pixels at intersections of a plurality of gate lines and a plurality of data lines, each of the pixels including an organic light emitting diode and a driving switching element for supplying a driving current to the organic light emitting diode;
A timing controller including an average luminance extraction unit for extracting and outputting an average image level from an input image and a voltage recovery adjustment unit for outputting a voltage recovery signal when the average image level is lower than a reference average image level;
A gate driver for supplying a plurality of gate signals to the plurality of gate lines in response to a gate control signal provided from the timing controller; And
And a data driver for supplying a data voltage to the plurality of data lines in response to a data control signal provided from the timing controller; And
The pixel includes a first period in which a pixel driver for driving the organic light emitting diode is initialized, a second period in which the data voltage is programmed in the pixel driver, and a second period in which the driving voltage is driven to the organic light emitting diode A third period for supplying a current and a fourth period for which the gate voltage charges the plurality of data lines;
Wherein the data driver includes a voltage recovery unit for recovering and storing charges charged in the plurality of data lines in response to the voltage recovery signal. The method according to claim 1,
The data driver
A shift register for sequentially outputting sampling signals;
A latch unit latching the image data provided from the timing controller in response to the sampling signal for one horizontal line and outputting the same at the same time;
A DAC unit for converting image data provided from the latch unit into the data voltage and outputting the data voltage; And
And an output buffer unit connected to the output terminal of the voltage recovery unit and having an operational amplifier for supplying a data voltage output from the DAC unit to the plurality of data lines. 3. The method of claim 2,
The voltage-
A voltage recovery switching element that is switching-controlled in response to the voltage recovery signal;
And a voltage recovery capacitor connected between the voltage recovery switching device and the base voltage source. 3. The method of claim 2,
The pixel
The driving switching element adjusting the driving current according to a potential of a second node;
A first switching element for supplying the data voltage to the first node in response to a scan signal;
A second switching element for supplying a reference voltage to the first node in response to the light emitting signal;
A third switching element for connecting the drain electrode of the driving switching element and the second node to each other in response to the scan signal;
A fourth switching device for connecting the drain electrode of the driving switching device and a third node connected to the anode electrode of the organic light emitting diode in response to the light emitting signal;
A fifth switching element for supplying the reference voltage to the third node in response to an initialization signal; And
And a capacitor connected between the first node and the second node. 5. The method of claim 4,
Wherein the scan signal, the emission signal, and the initialization signal are output in the first period. 6. The method of claim 5,
And the scan signal is output in the second period. The method according to claim 6,
And the emission signal is output in the third period. 8. The method of claim 7,
In the fourth period
And the scan signal and the voltage recovery signal are output. 9. The method of claim 8,
Wherein the first to fifth switching elements and the driving switching element are P-type thin film transistors. 5. The method of claim 4,
A high potential driving voltage is supplied to a source electrode of the driving switching element, a low potential driving voltage is supplied to a cathode electrode of the organic light emitting diode,
The high-potential driving voltage has a potential that is relatively higher than the low-potential driving voltage,
Wherein the reference voltage has a potential between the high potential driving voltage and the low potential driving voltage.

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