KR20180135844A - Organic light emitting display device - Google Patents

Abstract

The present invention provides an organic light emitting display device capable of uniformly maintaining the luminance of pixels by compensating for a threshold voltage of a driving transistor. The organic light emitting display device according to one embodiment of the present invention includes: a display panel having pixels coupled to data lines, scan lines, and first power voltage lines; a data driver configured to supply data voltages to the data lines; and a scan driver configured to supply scan signals to the scan lines. The data driver is configured to supply the reference voltage to a j^th data line (j is a positive integer) during a first period, supply a compensation voltage during a second period, and supply a data voltage during a third period. The scan driver is configured to supply a k^th scan signal (k is a positive integer) having a gate-on voltage to a k^th scan line during the first to third periods, and supply the k^th scan signal having a gate-off voltage during a fourth period.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

An embodiment of the present invention relates to an organic light emitting display.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. In recent years, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been used.

Of these, the organic light emitting display device can be driven at a low voltage, is thin, has excellent viewing angle, and has a high response speed. The organic light emitting display includes a display panel having data lines, scan lines, a plurality of pixels formed at intersections of the data lines and the scan lines, a scan driver for supplying scan signals to the scan lines, And a data driver for supplying data voltages. Each of the pixels includes an organic light emitting diode, a driving transistor for controlling the amount of current supplied to the organic light emitting diode according to the voltage of the gate electrode, And supplies a voltage to the gate electrode of the driving transistor.

However, there is a problem that the threshold voltage of the driving transistor varies from pixel to pixel due to the non-uniformity of the manufacturing process. In this case, even if the same data voltage is applied to each of the pixels, the luminance at which the organic light emitting diode emits light is different for each pixel due to the threshold voltage difference of the driving transistor between the pixels. To solve this problem, a compensation method for compensating the threshold voltage of the driving transistor has been proposed.

An embodiment of the present invention provides an organic light emitting display in which luminance of pixels can be made uniform by compensating a threshold voltage of a driving transistor.

An OLED display according to an exemplary embodiment of the present invention includes a display panel having pixels connected to data lines, scan lines, and first power source voltage lines; A data driver for supplying data voltages to the data lines; And a scan driver for supplying scan signals to the scan lines. The pixel includes an organic light emitting diode; A driving transistor connected to the first power supply voltage line of the organic light emitting diode and the first power supply voltage lines; A first transistor connected to one of the data lines and a gate electrode of the driving transistor; A second transistor for supplying a reference voltage of one of the data lines to a source electrode of the driving transistor; And a capacitor connected to the gate electrode and the source electrode of the driving transistor. The data driver supplies the reference voltage to the jth (j is a positive integer) data line during the first period, supplies the compensation voltage during the second period, and supplies the data voltage during the third period. The scan driver supplies a kth (k is a positive integer) scan signal having a gate-on voltage during the first to third periods to the kth scan line. The scan driver supplies a kth scan signal having a gate- Signal to the k < th > scan line. The second period immediately follows the first period, and the third period continues immediately after the second period.

An organic light emitting display according to an embodiment of the present invention includes a display panel having pixels connected to data lines, scan lines, initialization lines, and first power supply voltage lines; And a data driver for supplying data voltages to the data lines. The pixel includes an organic light emitting diode; A driving transistor connected to the first power supply voltage line of the organic light emitting diode and the first power supply voltage lines; A first transistor connected to one of the data lines and a gate electrode of the driving transistor; A second transistor for supplying a reference voltage of one of the data lines to a source electrode of the driving transistor; And a capacitor connected to the gate electrode and the source electrode of the driving transistor. The first transistor is turned on by a kth scan signal of a kth (k is a positive integer) scan line to supply a voltage of a jth (j is a positive integer) data line to the gate electrode of the driving transistor And the second transistor is turned on by the k-th initialization signal of the k-th initialization line to connect the gate electrode and the source electrode of the driving transistor to each other. Wherein the data driver supplies the reference voltage to the j data line during a first period, supplies a compensation voltage to the j data line during a second period, and supplies a data voltage during the third period to the j data line Supply.

The embodiment of the present invention initializes the gate electrode and the source electrode of the driving transistor to a reference voltage, and then supplies a compensation voltage to the gate electrode of the driving transistor. As a result, the embodiment of the present invention can sense the threshold voltage of the driving transistor to the source electrode of the driving transistor. Therefore, the embodiment of the present invention can emit the organic light emitting diode according to the current of the driving transistor whose threshold voltage is compensated.

In the embodiment of the present invention, the data voltage is supplied to the gate electrode of the driving transistor DT for a predetermined period, and the source voltage is raised by "? & It depends on mobility. As a result, in the embodiment of the present invention, the voltage difference between the gate electrode and the source electrode can be adjusted according to the electron mobility of the driving transistor for a predetermined period, so that the electron mobility of the driving transistor can be compensated.

1 is a block diagram showing an organic light emitting display according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of the pixel of FIG. 1; FIG.
3 is a waveform diagram showing a k-th scan signal, a k-th initialization signal, a j-th data signal, and a gate voltage and a source voltage of the driving transistor.
4 is a flow chart illustrating a method of driving a pixel according to an embodiment of the present invention.
5A to 5D are circuit diagrams showing the operation of the pixel of FIG. 2 during the first to fourth periods of FIG. 3;
FIG. 6 is a circuit diagram showing another example of the pixel of FIG. 1; FIG.
7 is an exemplary view showing a display panel divided into blocks.
8 is a waveform diagram showing scan signals and initialization signals supplied to a display panel;
9 is a waveform diagram showing a k-th scan signal, a k-th initialization signal, a j-th data signal, and a gate voltage and a source voltage of the driving transistor.
10 is a flow chart illustrating a method of driving a pixel according to another embodiment of the present invention.
11A to 11E are circuit diagrams showing the operation of the pixel of FIG. 2 during the first to sixth periods of FIG. 9;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

1 is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention. Referring to FIG. 1, an OLED display includes a display panel 10, a data driver 20, a scan driver 30, an initialization driver 40, and a timing controller 50. do.

The display panel 10 includes a display area AA and a non-display area NDA provided around the display area AA. The display area AA is an area where pixels P are provided to display an image. In the display panel 10, data lines (D1 to Dm, m is a positive integer of 2 or more), scan lines (S1 to Sn, n is a positive integer of 2 or more), and initialization lines SEN1 to SENn . The data lines D1 to Dm may be formed to intersect the scan lines S1 to Sn and the initialization lines SEN1 to SENn. The scan lines S1 to Sn and the initialization lines SEN1 to SENn may be formed in parallel with each other.

Each of the pixels P of the display panel 10 is connected to one of the data lines D1 to Dm, one of the scan lines S1 to Sn and one of the initialization lines SEN1 to SENn Can be connected. Each of the pixels P of the display panel 10 includes a driving transistor, a first transistor controlled by the scan signal of the scan line, a second transistor controlled by the initialization signal of the initialization line, an organic light emitting diode a light emitting diode, and a capacitor. The pixel P will be described later in detail with reference to FIG.

The data driver 20 includes at least one source driver IC (hereinafter referred to as "IC"). The source drive IC is connected to the data lines D1 to Dm to supply the data voltages. The source driver IC receives the digital video data (DATA) and the source timing control signal (DCS) from the timing controller 50. The source driver IC converts the digital video data (DATA) into data voltages according to the source timing control signal (DCS) and supplies the data voltages to the data lines (D1 to Dm). Further, the source drive IC can supply the reference voltage and the compensation voltage to the data lines D1 to Dm in addition to the data voltages. A detailed description of the reference voltage, the compensation voltage, and the data voltage supply of the source drive IC will be described later in conjunction with FIG. 3 and FIG.

The scan driver 30 is connected to the scan lines S1 to Sn to supply scan signals. The scan driver 30 supplies scan signals to the scan lines S1 to Sn in accordance with a scan timing control signal SCS input from the timing controller 50. [ A detailed description of the scan signal supply of the scan driver 30 will be given later with reference to FIGS. 3, 9 and 10. FIG.

The initialization driver 40 is connected to the initialization lines SEN1 to SENn to supply initialization signals. Specifically, the initialization driver 40 supplies initialization signals to the initialization lines SEN1 to SENn according to the initialization timing control signal SENCS input from the timing controller 50. [ The initialization signal supply of the initialization driver 40 will be described later in detail with reference to FIGS. 3, 9, and 10. FIG.

The timing controller 50 receives digital video data DATA from the outside. The timing controller 50 generates timing control signals for controlling the operation timings of the data driver 20, the scan driver 30, and the initialization driver 40. The timing control signals include a data timing control signal DCS for controlling the operation timing of the data driver 20, a scan timing control signal SCS for controlling the operation timing of the scan driver 30, And an initialization timing control signal (SENCS) for controlling the operation timing.

The timing controller 50 outputs the digital video data DATA and the data timing control signal DCS to the data driver 20. The timing controller 50 outputs the scan timing control signal SCS to the scan driver 30. The timing controller 50 outputs the initialization timing control signal SENCS to the initialization driver 40. [

FIG. 2 is a circuit diagram showing the pixel of FIG. 1 in detail. 2, the pixel P includes an organic light emitting diode (OLED), a driving transistor DT, first and second transistors ST1 and ST2, and a capacitor C.

The organic light emitting diode OLED emits light according to the current supplied through the driving transistor DT. The anode electrode of the organic light emitting diode OLED is connected to the source electrode of the driving transistor DT and the cathode electrode can be connected to the low potential voltage line VSSL to which a low potential voltage lower than the high potential voltage is supplied.

The organic light emitting diode OLED may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In the organic light emitting diode (OLED), when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively.

The driving transistor DT is connected to the first power supply voltage line VDDL and the organic light emitting diode OLED. The driving transistor DT controls the current flowing from the first power supply voltage line VDDL to the organic light emitting diode OLED according to the voltage of the gate electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first transistor ST1, the source electrode of the driving transistor DT is connected to the anode electrode of the organic light emitting diode OLED, 1 power supply voltage line VDDL.

The first transistor ST1 is turned on by the kth scan signal of the kth scan line Sk (k is a positive integer satisfying 1? K? N) so that the jth (j is 1? J? M To the gate electrode of the driving transistor DT. The gate electrode of the first transistor T1 is connected to the kth scan line Sk and the first electrode thereof is connected to the gate electrode of the driving transistor DT and the second electrode thereof is connected to the jth data line Dj .

The second transistor ST2 is turned on by the k-th initialization signal of the k-th initialization line SENk to supply the voltage of the j-th data line Dj to the source electrode of the driving transistor DT. The gate electrode of the second transistor ST2 is connected to the kth initializing line SENk and the first electrode thereof is connected to the jth data line Dj and the second electrode thereof is connected to the source electrode of the driving transistor DT .

The capacitor C is connected to the gate electrode and the source electrode of the driving transistor DT1. The capacitor C maintains a constant voltage difference between the gate electrode and the source electrode of the driving transistor DT. 2, a parasitic capacitor Cp may be formed between the anode electrode and the cathode electrode of the organic light emitting diode OLED.

In FIG. 2, the first electrode of the first and second transistors ST1 and ST2 may be a source electrode or a drain electrode, and the second electrode may be a different electrode from the first electrode. For example, when the first electrode is a source electrode, the second electrode may be a drain electrode.

2, the driving transistor DT and the first and second transistors ST1 and ST2 are formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, it should be noted that the driving transistor DT and the first and second transistors ST1 and ST2 are not limited thereto. The driving transistor DT and the first and second transistors ST1 and ST2 may be formed of a P-type MOSFET. In this case, the waveforms of FIGS. 3, 9 and 10 are suitable for the characteristics of the P- .

As described above, the pixel P according to the embodiment of the present invention includes the first transistor ST1 connected to the gate electrode of the jth data line Dj and the driving transistor DT, And a second transistor ST2 connected to the source electrode of the driving transistor DT and the driving transistor DT. As a result, in the embodiment of the present invention, by adjusting the turn-on of the first and second transistors ST1 and ST2 and the voltage supplied to the jth data line Dj, the threshold voltage of the driving transistor DT Sensing can be performed. A detailed description of the threshold voltage compensation of the driving transistor DT of the pixel P shown in Fig. 2 will be described later in conjunction with Figs. 3, 4, 5A to 5D.

FIG. 3 is a waveform diagram showing a k-th scan signal, a k-th initialization signal, a j-th data signal, and a gate voltage and a source voltage of the driving transistor of FIG. 3, a k-th scan signal SCANk supplied to the k-th scan line Sk connected to the pixel P of Fig. 2, a k-th initialization signal SENSk supplied to the k-th initialization line SENk, the voltage DVj supplied to the data line Dj and the gate voltage Vg and the source voltage Vs of the driving transistor DT are shown.

Referring to FIG. 3, one frame period may be divided into first to fourth periods t1 to t4. The first period t1 is a period for initializing the gate electrode and the source electrode of the driving transistor DT to the reference voltage Vref. The second period t2 is a period for sensing the threshold voltage of the driving transistor DT. The third period t3 is a period for supplying the data voltage to the gate electrode of the driving transistor DT. The fourth period t4 is a period during which the organic light emitting diode OLED emits light in accordance with the current Ids flowing through the driving transistor DT. The first to third periods t1 to t3 may be one horizontal period (1H) as shown in FIG. In FIG. 3, the second period t2 is preferably longer than the first and third periods t1 and t3, but it is not limited thereto. That is, the first to third periods t1 to t3 may be set to the same period, or the second period t2 may be set to be shorter than the first and third periods t1 and t3, respectively. The first and third periods t1 and t3 may be set to different periods. The first to third periods t1 to t3 may be designed according to the characteristics of the driving transistor DT, the first and second transistors T1 and T2.

The data driver 20 supplies the reference voltage Vref to the j-th data line Dj during the first period t1. The reference voltage Vref is a voltage for initializing the gate electrode and the source electrode of the driving transistor DT. The data driver 20 supplies the compensation voltage Vcomp to the j-th data line Dj during the second period t2. The compensation voltage Vcomp is a voltage for compensating the threshold voltage of the driving transistor DT. When the driving transistor DT is formed of an N-type MOSFET, the compensation voltage Vcomp may be a voltage higher than the reference voltage Vref as shown in FIG. The data driver 20 supplies the data voltage Vdata to the j-th data line Dj during the third period t3. The data voltage Vdata is a voltage supplied to the gate electrode of the driving transistor DT to emit the organic light emitting diode OLED at a predetermined luminance. When the digital video data DATA supplied to the data driver 20 is 8 bits, the data voltage Vdata may be supplied in any one of 256 voltages. When the driving transistor DT is formed of an N-type MOSFET, the data voltage Vdata may be a voltage higher than the compensation voltage Vcomp as shown in FIG.

The pixel P according to an embodiment of the present invention includes a first transistor ST1 connected to a gate electrode of a jth data line Dj and a driving transistor DT as shown in Fig. 2, And a second transistor ST2 connected to a source electrode of the driving transistor DT. As a result, the embodiment of the present invention controls the turn-on of the first and second transistors ST1 and ST2 during the first to third periods t1 to t3, By adjusting the supplied voltage to the reference voltage Vref, the compensation voltage Vcomp and the data voltage Vdata, not only the threshold voltage of the driving transistor DT can be sensed, but also the electron mobility can be compensated. A detailed description thereof will be given later with reference to Fig. 4 and Figs. 5A to 5D.

The scan driver 30 may sequentially supply the scan signals SCAN1 to SCANn to the scan lines S1 to Sn. A scan signal SCANk having a gate-on voltage Von is supplied to the kth scan line Sk during the first to third periods t1 to t3. The scan driver 30 supplies the kth scan signal SCANk having the gate off voltage Voff to the kth scan line Sk during the fourth period t4. The kth scan signal SCANk may have a gate-on voltage Von during one horizontal period (1H).

The initialization driver 40 may sequentially supply the initialization signals SENS1 to SENSn to the initialization lines SEN1 to SENn. The initialization driver 40 supplies the k-th initialization signal SENSk having the gate-on voltage Von to the k-th initialization line SENk during the first period t1. The initialization driver 40 supplies the k-th initialization signal SENSk having the gate-off voltage Voff to the k-th initialization line SENk during the second to fourth periods t2 to t4.

4 is a flowchart illustrating a method of driving a pixel according to an exemplary embodiment of the present invention. FIGS. 5A to 5D are circuit diagrams showing the operation of the pixel P of FIG. 2 during the first to fourth periods of FIG.

The compensation method for compensating the threshold voltage of the driving transistor of the pixel P is classified into an internal compensation method and an external compensation method. The internal compensation method is a method of sensing and compensating the threshold voltage of the driving transistor DT in the pixel P. The external compensation method supplies a preset voltage to the pixel P and senses the voltage of the source electrode of the driving transistor DT of the pixel P through a predetermined sensing line according to the preset voltage, And compensates digital video data to be supplied to the pixel P using a voltage. The embodiment of the present invention compensates the threshold voltage of the driving transistor DT by an internal compensation method. Hereinafter, a driving method of the pixel P according to an embodiment of the present invention will be described in detail with reference to FIGS. 3, 4 and 5A to 5D. FIG.

First, during the first period t1, the gate electrode and the source electrode of the driving transistor DT are initialized to the reference voltage Vref.

During the first period t1, the kth scan signal SCANk having the gate-on voltage Von is supplied to the kth scan line Sk. During the first period t1, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-on voltage Von. The reference voltage Vref is supplied to the j-th data line Dj during the first period t1.

During the first period t1, the first transistor ST1 is turned on by the k-th scan signal SCANk having the gate-on voltage Von. Due to the turn-on of the first transistor ST1, the reference voltage Vref is supplied to the gate electrode of the driving transistor DT. During the first period t1, the second transistor ST2 is turned on by the k-th initialization signal SENk having the gate-on voltage Von. Due to the turn-on of the second transistor ST2, the reference voltage Vref is supplied to the source electrode of the driving transistor DT. That is, the second transistor ST2 is a transistor for supplying the reference voltage Vref of the jth data line Dj to the source electrode of the driving transistor DT. The gate electrode and the source electrode of the driving transistor DT are initialized to the reference voltage Vref as shown in Figs. 3 and 5A. (S101 in Fig. 4)

Secondly, the threshold voltage of the driving transistor DT is sensed during the second period t2.

During the second period t2, the kth scan signal SCANk having the gate-on voltage Von is supplied to the kth scan line Sk. During the second period t2, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. And the compensation voltage Vcomp is supplied to the j-th data line Dj during the second period t2.

During the second period t2, the first transistor ST1 is turned on by the k-th scan signal SCANk having the gate-on voltage Von. Due to the turn-on of the first transistor ST1, the compensation voltage Vcomp is supplied to the gate electrode of the driving transistor DT. During the second period t2, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

Since the voltage difference (Vgs = Vcomp-Vref) between the gate electrode and the source electrode of the driving transistor DT is larger than the threshold voltage Vth of the driving transistor DT during the second period t2, DT flows a current until the voltage difference Vgs between the gate electrode and the source electrode reaches the threshold voltage Vth. As a result, the source voltage Vs of the driving transistor DT rises to "Vcomp-Vth" as shown in Figs. 3 and 5B. Therefore, the threshold voltage of the driving transistor DT is sensed to the source electrode of the driving transistor DT during the second period t2. (S102 in Fig. 4)

Thirdly, the data voltage is supplied to the gate electrode of the driving transistor DT during the third period t3.

During the third period t3, the kth scan line SC is supplied with the kth scan signal SCANk having the gate-on voltage Von. During the third period t3, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. During the third period t3, the data voltage Vdata is supplied to the j-th data line Dj.

During the third period t3, the first transistor ST1 is turned on by the kth scan signal SCANk having the gate-on voltage Von. Due to the turn-on of the first transistor ST1, the data voltage Vdata is supplied to the gate electrode of the driving transistor DT. During the third period t3, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

Meanwhile, the embodiment of the present invention can compensate the electron mobility () of the driving transistor DT during the third period t3. During the third period t3, the driving transistor DT has a voltage difference (Vgs = Vdata- (Vcomp-Vth)) between the gate electrode and the source electrode is larger than the threshold voltage Vth, And the voltage difference (Vgs) between the source electrode and the source electrode reaches the threshold voltage. However, the third period t3 is shorter than the second period t2, so that the third period t3 is ended before the source voltage Vs of the driving transistor DT reaches "Vdata-Vth" do.

At this time, the current of the driving transistor DT can be defined as shown in Equation (1).

&Quot; W "is the channel width of the driving transistor DT," L "is the capacitance of the driving transistor DT, Quot; means the channel length of the driving transistor DT.

Since the current of the driving transistor DT is proportional to the electron mobility K of the driving transistor DT as shown in Equation 1, the rising amount of the source voltage Vs of the driving transistor DT during the third period t3 is And is proportional to the electron mobility K of the driving transistor DT. That is, the greater the electron mobility K of the driving transistor DT, the greater the amount of rise of the source voltage Vs of the driving transistor DT during the third period t3.

As a result, the amount of rise of the source voltage Vs varies in accordance with the electron mobility K of the driving transistor DT during the third period t3, and as a result, the voltage difference between the gate electrode and the source electrode of the driving transistor DT (Vgs). That is, in the embodiment of the present invention, the voltage difference Vgs between the gate electrode and the source electrode can be adjusted according to the electron mobility K of the driving transistor DT during the third period t3, Can be compensated for.

As described above, during the third period t3, the gate voltage Vg of the driving transistor is "Vdata" and the source voltage Vs is the electron mobility of the driving transistor DT V " to " Vcomp-Vth + alpha " "alpha" may be defined as a rising amount of the source voltage Vs during the third period t3. Therefore, during the third period t3, the capacitor C stores "Vdata- (Vcomp-Vth +?)" Which is the voltage difference Vgs between the gate electrode and the source electrode of the driving transistor DT. (S103 in Fig. 4)

Fourth, during the fourth period t4, the organic light emitting diode OLED emits light according to the current Ids of the driving transistor DT.

During the fourth period t4, the kth scan signal SCANk having the gate off voltage Voff is supplied to the kth scan line Sk. During the fourth period t4, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff.

During the fourth period t4, the first transistor ST1 is turned off by the kth scan signal SCANk having the gate-off voltage Voff. During the fourth period t4, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

The voltage difference (Vgs = Vdata- (Vcomp-Vth + alpha)) between the gate electrode and the source electrode of the driving transistor DT can be kept constant by the capacitor C during the fourth period t4. As a result, the current Ids of the driving transistor DT flowing into the organic light emitting diode OLED can be defined as shown in Equation (2).

Summarizing the expression (2), the expression (3) is derived.

As a result, the current Ids of the driving transistor DT does not depend on the threshold voltage Vth of the driving transistor DT as shown in Equation (3). That is, the threshold voltage Vth of the driving transistor DT is compensated. 5D, the organic light emitting diode OLED emits light according to the current Ids of the driving transistor DT whose threshold voltage Vth of the driving transistor DT is compensated. (S104 in Fig. 4)

As described above, in the embodiment of the present invention, the gate electrode and the source electrode of the driving transistor DT are initialized to the reference voltage Vref during the first period t1, and during the second period t2, DT is supplied to the gate electrode of the transistor QD1. As a result, the embodiment of the present invention can sense the threshold voltage of the driving transistor DT to the source electrode of the driving transistor DT during the second period t2. Therefore, the embodiment of the present invention can emit the organic light emitting diode OLED according to the current Ids of the driving transistor whose threshold voltage is compensated.

In the embodiment of the present invention, the data voltage is supplied to the gate electrode of the driving transistor DT during the third period t3, the source voltage Vs is raised by "? &Quot;, the rising amount of the source voltage Vs Quot; alpha "differs depending on the electron mobility of the driving transistor DT. As a result, in the embodiment of the present invention, the voltage difference Vgs between the gate electrode and the source electrode can be adjusted according to the electron mobility K of the driving transistor DT during the third period t3, The electron mobility K of the electron beam can be compensated.

6 is a circuit diagram showing another example of the pixel of FIG. 6, the pixel P includes an organic light emitting diode (OLED), a driving transistor DT, first and second transistors ST1 and ST2, and a capacitor C.

The organic light emitting diode OLED, the driving transistor DT, the first transistor ST1 and the capacitor C of the pixel P shown in FIG. 6 are connected to the organic light emitting diode OLED, the driving transistor DT, the first transistor ST1, and the capacitor C. [ Therefore, detailed description of the organic light emitting diode OLED, the driving transistor DT, the first transistor ST1, and the capacitor C of the pixel P shown in FIG. 6 will be omitted.

The second transistor ST2 is turned on by the k-th initialization signal of the k-th initialization line SENk to connect the gate electrode and the source electrode of the driving transistor DT. The gate electrode of the second transistor ST2 is connected to the kth initializing line SENk and the first electrode is connected to the source electrode of the driving transistor DT and the second electrode is connected to the gate electrode of the driving transistor DT Can be connected.

A k-th scan signal SCANk supplied to the k-th scan line Sk connected to the pixel P shown in Fig. 6, a k-th initialization signal SENSk supplied to the k-th initialization line SENk, The voltage DVj supplied to the data line Dj and the gate voltage Vg and the source voltage Vs of the driving transistor DT are substantially the same as those shown in FIG. Since the method of driving the pixel P shown in FIG. 6 is substantially the same as that shown in FIG. 4, a detailed description thereof will be omitted.

7 is an exemplary view showing a display panel divided into blocks. 7, the scan lines S1 to S3p of the display panel 10, the initialization lines SEN1 to SEN3p, the pixels P, the scan driver 30, and the initialization driver 40 ). In FIG. 7, the display panel 10 is divided into three blocks BL1, BL2, and BL3 for convenience of explanation. However, the present invention is not limited thereto. That is, the display panel 10 may be divided into two or more blocks.

Referring to FIG. 7, each of the blocks BL1, BL2, and BL3 may include the same number of pixels. Specifically, when the display panel 10 is divided into q (q is a positive integer of 2 or more) blocks, each of q blocks is connected to p (p is a positive integer of 2 or more) scan lines And may include pixels (P). Here, p may be n (the total number of scan lines) / q (the number of blocks).

For example, when the display panel 10 is divided into three blocks BL1, BL2, and BL3 as shown in FIG. 7, each of the blocks BL1, BL2, and BL3 is connected to p (P). As shown in FIG. 7, the first block BL1 includes pixels P connected to the first through pth scan lines S1 through Sp, and the second block BL2 includes p + And the pixels P connected to the lines Sp + 1 to S2p and the third block BL3 includes pixels P connected to the second p + 1 th to the third p scan lines S2p + 1 to S3p ).

8 is a waveform diagram showing scan signals and initialization signals supplied to the display panel. 8 shows the first to third p scan signals SCAN1 to SCAN3p and the first to third p initialization lines S1 to S3p supplied to the first to third p scan lines S1 to S3p of FIG. The first to third p initialization signals SENS1 to SENS3p to be supplied are shown.

Referring to FIG. 8, one frame period includes q subframe periods. For example, when the display panel 10 is divided into three blocks BL1, BL2, and BL3 as shown in FIG. 7, one frame period includes three subframe periods SF1, SF2, and SF3 .

The scan driver 30 supplies the first to pth scan signals SCAN1 to SCANp to the first to pth scan lines S1 to Sp during the first sub frame period SF1. The initialization driver 40 supplies the first to p initialization signals SENS1 to SENSp to the first to pth initialization lines SEN1 to SENp during the first sub frame period SF1.

The scan driver 30 also supplies the p + 1 to the second p scan signals SCANp + 1 to SCnp + 1 to the second p scan lines Sp + 1 to S2p during the second sub frame period SF2, SCAN2p). The initialization driving unit 40 outputs the p + 1 to the 2p initialization signals SENSp + 1 to SENS2p to the p + 1 to 2p initialization lines SENp + 1 to SEN2p during the second sub frame period SF2, .

The scan driver 30 also applies the second p + 1 th to the third p scan signals SCAN2p + 1 to SCn2p + 1 to the third p scan lines S2p + 1 to S3p during the third sub frame period SF3, SCAN3p). The initialization driving unit 40 supplies the second p + 1 th to the third p initialization signals SENS2p + 1 to SENS3p to the second p + 1 th to the third p initializing lines SEN2p + 1 to SEN3p during the third sub frame period SF3, .

That is, the scan driver 30 and the initialization driver 40 supply the scan signals and the initialization signals only to the scan lines and the initialization lines connected to the pixels of the first block BL1, And the scan lines and the initialization signals are supplied only to the scan lines and the initialization lines connected to the pixels of FIG. The scan driver 30 and the initialization driver 40 supply the scan signals and the initialization signals only to the scan lines and the initialization lines connected to the pixels of the second block BL2, And the scan lines and the initialization signals are supplied only to the scan lines and the initialization lines connected to the pixels of FIG. Therefore, q blocks of the display panel 10 are sequentially driven, and q blocks of the display panel 10 are driven block by block.

Each of the q subframe periods includes a threshold voltage sensing period ST and a data voltage supply period DP as shown in FIG. The threshold voltage sensing period ST is a period for sensing the threshold voltage of the driving transistor DT of each of the pixels P of the block. The data voltage supply period DP is a period of supplying data voltages to the pixels P of the block. A detailed description of the threshold voltage sensing period ST and the data voltage supply period DP will be described later with reference to FIG.

9 is a waveform diagram showing the k-th scan signal, the k-th initialization signal, the j-th data signal, and the gate voltage and the source voltage of the driving transistor. 9 shows a k-th scan signal SCANk supplied to the k-th scan line Sk connected to the pixel P of Fig. 2, a k-th initialization signal SENSk supplied to the k-th initialization line SENk, the voltage DVj supplied to the data line Dj and the gate voltage Vg and the source voltage Vs of the driving transistor DT are shown.

Referring to FIGS. 8 and 9, each of the sub-frame periods SF1, SF2, and SF3 includes a threshold voltage sensing period ST and a data voltage supply period DP. The threshold voltage sensing period ST includes first to third periods t1 to t3 and the data voltage supply period DP may include fourth to sixth periods t4 to t6.

The first period t1 is a period for initializing the gate electrode and the source electrode of the driving transistor DT to the reference voltage Vref. The second period t2 is a period for sensing the threshold voltage of the driving transistor DT. The third period t3 is a period for supplying the turn-off voltage Vt to the gate electrode of the driving transistor DT. The fourth period t4 is a period for maintaining the gate-source voltage Vgs of the driving transistor DT. The fifth period t5 is a period for supplying the data voltage Vdata to the gate electrode of the driving transistor DT. The sixth period t6 is a period during which the organic light emitting diode OLED emits light according to the current of the driving transistor DT. The second period t2 is preferably longer than the first, third and fifth periods t1, t3 and t5, respectively. Meanwhile, since the p scan signals are sequentially supplied in each of the sub-frame periods SF1, SF2, and SF3 as shown in FIG. 8, the lengths of the fourth periods t4 of the p scan signals are different from each other.

The data driver 20 supplies the reference voltage Vref to the j-th data line Dj during the first period t1. The reference voltage Vref is a voltage for initializing the gate electrode and the source electrode of the driving transistor DT. The data driver 20 supplies the compensation voltage Vcomp to the j-th data line Dj during the second period t2. The compensation voltage Vcomp is a voltage for compensating the threshold voltage of the driving transistor DT. When the driving transistor DT is formed of an N-type MOSFET, the compensation voltage Vcomp may be a voltage higher than the reference voltage Vref as shown in FIG. The data driver 20 supplies the turn-off voltage Vt to the j-th data line Dj during the third and fourth periods t3 and t4. The turn-off voltage Vt is a voltage capable of turning off the driving transistor DT. When the driving transistor DT is formed of an N-type MOSFET, the turn-off voltage Vt may be a voltage lower than the compensation voltage Vcomp as shown in FIG. Further, the turn-off voltage Vt may be set to the same voltage as the reference voltage Vref. The data driver 20 supplies the data voltage Vdata to the j-th data line Dj during the fifth period t5. The data voltage Vdata is a voltage supplied to the gate electrode of the driving transistor DT to emit the organic light emitting diode OLED at a predetermined luminance. When the driving transistor DT is formed of an N-type MOSFET, the data voltage Vdata may be higher than the compensation voltage Vcomp as shown in FIG.

The scan driver 30 simultaneously supplies the scan signals to the scan lines during the first to fourth and sixth periods t1 to t4 and t6 as shown in FIG. And sequentially supplies the scan signals. The scan driver 30 supplies the k-th scan signal SCANk having the gate-on voltage Von to the k-th scan line Sk during the first to third and fifth periods t1 to t3 and t5 . The scan driver 30 supplies the kth scan signal SCANk having the gate off voltage Voff to the kth scan line Sk during the fourth and sixth periods t4 and t6.

The initialization driver 40 simultaneously supplies initialization signals SENS1 to SENSn to the initialization lines SEN1 to SENn during the first to sixth periods t1 to t6 as shown in FIG. The initialization driver 40 supplies the k-th initialization signal SENSk having the gate-on voltage Von to the k-th initialization line SENk during the first period t1. The initialization driver 40 supplies the k-th initialization signal SENSk having the gate-off voltage Voff to the k-th initialization line SENk during the second to sixth periods t2 to t6.

3, in the first period t1 for initializing the gate electrode and the source electrode of the driving transistor DT in one horizontal period 1H, A second period t2 for sensing the threshold voltage of the driving transistor DT and a third period t3 for supplying the data voltage to the driving transistor DT. Therefore, in the case of performing sequential driving as shown in FIG. 3, the embodiment of the present invention may have a problem that the period for initialization, threshold voltage sensing, and data voltage supply is insufficient if the high-speed driving is 120 Hz or more.

In order to solve this problem, the embodiment of the present invention divides the display panel 10 into a plurality of blocks BL1, BL2, and BL3, sequentially drives the blocks BL1, BL2, and BL3, . As a result, in the embodiment of the present invention, the initialization of the gate electrode and the source electrode of the driving transistor DT and the threshold voltage sensing of the driving transistor DT are performed simultaneously for each block as shown in FIG. 8, A first period t1 for initializing the electrode and the source electrode, a second period t2 for sensing the threshold voltage of the driving transistor DT, and a fifth period for supplying the data voltage to the driving transistor DT t5 can be increased as compared with the case of performing sequential driving as shown in Fig. Therefore, the embodiment of the present invention has an advantage that a period for initialization, threshold voltage sensing, and data voltage supply can be sufficiently secured even when high-speed driving is performed at 120 Hz or more.

10 is a flowchart illustrating a method of driving a pixel according to another embodiment of the present invention. Hereinafter, a driving method of a pixel according to another embodiment of the present invention will be described in detail with reference to FIGS. 9, 10 and 11A to 11F.

First, during the first period t1, the gate electrode and the source electrode of the driving transistor DT are initialized to the reference voltage Vref as shown in Figs. 9 and 11A. The operation of the pixel P during the first period t1 shown in FIG. 10 is substantially the same as the operation of the pixel P during the first period t1 described with reference to FIG. 4, do. (S201 in Fig. 10)

Secondly, during the second period t2, the threshold voltage of the driving transistor DT is sensed as shown in Figs. 9 and 11B. The operation of the pixel P during the second period t2 shown in FIG. 10 is substantially the same as the operation of the pixel P during the second period t2 described with reference to FIG. 4, do. (S202 in Fig. 10)

Thirdly, the turn-off voltage Vt is supplied to the gate electrode of the driving transistor DT during the third period t3.

During the third period t3, the kth scan line SC is supplied with the kth scan signal SCANk having the gate-on voltage Von. During the third period t3, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. During the third period t3, the turn-off voltage Vt is supplied to the j-th data line Dj.

During the third period t3, the first transistor ST1 is turned on by the kth scan signal SCANk having the gate-on voltage Von. Due to the turn-on of the first transistor ST1, the turn-off voltage Vt is supplied to the gate electrode of the driving transistor DT. During the third period t3, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

During the third period t3, the gate voltage Vg of the driving transistor DT is "Vt" as shown in Figs. 9 and 11C, The source voltage Vs is lowered to "Vcomp-Vth-beta" At this time,? Can be defined as shown in Equation (4).

In Equation 4, "Vcomp" denotes a compensation voltage, "Vt" denotes a turn-off voltage, "CCc" denotes a capacitance of the capacitor C, and "CCcp" denotes a capacitance of the parasitic capacitor Cp. (S203 in Fig. 10)

Fourth, the voltage Vs of the source electrode of the driving transistor DT is maintained during the fourth period t4.

During the fourth period t4, the kth scan signal SCANk having the gate off voltage Voff is supplied to the kth scan line Sk. During the fourth period t4, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. The turn-off voltage Vt is supplied to the j-th data line Dj during the fourth period t4.

During the fourth period t4, the first transistor ST1 is turned off by the kth scan signal SCANk having the gate-off voltage Voff. During the fourth period t4, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

The voltage Vg of the gate electrode of the driving transistor DT during the fourth period t4 maintains the turn-off voltage Vt supplied during the third period t3. Therefore, during the fourth period t4, the driving transistor DT remains in the turned-off state following the third period t3.

Since p scan signals are sequentially supplied during the data voltage supply period DP of each of the sub frame periods SF1, SF2 and SF3 as shown in FIG. 8, the fourth period t4 of the p scan signals The lengths are different. That is, the length of the fourth period t4 may vary depending on which scan line the pixel is connected to in each of the blocks. The voltage difference Vgs between the gate electrode and the source electrode of the driving transistor DT is set to the second period t2 without turning off the driving transistor DT during the third and fourth periods t3 and t4 In the case of keeping the same, a current can flow finely through the driving transistor DT. Therefore, if the driving transistor DT is not turned off during the fourth period t4, the voltage Vs of the source electrode may fluctuate due to the current flowing finely through the driving transistor DT.

However, the embodiment of the present invention can maintain the voltage Vs of the source electrode of the driving transistor DT as it is by turning off the driving transistor DT during the fourth period t4. Therefore, during the fourth period t4, the source voltage Vs of the driving transistor DT maintains "Vcomp-Vth-beta" as shown in Figs. 9 and 11D. (S204 in Fig. 10)

Fifth, the data voltage is supplied to the gate electrode of the driving transistor DT during the fifth period t5.

During the fifth period t5, the kth scan signal SCANk having the gate-on voltage Von is supplied to the kth scan line Sk. During the fifth period t5, the k-th initialization line SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. During the fifth period t3, the data voltage Vdata is supplied to the j-th data line Dj.

During the fifth period t5, the first transistor ST1 is turned on by the k-th scan signal SCANk having the gate-on voltage Von. Due to the turn-on of the first transistor ST1, the data voltage Vdata is supplied to the gate electrode of the driving transistor DT. During the fifth period t5, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

Meanwhile, the embodiment of the present invention can compensate for the electron mobility () of the driving transistor DT during the fifth period (t5). During the fifth period t5, the driving transistor DT has a voltage difference (Vgs = Vdata- (Vcomp-Vth-beta)) between the gate electrode and the source electrode is larger than the threshold voltage Vth, The current is allowed to flow until the voltage difference between the gate electrode and the source electrode reaches the threshold voltage. However, the fifth period t5 is shorter than the second period t2, so that the fifth period t5 ends before the source voltage Vs of the driving transistor DT reaches "Vdata-Vth" do.

Since the current of the driving transistor DT is proportional to the electron mobility K of the driving transistor DT as shown in Equation 1, the rising amount of the source voltage Vs of the driving transistor DT during the fifth period t5 is And is proportional to the electron mobility K of the driving transistor DT. That is, the greater the electron mobility of the driving transistor DT, the greater the amount of rise of the source voltage Vs of the driving transistor DT during the fifth period t5.

As a result, the amount of rise of the source voltage Vs varies depending on the electron mobility K of the driving transistor DT during the fifth period t5. As a result, the voltage difference between the gate electrode and the source electrode of the driving transistor DT (Vgs). That is, in the embodiment of the present invention, the voltage difference Vgs between the gate electrode and the source electrode can be adjusted according to the electron mobility K of the driving transistor DT during the fifth period t5, Can be compensated for.

On the other hand, during the fifth period t5, the gate voltage Vg of the driving transistor is "Vdata ", and the source voltage Vs rises to" Vcomp-Vth-beta + alpha " At this time, "alpha" may be defined as the amount of increase of the source voltage Vs during the fifth period t5. Therefore, during the fifth period t5, the capacitor C stores "Vdata- (Vcomp-Vth-beta + alpha) ", which is the voltage difference Vgs between the gate electrode and the source electrode of the driving transistor DT. (S205 in Fig. 10)

Sixth, during the sixth period t6, the organic light emitting diode OLED emits light according to the current of the driving transistor DT.

During the sixth period t6, the k-th scan line SC is supplied with the k-th scan signal SCANk having the gate-off voltage Voff. During the sixth period t6, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff.

During the sixth period t6, the first transistor ST1 is turned off by the kth scan signal SCANk having the gate-off voltage Voff. During the sixth period t6, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

The voltage difference (Vgs = Vdata- (Vcomp-Vth-beta + alpha)) between the gate electrode and the source electrode of the driving transistor DT can be kept constant by the capacitor C during the sixth period t6. As a result, the current Ids of the driving transistor DT flowing to the organic light emitting diode OLED can be defined as shown in Equation (5).

Summarizing the expression (5), the expression (6) is derived.

As a result, the current Ids of the driving transistor DT does not depend on the threshold voltage Vth of the driving transistor DT as in Equation (6). That is, the threshold voltage Vth of the driving transistor DT is compensated. As a result, the organic light emitting diode OLED emits light according to the current Ids of the driving transistor DT whose threshold voltage Vth of the driving transistor DT is compensated as shown in FIG. 11F. (S206 in Fig. 10)

As described above, in the embodiment of the present invention, the gate electrode and the source electrode of the driving transistor DT are initialized to the reference voltage Vref during the first period t1, and during the second period t2, DT is supplied to the gate electrode of the transistor QD1. In this case, since the voltage difference Vgs between the gate electrode and the source electrode of the driving transistor DT is greater than the threshold voltage during the second period t2, the driving transistor has a voltage difference Vgs between the gate electrode and the source electrode, The current is allowed to flow until the voltage is reached. As a result, the embodiment of the present invention can sense the threshold voltage of the driving transistor DT to the source electrode of the driving transistor DT during the second period t2. Therefore, the embodiment of the present invention can emit the organic light emitting diode OLED according to the current Ids of the driving transistor whose threshold voltage is compensated.

Further, the embodiment of the present invention supplies the data voltage to the gate electrode of the driving transistor DT during the fifth period t5, and raises the voltage Vs of the source electrode by "?". At this time, "? &Quot;, which is an amount of rise of the voltage Vs of the source electrode, varies depending on the electron mobility of the driving transistor DT. As a result, the embodiment of the present invention can adjust the voltage difference Vgs between the gate electrode and the source electrode in accordance with the electron mobility K of the driving transistor DT during the fifth period t5, The electron mobility K of the electron beam can be compensated.

On the other hand, a k-th scan signal SCANk supplied to the k-th scan line Sk connected to the pixel P shown in Fig. 6, a k-th initialization signal SENSk supplied to the k-th initialization line SENk, Since the voltage DVj supplied to the jth data line Dj and the gate voltage Vg and the source voltage Vs of the driving transistor DT are substantially the same as those shown in Fig. 9, do. The driving method of the pixel P shown in FIG. 6 is substantially the same as that shown in FIG. 10, and a detailed description thereof will be omitted.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 20: data driver
30: scan driver 40: initialization driver
50: timing control section P: pixel
DT: driving transistor ST1: first transistor
ST2: second transistor OLED: organic light emitting diode
C: capacitor Sk: kth scan line
SENk: kth initialization line Dj: jth data line
SCANk: kth scan signal SENSk: kth initialization signal
Vg: gate voltage Vs: source voltage
Vref: reference voltage Vcomp: compensation voltage
Vdata: data voltage Von: gate-on voltage
Voff: gate-off voltage

Claims (1)

A display panel having pixels connected to data lines, scan lines, and first power supply voltage lines;
A data driver for supplying data voltages to the data lines; And
And a scan driver for supplying scan signals to the scan lines,
The pixel includes:
Organic light emitting diodes;
A driving transistor connected to the first power supply voltage line of the organic light emitting diode and the first power supply voltage lines;
A first transistor connected to one of the data lines and a gate electrode of the driving transistor;
A second transistor for supplying a reference voltage of one of the data lines to a source electrode of the driving transistor; And
And a capacitor connected to a gate electrode and a source electrode of the driving transistor,
The data driver supplies the reference voltage to a jth (j is a positive integer) data line during a first period, supplies a compensating voltage during a second period, supplies a data voltage during a third period,
The scan driver supplies a k-th (k is a positive integer) scan signal having a gate-on voltage continuously during the first to third periods to the k-th scan line, k scan signal to the k < th > scan line,
Wherein the second period immediately follows the first period and the third period continues immediately after the second period.

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