KR101907962B1 - Organic light emitting diode display device - Google Patents

Abstract

An organic light emitting diode display device according to an embodiment of the present invention includes a display panel having a plurality of pixels formed in a matrix shape, each of the pixels having a gate electrode connected to a first node, And a drain electrode connected to the third node; An organic light emitting diode including an anode electrode connected to the third node and a cathode electrode connected to a low potential voltage source for supplying a low potential voltage; A first TFT which is turned on in response to a first scan signal of the first scan line to connect the data line to the first node; A second TFT connected to the first node and a first reference voltage line for supplying a first reference voltage from the first reference voltage source, the second TFT being turned on in response to a second scan signal of the second scan line; A third TFT which is turned on in response to a second scan signal of the second scan line and connects the third node and a second reference voltage line supplying a second reference voltage from the second reference voltage source; A fourth TFT which is turned on in response to a light emitting signal of the light emitting line to connect a high potential voltage source for supplying a high potential voltage to the second node; A fifth TFT which is turned on in response to a control signal of a control line to connect the second node and the fourth node; A first capacitor connected between the first node and the fourth node; And a second capacitor connected between the fourth node and the high potential voltage source.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display device capable of compensating a threshold voltage of a driving TFT.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. In recent years, various flat panel display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) have been used . Among these flat panel display devices, organic light emitting diode display devices are capable of low voltage driving, are thin, have excellent viewing angles, and have a high response speed. An active matrix type organic light emitting diode display device in which a plurality of pixels are arranged in a matrix form to display an image is widely used in organic light emitting diode display devices.

A display panel of an active matrix type organic light emitting diode display device includes a plurality of pixels arranged in a matrix form. Each of the pixels includes a scan TFT (Thin Film Transistor) for supplying a data voltage of the data line in response to a scan signal of the scan line, and a current And a driving TFT for adjusting the amount of the driving TFT. At this time, the drain-source current Ids of the driving TFT supplied to the organic light emitting diode can be expressed by Equation (1).

In Equation 1, k 'is a proportional coefficient determined by the structure and physical characteristics of the driving TFT, Vgs is the gate-source voltage of the driving TFT, and Vth is the threshold voltage of the driving TFT.

On the other hand, the threshold voltage (Vth) of each of the driving TFTs of the pixels may have different values due to the threshold voltage shift due to deterioration of the driving TFT. In this case, since the drain-source current Ids of the driving TFT depends on the threshold voltage Vth of the driving TFT, even if the same data voltage is supplied to each of the pixels, the current Ids supplied to the organic light- It is different. Therefore, even if the same data voltage is supplied to each of the pixels, the luminance of the light emitted by each of the organic light emitting diodes of the pixels varies. To solve this problem, various types of pixel structures for compensating a threshold voltage of a driving TFT have been proposed.

However, in recent years, an organic light emitting diode display device has been manufactured to realize a stereoscopic image realization or a high-speed driving with a frame frequency of 240 Hz or more in order to improve image quality. In this case, since the threshold voltage sensing period is shortened, the accuracy of the threshold voltage sensing of the driving TFT is lowered. In addition, recently, organic light emitting diode display devices have been manufactured in a large-area high resolution according to a demand of a consumer. In this case, since the wiring length becomes long, the wiring resistance becomes high and an RC delay may occur. As a result, the pulse of the threshold voltage sensing signal is delayed to shorten the threshold voltage sensing period. There is a problem that the accuracy is lowered.

The present invention provides an organic light emitting diode display device capable of increasing the accuracy of threshold voltage sensing of a driving TFT.

An organic light emitting diode display device according to an exemplary embodiment of the present invention includes a display panel having a data line, a first scan line, a second scan line, a control line, and a light emitting line, , Each of the pixels including: a driver TFT having a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to the third node; An organic light emitting diode including an anode electrode connected to the third node and a cathode electrode connected to a low potential voltage source for supplying a low potential voltage; A first TFT which is turned on in response to a first scan signal of the first scan line to connect the first node and the data line; A second TFT connected to the first node and a first reference voltage line supplying a first reference voltage from the first reference voltage source, the second TFT being turned on in response to a second scan signal of the second scan line; A third TFT which is turned on in response to a second scan signal of the second scan line and connects the third node and a second reference voltage line supplying a second reference voltage from the second reference voltage source; A fourth TFT which is turned on in response to the light emitting signal of the light emitting line to connect a high potential voltage source supplying the high potential voltage to the second node; A fifth TFT which is turned on in response to a control signal of the control line to connect the second node and the fourth node; A first capacitor connected between the first node and the fourth node; And a second capacitor connected between the fourth node and the high potential voltage source.

The present invention senses the threshold voltage of the driving TFT for a period longer than two horizontal periods. As a result, the present invention can accurately sense the threshold voltage of the driving TFT even when the large-area, high-resolution organic light emitting display device is driven at a high frame frequency of 240 Hz or higher.

Further, the present invention connects the fourth TFT between the high potential source and the driving TFT, and controls on / off of the fourth TFT by using the light emitting signal. As a result, the present invention can compensate the voltage drop of the high-potential voltage by compensating the threshold voltage using the voltage reflecting the voltage drop of the high-potential voltage.

Further, the present invention can sense the drain-source current of the driving TFT and the current of the organic light emitting diode using the second reference voltage line. As a result, since the present invention can externally compensate the sensed current using an external compensation method, it is possible to compensate not only the threshold voltage of the driving TFT but also the electron mobility of the driving TFT and the threshold voltage of the organic light emitting diode.

1 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention;
FIG. 2 is a waveform diagram showing a voltage change of signals and nodes input to a pixel in the case of internal compensation of a driving TFT; FIG.
3 is a graph showing a threshold voltage compensation error according to a threshold voltage change of a driving TFT according to a threshold voltage sensing period.
4 is a waveform diagram showing signals input to a pixel in the case of external compensation of a driving TFT;
5 shows a current flow diagram of a pixel in the case of external compensation of a driving TFT;
6 is a waveform diagram showing signals input to a pixel in the case of external compensation of an organic light emitting diode;
7 is a current flow diagram of a pixel in the case of external compensation of an organic light emitting diode;
8 is a block diagram schematically showing an organic light emitting diode display device according to an embodiment of the present invention.
9 is a block diagram showing an external compensation unit of the timing controller;
10 is a flow chart illustrating an external compensation method in accordance with an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

The pixel of the organic light emitting diode display device according to the embodiment of the present invention not only internally compensates the threshold voltage of the driving TFT but also compensates the threshold voltage and electron mobility of the driving TFT and the threshold voltage of the organic light emitting diode, can do. The internal compensation means to sense and compensate the threshold voltage of the driving TFT in real time in the pixel. The external compensation senses the current between the drain and the source of the driving TFT and the current of the organic light emitting diode and compensates the digital video data to be input to the pixel using the sensed current and then supplies the compensated digital video data to the pixel do. Description of the pixel for internally compensating the threshold voltage of the driving TFT has been described with reference to FIGS. 1 to 3. The threshold voltage of the driving TFT, the electron mobility, the threshold voltage of the organic light emitting diode, The description has been made by referring to Figs. 4 to 7. Fig.

1 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. 1, a pixel P according to an embodiment of the present invention includes a driving TFT (Thin Film Transistor) DT, an organic light emitting diode (OLED), a control circuit, and a capacitor .

The driving TFT DT adjusts the amount of the drain-source current Ids differently depending on the amount of voltage applied to the gate electrode. The gate electrode of the driving TFT DT is connected to the first node N1, the source electrode thereof is connected to the second node N2, and the drain electrode thereof is connected to the third node N3.

The anode electrode of the organic light emitting diode (OLED) is connected to the third node (N3), and the cathode electrode is connected to the low potential voltage source for supplying the low potential voltage (VSS). The organic light emitting diode OLED emits light in accordance with the drain-source current Ids of the driving TFT DT.

The control circuit includes the first to fifth TFTs T1, T2, T3, T4, and T5. The first TFT T1 is turned on in response to the first scan signal SCAN1 supplied from the first scan line SL1 and is supplied with the first node N1 and the data line DL ). The gate electrode of the first TFT T1 is connected to the first scan line SL1, the source electrode thereof is connected to the data line DL, and the drain electrode thereof is connected to the first node N1.

The second TFT T2 is turned on in response to the second scan signal SCAN2 supplied from the second scan line SL2 to connect the first node N1 to the first reference voltage line RL1. The first reference voltage line RL1 is connected to the first reference voltage source to which the first reference voltage REF1 is supplied. The gate electrode of the second TFT T2 is connected to the second scan line SL2, the source electrode thereof is connected to the first node N1, and the drain electrode thereof is connected to the first reference voltage line RL1.

The third TFT T3 is turned on in response to the second scan signal SCAN2 supplied from the second scan line SL2 to connect the third node N3 and the second reference voltage line RL2. And the second reference voltage line RL2 is connected to the second reference voltage source to which the second reference voltage REF2 is supplied. The gate electrode of the third TFT T3 is connected to the second scan line SL2, the source electrode thereof is connected to the third node N3, and the drain electrode thereof is connected to the second reference voltage line RL2.

The fourth TFT T4 is turned on in response to the emission signal EM of the light emission line EML to connect the high potential voltage source supplying the second node N2 with the high potential voltage VDD. The gate electrode of the fourth TFT T4 is connected to the light emitting line EML, the source electrode thereof is connected to the high potential voltage source, and the drain electrode thereof is connected to the second node N2.

The fifth TFT T5 is turned on in response to the control signal MG of the control line MGL to connect the second node N2 and the fourth node N4. The gate electrode of the fifth TFT T5 is connected to the control line MGL, the source electrode thereof is connected to the second node N2, and the drain electrode thereof is connected to the fourth node N4.

The first capacitor C1 is connected between the first node N1 and the fourth node N4 and stores the difference voltage between the first node N1 and the fourth node N4. The second capacitor C2 is connected between the high potential source and the fourth node N4 and stores the difference voltage between the high potential source and the fourth node N4.

The first node N1 is a contact point between the gate electrode of the driving TFT DT, the drain electrode of the first TFT T1, the source electrode of the second TFT T2, and one electrode of the first capacitor C1. The second node N2 is a contact point between the source electrode of the driving TFT DT, the drain electrode of the fourth TFT T4, and the source electrode of the fifth TFT T5. The third node N3 is a contact point between the drain electrode of the driving TFT DT, the source electrode of the third TFT T3, and the anode electrode of the organic light emitting diode OLED. The fourth node N4 is a contact point between the drain electrode of the fifth TFT T5, the other electrode of the first capacitor C1, and the other electrode of the second capacitor C2.

The semiconductor layers of the first to fifth TFTs T1, T2, T3, T4, and T5 and the driver TFT DT may be formed of any one of a-Si, Poly-Si, and an oxide semiconductor. In the embodiment of the present invention, the first through fifth TFTs T1, T2, T3, T4, and T5 and the driving TFT DT are implemented by a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) However, the present invention is not limited to this, and it may be implemented as an N-type MOSFET.

The high potential voltage source is set to supply the direct current high potential voltage VDD in consideration of the characteristics of the driving TFT DT and the characteristics of the organic light emitting diode OLED and the low potential potential source supplies the direct current low potential potential VSS . ≪ / RTI > The first reference voltage REF1 is a voltage for initializing the first node N1 and may be set to a voltage lower than the high potential voltage VDD by at least the threshold voltage Vth of the driving TFT DT. The second reference voltage REF2 is a voltage for initializing the third node N3 and may be set to a voltage lower than the threshold voltage Vth of the organic light emitting diode OLED. For example, the high potential voltage VDD may be set to 12V, the low potential voltage VSS may be set to 0V, the first reference voltage REF1 may be set to 6V, and the second reference voltage REF2 may be set to 0V.

The organic light emitting diode display device of the present invention includes a second reference voltage switching circuit for externally compensating the threshold voltage Vth of the driving TFT DT and the electron mobility and the threshold voltage of the organic light emitting diode OLED REF2_SW). The second reference voltage switching circuit REF2_SW includes first and second switches S1 and S2, an inverter Inv, and a current sensing circuit ADC. Although the first and second switches S1 and S2 are formed of TFTs, the present invention is not limited thereto.

The first switch S1 is turned on in response to the switching control signal SC supplied from the switching control line SCL and supplies a second reference voltage REF2 to the second reference voltage line RL2. To the reference voltage source. The gate electrode of the first switch S1 is connected to the switching control line SCL, the source electrode thereof is connected to the second reference voltage source, and the drain electrode thereof is connected to the second reference voltage line RL2.

The second switch S2 is turned on in response to the inversion signal of the switching control signal SC supplied from the switching control line SCL to connect the second reference voltage line RL2 to the current sensing circuit ADC . The gate electrode of the second switch S2 is connected to the inverter Inv, the source electrode thereof is connected to the current sensing circuit ADC and the drain electrode thereof is connected to the second reference voltage line RL2.

The inverter Inv inverts the switching control signal SC supplied from the switching control line SCL. The inverter Inv is connected between the switching control line SCL and the gate electrode of the second switch S2.

The current sensing circuit ADC senses the current flowing in the second reference voltage line RL2. The current sensing circuit ADC converts the sensed current into digital data and outputs the converted digital data to the timing controller 40. [

FIG. 2 is a waveform diagram showing signals input to a pixel and voltage changes of nodes in the case of internal compensation. FIG. 2 shows the first and second scan signals SCAN1 and SCAN2, the control signal MG, the light emission signal EM, and the switching control signal SC, which are input to one pixel P of the display panel 10 in the case of internal compensation. (SC), and a data voltage (DATA). In addition, FIG. 2 shows voltage changes of the first to third nodes N1, N2 and N3.

2, the first and second scan signals SCAN1 and SCAN2, the control signal MG and the emission signal EM are applied to the first to fifth TFTs T1, T2, T3 and T4 of the pixel P, , T5). The switching control signal SC is a signal for controlling the first and second switches S1 and S2 of the second reference voltage switching circuit REF2_SW.

Each of the first and second scan signals SCAN1 and SCAN2, the control signal MG, the emission signal EM and the switching control signal SC occurs in a period of one frame period. The data voltage DATA is generated in a period of one horizontal period (1H). In FIG. 2, only the n-th data voltage DATA (n) supplied during the third period t3 is illustrated for convenience of explanation. The third period t3 is a period during which the data voltage is supplied to the pixel P. [ One horizontal period means one line scanning time in which data is written to pixels of one horizontal line in the display panel 10. [

The first scan signal SCAN1 is generated at the gate high voltage VGH during the first, second and fourth periods t1, t2 and t4 and at the gate low voltage VGL during the third period t3. Occurs. The second scan signal SCAN2 is generated at the gate low voltage VGL during the first and second periods t1 and t2 and is generated at the gate high voltage VGH during the third and fourth periods t3 and t4 do. The control signal MG is generated as the gate-low voltage VGL during the first and second periods t1 and t2 and the B period t4-B of the fourth period t4, and the third period t3 and Occurs at the gate high voltage (VGH) during the A period (t4-A) of the fourth period (t4). The A period (t4-A) of the fourth period t4 may be set to approximately several to several tens of horizontal periods. The emission signal EM is generated at the gate low voltage VGL during the first and fourth periods t1 and t4 and at the gate high voltage VGH during the second and third periods t2 and t3. The switching control signal SC is generated as a gate low voltage VGL during the first to fourth periods t1 to t4. The gate high voltage VGH may be set between about 14V and 20V, and the gate low voltage VGL may be set between about -12V and -5V. On the other hand, the second period t2 is preferably set to be equal to or longer than two horizontal periods.

Meanwhile, FIG. 2 shows voltage changes of the first to third nodes N1, N2 and N3. Hereinafter, the operation of the pixel P according to the embodiment of the present invention will be described in detail for the first to fourth periods t1 to t4 with reference to the voltage change of the first to third nodes N1, N2 and N3 Explain. The first period t1 is a period for initializing the first node N1 and the third node N3, the second period t2 is a period for sensing the threshold voltage of the driving TFT DT, (t3) is a period during which the data voltage is supplied, and the fourth period (t4) is a period during which the organic light emitting diode (OLED) emits light. The second period t2 continues in the first period t1 and the third period t3 continues in the second period t2 and the fourth period t4 continues in the third period t3 . The fourth period t4 is divided into an A period (t4-A) and a B period (t4-B).

The switching control signal SC of the gate low voltage VGL is supplied through the switching control line SCL during the first to fourth periods t1 to t4. The first switch S1 is turned on in response to the switch control signal SC of the gate low voltage VGL to connect the second reference voltage line and the second reference voltage line RL2. The second switch S2 is turned off by the inversion signal of the switch control signal SC. Due to the turn-on of the first switch S1 and the turn-off of the second switch S2, the second reference voltage line RL2 is supplied with the second reference voltage Vdd during the first to fourth periods t1 to t4 REF2).

The first scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1 and the second scan signal VGL of the gate low voltage VGL is supplied during the first period t1 SCAN2 are supplied through the second scan line SL2. The control signal MG of the gate low voltage VGL is supplied through the control line MGL and the emission signal EM of the gate low voltage VGL is supplied to the emission line EML during the first period t1, Lt; / RTI >

The first TFT T1 is turned off by the first scan signal SCAN1 of the gate high voltage VGH. The second TFT T2 is turned on in response to the second scan signal SCAN2 of the gate low voltage VGL to connect the first node N1 to the first reference voltage line RL1. Due to the turn-off of the first TFT T1 and the turn-on of the second TFT T2, the first node N1 is discharged to the first reference voltage REF1. The third TFT T3 is turned on in response to the second scan signal SCAN2 of the gate low voltage VGL to connect the third node N3 to the second reference voltage line RL2. Due to the turn-on of the third TFT (T3), the third node (N3) is discharged to the second reference voltage (REF2). The fourth TFT T4 is turned on in response to the emission signal EM of the gate low voltage VGL to connect the second node N2 to the high potential voltage source. Due to the turn-on of the fourth TFT T4, the second node N2 is charged to the high-potential voltage VDD. The fifth TFT T5 is turned on in response to the control signal MG of the gate low voltage VGL to connect the second node N2 and the fourth node N4. Due to the turn-on of the fifth TFT T5, the fourth node N4 is charged to the high-potential voltage VDD. As a result, during the period t1, the first node N1 is discharged to the first reference voltage REF1, the third node N3 is discharged to the second reference voltage REF2, and the second and fourth nodes N2, N4 are charged to the high potential voltage VDD.

Second, during the second period t2, the first scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1 and the second scan signal SCAN1 of the gate low voltage VGL SCAN2 are supplied through the second scan line SL2. The control signal MG of the gate low voltage VGL is supplied through the control line MGL and the emission signal EM of the gate high voltage VGH is supplied to the emission line EML during the second period t2, Lt; / RTI >

The first TFT T1 is turned off by the first scan signal SCAN1 of the gate high voltage VGH. The second TFT T2 is turned on in response to the second scan signal SCAN2 of the gate low voltage VGL to connect the first node N1 to the first reference voltage line RL1. Due to the turn-off of the first TFT (T1) and the turn-on of the second TFT (T2), the third node (N3) maintains the first reference voltage (REF1). The third TFT T3 is turned on in response to the second scan signal SCAN2 of the gate low voltage VGL to connect the third node N3 and the second reference voltage line RL2. Due to the turn-on of the third TFT (T3), the third node (N3) maintains the second reference voltage (REF2). The fourth TFT T4 is turned off by the emission signal EM of the gate high voltage VGH. Due to the turn-off of the fourth TFT T4, the second node N2 is floating. The fifth TFT T5 is turned on in response to the control signal MG of the gate low voltage VGL to connect the second node N2 and the fourth node N4. Due to the turn-on of the fifth TFT (T5), the fourth node (N4) floats to a potential substantially equal to the second node (N2).

Due to the floating of the second node N2 during the second period t2, the threshold voltage Vth of the driving TFT DT is sensed at the second node N2 and the fourth node N4. Since the voltage difference Vgs between the first node N1 connected to the gate electrode of the driving TFT DT and the second node N2 connected to the source electrode is larger than the threshold voltage Vth, Forms a current path until the voltage difference (Vgs) between the gate electrode and the source electrode reaches the threshold voltage (Vth). Therefore, the voltage of the second node N2 is lowered to the difference voltage REF1-Vth between the first reference voltage REF1 and the threshold voltage Vth of the driving TFT DT. Further, since the fourth node N4 is also floated to a potential substantially equal to the second node N2 due to the turn-on of the fifth TFT T5, the voltage of the fourth node N4 also becomes the first reference voltage REF1) between the threshold voltage (REF1) and the threshold voltage (Vth) of the driving TFT (DT).

As a result, during the second period t2, the second node N2 and the fourth node N4 sense the threshold voltage Vth of the driving TFT DT. In particular, the second period t2 may be appropriately set to a period longer than two horizontal periods through a preliminary experiment. That is, since the threshold voltage (Vth) of the driving TFT (DT) is sensed for a period longer than two horizontal periods, even when the organic light emitting display with a large area and high resolution is driven at a high frame frequency of 240 Hz or higher, It is possible to increase the accuracy of the threshold voltage sensing.

Third, during the third period t3, the first scan signal SCAN1 of the gate low voltage VGL is supplied through the first scan line SL1 and the second scan signal SCAN1 of the gate high voltage VGH SCAN2 are supplied through the second scan line SL2. The control signal MG of the gate high voltage VGH is supplied through the control line MGL and the emission signal EM of the gate high voltage VGH is supplied to the emission line EML during the third period t3, Lt; / RTI >

The first TFT T1 is turned on in response to the first scan signal SCAN1 of the gate low voltage VGL to connect the first node N1 to the data line DL. And the second TFT T2 is turned off by the second scan signal SCAN2 of the gate high voltage VGH. Due to the turn-on of the first TFT (T1) and the turn-off of the second TFT (T2), the first node (N1) is discharged to the data voltage (DATA). And the third TFT T3 is turned off by the second scan signal SCAN2 of the gate high voltage VGH. Due to the turn-off of the third TFT (T3), the third node (N3) floats. The fourth TFT T4 is turned off by the emission signal EM of the gate high voltage VGH. Due to the turn-off of the fourth TFT (T4), the second node (N2) floats. The fifth TFT T5 is turned off by the control signal MG of the gate high voltage VGH. Due to the turn-off of the fifth TFT (T5), the connection between the second node N2 and the fourth node N4 is cut off, and the fourth node N4 is floated.

Since the fourth node N4 is floated during the third period t3, the voltage variation of the first node N1 is reflected to the fourth node N4 by the first capacitor C1. That is, the voltage change amount of the first node N1 'REF1-DATA' is reflected to the fourth node N4. However, since the fourth node N4 is connected between the first and second capacitors C1 and C2 connected in series, the voltage change amount is reflected at the ratio of C 'as in Equation (2).

In Equation (2), CA1 denotes the capacitance of the first capacitor (C1) and CA2 denotes the capacitance of the second capacitor (C2). As a result, 'C' (REF1-DATA) 'is reflected in the fourth node N4, and thus the voltage of the fourth node N4 is changed to' REF1-Vth-C '(REF1-DATA).

Fourth, during the fourth period t4, the first scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1 and the second scan signal SCAN1 of the gate high voltage VGH SCAN2 are supplied through the second scan line SL2. The control signal MG of the gate high voltage VGH is supplied through the control line MGL during the period A4 of the fourth period t4 and the period B during the period B of the fourth period t4 the control signal MG of the gate low voltage VGL is supplied through the control line MGL during the period t4-B. Further, during the fourth period t4, the emission signal EM of the gate-low voltage VGL is supplied through the emission line EML.

The first TFT T1 is turned off by the first scan signal SCAN1 of the gate high voltage VGH. And the second TFT T2 is turned off by the second scan signal SCAN2 of the gate high voltage VGH. Due to the turn-off of the first TFT (T1) and the second TFT (T2), the first node (N1) floats. And the third TFT T3 is turned off by the second scan signal SCAN2 of the gate high voltage VGH. Due to the turn-off of the third TFT (T3), the third node (N3) floats. The fourth TFT T4 is turned on by the emission signal EM of the gate-low voltage VGL. Due to the turn-on of the fourth TFT T4, the second node N2 is charged to the high-potential voltage VDD. The fifth TFT T5 is turned off by the control signal MG of the gate high voltage VGH during the A period t4-A of the fourth period t4. The fourth node N4 is disconnected from the second node N2 due to the turn-off of the fifth TFT T5 during the A period t4-A of the fourth period t4. The fifth TFT T5 is turned on in response to the control signal MG of the gate low voltage VGL during the period B4-B of the fourth period t4. Because the fourth node N4 is connected to the second node N2 due to the turn-on of the fifth TFT T5 during the B period (t4-B) of the fourth period t4, the fourth node N4 Is charged to the high potential voltage VDD.

the first node N1 is floated during the period t4 and the fourth node N4 is charged to the high potential voltage VDD during the period B4 of the fourth period t4, Is reflected to the first node N1 by the first capacitor C1. That is, 'REF1-Vth-C' (REF1-DATA) -VDD ', which is the voltage change amount of the fourth node N4, is reflected in the first node N1. Therefore, the voltage of the first node N1 changes to 'DATA- {REF1-Vth-C' (REF1-DATA) -VDD} '.

Meanwhile, the drain-source current Ids of the driving TFT DT supplied to the organic light emitting diode (OLED) is expressed by Equation (3).

In Equation 3, k 'is a proportional coefficient determined by the structure and physical characteristics of the driving TFT DT, and is determined by the electron mobility, the channel width, and the channel length of the driving TFT DT. Vgs denotes a difference between the gate voltage Vg and the source voltage Vs of the driving TFT DT and Vth denotes a threshold voltage of the driving TFT DT. During the fourth period (t4), 'Vgs-Vth' is expressed by Equation (4).

Summarizing the expression (4), the drain-source current Ids of the driving TFT DT is derived as shown in expression (5).

As a result, the drain-source current Ids of the driving TFT DT supplied to the organic light emitting diode OLED during the fourth period t4 is equal to the threshold voltage Vth of the driving TFT DT It does not depend on it. That is, the present invention can compensate the threshold voltage of the driving TFT DT.

On the other hand, the high potential voltage source supplies a high potential voltage (VDD) to a plurality of pixels (P). When the fourth TFT T4 is turned on in response to the light emission pulse EM of the gate low voltage VGL during the B period t4-B of the fourth period t4, the high-potential voltage VDD and the high- The high-potential voltage VDD drops in voltage due to the parasitic resistance of the driving TFT DT, the organic light-emitting diode OLED, and the like existing along the current path between the low-potential voltage VSS. (VDD) of the gate voltage Vg is a voltage before the voltage drop of the high-potential voltage VDD, and 'VDD' of the source voltage Vs is the voltage of the organic light emitting diode OLED). ≪ / RTI > In this case, 'VDD' is not deleted in Equation (4) because 'VDD' of the gate voltage Vg and 'VDD' of the source voltage Vs are different. Therefore, the drain-source current Ids of the driving TFT DT, Has a problem that it becomes dependent on the high-potential voltage (VDD). However, in the pixel P according to the embodiment of the present invention, 'VDD' sampled at the gate voltage Vg at 'Vgs-Vth' in Equation 4 and 'VDD', which is the source voltage Vs, Since the voltage is reflected, 'VDD' is deleted in Equation (4), so that the drain-source current Ids of the driving TFT DT is not dependent on the high-potential voltage VDD. That is, the present invention can compensate the voltage drop of the high-potential voltage (VDD).

3 is a graph showing a threshold voltage compensation error according to a threshold voltage change of a driving TFT according to a threshold voltage sensing period. 3, the threshold voltage variation range (Vth Variation) of the driving TFT DT is shown on the x axis and the drain-source current (Vth Variation) of the driving TFT DT supplied to the organic light emitting diode OLED Ids) of the input signal.

The threshold voltage Vth of the driving TFT DT can be shifted by -1.0 V to +1.0 V with respect to the reference value for each pixel P due to deterioration of the driving TFT DT. Therefore, in recent organic light emitting diode display devices, the threshold voltage Vth is sensed by sensing the threshold voltage Vth of the driving TFT DT for each pixel P, so that the organic light emitting diode OLED is shifted to the threshold voltage Vth So that the light can be emitted without depending on it. However, when the accuracy of sensing the threshold voltage (Vth) of the driving TFT (DT) is low, the threshold voltage (Vth) compensation value sensed during the second period (t2) 'Vth' in Equation (4) is not deleted. This causes an error in the drain-source current Ids of the driving TFT DT supplied to the organic light emitting diode OLED.

3, an error of the drain-source current Ids of the driving TFT DT is set to be one horizontal period (1H) and two horizontal periods (2H) in the threshold voltage (Vth) sensing period of the driving TFT (DT) . When the threshold voltage (Vth) sensing period of the driving TFT DT is set to one horizontal period (1H), when the threshold voltage variation of the driving TFT DT is -1.0 V or +1.0 V, The error of the drain-source-to-source current (Ids) was about -2.5% to 1% of the reference value of 100%. However, when the threshold voltage (Vth) sensing period of the drive TFT (DT) is set to two horizontal periods, the error of the drain-source current Ids of the drive TFT (DT) (error) of about -1.5% to 0.5% compared to 100%. That is, when the threshold voltage (Vth) sensing period is made sufficiently longer than the two horizontal periods (2H) as shown in Fig. 3, the threshold voltage Vth of the driving TFT DT can be accurately sensed, The error of the inter-source current Ids can be minimized.

4 is a waveform diagram showing signals input to the pixel in the case of external compensation of the driving TFT. 4 shows the case where the first and second scan signals SCAN1 and SCAN2, the control signal MG, the light emission signal EM, and the like, which are input to one pixel P of the display panel 10 in the case of external compensation of the drive TFT, And a switching control signal SC are shown. In the case of external compensation of the driving TFT, the drain-source current Ids of the driving TFT DT is sensed by using the second reference voltage line RL2, and the drain-source current of the sensed driving TFT DT (Ids). A detailed description of the external compensation method will be given later with reference to FIGS. 9 and 10. FIG.

Referring to FIG. 4, the first and second scan signals SCAN1 and SCAN2, the control signal MG, and the emission signal EM are applied to the first to fifth TFTs T1, T2, T3, and T4 of the pixel P, , T5). The switching control signal SC is a signal for controlling the first and second switches S1 and S2 of the second reference voltage switching circuit REF2_SW.

In the case of external compensation of the driving TFT, the first scan signal SCAN1 and the switching control signal SC are generated at the gate high voltage VGH and the second scan signal SCAN2, the control signal MG, (EM) occurs at the gate-low voltage (VGL). In FIG. 4, the control signal MG is generated as the gate low voltage VGL, but it may be generated by the gate high voltage VGH.

5 is a diagram showing a current flow chart of a pixel in the case of external compensation of a driving TFT. Hereinafter, the operation of the pixel P in the case of external compensation of the driving TFT will be described in detail with reference to FIGS. 4 and 5. FIG.

In the case of external compensation of the driving TFT, the switching control signal SC of the gate high voltage VGH is supplied through the switching control line SCL. The first switch S1 is turned off by the switch control signal SC of the gate high voltage VGH. The second switch S2 is turned on in response to the inversion signal of the switch control signal SC to connect the current sensing circuit ADC and the second reference voltage line RL2. In the case of external compensation of the driving TFT, the second reference voltage line RL2 serves to sense the current due to the turn-on of the first switch S1 and the turn-off of the second switch S2.

Further, in the case of external compensation of the driving TFT, the first reference voltage source supplies the first voltage V1. The first voltage V1 is a voltage capable of turning on the driving TFT DT and can be set to a voltage at least lower than the high potential voltage VDD by the threshold voltage Vth of the driving TFT DT. For example, the first voltage V1 may be set to the same level as the first reference voltage REF1.

In the case of external compensation of the driving TFT, the first scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1 and the second scan signal SCAN2 of the gate low voltage VGL Is supplied through the second scan line SL2. The control signal MG of the gate low voltage VGL is supplied through the control line MGL and the emission signal EM of the gate low voltage VGL is supplied to the emission line EML ).

The first TFT T1 is turned off by the first scan signal SCAN1 of the gate high voltage VGH. The second TFT T2 is turned on in response to the second scan signal SCAN2 of the gate low voltage VGL to connect the first node N1 to the first reference voltage source. Due to the turn-on of the second TFT T2, the first voltage V1 is supplied from the first reference voltage source to the first node N1. The third TFT T3 is turned on in response to the second scan signal SCAN2 of the gate low voltage VGL to connect the third node N3 and the second reference voltage line RL2. The fourth TFT T4 is turned on in response to the emission signal EM of the gate low voltage VGL to connect the second node N2 to the high potential voltage source. The fifth TFT T5 is turned on in response to the control signal MG of the gate low voltage VGL to connect the second node N2 and the fourth node N4.

As a result, since the difference between the first voltage V1 applied to the gate electrode and the high-potential voltage VDD applied to the source electrode is larger than the threshold voltage Vth of the driving TFT DT, the driving TFT DT is turned- Is turned on. Further, since the third and fourth TFTs T3 and T4 are turned on, the drain-source current Ids of the driving TFT DT is higher than the third node N3, the third TFT T3, The reference voltage line RL2, and the second switch S2 in the current sensing circuit ADC. The current sensing circuit ADC converts the sensed current into digital data and outputs the converted digital data to the external compensation section 41 of the timing controller 40. [

6 is a waveform diagram showing signals input to the pixel in the case of external compensation of the organic light emitting diode. 6 shows the first and second scan signals SCAN1 and SCAN2 input to one pixel P of the display panel 10 in the case of external compensation of the organic light emitting diode OLED, (EM), and a switching control signal (SC). In the case of external compensation of the organic light emitting diode OLED, the current Ioled of the organic light emitting diode OLED is sensed using the second reference voltage line RL2 and the current Ioled of the sensed organic light emitting diode OLED ) To make external compensation. A detailed description of the external compensation method will be given later with reference to FIGS. 9 and 10. FIG.

6, the first and second scan signals SCAN1 and SCAN2, the control signal MG and the emission signal EM are applied to the first to fifth TFTs T1, T2, T3, and T4 of the pixel P, , T5). The switching control signal SC is a signal for controlling the first and second switches S1 and S2 of the second reference voltage switching circuit REF2_SW.

In the case of external compensation of the organic light emitting diode OLED, the first scan signal SCAN1, the control signal MG, the emission signal EM, and the switching control signal SC are generated at the gate high voltage VGH. The second scan signal SCAN2 is generated at the gate low voltage VGL during the fifth period t5 and at the gate high voltage VGH during the remaining period. The fifth period t5 is a period for sensing the current Ioled of the organic light emitting diode OLED for external compensation of the organic light emitting diode OLED.

7 is a diagram showing a current flow of a pixel in the case of external compensation of an organic light emitting diode. Hereinafter, the operation of the pixel P in the case of external compensation of the organic light emitting diode OLED will be described in detail with reference to FIGS. 6 and 7. FIG.

In the case of external compensation of the organic light emitting diode OLED, the switching control signal SC of the gate high voltage VGH is supplied through the switching control line SCL. The first switch S1 is turned off by the switch control signal SC of the gate high voltage VGH. The second switch S2 is turned on in response to the inversion signal of the switch control signal SC to connect the current sensing circuit ADC and the second reference voltage line RL2. In the case of external compensation of the organic light emitting diode OLED, due to the turn-on of the first switch S1 and the turn-off of the second switch S2, the second reference voltage line RL2 senses the current .

Further, in the case of external compensation of the organic light emitting diode (OLED), the first reference voltage source supplies the second voltage (V2). The second voltage V2 is a voltage capable of turning off the driving TFT DT and the difference between the high voltage VDD and the high voltage VDD can be set to a voltage lower than the threshold voltage Vth of the driving TFT DT . For example, the second voltage V2 may be set to a voltage at the same level as the high-potential voltage VDD.

In the case of external compensation of the organic light emitting diode OLED, the first scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1 during the fifth period t5, And the second scan signal SCAN2 of the voltage VGL is supplied through the second scan line SL2. In the case of external compensation of the driving TFT, the control signal MG of the gate high voltage VGH is supplied through the control line MGL during the fifth period t5, and the control signal MG of the gate high voltage VGH EM) are supplied through the light emission line (EML).

The first TFT T1 is turned off by the first scan signal SCAN1 of the gate high voltage VGH. The second TFT T2 is turned on in response to the second scan signal SCAN2 of the gate low voltage VGL to connect the first node N1 to the first reference voltage source. Due to the turn-on of the second TFT (T2), the second voltage (V2) is supplied from the first reference voltage source to the first node (N1). The third TFT T3 is turned on in response to the second scan signal SCAN2 of the gate low voltage VGL to connect the third node N3 and the second reference voltage line RL2. The fourth TFT T4 is turned off by the emission signal EM of the gate high voltage VGH. The fifth TFT T5 is turned off by the control signal MG of the gate high voltage VGH.

As a result, the driving TFT DT is turned off because the difference between the second voltage V2 applied to the gate electrode and the high potential source VDD applied to the source electrode is smaller than the threshold voltage of the driving TFT DT. Further, since the third TFT T3 is turned on, the current Ioled of the organic light emitting diode OLED flows through the second reference voltage line RL2, the third TFT T3, the third node N3, And is discharged to the low potential voltage source through the organic light emitting diode (OLED). The current sensing circuit ADC is connected to the second reference voltage line RL2 during the fifth period t5 to sense the current Ioled of the organic light emitting diode OLED. The current sensing circuit ADC converts the sensed current into digital data and outputs the converted digital data to the external compensation section 41 of the timing controller 40. [

8 is a block diagram schematically showing an organic light emitting diode display device according to an embodiment of the present invention. 8, an organic light emitting diode display device according to an embodiment of the present invention includes a display panel 10, a data driver 20, a scan driver 30, a timing controller 40, a host system 50, Respectively.

The display panel 10 is formed such that the data lines DL and the first scan lines SL1 intersect with each other. The second scan lines SL2, the control lines MG, and the emission lines EML are formed on the display panel 10 in parallel with the first scan lines SL1. In addition, switching control lines SCL may be formed on the display panel 10 in parallel with the first scan lines SL1. In addition, in the display panel 10, pixels P arranged in a matrix form are formed. Each of the pixels P of the display panel 10 is as described with reference to FIG.

The data driver 20 includes a plurality of source drive ICs. The source drive ICs receive the digital video data RGB (RGB) from the timing controller 40 with the threshold voltage Vth of the driving TFT DT, the electron mobility, the threshold voltage Vth of the organic light emitting diode OLED, '). The source drive ICs generate a data voltage by converting the compensated digital video data RGB 'into a gamma compensation voltage in response to a source timing control signal DCS from the timing controller 40, (DL) of the display panel 10 so as to be synchronized with the scan line SCAN1.

The scan driver 30 includes a first scan signal output unit, a second scan signal output unit, a control signal output unit, a light emission signal output unit, and a switching control signal output unit. The first scan signal output unit sequentially outputs the first scan signal SCAN1 to the first scan lines SL1 of the display panel 10. [ The second scan signal output unit sequentially outputs a second scan signal ( SCAN2 ) to the second scan lines ( SL2 ) of the display panel (10) . The control signal output unit sequentially outputs the control signal MG to the control lines MGL of the display panel 10 . The light emitting signal output unit sequentially outputs the light emitting signal EM to the light emitting lines ( EML ) of the display panel 10 . A switching control line switching control signal (SC) to (SCL) of the switching control signal output unit display panel 10, and outputs one by one. Detailed descriptions of the first and second scan signals SCAN1 and SCAN2, the control signal MG, the light emission signal EM and the switching control signal SC are given in detail in connection with FIGS. 2, 4 and 6 .

The timing controller 40 receives digital video data RGB from the host system 50 via an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. The timing controller 40 may include an external compensation section 41 for externally compensating the threshold voltage Vth of the driving TFT DT and the electron mobility and the threshold voltage Vth of the organic light emitting diode OLED. have. The external compensation unit 41 of the timing controller 40 reflects the compensation data calculated by using the external compensation method on the digital video data RGB input from the host system 50 and outputs the compensated digital video data RGB ' And outputs it to the data driver 20.

The timing controller 40 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal (Data Enable), and a dot clock (Dot Clock). The timing controller 50 generates timing control signals for controlling the operation timing of the data driver 20 and the scan driver 30 based on the timing signal from the host system. The timing control signals include a scan timing control signal for controlling the operation timing of the scan driver 30 and a data timing control signal for controlling the operation timing of the data driver 20. [ The timing controller 40 outputs a scan timing control signal to the scan driver 30 and a data timing control signal to the data driver 20.

The display panel may further include a power supply unit (not shown). The power supply unit supplies a high potential voltage (VDD), a low potential voltage (VSS), a first reference voltage (REF1), and a second reference voltage (REF2) to the display panel (10). The power supply unit supplies a gate high voltage (VGH) and a gate low voltage (VGL) to the scan driver (30).

9 is a block diagram showing the external compensation unit of the timing controller. 10 is a flowchart illustrating an external compensation method according to an embodiment of the present invention. 9, the external compensation unit 41 of the timing controller 40 includes a compensation data calculation unit 41a and a compensated digital video data output unit 41b. Hereinafter, an external compensation method of the external compensation unit 41 according to the embodiment of the present invention will be schematically described with reference to FIGS. 9 and 10. FIG.

First of all, by using a current sensing circuit ADC connected to the second reference voltage line RL2 of each of the pixels P of the display panel 10, Source-to-source current Ids and the current Ioled of the organic light emitting diode OLED. The method of sensing the drain-source current (Ids) of the driver TFT (DT) of the current sensing circuit (ADC) has been described in detail with reference to FIGS. 4 and 5. FIG. The current sensing of the organic light emitting diode (OLED) of the current sensing circuit (ADC) has been described in detail with reference to FIGS. 6 and 7. FIG. The current sensing circuit ADC converts the sensed current into digital data and outputs the converted digital data to the compensation data calculation section 41a of the external compensation section 41. [ (S1)

Secondly, the compensation data calculation section 41a calculates the external compensation data using the digital data inputted from the current sensing circuit ADC. The compensation data calculating unit 41a calculates the compensation voltage Vth and the electron mobility of the driving TFT DT and the threshold voltage Vth of the organic light emitting diode OLED from the digital data inputted using known external compensation calculation methods ) Can calculate compensated external compensation data. (S2)

Thirdly, the compensated digital video data output section 41b receives digital video data (RGB) from the host system 50 and receives external compensation data from the compensation data calculation section 41a. The compensated digital video data output section 41b generates compensated digital video data RGB 'by reflecting external compensation data to the input digital video data RGB. The compensated digital video data output section 41b outputs the compensated digital video data RGB 'to the data driver 20. (S3)

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

OLED: organic light emitting diode DT: driving TFT
T1: first TFT T2: second TFT
T3: third TFT T4: fourth TFT
T5: fifth TFT S1: first switch
S2: second switch Inv: inverter
ADC: current sensing circuit C1: first capacitor
C2: second capacitor N1: first node
N2: second node N3: third node
N4: fourth node SCAN1: first scan signal
SCAN2: Second scan signal MG: Control signal
EM: Emission signal SC: Switching control signal
10: display panel 20: data driver
30: scan driver 40: timing controller
41: external compensation unit 41a: external compensation data calculation unit
41b: Compensated digital video data output section
50: Host system

Claims (16)

And a display panel on which a plurality of pixels formed in a matrix form are formed, in which a data line, a first scan line, a second scan line, a control line,
Each of the pixels includes:
A driver TFT having a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to the third node;
An organic light emitting diode including an anode electrode connected to the third node and a cathode electrode connected to a low potential voltage source for supplying a low potential voltage;
A first TFT which is turned on in response to a first scan signal of a gate low voltage of the first scan line to connect the first node and the data line;
And a second transistor connected between the first node and a first reference voltage line for supplying a first reference voltage from the first reference voltage source, the second transistor being turned on in response to a second scan signal of the gate low voltage of the second scan line, ;
A third TFT connected to the third node and a second reference voltage line for supplying a second reference voltage from the second reference voltage source, the third TFT being turned on in response to the second scan signal;
A fourth TFT which is turned on in response to the light-emitting signal of the gate-low voltage of the light-emitting line to connect a high potential voltage source supplying the high voltage with the second node;
A fifth TFT which is turned on in response to a control signal of the gate-low voltage of the control line to connect the second node and the fourth node;
A first capacitor connected between the first node and the fourth node; And
And a second capacitor connected between the fourth node and the high potential voltage source. The method according to claim 1,
During a first period of initializing the first node and the third node,
Wherein the first scan signal is generated at a gate high voltage higher than the gate low voltage,
And the second scan signal, the control signal, and the emission signal are generated at the gate low voltage. 3. The method of claim 2,
During a second period following the first period and sensing a threshold voltage of the driving TFT,
The first scan signal and the emission signal are generated at the gate high voltage,
And the second scan signal and the control signal are generated at the gate low voltage. The method of claim 3,
During a third period in which the data voltage is supplied through the data line,
The second scan signal, the control signal, and the emission signal are generated at the gate high voltage,
Wherein the first scan signal is generated at the gate low voltage. 5. The method of claim 4,
During the fourth period in which the organic light emitting diode emits light,
The first scan signal and the second scan signal are generated at the gate high voltage,
The light emitting signal is generated at the gate low voltage,
The fourth period is divided into an A period and a B period,
Wherein the control signal is generated at the gate high voltage during the A period and is generated at the gate low voltage during the B period. The method according to claim 1,
Wherein the first reference voltage is set to a voltage lower than the high-potential voltage by at least a threshold voltage of the driving TFT. The method according to claim 1,
Wherein the second reference voltage is set to a voltage lower than a threshold voltage of the organic light emitting diode. The method according to claim 1,
When the drain-source current of the driving TFT is sensed using the second reference voltage line,
Wherein the first scan signal is generated at a gate high voltage higher than the gate low voltage,
And the second scan signal, the control signal, and the emission signal are generated at the gate low voltage. 9. The method of claim 8,
When the drain-source current of the driving TFT is sensed using the second reference voltage line,
Wherein the first reference voltage source supplies a first voltage set to a voltage lower than the high potential voltage by at least a threshold voltage of the driving TFT. The method according to claim 1,
When the current of the organic light emitting diode is sensed using the second reference voltage line,
The first scan signal, the control signal, and the emission signal are generated at a gate high voltage higher than the gate low voltage,
Wherein the second scan signal is generated at the gate low voltage for a predetermined fifth period and is generated at the gate high voltage for the remaining period. 11. The method of claim 10,
When the current of the organic light emitting diode is sensed using the second reference voltage line,
Wherein the first reference voltage source supplies a second voltage, the difference between the first reference voltage and the high voltage being set to a voltage smaller than a threshold voltage of the driving TFT. The method according to claim 1,
A gate electrode of the first TFT is connected to the first scan line, a source electrode is connected to the data line, a drain electrode is connected to the first node,
A gate electrode of the second TFT is connected to the second scan line, a source electrode is connected to the first node, a drain electrode is connected to the first reference voltage line,
A gate electrode of the third TFT is connected to the second scan line, a source electrode is connected to the third node, a drain electrode is connected to the second reference voltage line,
A gate electrode of the fourth TFT is connected to the light emitting line, a source electrode is connected to the high potential voltage source, a drain electrode is connected to the second node,
A gate electrode of the fifth TFT is connected to the control line, a source electrode is connected to the second node, and a drain electrode is connected to the fourth node. 6. The method of claim 5,
The display panel further includes a switching control line,
A first switch that is turned on in response to a switching control signal of the switching control line to connect the second reference voltage line and the second reference voltage source;
A second switch that is turned on in response to an inverted signal of the switching control signal to connect the second reference voltage line to the current sensing circuit; And
Further comprising an inverter for inverting the switching control signal. 14. The method of claim 13,
Wherein the switching control signal is generated at the gate low voltage during the first to fourth periods. 14. The method of claim 13,
When the drain-source current of the driving TFT or the current of the organic light emitting diode is sensed using the second reference voltage line,
Wherein the switching control signal is generated at the gate high voltage. 14. The method of claim 13,
A gate electrode of the first switch is connected to the switching control line, a source electrode is connected to the second reference voltage line, a drain electrode is connected to the second reference voltage source,
A gate electrode of the second switch is connected to the inverter, a source electrode is connected to the current sensing circuit, a drain electrode is connected to the second reference voltage line,
And the inverter is connected between the gate electrode of the second switch and the switching control line.

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